Control method, device, equipment and system of heterogeneous multi-core chip

Abstract

The application discloses a control method, device, equipment and system of a heterogeneous multi-core chip, relates to the technical field of chips, and the control method of the heterogeneous multi-core chip is applied to a main core of a first core. The method comprises the following steps: when an external wake-up request is received, a first power-on control instruction is sent to a second core in the heterogeneous multi-core chip, so that the second core executes a starting program according to the first power-on control instruction; when the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to a parallel starting strategy, and the second power-on control instruction is sent to a plurality of sub-cores in the first core of the heterogeneous multi-core chip respectively, so that each sub-core executes a starting program according to the second power-on control instruction. In the above manner, the fast starting, high stability and high reliability of the heterogeneous multi-core chip are realized, and the comprehensive requirements of energy efficiency, safety and real-time performance of the heterogeneous multi-core chip under variable working conditions are met.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to control methods, apparatus, equipment and systems for heterogeneous multi-core chips. Background Technology

[0002] As the complexity of automotive electronic systems increases, the requirements for energy efficiency management, functional safety, and real-time performance of heterogeneous multi-core chips are also becoming more stringent. The S32G heterogeneous multi-core chip system, due to its multi-core parallel processing capabilities, low latency response, and high reliability, has become a key component of automotive electronic systems. However, existing power-on / off control strategies often fail to meet the comprehensive energy efficiency, safety, and real-time performance requirements of these systems under varying operating conditions. Summary of the Invention

[0003] The main objective of this application is to provide a control method, device, equipment, and system for heterogeneous multi-core chips, aiming to solve the technical problem that existing power-on / off control strategies often cannot meet the comprehensive requirements of heterogeneous multi-core chip systems for energy efficiency, safety, and real-time performance under varying operating conditions.

[0004] To achieve the above objectives, this application proposes a control method for a heterogeneous multi-core chip, the control method comprising:

[0005] Upon receiving an external wake-up request, a first power-on control command is sent to the second core in the heterogeneous multi-core chip, so that the second core executes the startup program according to the first power-on control command.

[0006] When the first power-on control command is sent to the second core, a second power-on control command is generated according to the parallel startup strategy, and the second power-on control command is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes the startup program according to the second power-on control command.

[0007] In one embodiment, sending a first power-on control command to the second core of the heterogeneous multi-core chip upon receiving an external wake-up request includes:

[0008] Upon receiving an external wake-up request, obtain the system initialization status;

[0009] When the system initialization state is complete and the control permission is received from the third core of the heterogeneous multi-core chip, a first power-on control command is sent to the second core of the heterogeneous multi-core chip. The control permission is transmitted by the third core after it has completed loading the user firmware through the target firmware when it obtains the system integrity confirmation result by executing the target firmware.

[0010] In one embodiment, the control method for the heterogeneous multi-core chip further includes:

[0011] When no target wake-up source is available, a first hibernation control command is sent to the second core in the heterogeneous multi-core chip according to the inter-core communication mechanism, so that the second core executes the hibernation program according to the first hibernation control command and feeds back hibernation confirmation information.

[0012] When the hibernation confirmation information is received from the second core and the preset hibernation duration is reached, the second hibernation control command is sent to multiple sub-cores in the second core of the heterogeneous multi-core chip, so that each sub-core executes the hibernation program according to the second hibernation control command and feeds back the status confirmation information.

[0013] Upon receiving the status confirmation information from each sub-core, the target hibernation procedure is executed.

[0014] In one embodiment, the method further includes:

[0015] Upon receiving the status confirmation information from each sub-core, shut down the target system service;

[0016] When the target system service is detected to have finished shutting down, the core state information is saved to the target storage location;

[0017] When the core state information is detected to be saved, the target hibernation procedure is executed.

[0018] In one embodiment, the control method for the heterogeneous multi-core chip is applied to multiple sub-cores in a first core, and the control method for the heterogeneous multi-core chip includes:

[0019] Upon receiving the second power-on control command sent by the main core of the first core, the interrupt service routine is triggered according to the second power-on control command, and the startup program is executed.

[0020] In one embodiment, the method further includes:

[0021] Upon receiving the second hibernation control command from the main core of the first core, the target task state is saved;

[0022] When the target task status is detected to be saved, the target processing mechanism is closed;

[0023] When the target processing mechanism is detected to have finished shutting down, a hibernation procedure is executed and a status confirmation message is sent back to the main core of the first core.

[0024] In one embodiment, the control method for the heterogeneous multi-core chip is applied to a second core, and the control method for the heterogeneous multi-core chip includes:

[0025] Upon receiving the first hibernation control command sent by the main core of the first core, hibernation confirmation information is fed back to the main core of the first core, and the hibernation program is executed when it is detected that the critical data has been saved.

[0026] Furthermore, to achieve the above objectives, this application also proposes a control device for a heterogeneous multi-core chip, the control device comprising:

[0027] The processing module is used to start the operating system and send a first power-on control command to the second core in the heterogeneous multi-core chip when an external wake-up request is received, so that the second core executes the startup program according to the first power-on control command;

[0028] The control module is used to generate a second power-on control instruction according to a parallel startup strategy when the first power-on control instruction is sent to the second core, and to send the second power-on control instruction to multiple sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes the startup program according to the second power-on control instruction.

[0029] In addition, to achieve the above objectives, this application also proposes a control device for a heterogeneous multi-core chip, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the control method for the heterogeneous multi-core chip as described above.

[0030] In addition, to achieve the above objectives, this application also proposes a control system for a heterogeneous multi-core chip, characterized in that the control system for the heterogeneous multi-core chip includes a main core of a first core as described in any one of claims 1 to 4, a plurality of sub-cores in the first core as described in any one of claims 5 to 6, and a second core as described in claim 7.

[0031] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the heterogeneous multi-core chip control method described above.

[0032] This application achieves rapid startup, high stability, and high reliability for the heterogeneous multi-core chip by sending a first power-on control command to the second core of the heterogeneous multi-core chip upon receiving an external wake-up request. This causes the second core to execute a startup program according to the first power-on control command. Simultaneously, while the first power-on control command is being sent to the second core, a second power-on control command is generated according to a parallel startup strategy and sent to multiple sub-cores within the first core of the heterogeneous multi-core chip. Each sub-core then executes its startup program according to the second power-on control command. This approach fulfills the comprehensive requirements of the heterogeneous multi-core chip for energy efficiency, security, and real-time performance under varying operating conditions. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart illustrating a first embodiment of the control method for a heterogeneous multi-core chip applied to the main core of the first core of this application.

[0036] Figure 2 This is a schematic diagram of the architecture of the S32G heterogeneous multi-core chip system provided in Embodiment 1 of the control method for heterogeneous multi-core chips in this application.

[0037] Figure 3 This is a schematic diagram of the specific startup process of core A after the main core sends the startup command to core A, as provided in Embodiment 1 of the control method for heterogeneous multi-core chips in this application.

[0038] Figure 4 This is a schematic diagram of the A-core power management state machine provided in Embodiment 1 of the control method for heterogeneous multi-core chips in this application;

[0039] Figure 5 This is a flowchart illustrating a second embodiment of the control method for a heterogeneous multi-core chip with multiple sub-cores of a first core, as described in this application.

[0040] Figure 6 This is a flowchart illustrating Embodiment 3 of the control method applied to a heterogeneous multi-core chip with a second core in this application;

[0041] Figure 7This is a schematic diagram of the module structure of the control device for a heterogeneous multi-core chip according to an embodiment of this application;

[0042] Figure 8 This is a schematic diagram of the device structure of the hardware operating environment involved in the control method of heterogeneous multi-core chips in the embodiments of this application.

[0043] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0044] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0045] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0046] The main solution of this application embodiment is: when receiving an external wake-up request, a first power-on control instruction is sent to the second core in the heterogeneous multi-core chip, so that the second core executes the startup program according to the first power-on control instruction; when the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to the parallel startup strategy, and the second power-on control instruction is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes the startup program according to the second power-on control instruction.

[0047] As the complexity of automotive electronic systems increases, the requirements for energy efficiency management, functional safety, and real-time performance of heterogeneous multi-core chips are also becoming more stringent. The S32G heterogeneous multi-core chip system, due to its multi-core parallel processing capabilities, low latency response, and high reliability, has become a key component of automotive electronic systems. However, existing power-on / off control strategies often fail to meet the comprehensive energy efficiency, safety, and real-time performance requirements of these systems under varying operating conditions.

[0048] This application achieves rapid startup, high stability, and high reliability for the heterogeneous multi-core chip by sending a first power-on control command to the second core of the heterogeneous multi-core chip upon receiving an external wake-up request. This causes the second core to execute a startup program according to the first power-on control command. Simultaneously, while the first power-on control command is being sent to the second core, a second power-on control command is generated according to a parallel startup strategy and sent to multiple sub-cores within the first core of the heterogeneous multi-core chip. Each sub-core then executes its startup program according to the second power-on control command. This approach fulfills the comprehensive requirements of the heterogeneous multi-core chip for energy efficiency, security, and real-time performance under varying operating conditions.

[0049] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or a control device for a heterogeneous multi-core chip capable of performing the above functions. The following description uses a control device for a heterogeneous multi-core chip as the executing entity to illustrate this embodiment and the subsequent embodiments.

[0050] Based on this, embodiments of this application provide a control method for a heterogeneous multi-core chip, wherein the control method for the heterogeneous multi-core chip is applied to the main core of the first core, as described above. Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the control method for heterogeneous multi-core chips in this application.

[0051] In this embodiment, the control method for the heterogeneous multi-core chip includes steps S10 to S20:

[0052] Step S10: Upon receiving an external wake-up request, a first power-on control command is sent to the second core in the heterogeneous multi-core chip, so that the second core executes the startup program according to the first power-on control command;

[0053] It should be noted that the schematic diagram of the S32G heterogeneous multi-core chip system in this embodiment is as follows: Figure 2 As shown, the S32G heterogeneous multi-core chip system includes an A core and an M core. The M core further includes core 0, core 1, core 2, and core 3. In this embodiment, core 0 of the M core is used as the execution entity.

[0054] It is understandable that an external wake-up request refers to a request signal from an external control system to wake up the vehicle from a low-power mode to a normal operating state, and the first power-on control command refers to the command to control the second core (A core) to switch to the power-on state.

[0055] In practice, when the S32G's M core receives a request signal from an external control unit to wake up the vehicle from low-power mode to normal operation, the operating system (OS) will initialize and start on core 0 of the M core (hereinafter referred to as the main core). During the initial operation phase, the main core is responsible for issuing a startup command to the A core to ensure that the A core (secondary core) can respond in a timely manner and begin its startup process.

[0056] In one feasible implementation, step S10 may include steps A11 to A12:

[0057] Step A11: Upon receiving an external wake-up request, obtain the system initialization status;

[0058] It is understandable that the system initialization state includes a completed state and an incomplete state.

[0059] In practice, when the main core of the M core receives a request signal from the external control vehicle to wake up from low power mode to normal working state, the S32G chip will undergo a hardware reset process to restore the system to the initial state, thereby determining the initial state of the system.

[0060] Step A12: When the system initialization state is complete and the control permission is received from the third core of the heterogeneous multi-core chip, a first power-on control command is sent to the second core of the heterogeneous multi-core chip. The control permission is transmitted by the third core after it has completed loading the user firmware through the target firmware when it obtains the system integrity confirmation result by executing the target firmware.

[0061] Understandably, the third core refers to the processor core located in the HSE_H subsystem, and the target firmware refers to the firmware written by the user.

[0062] In practice, after the hardware reset is completed, the integrity of the system is checked. Once the integrity of the system is confirmed, the BootROM firmware will load the user-written firmware or operating system into memory and prepare to pass it to the main processor core for execution. After the user firmware is loaded, the HSE_H core will transfer control to the main processor core. The main processor core will start executing the user firmware and take over the control of the system. The main core will send instructions to the second core (A core) to switch to the power-on state.

[0063] Step S20: When the first power-on control instruction is sent to the second core, a second power-on control instruction is generated according to the parallel startup strategy, and the second power-on control instruction is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes the startup program according to the second power-on control instruction.

[0064] It is understandable that the parallel startup strategy refers to the strategy of controlling the A core and the M core to enter the working state almost simultaneously. The second power-on control instruction refers to the instruction that controls the M core (core 1, core 2 and core 3) to switch to the power-on state. Multiple sub-cores refer to core 1, core 2 and core 3 in the M core.

[0065] In practice, after sending the A-core boot command, the main core continues to execute the parallel boot strategy, sequentially booting the remaining cores (core 1, core 2, and core 3) within the M-core. This strategy ensures that the A-core and M-core cores can enter the working state almost simultaneously, significantly shortening the overall system boot time. Simultaneously, through parallel booting, the system can establish communication links between cores in the shortest possible time to meet the processing needs of various real-time events and improve system response efficiency.

[0066] In one feasible implementation, the control method for the heterogeneous multi-core chip is applied to core 0 of the M-core, and the method further includes steps S11 to S13:

[0067] Step S11: When there is no target wake-up source, a first hibernation control command is sent to the second core in the heterogeneous multi-core chip according to the inter-core communication mechanism, so that the second core executes the hibernation program according to the first hibernation control command and feeds back hibernation confirmation information;

[0068] It is understandable that the target wake-up source includes external wake-up sources (such as external interrupts, signal triggers, etc.) and internal wake-up sources (such as timers, task scheduling, etc.). The inter-core communication mechanism refers to the pre-set mechanism for communication between cores. The first hibernation control instruction refers to the instruction that controls the second core (core A) to switch to hibernation state. The hibernation confirmation information refers to the information indicating that core A has received the shutdown instruction.

[0069] In practice, the main core performs a comprehensive check to ensure that no external wake-up sources (such as external interrupts, signal triggers, etc.) or internal wake-up sources (such as timers, task scheduling, etc.) are maintaining the system's wake-up state. Once it is confirmed that there are no such wake-up sources, the main core will issue a command to shut down core A through the inter-core communication mechanism.

[0070] Step S12: When the hibernation confirmation information is received from the second core and the preset hibernation duration is reached, the second hibernation control command is sent to the multiple sub-cores in the second core of the heterogeneous multi-core chip, so that each sub-core executes the hibernation program according to the second hibernation control command and feeds back the status confirmation information.

[0071] It is understandable that the preset hibernation duration refers to the pre-set hibernation waiting time, the second hibernation control command refers to the command to control each core of the M core (core 1, core 2 and core 3) to switch to hibernation state, and the status confirmation information refers to the information indicating that each core of the M core (core 1, core 2 and core 3) has successfully entered the safe shutdown state.

[0072] In practice, the main core will use a time reservation method to ensure that core A has enough time to complete all shutdown operations. Once the main core detects that core A has been completely shut down, it will send shutdown commands to core 1, core 2 and core 3 through the system control interface. After each sub-core completes the shutdown sequence, it will send a status confirmation signal to the main core, indicating that it has successfully entered the safe shutdown state.

[0073] Step S13: Upon receiving the status confirmation information from each sub-core, execute the target hibernation procedure.

[0074] It is understandable that the target hibernation program refers to the program that controls the main core to hibernate.

[0075] In practice, after completing the shutdown sequence, each sub-core sends a status confirmation signal to the main core, indicating that it has successfully entered the safe shutdown state. The main core continuously monitors the shutdown status of cores 1, 2, and 3 to ensure that each core has completed the shutdown process as expected. After confirming that all sub-cores have safely shut down, the main core will execute its own shutdown operation.

[0076] In this embodiment, when no target wake-up source is present, a first hibernation control command is sent to the second core of the heterogeneous multi-core chip according to the inter-core communication mechanism. This causes the second core to execute a hibernation program according to the first hibernation control command and provide hibernation confirmation information. Upon receiving the hibernation confirmation information from the second core and reaching a preset hibernation duration, a second hibernation control command is sent to multiple sub-cores within the second core of the heterogeneous multi-core chip. Each sub-core then executes a hibernation program according to the second hibernation control command and provides status confirmation information. Upon receiving the status confirmation information from each sub-core, a target hibernation program is executed. Through this method, the operating status of the cores is intelligently monitored and dynamically adjusted, optimizing energy consumption and improving energy efficiency.

[0077] In one feasible implementation, the control method for the heterogeneous multi-core chip is applied to core 0 of the M-core, and the method further includes steps S21 to S23:

[0078] Step S21: Upon receiving the status confirmation information from each sub-core, shut down the target system service;

[0079] Understandably, the target system service refers to all remaining system services. After confirming that all sub-cores have been safely shut down, the main core will perform its own shutdown operation, that is, shut down all remaining system services and tasks.

[0080] Step S22: When the target system service is detected to have finished shutting down, save the core state information to the target storage location;

[0081] It is understandable that core state information refers to the state information of the main kernel, and target storage location refers to the location of non-volatile storage.

[0082] In practice, the main kernel's state information is saved to non-volatile storage only after all remaining system services have been shut down.

[0083] Step S23: When the core state information is detected to be saved, the target hibernation program is executed.

[0084] It is understandable that when the main core's state information is detected to be saved, the operating frequency is actively reduced to the minimum to enter a low-power state, that is, the program that controls the main core to enter a sleep state is executed.

[0085] In this embodiment, upon receiving status confirmation information from each sub-core, the target system service is shut down; upon detecting that the target system service shutdown is complete, core status information is saved to the target storage location; and upon detecting that the core status information has been saved completely, the target hibernation procedure is executed. This method ensures the continuity of critical tasks and the integrity of data.

[0086] It should be noted that this embodiment improves system response speed and energy efficiency management through an efficient parallel startup strategy and an orderly hibernation process. The specific implementation steps are described as follows: S1, When the S32G M core receives an external wake-up request, the operating system (OS) will initialize and start on core 0 of the M core (hereinafter referred to as the main core). In the initial running phase, the main core is responsible for issuing a startup command to the A core to ensure that the A core can respond in a timely manner and start its startup program;

[0087] Further, step S1 specifically includes: First, the S32G chip undergoes a hardware reset process to restore the system to its initial state. After the hardware reset is complete, the HSE_H core (the processor core located in the HSE_H subsystem) becomes the only available processor core. The HSE_H core is mainly responsible for security-related functions, including executing firmware from the HSE_H ROM module. The HSE_H core executes the BootROM firmware starting from the HSE_H ROM module. The BootROM firmware is a read-only code pre-installed in the chip, responsible for initializing the hardware, checking system integrity, and preparing to load user-written firmware or operating system. The BootROM firmware performs a series of security policy checks to ensure that the software loaded into the system has not been tampered with and is certified. These checks may include verifying the digital signature of the firmware or operating system, checking checksums, etc. Once system integrity is confirmed, the BootROM firmware loads the user-written firmware or operating system into memory and prepares to pass it to the main processor core for execution. After the user firmware is loaded, the HSE_H core transfers control to the main processor core. The main processor core will begin executing the user firmware and take over control of the system. After the BootROM stage, u-boot boots the subsequent kernel. The main core then executes the main operating system code, including the booting of core A. The specific boot process of core A after the main core sends the boot command is as follows: Figure 3 As shown.

[0088] S2. After sending the A-core boot command, the main core continues to execute the parallel boot strategy, sequentially booting the remaining cores (core 1, core 2, and core 3) within the M-core. This strategy ensures that the A-core and M-core cores can enter the working state almost simultaneously, significantly shortening the overall system boot time. Simultaneously, through parallel booting, the system can establish communication links between cores in the shortest possible time to meet the processing needs of various real-time events and improve system response efficiency.

[0089] Furthermore, step S2 specifically includes: after the main core (core 0) completes basic initialization, it executes a detailed software configuration process. This process not only includes setting up efficient communication mechanisms between cores (such as shared memory, message queues, etc.), but also involves customizing the runtime environment configuration for each core, such as clock frequency, power management strategy, etc., to ensure that each core runs in the optimal state.

[0090] The main core triggers the internal interrupt service routine of the core to be started by sending a specific formatted interrupt signal, thereby achieving non-active wake-up and code execution startup. This mechanism effectively reduces energy consumption and latency during system startup. In multi-core processor systems, especially for the four cores of an M-core architecture, this invention introduces a mutex-based synchronization mechanism to ensure mutual exclusion and consistency in critical aspects such as shared resource access and task scheduling, avoiding data conflicts and deadlocks, and improving system stability.

[0091] During development, rigorous multi-core boot reliability and stability testing was implemented, including but not limited to performance testing under multiple configuration environments, fault injection testing, and proactive scanning and immediate patching of security vulnerabilities, to ensure that the system performs excellently under various operating conditions.

[0092] For security-sensitive operations involved in the main core's startup of other cores, this invention follows a strict set of security protocols and operating procedures, including but not limited to encrypted data transmission, access control, and security auditing, to comprehensively protect system security.

[0093] S3. Before the system enters hibernation, the main core will first issue a command to shut down core A, and then enter a short waiting period to ensure that core A has successfully received the shutdown command and completed its shutdown process. This hibernation management strategy ensures the system's ability to wake up quickly in low-power states and reduces potential damage to core A caused by improper hibernation operations;

[0094] Furthermore, step S3 specifically includes: A schematic diagram of the core power management state machine, as shown below. Figure 4As shown, before the system enters the hibernation phase, a sophisticated hibernation management strategy is implemented to ensure a low-power state and reduce potential damage. First, the main core performs a comprehensive check to ensure that no external wake-up sources (such as external interrupts, signal triggers, etc.) or internal wake-up sources (such as timers, task scheduling, etc.) are maintaining the system's wake-up state. Once these wake-up sources are confirmed to be absent, the main core issues a command to shut down core A via inter-core communication. The core A state machine is shown in Table 1. After receiving the shutdown command from the main core, core A immediately sends an acknowledgment message indicating that the shutdown command has been received and begins executing the shutdown of all running applications and processes. During this process, core A ensures that all critical data is properly saved so that it can be restored to the correct state upon subsequent wake-up. Simultaneously, the main core uses time reservation to ensure that core A has sufficient time to complete all shutdown operations, including closing applications and processes and saving critical data. Once the main core detects that core A has been completely shut down and the system is in a stable state, the main core will begin executing its own shutdown procedure.

[0095] Table 1:

[0096]

[0097] S4. After ensuring that core A has been safely shut down, the main core continues to execute the shutdown operation of the remaining cores (core 1, core 2, and core 3) within core M. Once all these cores have successfully entered hibernation, the main core will execute its own shutdown action, completing the entire system hibernation process. This process not only ensures orderly system hibernation but also further improves the system's energy efficiency ratio through refined management strategies.

[0098] Further, step S4 specifically includes: First, the main core completes all ongoing tasks or saves them to non-volatile memory. This ensures data synchronization across all cores and prevents data loss. The main core sends shutdown commands to cores 1, 2, and 3 through the system control interface. Upon receiving the shutdown command, cores 1, 2, and 3 will respectively perform the following operations: stop the currently executing tasks and ensure all task states are properly saved; disable locally running interrupt and event handling mechanisms; and gradually reduce the processor's operating frequency until it stops. After completing the shutdown sequence, each sub-core will send a status confirmation signal to the main core, indicating that it has successfully entered the safe shutdown state. The main core will continuously monitor the shutdown status of cores 1, 2, and 3 to ensure that each core has completed the shutdown process as expected. After confirming that all sub-cores have safely shut down, the main core will perform its own shutdown operations, including but not limited to: shutting down all remaining system services and tasks; saving the main core's state information to non-volatile memory; and actively reducing its own operating frequency to the minimum, entering a low-power state. Ultimately, the main core will ensure that the power supply of the entire S32G chip system is properly managed, and all necessary hardware components will enter a low-power or shutdown state, completing the shutdown process of the entire system.

[0099] This embodiment sends a first power-on control command to the second core of the heterogeneous multi-core chip upon receiving an external wake-up request, causing the second core to execute a startup program according to the first power-on control command. While the first power-on control command is being sent to the second core, a second power-on control command is generated according to a parallel startup strategy and sent to multiple sub-cores within the first core of the heterogeneous multi-core chip, causing each sub-core to execute a startup program according to the second power-on control command. Through this method, the heterogeneous multi-core chip achieves rapid startup, high stability, and high reliability, and meets the comprehensive requirements of energy efficiency, safety, and real-time performance under varying operating conditions.

[0100] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 5 The control method for the heterogeneous multi-core chip is applied to multiple sub-cores in the first core, and the method includes step S101:

[0101] Step S101: Upon receiving the second power-on control command sent by the main core of the first core, trigger the interrupt service routine according to the second power-on control command and execute the startup program.

[0102] It is understood that an interrupt service routine refers to a pre-written piece of code used to handle interrupt events, and in this embodiment, cores 1, 2 and 3 of the M core are the execution entities.

[0103] In practice, the main core sends a specific formatted interrupt signal to the core to be started, triggering its internal interrupt service routine, thereby achieving non-active wake-up and code execution startup.

[0104] In one feasible implementation, step S101 may include steps A1011 to A1013:

[0105] Step A1011: Upon receiving the second hibernation control command sent by the main core of the first core, save the target task state;

[0106] It is understandable that the target task status refers to the task currently being executed by cores 1, 2, and 3 of core M.

[0107] In practice, when cores 1, 2, and 3 of the M core receive a hibernation command, they save the currently executing tasks.

[0108] Step A1012: When the target task status is detected to be saved, the target processing mechanism is closed;

[0109] It is understandable that the target processing mechanism refers to the interrupt and event handling mechanism.

[0110] In practice, when it is detected that the tasks currently being executed by cores 1, 2 and 3 of core M have all been saved and completed, the local interrupt and event handling mechanisms are turned off.

[0111] Step A1013: When the target processing mechanism is detected to be shut down, execute the hibernation procedure and send back status confirmation information to the main core of the first core.

[0112] Understandably, upon detecting that the interrupt and event handling mechanism has finished shutting down, the processor's operating frequency is gradually reduced until it stops, and information indicating that it has successfully entered the safe shutdown state is fed back to core 0 of the M core.

[0113] This embodiment triggers an interrupt service routine and executes the startup program upon receiving a second power-on control command from the main core of the first core. This parallel startup mechanism enables synchronous and rapid startup of the A core and M core, significantly shortening system startup time and improving system response speed.

[0114] Based on the first embodiment of this application, in the third embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 6 The control method for the heterogeneous multi-core chip is applied to the second core, and the method includes step S201:

[0115] Step S201: Upon receiving the first hibernation control command sent by the main core of the first core, hibernation confirmation information is fed back to the main core of the first core, and the hibernation program is executed when the key data is detected to be saved.

[0116] It is understood that the key data refers to the key operational data in core A, and this embodiment takes core A as the execution subject.

[0117] In practice, upon receiving a shutdown command from the main core, core A immediately sends an acknowledgment message to the main core, indicating that the shutdown command has been received, and begins to shut down all running applications and processes. During this process, core A ensures that all critical data is properly saved so that it can be restored to a correct state upon subsequent wake-up.

[0118] This embodiment improves system reliability and ensures the continuity of critical tasks and the integrity of data by sending hibernation confirmation information to the main core of the first core upon receiving the first power-on control command, and executing the hibernation procedure when it detects that critical data has been saved.

[0119] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the control method of heterogeneous multi-core chips in this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0120] This application also provides a control device for a heterogeneous multi-core chip; please refer to [reference needed]. Figure 7 The control device for the heterogeneous multi-core chip is applied to the main core of the first core, and the device includes:

[0121] Processing module 10 is used to start the operating system and send a first power-on control command to the second core in the heterogeneous multi-core chip when an external wake-up request is received, so that the second core executes the startup program according to the first power-on control command;

[0122] The control module 20 is used to generate a second power-on control instruction according to a parallel startup strategy when the first power-on control instruction is sent to the second core, and to send the second power-on control instruction to multiple sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes a startup program according to the second power-on control instruction.

[0123] Optionally, the processing module 10 is further configured to:

[0124] Upon receiving an external wake-up request, obtain the system initialization status;

[0125] When the system initialization state is complete and the control permission is received from the third core of the heterogeneous multi-core chip, a first power-on control command is sent to the second core of the heterogeneous multi-core chip. The control permission is transmitted by the third core after it has completed loading the user firmware through the target firmware when it obtains the system integrity confirmation result by executing the target firmware.

[0126] Optionally, the processing module 10 is further configured to:

[0127] When no target wake-up source is available, a first hibernation control command is sent to the second core in the heterogeneous multi-core chip according to the inter-core communication mechanism, so that the second core executes the hibernation program according to the first hibernation control command and feeds back hibernation confirmation information.

[0128] When the hibernation confirmation information is received from the second core and the preset hibernation duration is reached, the second hibernation control command is sent to multiple sub-cores in the second core of the heterogeneous multi-core chip, so that each sub-core executes the hibernation program according to the second hibernation control command and feeds back the status confirmation information.

[0129] Upon receiving the status confirmation information from each sub-core, the target hibernation procedure is executed.

[0130] Optionally, the processing module 10 is further configured to:

[0131] Upon receiving the status confirmation information from each sub-core, shut down the target system service;

[0132] When the target system service is detected to have finished shutting down, the core state information is saved to the target storage location;

[0133] When the core state information is detected to be saved, the target hibernation procedure is executed.

[0134] This application also provides a control device for a heterogeneous multi-core chip, wherein the control device is applied to multiple sub-cores in a first core, and the device includes:

[0135] The startup module 101 is used to trigger an interrupt service routine and execute a startup program according to the second power-on control instruction sent by the main core of the first core when it receives the second power-on control instruction.

[0136] Optionally, the startup module 10 is further configured to:

[0137] When the target task status is detected to be saved, the target processing mechanism is closed;

[0138] When the target processing mechanism is detected to have finished shutting down, a hibernation procedure is executed and a status confirmation message is sent back to the main core of the first core.

[0139] This application also provides a control device for a heterogeneous multi-core chip, wherein the control device is applied to a second core, and the device includes:

[0140] The hibernation module 102 is used to send hibernation confirmation information to the main core of the first core when it receives the first hibernation control command sent by the main core of the first core, and to execute the hibernation program when it detects that the key data has been saved.

[0141] The heterogeneous multi-core chip control device provided in this application, employing the heterogeneous multi-core chip control method described in the above embodiments, can solve the technical problem that existing power-on / off control strategies often fail to meet the comprehensive requirements of heterogeneous multi-core chip systems for energy efficiency, safety, and real-time performance under varying operating conditions. Compared with the prior art, the beneficial effects of the heterogeneous multi-core chip control device provided in this application are the same as those of the heterogeneous multi-core chip control method provided in the above embodiments, and other technical features in the heterogeneous multi-core chip control device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0142] This application provides a control device for a heterogeneous multi-core chip. The control device for a heterogeneous multi-core chip includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the control method for the heterogeneous multi-core chip in the first embodiment described above.

[0143] The following is for reference. Figure 8 This document illustrates a schematic diagram of a control device suitable for implementing heterogeneous multi-core chips in the embodiments of this application. The control device for heterogeneous multi-core chips in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 8 The control device for the heterogeneous multi-core chip shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0144] like Figure 8As shown, the control device for a heterogeneous multi-core chip may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the control device for the heterogeneous multi-core chip. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the control device of the heterogeneous multi-core chip to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows a control device of a heterogeneous multi-core chip with various systems, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented or possessed alternatively.

[0145] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0146] The heterogeneous multi-core chip control device provided in this application, employing the heterogeneous multi-core chip control method described in the above embodiments, can solve the technical problem that existing power-on / off control strategies often fail to meet the comprehensive requirements of heterogeneous multi-core chip systems for energy efficiency, safety, and real-time performance under varying operating conditions. Compared with the prior art, the beneficial effects of the heterogeneous multi-core chip control device provided in this application are the same as those of the heterogeneous multi-core chip control method provided in the above embodiments, and other technical features in this heterogeneous multi-core chip control device are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0147] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0148] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0149] In addition, to achieve the above objectives, the present invention also proposes a control system for a heterogeneous multi-core chip, wherein the control system for the heterogeneous multi-core chip includes the main core of the first core, a plurality of sub-cores in the first core, and a second core as described above.

[0150] Since the control system of this heterogeneous multi-core chip adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.

[0151] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the control method for heterogeneous multi-core chips in the above embodiments.

[0152] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0153] The aforementioned computer-readable storage medium may be included in a control device with a heterogeneous multi-core chip; or it may exist independently and not be assembled into a control device with a heterogeneous multi-core chip.

[0154] The aforementioned computer-readable storage medium carries one or more programs. When the one or more programs are executed by the control device of the heterogeneous multi-core chip, the control device of the heterogeneous multi-core chip: upon receiving an external wake-up request, sends a first power-on control instruction to the second core in the heterogeneous multi-core chip, so that the second core executes a startup program according to the first power-on control instruction; when the first power-on control instruction is sent to the second core, it generates a second power-on control instruction according to a parallel startup strategy, and sends the second power-on control instruction to multiple sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes a startup program according to the second power-on control instruction.

[0155] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0156] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0157] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0158] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the control method for heterogeneous multi-core chips described above. This solves the technical problem that existing power-on / off control strategies often fail to meet the comprehensive requirements of heterogeneous multi-core chip systems for energy efficiency, safety, and real-time performance under varying operating conditions. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the control method for heterogeneous multi-core chips provided in the above embodiments, and will not be elaborated upon here.

[0159] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the control method for heterogeneous multi-core chips as described above.

[0160] The computer program product provided in this application can solve the technical problem that existing power-on / off control strategies often cannot meet the comprehensive requirements of energy efficiency, safety, and real-time performance of heterogeneous multi-core chip systems under varying operating conditions. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the heterogeneous multi-core chip control method provided in the above embodiments, and will not be repeated here.

[0161] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A control method for a heterogeneous multi-core chip, characterized in that, The control method for the heterogeneous multi-core chip is applied to the main core of the first core, and the method includes: Upon receiving an external wake-up request, a first power-on control command is sent to the second core in the heterogeneous multi-core chip, so that the second core executes the startup program according to the first power-on control command. When the first power-on control command is sent to the second core, a second power-on control command is generated according to the parallel startup strategy, and the second power-on control command is sent to multiple sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes the startup program according to the second power-on control command.

2. The method as described in claim 1, characterized in that, The step of sending a first power-on control command to the second core of the heterogeneous multi-core chip upon receiving an external wake-up request includes: Upon receiving an external wake-up request, obtain the system initialization status; When the system initialization state is complete and the control permission is received from the third core of the heterogeneous multi-core chip, a first power-on control command is sent to the second core of the heterogeneous multi-core chip. The control permission is transmitted by the third core after it has completed loading the user firmware through the target firmware when it obtains the system integrity confirmation result by executing the target firmware.

3. The method as described in claim 1, characterized in that, The control method for the heterogeneous multi-core chip further includes: When no target wake-up source is available, a first hibernation control command is sent to the second core in the heterogeneous multi-core chip according to the inter-core communication mechanism, so that the second core executes the hibernation program according to the first hibernation control command and feeds back hibernation confirmation information. When the hibernation confirmation information is received from the second core and the preset hibernation duration is reached, the second hibernation control command is sent to multiple sub-cores in the second core of the heterogeneous multi-core chip, so that each sub-core executes the hibernation program according to the second hibernation control command and feeds back the status confirmation information. Upon receiving the status confirmation information from each sub-core, the target hibernation procedure is executed.

4. The method as described in claim 3, characterized in that, The method further includes: Upon receiving the status confirmation information from each sub-core, shut down the target system service; When the target system service is detected to have finished shutting down, the core state information is saved to the target storage location; When the core state information is detected to be saved, the target hibernation procedure is executed.

5. A control method for a heterogeneous multi-core chip, characterized in that, The control method for the heterogeneous multi-core chip is applied to multiple sub-cores in the first core, and the control method for the heterogeneous multi-core chip includes: Upon receiving the second power-on control instruction sent by the main core of the first core, the interrupt service routine is triggered according to the second power-on control instruction, and the startup program is executed. The second power-on control instruction is generated and sent by the main core of the first core according to the parallel startup strategy when the main core of the first core sends the first power-on control instruction to the second core. The first power-on control instruction is sent by the main core of the first core when it receives an external wake-up request.

6. The method as described in claim 5, characterized in that, The method further includes: Upon receiving the second hibernation control command from the main core of the first core, the target task state is saved; When the target task status is detected to be saved, the target processing mechanism is closed; When the target processing mechanism is detected to have finished shutting down, a hibernation procedure is executed and a status confirmation message is sent back to the main core of the first core.

7. A control method for a heterogeneous multi-core chip, characterized in that, The control method for the heterogeneous multi-core chip is applied to the second core, and the control method for the heterogeneous multi-core chip includes: Upon receiving the first power-on control command sent by the main core of the first core, the startup program is executed according to the first power-on control command; When the first power-on control command is sent to the second core, the main core of the first core generates a second power-on control command according to the parallel startup strategy, and sends the second power-on control command to multiple sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes the startup program according to the second power-on control command; Upon receiving the first hibernation control command sent by the main core of the first core, hibernation confirmation information is fed back to the main core of the first core, and the hibernation program is executed when the key data is detected to be saved. The first hibernation control command is sent by the main core of the first core according to the inter-core communication mechanism when there is no target wake-up source.

8. A control device for a heterogeneous multi-core chip, characterized in that, The device includes: The processing module is used to start the operating system and send a first power-on control command to the second core in the heterogeneous multi-core chip when an external wake-up request is received, so that the second core executes the startup program according to the first power-on control command; The control module is used to generate a second power-on control instruction according to a parallel startup strategy when the first power-on control instruction is sent to the second core, and to send the second power-on control instruction to multiple sub-cores in the first core of the heterogeneous multi-core chip, so that each sub-core executes the startup program according to the second power-on control instruction.

9. A control device for a heterogeneous multi-core chip, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the control method for a heterogeneous multi-core chip applied to a main core of a first core as described in any one of claims 1 to 4, or the control method for a heterogeneous multi-core chip applied to multiple sub-cores in a first core as described in claims 5 or 6, or the control method for a heterogeneous multi-core chip as described in claim 7.

10. A control system for a heterogeneous multi-core chip, characterized in that, The control system of the heterogeneous multi-core chip includes a main core of a first core as described in any one of claims 1 to 4, a plurality of sub-cores in the first core as described in any one of claims 5 to 6, and a second core as described in claim 7.

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