RISC-V vector store hardware resource release method and device

Abstract

The invention relates to the technical field of computers, and particularly discloses an RISC-V vector store hardware resource release method and device, and the method comprises the steps: responding to a vector store instruction, carrying out the decoding according to the vector store instruction and the store operation number to generate a plurality of vector STA and STD microinstruction pairs, and distributing a hardware resource item for each vector STA and STD microinstruction pair; and the vector storage decommissioning items in the vector storage decommissioning table are used as granularity decommissioning hardware resource items by assisting the reordering cache through a preset vector storage decommissioning table, so that hardware resources corresponding to the hardware resource items are released. Therefore, hardware resources required by the SB item do not need to be greatly increased, and the purpose of releasing the SB item as soon as possible is achieved by retraining the SB item as soon as possible.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method and device for releasing RISC-V vector store hardware resources. Background Art

[0002] The store instruction in an instruction set is used to write data to the memory. Its implementation in a high-performance, out-of-order CPU core is different from other instructions: other non-store instructions can be executed out of order (that is, when there are older instructions that have not been executed) and in a speculative state (the instruction may be on the wrong branch path), and the results are written to the physical register; if the speculation is wrong, the content of the physical register file can be restored to the correct state and then executed from the correct branch path. However, once the store instruction writes data to the memory / cache, it is difficult / impossible to restore it. Therefore, a store instruction will only write its data to the memory / cache after it is retired, that is, after entering the architectural state. There may be multiple clock cycles between the execution of the store instruction and its writing of data into the memory. During this period, the memory address and write data of the store are generally stored in a hardware resource store buffer (SB). In order to ensure program correctness, store writes to memory must strictly follow the program order, so the store buffer is generally a First In First Out (FIFO) circular buffer. Since the allocation and release of Store buffer items are sequential, their allocation must be in the front-end sequential stage of the CPU core pipeline, such as the dispatch pipeline stage.

[0003] A store operation consists of two independent sub-operations: 1) STA: calculate the write memory address; 2) STD: read the data written to the memory from the register. In a high-performance, out-of-order CPU core, these two operations are usually decomposed into two independent microinstructions for execution. Since the level 1 data cache (L1D) is shared by SB and other pipelines (such as load and L2 cache read and write, etc.), it needs to compete for it. Therefore, there is often a gap of several clock cycles from the SB item being allowed to be written to L1D (i.e., retiring the SB item) to its actual writing to L1D and releasing the SB item. The SB write operation to L1D is handled by the SB internal logic circuit. Most RISC-V vector instructions can support masked computing, that is, the instruction only writes the masked (i.e., the corresponding mask bit is 1) field in the target register, and the value of the maskoff (i.e., the corresponding mask bit is 0) field does not change. For these instructions, the vm bit in the opcode indicates whether mask calculation is performed: vm = 1: no mask calculation, all field calculation results will be written to the register. vm = 0: mask calculation, the mask value comes from the architectural register v0. At this time, each bit in v0 starting from the low bit identifies a field. When v0[i] is 1, the calculation result can be written to the corresponding field, otherwise it is not written.

[0004] In the case of mask (vm = 0), the mask value of a pair of STA and STD microinstructions in a vector store instruction is obtained in the execution stage. If mask off (v0[i] = 0), both microinstructions are converted to NOPs and their data will not be written to the memory. Since the allocation of SB items for store operations is performed at an earlier Dispatch pipeline stage, the value in the Mask register is not known at this time, so an SB item needs to be allocated for each store operation, even though the mask off store operation does not use its allocated SB item.

[0005] In a high-performance, out-of-order CPU core, although instruction execution is out-of-order, instruction retirement is sequential, which can ensure the correctness of program execution. Instruction sequential retirement is implemented through the reorder buffer (ROB). ROB is a first-in-first-out (FIFO) circular buffer. An instruction is assigned a ROB item at the end of the valid ROB item (ROB tail) in the sequential dispatch pipeline stage, and retirement always starts from the actual position of the ROB valid item (ROB head). Inside the RISC-V CPU, instructions are often decoded into one or more micro-ops or macro-ops. Correspondingly, each ROB item can choose to store instructions, micro-ops, or macro-ops. In order to improve the efficiency of ROB, most ROB architectures adopt the method of one instruction per item.

[0006] The solution is to simply expand the existing scalar ROB and SB to support RISC-V vector store instructions. SB allocation, retire, and release are still performed at the instruction granularity. However, this solution will face the following problems when extended to RISC-V vector instructions:

[0007] SB item allocation problem: In CPU architectures that only support scalar instructions, SBs often do not need too many items, and generally 16-48 items are sufficient. However, as mentioned earlier, when VLEN = 128b, a vector store instruction may require up to 128 SB items (and more SB items when VLEN is larger), otherwise the instruction cannot be dispatched. Increasing the number of SB items to meet the maximum demand of a single vector instruction will cause the SB to be too large, resulting in a waste of hardware resources and longer access delays to the SB, ultimately causing a decrease in the overall CPU performance and an increase in area and power consumption.

[0008] SB item retirement and release issues: Since a vector store instruction requires multiple SB items, if these SB items cannot be released until the instruction retires, the instruction will occupy multiple SB items for too long. In addition, a vector store instruction requires multiple SB items, which will cause the CPU front-end pipeline to stall due to SB item shortage, thereby causing CPU performance to degrade.

[0009] The store operation with Mask off still occupies the SB item, and the SB item is released only when the above store instruction retires, further causing a waste of SB resources.

[0010] To address the above problems, no effective solution has been proposed yet. Summary of the invention

[0011] The embodiments of this specification provide a RISC-V vector store hardware resource release method and device, an optimized SB allocation / retire scheme to better support RISC-V vector store instructions, and a special optimization for early retirement of SB items for mask off store operations, so as to achieve the same performance as the simple expansion scheme using fewer hardware resources and fewer SB items.

[0012] The embodiment of this specification provides a RISC-V vector store hardware resource release method, including:

[0013] In response to a vector store instruction, a plurality of vector STA and STD microinstruction pairs are generated by decoding according to the number of store operations, and a hardware resource item is allocated to each vector STA and STD microinstruction pair; a preset vector storage retirement table is used to assist the reorder cache in retiring the hardware resource items with the vector storage retirement items in the vector storage retirement table as the granularity, so as to release the hardware resources corresponding to the hardware resource items; wherein, the number of continuous unmasked store operation items stored in the vector storage retirement item is used to retire the hardware resource items corresponding to the vector storage retirement item, so as to retire the hardware resource items of all unmasked store operations of the vector store instruction after the vector storage retirement item.

[0014] In one embodiment, decoding and generating a plurality of STA and STD microinstruction pairs according to the number of store operations according to the vector store instruction includes:

[0015] An IS_LAST field is added to the vector STA microinstruction generated by the vector store instruction, and the last bit information of the vector STA microinstruction in the vector store instruction is defined by the value of the IS_LAST field.

[0016] In one embodiment, the method further comprises:

[0017] A vector store retirement item identification field, a vector STA microinstruction quantity field and a vector STD microinstruction quantity field are set in the reorder cache item; wherein the vector store retirement item identification field is used to configure different values ​​according to the vector store instruction or the non-vector store instruction; the vector STA microinstruction quantity field and the vector STD microinstruction quantity field are respectively used to record the number of vector STA microinstructions and the number of vector STD microinstructions generated by the vector store instruction, and adjust the corresponding recorded number of vector STA microinstructions and the number of vector STD microinstructions according to the execution status of the vector STA microinstructions and the vector STD microinstructions.

[0018] In one embodiment, the method further comprises:

[0019] When the source physical register value of the vector STA microinstruction exists and there is an idle vector storage retirement item, the vector storage retirement table sequentially allocates an idle vector storage retirement item to the vector STA microinstruction; releases the corresponding vector storage retirement item when retiring the vector STA microinstruction without masked store operation; releases the corresponding vector storage retirement item when the vector STA microinstruction executing the masked store operation is completed; wherein, the vector storage retirement item includes a vector storage retirement index field, a vector store instruction index field corresponding to the reorder cache, a store operation index field in the vector store instruction, an index field of a hardware resource item corresponding to the store operation, a store operation exception record identification field, and a masked store operation number field before the store operation.

[0020] In one embodiment, the vector storage retirement table sequentially allocates an idle vector storage retirement item to the vector STA microinstruction, including: when creating or writing a vector storage retirement item, the number of unmasked store operation items between the corresponding valid store operation and the adjacent previous valid store operation is written into the pre-store operation masked store operation number field of the vector storage retirement item; when releasing or reading a vector storage retirement item, and determining that the adjacent next item has valid data through the pre-store operation masked store operation number field, the pre-store operation masked store operation number field of the adjacent next item is read, so as to retire the hardware resource items corresponding to the vector storage retirement item, and retire all the hardware resource items of the unmasked store operations of the vector store instruction after the vector storage retirement item.

[0021] In one embodiment, the vector storage retirement table sequentially allocates an idle vector storage retirement item to the vector STA microinstruction, including: when the vector storage retirement item flag is abnormal, providing the corresponding field in the store operation index field in the vector store instruction of the vector storage retirement item and the exception type in the store operation exception record identification field to the reorder cache for exception handling.

[0022] In one embodiment, retiring the hardware resource items by using a preset vector storage retirement table to assist the reorder cache with the vector storage retirement items in the vector storage retirement table as the granularity includes: sequentially releasing the hardware resource items starting from the item pointed to by the preset vector storage pointer head in each clock cycle; sequentially allocating the hardware resource items starting from the item pointed to by the preset vector storage pointer tail in each clock cycle; wherein the vector storage pointer head points to the longest valid item in the vector storage retirement table, and the vector storage pointer tail points to the first invalid item in the vector storage retirement table.

[0023] In one embodiment, retiring the hardware resource items at the granularity of vector storage retirement items in the vector storage retirement table by assisting the reorder cache through a preset vector storage retirement table includes: when the vector storage retirement items corresponding to all vector STA microinstructions of the vector store instruction are released, the vector storage retirement table provides a notification signal to the reorder cache; when all vector STD microinstructions of the vector store instruction are executed, the reorder cache releases the reorder cache items corresponding to the vector store instruction according to the notification signal.

[0024] An embodiment of the present specification also provides a RISC-V vector store hardware resource release device, the device comprising: an allocation module and a release module; the allocation module is used to respond to a vector store instruction, decode and generate multiple vector STA and STD microinstruction pairs according to the number of store operations, and allocate a hardware resource item to each vector STA and STD microinstruction pair; the release module is used to assist the reordering cache through a preset vector storage retirement table to retire the hardware resource items with the vector storage retirement items in the vector storage retirement table as the granularity, so as to release the hardware resources corresponding to the hardware resource items; wherein, the number of consecutive unmasked store operation items stored in the vector storage retirement item is used to retire the hardware resource items of all unmasked store operations of the vector store instruction after the vector storage retirement item when retiring the hardware resource item corresponding to the vector storage retirement item.

[0025] An embodiment of the present specification also provides a central processing unit, which includes a central processing core with a reordering cache based on instructions, microinstructions and macroinstructions, and the central processing unit applies the above-mentioned RISC-V vector store hardware resource release method.

[0026] For a RISC-V CPU core that implements RISC-V vector extension, the RISC-V vector store hardware resource release method and device provided in the embodiments of this specification provide an optimization solution for extending ROB and SB to support RISC-V vector store instructions. Compared with the traditional solution, this application does not need to significantly increase the hardware resources required for the SB item, and achieves the purpose of releasing the SB item as soon as possible by retiring the SB item as soon as possible. At the same time, this application can also release the SB item corresponding to the mask off store operation as soon as possible, thereby further improving the SB utilization efficiency.

[0027] With reference to the following description and drawings, specific embodiments of the present invention are disclosed in detail, indicating the manner in which the principles of the present invention can be adopted. It should be understood that the embodiments of the present invention are not limited in scope. Features described and / or shown for one embodiment can be used in one or more other embodiments in the same or similar manner, combined with features in other embodiments, or replace features in other embodiments.

[0028] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, parts, steps or components, but does not exclude the presence or addition of one or more other features, parts, steps or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of this specification, constitute a part of this specification, and do not constitute a limitation of this specification. In the drawings:

[0030] Figure 1 A flowchart of a RISC-V vector store hardware resource release method provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of the application effect of the RISC-V vector store hardware resource release method provided in one embodiment of the present application;

[0032] Figure 3 A schematic diagram of the application effect of a RISC-V vector store hardware resource release method provided in another embodiment of the present application;

[0033] Figure 4 It is an example diagram of multiple pipeline stages of a CPU architecture in the prior art;

[0034] Figure 5 A flowchart of the execution phase provided by another embodiment of the present application;

[0035] Figure 6 A schematic diagram of a release process provided in another embodiment of the present application;

[0036] Figure 7 A schematic diagram of the structure of a RISC-V vector store hardware resource release device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0037] The principles and spirit of this specification will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement this specification, and are not intended to limit the scope of this specification in any way. On the contrary, these embodiments are provided to make this specification more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0038] Those skilled in the art will appreciate that the embodiments of this specification may be implemented as a system, device, method, or computer program product. Therefore, this specification may be implemented in the following forms: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0039] The details of the present invention can be more clearly understood by combining the accompanying drawings and the description of the specific embodiments of the present invention. However, the specific embodiments of the present invention described herein are only used for the purpose of explaining the present invention and cannot be understood as limiting the present invention in any way. Under the guidance of the present invention, technicians can conceive of any possible variations based on the present invention, which should be regarded as belonging to the scope of the present invention. It should be noted that when an element is referred to as "arranged on" another element, it can be directly on another element or there can also be a central element. When an element is considered to be "connected" to another element, it can be directly connected to another element or there may be a central element at the same time. The terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection, or it can be the communication between the two elements, it can be directly connected, or it can be indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are only for illustrative purposes and do not represent the only implementation method.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this specification belongs. The terms used herein in this specification are only for the purpose of describing specific embodiments and are not intended to limit this specification. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0041] The embodiments of this specification provide a RISC-V vector store hardware resource release method. Figure 1 A flowchart of a RISC-V vector store hardware resource release method in an embodiment of this specification is shown. Although this specification provides method operation steps or device structures as shown in the following embodiments or drawings, more or fewer operation steps or module units may be included in the method or device based on routine or no creative labor. In the steps or structures where there is no necessary causal relationship logically, the execution order of these steps or the module structure of the device is not limited to the execution order or module structure described in the embodiments of this specification and shown in the drawings. When the method or module structure is applied in an actual device or terminal product, it can be connected according to the method or module structure shown in the embodiment or drawings for sequential execution or parallel execution (for example, a parallel processor or a multi-threaded processing environment, or even a distributed processing environment).

[0042] Please refer to Figure 1 As shown, the RISC-V vector store hardware resource release method provided in the embodiments of this specification may specifically include:

[0043] S101 responds to the vector store instruction, decodes and generates a plurality of vector STA and STD microinstruction pairs according to the number of store operations, and allocates a hardware resource item to each vector STA and STD microinstruction pair;

[0044] S102 assists the reorder cache to retire the hardware resource item by using a preset vector storage retirement table with the vector storage retirement item in the vector storage retirement table as the granularity, so as to release the hardware resource corresponding to the hardware resource item;

[0045] Among them, the number of continuous unmasked store operation items stored in the vector storage retirement item is used to retire the hardware resource items of all unmasked store operations of the vector store instructions after the vector storage retirement item when retiring the hardware resource item corresponding to the vector storage retirement item.

[0046] In this embodiment, the RISC-V vector store instruction is divided into multiple STA / STD microinstruction pairs according to the number of store operations, and each pair of STA / STD (regardless of whether mask off) microinstructions corresponds to one SB item. This avoids the problem of vector store instructions applying for too many SB items at a time and blocking the CPU pipeline. The added hardware table: vector store retire buffer (VSRB) is used to assist the ROB in retiring SB items with VSRB items as the granularity. The number of consecutive mask off store operation items is saved in the subsequent VSRB items. Through the optimization of writing the same NOP_CNT in VSRB but reading the NOP_CNT of the next item, when retiring the SB item corresponding to a VSRB item, all subsequent mask offstore corresponding SB items are also retired, thereby further improving the utilization efficiency of the SB items. In this way, the same performance as the simple expansion solution is achieved by using fewer hardware resources and fewer SB items.

[0047] It should be noted that in many CPU cores, ROB does not store instructions, but microinstructions (microuop) or macroinstructions (macro op), which are specific conversion formats of instructions in a CPU core: an instruction may be converted into one or more microinstructions / macros, or two instructions may be merged into one microinstruction / macroinstruction, etc. ROBs based on instructions / microinstructions / macroinstructions are designed for scalar instructions and face the same problems for vector instructions. Therefore, this application is also applicable to CPU cores using ROBs based on microinstructions / macroinstructions. A store operation consists of two independent sub-operations: 1) STA: calculate the write memory address; 2) STD: read the data written to the memory from the register. In a high-performance, out-of-order CPU core, these two operations are usually decomposed into two independent microinstructions for execution; the CPU core of the present application can use this method, and is also applicable to other methods, such as the same store microinstruction is executed in two pipelines for address generation and register reading; further, many high-performance, superscalar CPU cores can rename, execute, and retire multiple instructions in one clock cycle; the present application is also applicable to superscalar CPU cores; the present application is not further limited here.

[0048] In one embodiment of the present application, decoding the vector store instruction according to the number of store operations to generate multiple STA and STD microinstruction pairs includes: adding an IS_LAST field to the vector STA microinstruction generated by the vector store instruction, and defining the last bit information of the vector STA microinstruction in the vector store instruction through the value of the IS_LAST field.

[0049] In this embodiment, an IS_LAST field is added to the vector STA microinstruction (uop) item. If the field is 1, it indicates that the STA uop is the last STA uop of the corresponding vector store instruction. This action is mainly applied to the Decode link of the pipeline stage. A vector store instruction will be decoded into at least one pair of STA / STD microinstructions. Each pair of microinstructions corresponds to a store operation and an SB item. The SB item required for a vector store instruction depends on parameters such as VLEN, current LMUL and SEW. For segment store instructions, the NFIELD parameter must also be considered, and the IS_LAST bit is set for the generated vector STA uop: the IS_LAST of the last uop is set to 1, and the IS_LAST of the remaining uops is set to 0.

[0050] In one embodiment of the present application, the method further includes: setting a vector storage retirement item identification field, a vector STA microinstruction number field and a vector STD microinstruction number field in the reorder cache item; wherein the vector storage retirement item identification field is used to configure different numerical values ​​according to the vector store instruction or the non-vector store instruction; the vector STA microinstruction number field and the vector STD microinstruction number field are respectively used to record the number of vector STA microinstructions and the number of vector STD microinstructions generated by the vector store instruction, and adjust the corresponding recorded number of vector STA microinstructions and the number of vector STD microinstructions according to the execution status of the vector STA microinstructions and the vector STD microinstructions.

[0051] In the above embodiment, the vector store retirement item identification field is a 1-bit use_VSRB field. If the ROB item is a vector store instruction, this bit is set to 1 when the ROB item is allocated; otherwise, this bit is set to 0. A vector store instruction has at least one VSRB item. The vector STA microinstruction quantity field is the STA_CNTDOWN field. Record the number of STA uops generated by the vector store instruction. This field is set when the ROB item is allocated. After each vector STA uop is executed, regardless of whether it is maskoff, the field will be reduced by one. When the field value is 0, all STA uops of the instruction have been executed. This field is multi-bit and can accommodate the maximum number of vector STA uops implemented by the CPU core. The vector STD microinstruction quantity field is the STD_CNTDOWN field. Record the number of STD uops generated by the vector store instruction. This field is set when the ROB item is allocated. After each vector STD uop is executed, regardless of whether it is masked off, the field will be reduced by one. When the field value is 0, all STD uops of the instruction are executed. This field is multi-bit and can accommodate the maximum number of vector STA uops implemented by the CPU core.

[0052] In one embodiment of the present application, the method further includes: when the source physical register value of the vector STA microinstruction exists and there is an idle vector storage retirement item, the vector storage retirement table sequentially allocates an idle vector storage retirement item to the vector STA microinstruction; when retiring the vector STA microinstruction without a masked store operation, the corresponding vector storage retirement item is released; when the vector STA microinstruction executing the masked store operation is completed, the corresponding vector storage retirement item is released; wherein the vector storage retirement item includes a vector storage retirement index field, a vector store instruction index field corresponding to the reorder cache, a store operation index field in the vector store instruction, an index field of a hardware resource item corresponding to the store operation, a store operation exception record identification field, and a masked store operation number field before the store operation.

[0053] In the above embodiment, VSRB is the same as ROB. VSRB is also a FIFO circular buffer. Each valid (that is, not mask off) vector STA microinstruction occupies one VSRB item. The Issue pipeline stage maintains the number of currently available VSRB items and allocates one VSRB item for each vector STA microinstruction. A non-mask off vector STA microinstruction releases its VSRB item when it retires; and a mask off vector STA microinstruction releases its VSRB item when it is executed.

[0054] The VSRB entry contains the following fields:

[0055] Vector storage retirement index field IDX: VSRB index, used to sequentially allocate and release VSRB items;

[0056] The vector store instruction index field IID corresponding to the reorder buffer: instruction index, corresponding to the IID field in the ROB, used to identify the ROB item / instruction to which the VSRB item belongs;

[0057] Store operation index field SOID in vector store instruction: (store operation ID) The index of the store operation in a vector store instruction;

[0058] The index field SBID of the hardware resource item corresponding to the store operation: (store buffer ID) The index of the SB item corresponding to the store operation;

[0059] Store operation exception record identification field Exception: The initial value is -1. If an exception occurs during address translation of the store operation, the exception type (value >= 0) is written into this field;

[0060] The number of masked store operations before the store operation field NOP_CNT: the number of mask off store operations before the store operation; these mask off store operations may come from different vector store instructions.

[0061] In one embodiment of the present application, retiring the hardware resource items by using a preset vector storage retirement table to assist the reordering cache with the vector storage retirement items in the vector storage retirement table as the granularity includes: releasing the hardware resource items sequentially starting from the item pointed to by the preset vector storage pointer head in each clock cycle; allocating the hardware resource items sequentially starting from the item pointed to by the preset vector storage pointer tail in each clock cycle; wherein the vector storage pointer head points to the longest valid item in the vector storage retirement table, and the vector storage pointer tail points to the first invalid item in the vector storage retirement table.

[0062] In the above embodiment, the present application releases and allocates SB items through two newly added pointers, wherein the vector storage pointer VSRB head points to the oldest valid item in the VSRB, and attempts to release SB items sequentially starting from the item pointed to by the VSRB head in each clock cycle. The vector storage pointer VSRB tail points to the first invalid item in the VSRB, and allocates new SB items sequentially starting from the item pointed to by the VSRB tail in each clock cycle.

[0063] For details, please refer to Figure 2 As shown, Figure 2 That is, ROB+VSRB with added vector instruction support. ROB shows two iterations of a memcpy-like loop code. The instructions in the first iteration are IID=0~6, and the instructions in the second iteration are IID=7~13. The code in the example executes a unit-strideload (IID=1 / 8) to read data from address (a1), and selectively writes the data to the strided store (IID=4 / 11) at address (a3+i*a4) according to the mask value. The figure also shows the mask values ​​(v0.t and v0'.t) used in the two iterations.

[0064] Assume that VLEN=128,IID=0 / 7 set SEW=32,LMUL=1, so the 5th and 12th instructions (IID=4 and 11) in the ROB are vector store instructions, they each have 4 (=128 / 32) store operations, so each instruction is allocated 4 SB items, and STA_CNTDOWN and STD_CNTDOWN in the SB items are both set to 4. But if Figure 2 As shown in the mask value, since each instruction has only two valid (that is, not masked off) vector store operations, each store instruction is only allocated two VSRB items, and the NOP_CNT of each item records the number of mask off store operations before the store operation.

[0065] In one embodiment of the present application, the vector storage retirement table sequentially allocates an idle vector storage retirement item to the vector STA microinstruction, including: when creating or writing a vector storage retirement item, the number of unmasked store operation items between the corresponding valid store operation and the adjacent previous valid store operation is written into the pre-store operation masked store operation number field of the vector storage retirement item; when releasing or reading a vector storage retirement item, and determining that the adjacent next item has valid data through the pre-store operation masked store operation number field, the pre-store operation masked store operation number field of the adjacent next item is read, so as to retire the hardware resource items corresponding to the vector storage retirement item, and retire all the hardware resource items of the unmasked store operations of the vector store instruction after the vector storage retirement item.

[0066] Please refer to Figure 3As shown in the figure, when a vector instruction becomes the oldest unreleased instruction in the ROB (that is, ROBhead points to its ROB item), if its use_VSRB field is 1, it has one or more corresponding VSRB items. At this time, the VSRBhead pointer should point to the first VSRB item of the vector instruction. Starting from the VSRB head item, all consecutive VSRB items of the instruction with Exception being -1 can be released, and the SB items corresponding to the NOP_CNT field in these items and the next item will also be released. After all VSRB items of the instruction are released, the VSRB head will move to the first VSRB item of the next vector instruction.

[0067] If the oldest instruction in the ROB is a vector store instruction, but its STA / STD microinstructions have not been fully executed, the instruction will wait for all of these STA / STD microinstructions to be fully executed (that is, the STA_CNTDOWN and STD_CNTDOWN values ​​of the ROB item are both 0) before retiring. It should be noted that the allocation and release of VSRB items are only related to STA microinstructions, but not STD microinstructions. However, when a retired SB item is to be written to memory, its corresponding data field must be valid, that is, the corresponding STD microinstruction has been executed.

[0068] One purpose of the present application is to release the SB items corresponding to the mask off store operation as soon as possible. To this end, in the above embodiment, the allocation of VSRB items is performed sequentially. When creating / writing a VSRB item, the number of mask off store operations between the corresponding valid store operation and the previous valid store operation is written into the NOP_CNT field of the newly allocated VSRB item. However, when releasing / reading a VSRB item, if the next item has valid data, the NOP_CNT of the next item is read to retire / release more SB items as soon as possible, such as Figure 3 As shown in the figure. A vector store instruction is assigned at least one VSRB entry. If all store operations of the instruction are mask off, then the last store operation is assigned a VSRB entry, and its NOP_CNT is also set to the number of mask off store operations before the entry.

[0069] In one embodiment of the present application, the pre-set vector storage retirement table is used to assist the reorder cache to retire the hardware resource item with the vector storage retirement item in the vector storage retirement table as the granularity, including: when the vector storage retirement items corresponding to all the vector STA microinstructions of the vector store instruction are released, the vector storage retirement table provides a notification signal to the reorder cache; when all the vector STD microinstructions of the vector store instruction are executed, the reorder cache releases the reorder cache item corresponding to the vector store instruction according to the notification signal. In another embodiment, the vector storage retirement table sequentially allocates an idle vector storage retirement item to the vector STA microinstruction, including: when the vector storage retirement item flag is abnormal, the corresponding field in the store operation index field in the vector store instruction of the vector storage retirement item and the exception type in the store operation exception record identification field are provided to the reorder cache for exception handling.

[0070] In the above embodiment, when all VSRB items of a vector store instruction are released, the VSRB notifies the ROB; if all STD microinstructions of the instruction are also executed, the ROB item corresponding to the instruction is released. If a VSRB item flags an exception, the corresponding field of the VSRB item (in the SOID field) and the exception type (in the Exception field) will be passed to the ROB for exception handling.

[0071] Based on the above embodiments, for RISC-V vector store instructions, the RISC-V vector store hardware resource release method provided in the present application optimizes the store buffer item allocation and retire scheme, allocates and retires at the granularity of valid SB items, and can release the SB items occupied by mask off store operations as soon as possible, thereby improving SB utilization efficiency and achieving CPU performance optimization with a smaller number of SB items.

[0072] In order to more clearly illustrate the RISC-V vector store hardware resource release method provided by the present application, the following takes multiple pipeline stages as an example to further illustrate the application of the above embodiment to the RISC-V vector store hardware resource release method. Relevant technicians in the field should know that this example is only an application method to help understand the RISC-V vector store hardware resource release method provided by the present application, and does not limit it in any way.

[0073] Please refer to Figure 4 As shown, the existing CPU architecture generally includes multiple pipeline stages. The RISC-V vector store hardware resource release method provided by this application for the pipeline stage includes the following improvements:

[0074] Instruction decoding Decode: A vector store instruction will be decoded into at least a pair of STA / STD microinstructions, each pair of microinstructions corresponds to a store operation and an SB item. The SB item required for a vector store instruction depends on parameters such as VLEN, current LMUL and SEW, and the NFIELD parameter must also be considered for segment store instructions. And set the IS_LAST bit for the generated vector STA uop: the last uop has its IS_LAST set to 1, and the remaining uops have their IS_LAST set to 0.

[0075] Dispatch: If a microinstruction is a vector STA microinstruction and there are free items in SB, the required SB items are allocated to the microinstruction. If the microinstruction is the first microinstruction of the instruction to which it belongs and there are free items in ROB, the ROB items are allocated to the instruction. If all the above conditions are met, the microinstruction enters the next pipeline stage. Otherwise, the microinstruction congests Dispatch and all front-end pipeline stages, and continues to try to obtain SB and ROB items in the next clock cycle. An STD does not need to allocate SB items, it only needs to use the SB items allocated by its corresponding STA microinstruction.

[0076] Issue: This stage finds the oldest ready uop to execute and saves the number of currently free VSRBs. For vector STA uop, the STA uop is ready and assigned a VSRB entry only when its source physical register value already exists and there is a free VSRB entry.

[0077] Execution: The vector STA microinstruction must be executed in program order. In the STA execution unit, there is a register ST_NOP_CNT that stores the number of mask off store operations that have not been written to VSRB. A vector store instruction has at least one VSRB item. If all its store operations are mask off, its last STA microinstruction will use its VSRB item. Other mask off vector STA microinstructions will release their VSTA items (that is, update the number of free VSRB items in the Issue stage).

[0078] For details, please refer to Figure 5 As shown, the main process of this execution phase is as follows:

[0079] 1. First determine whether a vector STA uop is masked off. If so, execute the next step; otherwise, jump to step 3.

[0080] 2. If the IS_LAST of the STA uop is 1 and the corresponding ROB item use_VSRB field is 0, that is, all uops of the vector store instruction are masked off, then jump to step 6; otherwise, ST_NOP_CNT increases by 1, and releases the VSRB item, ending.

[0081] 3. Write the address to the SB item allocated for this uop in the Dispatch stage.

[0082] 4. If VSRB is empty (VSRB head == VSRB tail), execute the next step; otherwise, jump to step 6.

[0083] 5. If ST_NOP_CNT is not equal to 0, notify the SB to retire consecutive ST_NOP_CNT items, and then set the ST_NOP_CNT items to 0.

[0084] 6. Write the ST_NOP_CNT value to the NOP_CNT field of the VSRB item, and then set the ST_NOP_CNT item to 0. Set the use_VSRB field of the corresponding ROB item to 1.

[0085] 7. End execution.

[0086] Retire: The following process is used to release the ROB header item, release the corresponding VSRB item, and mark multiple SB items as retire.

[0087] For details, please refer to Figure 6 As shown in the figure, the main process of the decommissioning stage is as follows:

[0088] 1. First check the Use_VSRB value in the ROB head item. If it is 1, that means there is at least one VSRB item in the item, jump to step 4; otherwise, execute the next step.

[0089] 2. Check whether the instruction without VSRB item is abnormal. If it is abnormal, the exception handling is triggered and the process ends; otherwise, go to the next step.

[0090] 3. Determine whether the instruction has been executed. If it has been executed, jump to step 11; otherwise, the instruction has not been executed and cannot be retired, so the process ends.

[0091] 4. Read the VSRB head item.

[0092] 5. If the item is valid (SBID is not -1) and has the same IID as the ROB item, proceed to the next step; otherwise, jump to step 11.

[0093] 6. If the Exception item is not zero, it indicates that the corresponding vector uop execution exception occurs, and execute the next step; otherwise, jump to step 8.

[0094] 7. Send the exception index to ROB. After receiving it, ROB saves the exception index in vstart CSR, then triggers exception processing and ends.

[0095] 8. Release the VSRB head item, set the SBID of the item to -1, and notify the Issue stage of the release of the VSRB item; then, move the VSRB head pointer to the next item (VSRB_head+1)%VSRB_size.

[0096] 9. If the new VSRB head entry is valid (SBID is not equal to -1), set CNT=1+the NOP_CNT value of the entry; otherwise, set CNT to 1.

[0097] 10. Release the consecutive CNT items Store buffer items and jump to step 4.

[0098] 11. Determine whether the STA and STD microinstructions in the ROB head item have been executed (STA_CNTDOWN is 0 and STD_CNTDOWN is 0). If yes, execute the next step, otherwise the instruction has not been completed and cannot be retired.

[0099] 12. At this time, the instruction corresponding to the ROB head item has been executed without exception and can be retired, so all other hardware resources corresponding to the instruction are released.

[0100] 13. Release the ROB head item, that is, move the ROB head pointer to the next position (ROB_head+1)%ROB_size, and end.

[0101] Please refer to Figure 7As shown, the embodiment of this specification also provides a RISC-V vector store hardware resource release device, the device includes an allocation module 701 and a release module 702; the allocation module 701 is used to respond to the vector store instruction, decode and generate multiple vector STA and STD microinstruction pairs according to the number of store operations, and allocate a hardware resource item to each vector STA and STD microinstruction pair; the release module 702 is used to assist the reorder cache through the preset vector storage retirement table to retire the hardware resource item with the vector storage retirement item in the vector storage retirement table as the granularity to release the hardware resource corresponding to the hardware resource item; wherein, the number of continuous unmasked store operation items stored in the vector storage retirement item is used to retire the hardware resource items of all unmasked store operations of the vector store instruction after the vector storage retirement item when retiring the hardware resource item corresponding to the vector storage retirement item. Since the principle of solving the problem by the device is similar to the RISC-V vector store hardware resource release method, the implementation of the device can refer to the implementation of the RISC-V vector store hardware resource release method, and the repeated parts will not be repeated.

[0102] An embodiment of the present specification also provides a central processing unit, which includes a central processing core with a reordering cache based on instructions, microinstructions and macroinstructions, and the central processing unit applies the above-mentioned RISC-V vector store hardware resource release method.

[0103] In the above embodiments, because many CPU cores do not store instructions in the ROB, but store microinstructions (microuop) or macroinstructions (macro op), which are specific conversion formats of instructions in a CPU core: an instruction may be converted into one or more microinstructions / macroinstructions, or two instructions may be merged into one microinstruction / macroinstruction, etc. ROBs based on instructions / microinstructions / macroinstructions are designed for scalar instructions, and face the same problems for vector instructions. Therefore, the present application is also applicable to CPU cores using ROBs based on microinstructions / macroinstructions. Similarly, the present application is also applicable to high-performance, superscalar CPU cores that can rename, execute, and retire multiple instructions in one clock cycle. It should be noted that in a high-performance, out-of-order execution CPU core, the two operations STA and STD contained in a store operation are usually decomposed into two independent microinstructions for execution. In addition to this method, the present application is also applicable to other methods, such as the same store microinstruction being executed in two pipelines of address generation and register reading.

[0104] For a RISC-V CPU core that implements RISC-V vector extension, the RISC-V vector store hardware resource release method and device provided in the embodiments of this specification provide an optimization solution for extending ROB and SB to support RISC-V vector store instructions. Compared with the traditional solution, this application does not need to significantly increase the hardware resources required for the SB item, and achieves the purpose of releasing the SB item as soon as possible by retiring the SB item as soon as possible. At the same time, this application can also release the SB item corresponding to the mask off store operation as soon as possible, thereby further improving the SB utilization efficiency.

[0105] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of this specification can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the embodiments of this specification are not limited to any specific combination of hardware and software.

[0106] It should be understood that the above description is for illustration and not for limitation. Many embodiments and many applications beyond the examples provided will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this specification should not be determined with reference to the above description, but should be determined with reference to the preceding claims and the full scope of equivalents to which these claims belong.

[0107] The above description is only the preferred embodiment of this specification and is not intended to limit this specification. For those skilled in the art, the embodiments of this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included in the protection scope of this specification.

Claims

1. A RISC-V vector store hardware resource release method, characterized in that: The method comprises: In response to the vector store instruction, a plurality of vector STA and STD microinstruction pairs are generated by decoding according to the number of store operations, and a hardware resource item is allocated to each vector STA and STD microinstruction pair; Retiring the hardware resource item by using a preset vector storage retirement table to assist the reorder cache with a vector storage retirement item in the vector storage retirement table as a granularity, so as to release the hardware resource corresponding to the hardware resource item; Among them, the number of continuous unmasked store operation items stored in the vector storage retirement item is used to retire the hardware resource items of all unmasked store operations of the vector store instructions after the vector storage retirement item when retiring the hardware resource item corresponding to the vector storage retirement item.

2. The RISC-V vector store hardware resource release method according to claim 1, characterized in that: Decode and generate multiple STA and STD microinstruction pairs according to the number of store operations, including: An IS_LAST field is added to the vector STA microinstruction generated by the vector store instruction, and the last bit information of the vector STA microinstruction in the vector store instruction is defined by the value of the IS_LAST field.

3. The RISC-V vector store hardware resource release method according to claim 1, characterized in that: The method further comprises: Set the vector store retirement entry identification field, the vector STA microinstruction number field and the vector STD microinstruction number field in the reorder cache entry; Among them, the vector storage retirement item identification field is used to configure different numerical values ​​according to the vector store instruction or the non-vector store instruction; the vector STA microinstruction number field and the vector STD microinstruction number field are respectively used to record the number of vector STA microinstructions and the number of vector STD microinstructions generated by the vector store instruction, and adjust the corresponding recorded number of vector STA microinstructions and the number of vector STD microinstructions according to the execution status of the vector STA microinstructions and the vector STD microinstructions.

4. The RISC-V vector store hardware resource release method according to claim 1, characterized in that: The method further comprises: When the source physical register value of the vector STA microinstruction exists and there is an idle vector storage retirement item, the vector storage retirement table sequentially allocates an idle vector storage retirement item to the vector STA microinstruction; When retiring a vector STA microinstruction with no mask store operation, releasing the corresponding vector store retirement item; When the vector STA microinstruction executing the mask store operation is completed, the corresponding vector store retirement item is released; The vector storage retirement item includes a vector storage retirement index field, a vector store instruction index field corresponding to the reorder cache, a store operation index field in the vector store instruction, an index field of a hardware resource item corresponding to the store operation, a store operation exception record identification field, and a mask store operation number field before the store operation.

5. The RISC-V vector store hardware resource release method according to claim 4, characterized in that: The vector storage retirement table sequentially allocates an idle vector storage retirement entry for the vector STA microinstruction, including: When creating or writing a vector store retirement item, the number of unmasked store operations between the corresponding valid store operation and the previous valid store operation is written into the number of masked store operations before the store operation field of the vector store retirement item; When a vector storage retirement item is released or read, and it is determined through the store operation before masking the store operation number field that the adjacent next item has valid data, the store operation before masking the store operation number field of the adjacent next item is read, so that when retiring the hardware resource item corresponding to the vector storage retirement item, all the hardware resource items of the unmasked store operations of the vector store instruction after the vector storage retirement item are retired.

6. The RISC-V vector store hardware resource release method according to claim 4, characterized in that: The vector storage retirement table sequentially allocates an idle vector storage retirement entry for the vector STA microinstruction, including: When the vector store retirement item flag is abnormal, the corresponding field in the store operation index field in the vector store instruction of the vector store retirement item and the abnormal type in the store operation abnormal record identification field are provided to the reorder cache for abnormal processing.

7. The RISC-V vector store hardware resource release method according to claim 1, characterized in that: Assisting the reorder cache by presetting a vector storage retirement table to retire the hardware resource item at the granularity of the vector storage retirement item in the vector storage retirement table includes: Each clock cycle starts to release hardware resource items sequentially by presetting the items pointed to by the vector storage pointer head; Each clock cycle starts with sequentially allocating hardware resource items by presetting the item pointed to by the tail of the vector storage pointer; The vector storage pointer head points to the longest valid entry in the vector storage retirement table, and the vector storage pointer tail points to the first invalid entry in the vector storage retirement table.

8. The RISC-V vector store hardware resource release method according to claim 1, characterized in that: Assisting the reorder cache by presetting a vector storage retirement table to retire the hardware resource item at the granularity of the vector storage retirement item in the vector storage retirement table includes: When all vector store retirement items corresponding to the vector STA microinstructions of the vector store instruction are released, the vector store retirement table provides a notification signal to the reorder cache; When all vector STD microinstructions of the vector store instruction are executed, the reorder cache releases the reorder cache entry corresponding to the vector store instruction according to the notification signal.

9. A RISC-V vector store hardware resource release device, characterized in that: The device comprises: an allocation module and a release module; The allocation module is used for generating a plurality of vector STA and STD microinstruction pairs according to the number of store operations in response to the vector store instruction, and allocating a hardware resource item to each vector STA and STD microinstruction pair; The release module is used to assist the reorder cache to retire the hardware resource item with the vector storage retirement item in the vector storage retirement table as the granularity through the preset vector storage retirement table, so as to release the hardware resource corresponding to the hardware resource item; Among them, the number of continuous unmasked store operation items stored in the vector storage retirement item is used to retire the hardware resource items of all unmasked store operations of the vector store instructions after the vector storage retirement item when retiring the hardware resource item corresponding to the vector storage retirement item.

10. A central processing unit, comprising a central processing core based on a reorder cache of instructions, microinstructions and macroinstructions, characterized in that: The central processing unit applies the RISC-V vector store hardware resource release method described in any one of claims 1 to 8.

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