Loading storage unit, processor and computer equipment

Abstract

The invention discloses a loading storage unit, a processor and computer equipment, and relates to the technical field of chips. The loading storage unit comprises an address calculation circuit, a prediction circuit, a storage queue and a storage buffer, the address calculation circuit is connected with the prediction circuit, and the prediction circuit is connected with the storage queue, the storage buffer and the data cache; the address calculation circuit is used for calculating a loading data address corresponding to the loading instruction and sending the loading data address to the prediction circuit; and the prediction circuit is used for predicting whether the data corresponding to the loading instruction exists in the storage queue or the storage buffer based on the loading data address, and triggering to query the data corresponding to the loading instruction in the storage queue and the storage buffer under the condition that the data corresponding to the loading instruction is predicted to exist in the storage queue or the storage buffer. The scheme can improve the utilization rate of the data cache and reduce the power consumption of the processor.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a loading and storing unit, a processor and a computer device. Background Art

[0002] In the processor, the Load Store Unit (LSU) is responsible for accessing memory to obtain data.

[0003] In the related art, the LSU includes multiple buffers. When accessing memory to obtain data, the LSU needs to query data from multiple buffers and a data cache (DCache) at the same time, and merge the query results of the multiple buffers and the data cache.

[0004] However, in the above solution, there are invalid queries on the data cache, which affects the utilization of the data cache and the power consumption of the processor. Summary of the invention

[0005] The embodiment of the present application provides a loading storage unit, a processor and a computer device, which can improve the utilization rate of data cache and reduce the power consumption of the processor. The technical solution is as follows.

[0006] In one aspect, a load storage unit is provided, the load storage unit comprising: an address calculation circuit, a prediction circuit, a storage queue, and a storage buffer;

[0007] The address calculation circuit is connected to the prediction circuit, and the prediction circuit is respectively connected to the storage queue, the storage buffer and the data cache;

[0008] An address calculation circuit is used to calculate a load data address corresponding to a load instruction and send the load data address to a prediction circuit;

[0009] A prediction circuit, used for predicting whether data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address;

[0010] The prediction circuit is also used to trigger a query of the data corresponding to the load instruction in the prediction circuit and the storage queue when it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer.

[0011] In one aspect, an instruction processing method is provided. The method may be performed by a load storage unit. The load storage unit may be the load storage unit described above. The method may include the following steps:

[0012] Calculate the load data address corresponding to the load instruction through the address calculation circuit, and send the load data address to the prediction circuit;

[0013] Predicting, by a prediction circuit, whether data corresponding to the load instruction exists in a storage queue or a storage buffer based on a load data address;

[0014] When it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer, the prediction circuit triggers a query of the data corresponding to the load instruction in the storage queue and the storage buffer.

[0015] In some embodiments, the method further includes: triggering a query of the data corresponding to the load instruction in the storage queue, storage buffer and data cache by the prediction circuit when it is predicted that the data corresponding to the load instruction does not exist in the storage queue or storage buffer.

[0016] In some embodiments, the prediction circuit includes a cache circuit, and the cache circuit is used to store fingerprint information of the address of the data in the storage queue and the storage buffer;

[0017] In some embodiments, the prediction circuit predicts whether the data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address, including:

[0018] The fingerprint information of the load data address is calculated by the prediction circuit, and the fingerprint information of the load data address is matched with the fingerprint information stored in the cache circuit. When the fingerprint information of the load data address matches the fingerprint information stored in the cache circuit successfully, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or storage buffer.

[0019] In some embodiments, the cache circuit includes a first cache and a second cache; the first cache and the second cache each include a plurality of entries;

[0020] The above prediction circuit predicts whether the data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address, including:

[0021] Calculating, by the prediction circuit, a position of a first entry in the first cache and a position of a second entry in the second cache based on the load data address;

[0022] The fingerprint information of the load data address is matched with the fingerprint information in the first entry and the second entry respectively through the prediction circuit. When the fingerprint information of the load data address successfully matches the fingerprint information in the first entry or the second entry, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or the storage buffer.

[0023] In some embodiments, the fingerprint information of the loaded data address calculated by the prediction circuit includes:

[0024] The prediction circuit performs hash calculation on the address portion of the loaded data address that is higher than the cache line granularity to obtain fingerprint information of the loaded data address.

[0025] In some embodiments, the above-mentioned calculating the position of the first entry in the first cache and the position of the second entry in the second cache based on the load data address by the prediction circuit includes:

[0026] By using a prediction circuit, based on a first position function of a cuckoo filter, a portion of an address of a loaded data address that is higher than a cache line granularity is calculated to obtain a position of a first entry;

[0027] The prediction circuit calculates the address portion of the loaded data address that is higher than the cache line granularity based on the second position function of the cuckoo filter to obtain the position of the second entry.

[0028] In some embodiments, the above method further comprises:

[0029] In response to the first data being written into the storage queue, a prediction circuit performs a hash calculation on an address portion of the first data that is higher than the cache line granularity to obtain fingerprint information of the address of the first data;

[0030] By using a prediction circuit, based on a first position function of a cuckoo filter, calculating an address portion of the address of the first data that is higher than a cache line granularity, to obtain a position of a third entry in the first cache;

[0031] The fingerprint information of the address of the first data is stored in the third entry through the prediction circuit.

[0032] In some embodiments, the above method further comprises:

[0033] Removing, by the prediction circuit, the first fingerprint information from the third entry in response to the first fingerprint information already existing in the third entry;

[0034] By using the prediction circuit, based on the second position function of the cuckoo filter, calculating the address portion of the data corresponding to the first fingerprint information that is higher than the cache line granularity, to obtain the position of the fourth entry in the second cache;

[0035] In response, by the prediction circuit, the first fingerprint information is stored in the fourth entry.

[0036] In some embodiments, the above method further comprises:

[0037] By the prediction circuit, in response to the second fingerprint information already existing in the fourth entry, the second fingerprint information is removed from the fourth entry.

[0038] In some embodiments, the entry includes a fingerprint field and a bitmap field; the bitmap field includes N bits, each bit corresponds to an address range of cache line granularity / N; N is an integer greater than or equal to 2; the above method further includes:

[0039] Through the prediction circuit, when the fingerprint information of the address of the first data is stored in the third entry, it is determined that the address portion of the first data that is lower than the cache line granularity corresponds to the target bit in the bitmap field, and the target bit in the third entry is set to the first value.

[0040] In some embodiments, the above method further comprises:

[0041] In response to the second data being removed from the storage buffer, performing a hash calculation on an address portion of the second data that is higher than the cache line granularity in the address of the second data by the prediction circuit to obtain fingerprint information of the address of the second data;

[0042] By the prediction circuit, the position of the fifth entry in the first cache and the position of the sixth entry in the second cache are calculated based on the address of the second data;

[0043] The fingerprint information of the address of the second data is matched with the fingerprint information in the fifth entry and the sixth entry respectively through the prediction circuit. If the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry, the successfully matched fingerprint information is removed.

[0044] In some embodiments, the above-mentioned matching the fingerprint information of the address of the second data with the fingerprint information in the fifth entry and the sixth entry respectively by the prediction circuit includes:

[0045] Through the prediction circuit, when the fingerprint information of the address of the second data is the same as the fingerprint information in the fifth entry or the sixth entry, and the address range corresponding to the bits set to the specified value in the entry with the same fingerprint information includes the address part of the address of the second data that is lower than the cache line granularity, it is determined that the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry.

[0046] In some embodiments, the above-mentioned removing the successfully matched fingerprint information by the prediction circuit when the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry includes: setting the bit of the address portion of the address of the second data below the cache line granularity in the bitmap field of the entry where the successfully matched fingerprint information is located to a second value by the prediction circuit when the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry.

[0047] In some embodiments, the prediction circuit predicts whether the data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address, including:

[0048] Through the prediction circuit, multiple positions of the load data address in the target array are calculated based on the Bloom filter algorithm. When the values ​​of the multiple positions of the load data address in the target array are all specified values, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or storage buffer.

[0049] In some embodiments, the above method further comprises:

[0050] Through the prediction circuit, in response to the third data being written into the storage queue, multiple locations of the address of the third data in the target array are calculated through the Bloom filter algorithm, and the values ​​of the multiple locations of the address of the third data in the target array are set to specified values.

[0051] In some embodiments, the load store unit further comprises: a load reservation station and a data merge circuit;

[0052] The load reservation station is connected to the address calculation circuit, the storage queue, the storage buffer and the data cache are respectively connected to the data merging circuit, and the data merging circuit is also connected to the load reservation station;

[0053] The above method further includes:

[0054] Sending a load instruction to the address calculation circuit via the load reservation station;

[0055] Through the storage queue and the storage buffer, when the prediction circuit predicts that the data corresponding to the load instruction exists in the storage queue or the storage buffer, the queried data is sent to the data merging circuit;

[0056] Merging the data sent by the storage queue and the storage buffer through the data merging circuit, performing an abnormality detection on the merged data, and sending an abnormality instruction to the load reservation station when the data abnormality is detected;

[0057] Reissue the load instruction to the address calculation circuit via the load reservation station;

[0058] Through the prediction circuit, based on the reissued load instruction, a query of the data corresponding to the load instruction in the data cache is triggered.

[0059] In some embodiments, reissuing the load instruction to the address calculation circuit by loading the reservation station includes:

[0060] reissuing the load instruction to the address calculation circuit through the load reservation station, and setting the value of the specified flag bit in the reissued load instruction to the specified flag value;

[0061] The above prediction circuit triggers querying the data corresponding to the load instruction in the data cache based on the reissued load instruction, including:

[0062] The prediction circuit is used to trigger a query of the data cache for the data corresponding to the load instruction when the value of the designated flag bit in the reissued load instruction is the designated flag value.

[0063] On the other hand, a processor is provided, the processor comprising at least one load storage unit as described above.

[0064] On the other hand, a computer device is provided, the computer device comprising at least one processor, the processor comprising at least one load storage unit as described above.

[0065] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0066] In the load storage unit of the processor, a prediction circuit is set, and the prediction circuit can predict whether the data corresponding to the load instruction exists in the storage queue or the storage buffer through the load data address corresponding to the load instruction. If the prediction hits, that is, it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer, the data corresponding to the load instruction can be queried in the prediction circuit and the storage queue, thereby skipping the query process in the data cache, thereby reducing invalid access to the data cache, thereby improving the utilization rate of the data cache and reducing the power consumption of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0068] Figure 1 It is a schematic diagram of a load access pipeline;

[0069] Figure 2 It is a cuckoo filter implementation structure;

[0070] Figure 3 is a schematic diagram of a load storage unit provided by an exemplary embodiment of the present application;

[0071] Figure 4 is a schematic diagram of a load storage unit provided by an exemplary embodiment of the present application;

[0072] Figure 5is a schematic diagram of a load storage unit provided by an exemplary embodiment of the present application;

[0073] Figure 6 is a structural schematic diagram of a prediction circuit involved in an embodiment of the present application;

[0074] Figure 7 is a schematic diagram of the structure of another prediction circuit involved in an embodiment of the present application;

[0075] Figure 8 is a structural schematic diagram of another prediction circuit involved in an embodiment of the present application;

[0076] Fig. 9 This is a schematic diagram of a cache structure involved in an embodiment of the present application;

[0077] Fig.10 is a structural diagram of another prediction circuit involved in an embodiment of the present application;

[0078] Fig.11 is a structural schematic diagram of a prediction circuit involved in an embodiment of the present application;

[0079] Fig.12 is a schematic diagram of a load storage unit provided by an exemplary embodiment of the present application;

[0080] Fig.13 is a structural schematic diagram of another prediction circuit involved in an embodiment of the present application;

[0081] Fig.14 is a schematic diagram of the load access pipeline involved in this application;

[0082] Fig.15 is a schematic diagram of inserting a new address into a predictor involved in the present application;

[0083] Fig.16 is another schematic diagram of inserting a new address into a predictor involved in the present application;

[0084] Fig.17 is a schematic diagram of an address in a query predictor involved in the present application;

[0085] Fig.18 It is a flowchart of an instruction processing method involved in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0086] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0087] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0088] The following first introduces some concepts involved in this application:

[0089] 1) Load Store Unit (LSU):

[0090] The LSU module of the processor (such as the central processing unit CPU) is responsible for accessing memory to obtain data. There are multiple buffers in the LSU, such as the store queue (SQ) and the store buffer (SB). The SQ is responsible for buffering the execution results of the Store instructions (store instructions, storing data in registers to external memory (the computer system's memory, the cache in the CPU is collectively referred to as the CPU's external memory)) that have not yet been submitted, and the SB is responsible for buffering the execution results that have been submitted but not yet written to the Dcache (data cache). During the execution process of the Load instruction (load instruction, load external memory data into the processor's register), it is necessary to check whether there is data that it needs (address matching) in the SQ and SB. If so, the data in them is taken first, and the data retrieved from the Dcache is discarded. From the perspective of the Load instruction, the priority of obtaining data is SQ>SB>Dcache. However, considering performance priority, access to SQ, SB, and Dcache is performed simultaneously, and data merging operations are performed after all data are obtained. For example, if address matching data is obtained from SQ, SB, and Dcache, the data in SB and DCache needs to be discarded. For example, please refer to Figure 1 , which shows a schematic diagram of a load memory access pipeline.

[0091] In the above process, if there is a hit in SQ and SB, accessing Dcache is an invalid operation. Since Dcache resources are limited, this invalid access to Dcache will cause Dcache access conflicts and affect other normal requests to access Dcache. In addition, Dcache access consumes a lot of power.

[0092] 2) Cuckoo filter:

[0093] Please refer to Figure 2 , which shows an implementation structure of a cuckoo filter. Figure 2 As shown in the figure, Cuckoo Filter and Bloom Filter are both probabilistic data structures used to efficiently check whether an element belongs to a set. They are very useful in many applications, such as network routing, caching, databases, etc. Although they have similar purposes, their implementation and performance characteristics are different. The insertion and deletion principles of Cuckoo filter are as follows:

[0094] (1) Insertion principle:

[0095] like Figure 2 As shown, for the element x to be inserted, its hash value h(x) and fingerprint f(x) are calculated. The fingerprint is a shorter representation of the element, usually represented by a few bits, generally taking the last few bits of the element's hash value, for example Figure 2 If the x fingerprint in is 0101, the following will try to insert the fingerprint into the bucket.

[0096] Two candidate positions i1 and i2 are calculated using two hash functions. Where i1 = h(x) and i2 = h(x)xor h(f(x)). This means that element x can be stored in position i1 or i2.

[0097] Check if there is an empty space at positions i1 and i2. If there is an empty space, store f(x) in one of the positions and complete the insertion.

[0098] If both positions i1 and i2 are full, then one of the positions (say i1) is selected, its current fingerprint f(y) is moved out, and f(x) is stored in that position.

[0099] Calculate the new position for the removed element y using the method calculated previously. Then try to insert f(y) into the new position. If the new position is also full, continue to remove the existing elements and try to insert f(y).

[0100] If after a number of iterations (usually set to a fixed threshold), f(y) cannot be inserted, the CuckooFilter is considered full. At this time, you can choose to increase the size of the filter or report that the insertion failed.

[0101] (2) Deletion principle:

[0102] For the element x to be deleted, calculate its hash value h(x) and fingerprint f(x).

[0103] The hash value is used to calculate two candidate positions i1 and i2, where i1 = h(x) and i2 = i1⊕h(f(x)).

[0104] Check if positions i1 and i2 contain fingerprint f(x). If f(x) is found, set its position to empty and complete the deletion.

[0105] If f(x) is not found in both positions i1 and i2, the element x is not in the Cuckoo Filter.

[0106] Please refer to Figure 3 , which shows a schematic diagram of a load storage unit provided by an exemplary embodiment of the present application, the load storage unit includes: an address calculation circuit 310, a prediction circuit 320, a storage queue 330 and a storage buffer 340.

[0107] The address calculation circuit 310 is connected to the prediction circuit 320 , and the prediction circuit 320 is connected to the storage queue 330 , the storage buffer 340 , and the data cache 350 , respectively.

[0108] An input / output port of the address calculation circuit 310 is electrically connected to an input port of the prediction circuit 320 , and an output port of the prediction circuit 320 is electrically connected to an input port of each of the storage queue 330 , the storage buffer 340 , and the data cache 350 .

[0109] The address calculation circuit 310 is used to calculate the load data address corresponding to the load instruction and send the load data address to the prediction circuit 320 .

[0110] The address calculation circuit 310 may calculate the load data address based on the load instruction, and output the load data address to the input port of the prediction circuit 320 through the output port between the address calculation circuit 310 and the prediction circuit 320 .

[0111] For example, the above-mentioned load instruction may include the base position / starting position (base) and offset (offset) of the data to be loaded. The address calculation circuit 310 may parse the base position and offset in the load instruction, and calculate the loaded data address through the parsed base position and offset.

[0112] The prediction circuit 320 is used to predict whether the data corresponding to the load instruction exists in the storage queue or the storage buffer according to the load data address.

[0113] The prediction circuit 320 may determine whether data corresponding to the load data address is present in the storage queue or storage buffer according to the load data address input by the address calculation circuit 310 .

[0114] For example, the prediction circuit 320 may store information about the addresses of all or part of the data in the storage queue and the storage buffer, and then compare the information about the load data address with the information stored at the address. If the information stored at the address contains information that matches the information about the load data address, it can be considered that the data corresponding to the load instruction is predicted to exist in the storage queue or the storage buffer. Conversely, if the information stored at the address does not contain information that matches the information about the load data address, it can be considered that the data corresponding to the load instruction is predicted to not exist in the storage queue or the storage buffer.

[0115] The prediction circuit 320 is further configured to trigger a query of the data corresponding to the load instruction in the storage queue 330 or the storage buffer 340 when it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer.

[0116] If the prediction circuit 320 predicts that the data corresponding to the load instruction exists in the storage queue or storage buffer, it can trigger a query for the corresponding data in the storage queue 330 or storage buffer 340. At this time, the process of querying the corresponding data in the data cache 350 may not be executed.

[0117] In some embodiments, the prediction circuit 320 is further used to trigger a query for the data corresponding to the load instruction in the storage queue 330, the storage buffer 340 and the data cache 350 when it is predicted that the data corresponding to the load instruction does not exist in the storage queue or the storage buffer.

[0118] In the embodiment of the present application, the prediction circuit 320 predicts that the data corresponding to the load instruction does not exist in the storage queue or storage buffer, which can also be referred to as the prediction circuit 320 failing to predict that the data corresponding to the load instruction exists in the storage queue or storage buffer.

[0119] Optionally, in an embodiment of the present application, a certain error is allowed in the prediction result of the prediction circuit 320. If the prediction circuit 320 predicts that the data corresponding to the load instruction does not exist in the storage queue or the storage buffer, it can trigger a process of querying the corresponding data in parallel in the storage queue 330, the storage buffer 340 and the data cache 350 to ensure the accuracy of the data query process.

[0120] To summarize, in the scheme shown in the embodiment of the present application, a prediction circuit is set in the load storage unit of the processor, and the prediction circuit can predict whether the data corresponding to the load instruction exists in the storage queue or the storage buffer through the load data address corresponding to the load instruction. If the prediction hits, that is, it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer, the data corresponding to the load instruction can be queried in the prediction circuit and the storage queue, thereby skipping the query process in the data cache, thereby reducing invalid access to the data cache, thereby improving the utilization rate of the data cache and reducing the power consumption of the processor.

[0121] Based on the above examples, please refer to Figure 4 , which shows a schematic diagram of a load storage unit provided by an exemplary embodiment of the present application, such as Figure 4 As shown, the prediction circuit 320 includes a cache circuit 322 , and the cache circuit 322 is used to store fingerprint information of the address of the data in the storage queue 330 and the storage buffer 340 .

[0122] The prediction circuit 320 is used to calculate the fingerprint information of the load data address, match the fingerprint information of the load data address with the fingerprint information stored in the cache circuit 322, and when the fingerprint information of the load data address matches the fingerprint information stored in the cache circuit 322 successfully, determine that the data corresponding to the load instruction is predicted to exist in the storage queue or storage buffer.

[0123] Accordingly, when the fingerprint information of the load data address fails to match the fingerprint information stored in the cache circuit 322 , it is determined that the data corresponding to the predicted load instruction does not exist in the storage queue or storage buffer.

[0124] The fingerprint information may be information obtained by performing a hash calculation on the address of the data, or may be information obtained by processing the address of the data using other algorithms (such as a secure hash algorithm, a message digest (MD) algorithm, etc.).

[0125] That is to say, the data volume (or length) of the fingerprint information is smaller than the data volume of the corresponding address, and the fingerprint information of different data addresses is different.

[0126] Among them, the above-mentioned cache circuit 322 can cache fingerprint information of the addresses of all or part of the data in the storage queue 330 and the storage buffer 340. During the prediction process, the prediction circuit 320 matches the fingerprint information of the input address with the fingerprint information stored in the cache circuit 322. If the match is successful, it is determined that the data corresponding to the input address is present in the storage queue or the storage buffer. If the match is unsuccessful, it is determined that the data corresponding to the input address is not present in the storage queue or the storage buffer. Since the data volume of the above-mentioned fingerprint information is smaller than the data volume of the address, the storage queue 330 performs subsequent predictions by caching the fingerprint information of the data address. On the one hand, it can reduce the amount of data stored in the cache circuit 322 and simplify the structural complexity of the cache circuit 322. On the other hand, the matching speed between the fingerprint information of a small amount of data is faster, which can improve the prediction efficiency.

[0127] Based on the above examples, please refer to Figure 5 , which shows a schematic diagram of a load storage unit provided by an exemplary embodiment of the present application, such as Figure 5 As shown, the cache circuit 322 includes a first cache 322 a and a second cache 322 b ; the first cache 322 a and the second cache 322 b each include a plurality of entries.

[0128] The prediction circuit 320 is used to calculate the position of the first entry in the first cache 322a and the position of the second entry in the second cache 322b based on the load data address.

[0129] The prediction circuit 320 is used to match the fingerprint information of the load data address with the fingerprint information in the first entry and the second entry respectively, and when the fingerprint information of the load data address successfully matches the fingerprint information in the first entry or the second entry, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue 330 or the storage buffer 340.

[0130] In the embodiment of the present application, two caches may be provided in the cache circuit 322, and a plurality of entries for caching fingerprint information may be provided in each cache, and each entry is used to store fingerprint information of a corresponding segment of address (that is, each entry is shared by a segment of continuous address), and for one address, corresponding entries may be found in the two caches respectively, and when a data is written to the storage queue, the fingerprint information of the address of the data may be cached in one entry of the two caches; accordingly, for one address, the prediction circuit 320 may calculate the entry positions of the address in the two caches respectively, and then match the fingerprint information of the address with the cache fingerprint information in the calculated entry positions respectively, and if the fingerprint information of the address matches the fingerprint information of the cache at any of the calculated entry positions of the two caches, it is determined that the data corresponding to the address exists in the storage queue 330 or the storage buffer 340; conversely, if the fingerprint information of the address does not match the fingerprint information in the calculated entry positions of the two caches, it is determined that the data corresponding to the address is predicted not to exist in the storage queue 330 or the storage buffer 340 (or in other words, it is not predicted that the data corresponding to the address exists in the storage queue 330 or the storage buffer 340).

[0131] Among them, since the above-mentioned entry corresponds to a section of address, there may be a situation where the data of two addresses in a section of address corresponding to the same entry are written into the storage queue. At this time, the entry can only store the fingerprint information of one of the addresses, which leads to an address conflict, resulting in a reduction in the accuracy of subsequent predictions. In this regard, the scheme shown in the embodiment of the present application sets two caches, each of which contains multiple entries. In the case where the data of two addresses in a section of address corresponding to the same entry are written into the storage queue, the fingerprint information of the two addresses can be cached in entries corresponding to different caches respectively, thereby effectively reducing the address conflict.

[0132] The solution shown in the above-mentioned embodiment of the present application is to set multiple entries in the cache, each entry corresponds to a segment of address. When the data of a certain address is written into the storage queue, the fingerprint information of the address is cached in the corresponding entry for matching in the subsequent prediction process. On the one hand, each entry is shared by a segment of address, and the largest possible address range can be covered with a lower number of entries. On the other hand, by storing the fingerprint information of two addresses in the same segment of address in two caches respectively, address conflicts can be reduced and prediction accuracy can be improved.

[0133] In addition to setting two caches in the cache circuit 322, three or more caches can also be set in the cache circuit 322, each cache containing multiple entries, so that fingerprint information of three or more addresses in the same segment address can be cached in the cache circuit 322 at the same time, further reducing address conflicts and improving prediction accuracy.

[0134] In some embodiments, the prediction circuit 320 is used to perform hash calculation on the address portion of the loaded data address that is higher than the cache line granularity to obtain fingerprint information of the loaded data address.

[0135] In a computer system, a cache can be composed of multiple cache lines. Cacheline is the smallest storage unit of cache management, also called cache block. Each cache line can contain Flag, Tag and Data. The Flag and Tag of different processor models may be different. Cache line is the smallest unit for exchanging data between cache and RAM. The storage space of a cache line can be called cache line granularity. For example, the cache line granularity can be 64 bytes. Based on spatial locality, that is, the possibility of adjacent data being accessed in the future is high, when the processor loads the data from the memory into the cache, it will put the adjacent 64-Byte data into the same cache line.

[0136] In an embodiment of the present application, a continuous address segment corresponding to a cache line granularity can be set to share an entry in the above-mentioned cache, and for a segment of addresses that share an entry in the above-mentioned cache, the address portion of this segment of addresses that is higher than the cache line granularity is the same; when calculating the fingerprint information of an address, the prediction circuit 320 can perform a hash calculation through the address portion of the address that is higher than the cache line granularity to obtain the corresponding fingerprint information.

[0137] For example, taking the cache line granularity of 64B (i.e. 64Byte) and an address of 0x20000f74f8 (binary representation is 100000000000000000011110111010011111000) as an example, the address above 64B is 0x20000f74c0 (binary representation is 10000000000000000011110111010011000000), and the address within 64B is 0x38 (binary representation is 111000). At this time, the prediction circuit 320 can perform hash calculation on 0x20000f74c0 to obtain the corresponding fingerprint information.

[0138] For example, please refer to Figure 6, which shows a schematic diagram of the structure of a prediction circuit involved in an embodiment of the present application. Figure 6 As shown, the prediction circuit 320 includes a fingerprint calculation circuit 323 in addition to the cache circuit 322. The fingerprint calculation circuit 323 is connected to the address calculation circuit 310. The fingerprint calculation circuit 323 is used to perform hash calculation on the address part of the address input by the address calculation circuit 310 (i.e., the above-mentioned load data address) that is higher than the cache line granularity to obtain the fingerprint information of the load data address. The fingerprint information of the load data address can be matched with the fingerprint information in the first entry of the first cache 322a and the fingerprint information in the second entry of the second cache 322b respectively. If the fingerprint information of the load data address matches the fingerprint information in the first entry or the second entry, it can be determined that the data corresponding to the load instruction is predicted to exist in the storage queue 330 or the storage buffer 340. On the contrary, if the fingerprint information of the load data address does not match the fingerprint information in the first entry or the second entry, it can be considered that the data corresponding to the load instruction is not predicted to exist in the storage queue 330 or the storage buffer 340.

[0139] In an embodiment of the present application, a hash calculation is performed on the address portion that is higher than the cache line granularity in the address to obtain fingerprint information, so that a segment of address corresponding to a cache line granularity shares one entry, and the hash value is used as the fingerprint information to reduce the amount of data represented by the address, so as to cover a sufficiently large address range with as little data as possible, thereby reducing the complexity of storage and matching of address information in the prediction circuit 320 and improving matching efficiency.

[0140] In some embodiments, the prediction circuit 320 is used to calculate the address portion of the loaded data address that is higher than the cache line granularity through the first position function of the cuckoo filter to obtain the position of the first entry; the prediction circuit 320 is used to calculate the address portion of the loaded data address that is higher than the cache line granularity through the second position function of the cuckoo filter to obtain the position of the second entry.

[0141] For example, please refer to Figure 6 In addition to the cache circuit 322 and the fingerprint calculation circuit 323, the prediction circuit 320 also includes a first position calculation circuit 324 and a second position calculation circuit 325; wherein the first position calculation circuit 324 is provided with a first position function for calculating the address portion of the load data address input by the address calculation circuit 310 that is higher than the cache line granularity, so as to obtain the position of the first entry in the first cache 322a; correspondingly, the second position calculation circuit 325 is provided with a second position function for calculating the address portion of the load data address input by the address calculation circuit 310 that is higher than the cache line granularity, so as to obtain the position of the second entry in the second cache 322b.

[0142] like Figure 6 As shown, the prediction circuit 320 also includes a fingerprint matching circuit 326, which is connected to the cache circuit 322, and the fingerprint matching circuit 326 is also connected to the fingerprint calculation circuit 323; the cache circuit 322 queries the fingerprint information cached in the first entry from the first cache 322a according to the position of the first entry calculated by the first position calculation circuit 324, and queries the fingerprint information cached in the second entry from the second cache 322b according to the position of the second entry calculated by the second position calculation circuit 325, and sends the two queried fingerprint information to the fingerprint matching circuit 326; the fingerprint calculation circuit 323 also calculates the fingerprint information of the load data address The fingerprint matching circuit 326 is used to match the fingerprint information of the load data address with the two fingerprint information queried and sent by the cache circuit 322. If the fingerprint information of the load data address matches one of the two fingerprint information queried and sent by the cache circuit 322, it can be determined that the data corresponding to the predicted load instruction exists in the storage queue 330 or the storage buffer 340. Conversely, if the fingerprint information of the load data address does not match the two fingerprint information queried and sent by the cache circuit 322, it can be considered that the data corresponding to the unpredicted load instruction exists in the storage queue 330 or the storage buffer 340.

[0143] Optionally, the fingerprint matching circuit 326 is connected to the storage queue 330, the storage buffer 340 and the data cache 350 respectively; when the matching result of the fingerprint matching circuit 326 is that the fingerprint information of the loaded data address matches one of the two fingerprint information queried and sent by the cache circuit 322, the fingerprint matching circuit 326 can trigger the storage queue 330 and the storage buffer 340 to query the data corresponding to the loaded data address; when the matching result of the fingerprint matching circuit 326 is that the fingerprint information of the loaded data address does not match the two fingerprint information queried and sent by the cache circuit 322, the fingerprint matching circuit 326 can trigger the storage queue 330, the storage buffer 340 and the data cache 350 to query the data corresponding to the loaded data address respectively.

[0144] For example, in Figure 6In the embodiment, the fingerprint matching circuit 326 is also connected to the address calculation circuit 310. The address calculation circuit 310 sends the loaded data address to the fingerprint matching circuit 326. When the fingerprint matching circuit 326 triggers the storage queue 330 and the storage buffer 340 to query the data corresponding to the loaded data address, the loaded data address can be sent to the storage queue 330 and the storage buffer 340. When the fingerprint matching circuit 326 triggers the storage queue 330, the storage buffer 340 and the data cache 350 to respectively query the data corresponding to the loaded data address, the loaded data address can be sent to the storage queue 330, the storage buffer 340 and the data cache 350.

[0145] Alternatively, the above-mentioned load data address can also be provided to the storage queue 330, the storage buffer 340 and the data cache 350 through other circuits other than the fingerprint matching circuit 326; for example, the load data address can be cached in a register in the prediction circuit 320, and when the fingerprint matching circuit 326 triggers the storage queue 330 and the storage buffer 340 to query the data corresponding to the load data address, the storage queue 330 and the storage buffer 340 can be triggered to read the load data address from the register; accordingly, when the fingerprint matching circuit 326 triggers the storage queue 330, the storage buffer 340 and the data cache 350 to respectively query the data corresponding to the load data address, the storage queue 330, the storage buffer 340 and the data cache 350 can be triggered to read the load data address from the register.

[0146] Among them, the above-mentioned first position function and second position function can be two different hash functions in the cuckoo filter, and the two different hash functions correspond to a cache respectively. For the same address, the different entry positions in the two caches can be calculated through the first position function and the second position function, so that the fingerprint information of two addresses in the same address segment can be stored in two caches respectively, thereby reducing address conflicts and improving prediction accuracy.

[0147] In some embodiments, the prediction circuit 320 is further used to perform a hash calculation on the address portion of the first data that is higher than the cache line granularity in response to the first data being written into the storage queue, to obtain fingerprint information of the address of the first data; the prediction circuit 320 is further used to calculate the address portion of the first data that is higher than the cache line granularity through the first position function of the cuckoo filter, to obtain the position of the third entry in the first cache; the prediction circuit 320 is further used to store the fingerprint information of the address of the first data in the third entry.

[0148] In an embodiment of the present application, when the first data is written into the storage queue, the prediction circuit 320 can calculate the fingerprint information of the address of the first data, and at the same time, calculate the position of the third entry in the first cache corresponding to the address of the first data through the first position function, and then, regardless of whether the fingerprint information already exists in the third entry, the fingerprint information of the address of the first data is stored in the third entry. Through the above scheme, the fingerprint information corresponding to the address of the data newly written into the storage queue can be cached in the prediction circuit 320 in a timely manner, so that the prediction circuit can subsequently accurately predict whether the data corresponding to the newly received load instruction exists in the storage queue or the storage buffer, thereby ensuring the accuracy of the prediction.

[0149] In some embodiments, the prediction circuit 320 is further used to remove the first fingerprint information from the third entry in response to the first fingerprint information already existing in the third entry; the prediction circuit 320 is further used to calculate the address portion of the address of the data corresponding to the first fingerprint information that is higher than the cache line granularity through the second position function of the cuckoo filter to obtain the position of the fourth entry in the second cache; the prediction circuit is further used to store the first fingerprint information in the fourth entry.

[0150] Among them, the above-mentioned response to the first fingerprint information already existing in the third entry, removing the first fingerprint information from the third entry may mean that in response to the first fingerprint information already existing in the third entry and the first fingerprint information is different from the fingerprint information of the address of the first data, the first fingerprint information is removed from the third entry.

[0151] In the above embodiment of the present application, each entry is used to store fingerprint information of an address. When the fingerprint information of the address of the first data is written into the third entry, the fingerprint information of the address of the first data will overwrite the original information in the third entry. At this time, if the fingerprint information of the address of the first data is different from the original information in the third entry, it will result in the inability to subsequently predict the data corresponding to the first fingerprint information in the storage queue 330 or the storage buffer 340 based on the address in the third entry; at this time, the prediction circuit 320 can calculate the fourth entry in the second cache that can cache the first fingerprint information through the second position function, and then move the original first fingerprint information in the third entry to the fourth entry. Subsequently, it can be predicted that the data corresponding to the first fingerprint information exists in the storage queue 330 or the storage buffer 340 based on the address in the fourth entry, thereby avoiding the problem that the old fingerprint information in the cache circuit 322 is overwritten by the new fingerprint information, resulting in the inability to accurately predict the corresponding old fingerprint information in the storage queue 330 or the storage buffer 340, thereby improving the accuracy of the prediction.

[0152] In some embodiments, the prediction circuit 320 is further configured to remove the second fingerprint information from the fourth entry in response to the second fingerprint information already existing in the fourth entry.

[0153] In which, in response to the second fingerprint information already existing in the fourth entry, removing the second fingerprint information from the fourth entry may mean that in response to the second fingerprint information already existing in the fourth entry and the second fingerprint information is different from the first fingerprint information, the second fingerprint information is removed from the fourth entry.

[0154] In an embodiment of the present application, if the second fingerprint information already exists in the fourth entry and the second fingerprint information is different from the first fingerprint information, the prediction circuit 320 may remove the second fingerprint information from the fourth entry before writing the first fingerprint information into the fourth entry, or during the process of writing the first fingerprint information into the fourth entry, thereby ensuring the accuracy of the fingerprint information stored in the fourth entry.

[0155] For example, before writing the first fingerprint information into the fourth entry, the prediction circuit 320 may first clear the second fingerprint information already in the fourth entry; or, when writing the first fingerprint information into the fourth entry, the prediction circuit 320 may write the first fingerprint information into the fourth entry by overwriting.

[0156] For example, please refer to Figure 7 , which shows a schematic diagram of the structure of another prediction circuit involved in the embodiment of the present application. Figure 7 As shown, the storage queue 330 is also connected to the prediction circuit 320. For example, the storage queue 330 is also directly or indirectly connected to the fingerprint calculation circuit 323, the first position calculation circuit 324, and the second position calculation circuit 325 in the prediction circuit 320; when the first data is written into the storage queue 330, the storage queue 330 (or other circuit components outside the storage queue 330) can send the address of the first data to the prediction circuit 320; the prediction circuit 320 first calculates the fingerprint information of the address of the first data through the fingerprint calculation circuit 323 according to the address of the first data, and calculates the third entry in the first cache 322a through the first position calculation circuit 324, and writes the fingerprint information of the address of the first data into the third entry; further, if the first fingerprint information exists in the third entry, the second position calculation circuit 325 is further used to calculate the address of the data corresponding to the first fingerprint information corresponding to the fourth entry in the second cache 322b, and the first fingerprint information is written into the fourth entry; at this time, if the second fingerprint information already exists in the fourth entry, the second fingerprint information will be cleared or overwritten.

[0157] In some embodiments, the entry includes a fingerprint field and a bitmap field; the bitmap field includes N bits, each bit corresponds to an address range of cache line granularity / N; N is an integer greater than or equal to 2; the prediction circuit 320 is also used to determine the target bit in the bitmap field corresponding to the address portion of the first data that is lower than the cache line granularity when the fingerprint information of the address of the first data is stored in the third entry, and set the target bit in the third entry to the first value.

[0158] For example, the first value may be 1, and the initial value (second value) of each bit in the bitmap field may be 0. Alternatively, the first value may be 0, and the initial value (second value) of each bit in the bitmap field may be 1.

[0159] For example, please refer to Figure 8 , which shows a schematic diagram of the structure of another prediction circuit involved in the embodiment of the present application. Figure 8 As shown, the prediction circuit 320 may also include a bit calculation circuit 327, which is connected to the cache circuit 322; the bit calculation circuit 327 can calculate the bit in the bitmap field corresponding to the address portion of the address below the cache line granularity based on the address input to the prediction circuit 320, and output the calculated bit to the cache circuit 322; for example, in the process of storing the fingerprint information of the address of the first data, the cache circuit 322 can receive the bit in the bitmap field corresponding to the address portion of the address of the first data below the cache line granularity calculated by the bit calculation circuit 327 (i.e., the above-mentioned target bit), thereby setting the target bit in the third entry to the first value.

[0160] For example, please refer to Fig. 9 , which shows a schematic diagram of a cache structure involved in an embodiment of the present application; Fig. 9As shown, taking the value of N as 16 as an example, in the first cache 322a, each entry includes a fingerprint field 322a1 and a bitmap field 322a2, wherein the fingerprint field 322a1 is used to cache fingerprint information, and the bitmap field 322a2 includes 16 bits (numbered as Bit0 to Bit15); wherein each bit corresponds to an address range of 4 Bytes, for example, Bit0 corresponds to an address range of 0 to 3 Bytes, and Bit1 corresponds to an address range of 4 to 7 Bytes, and so on. Taking the address portion of the first data above, the address portion below 64 Bytes (this address portion can also be called an address offset within 64 Bytes) as 0x38 (in hexadecimal) as an example, the conversion Converted to decimal, it is 56, which corresponds to the address range of 56 to 59 bytes corresponding to Bit14. When the fingerprint information of the first data is stored in the third entry in the first cache 322a, the bit corresponding to Bit14 in the bitmap field of the third entry is also set to 1 (the initial value of each bit is 0). Alternatively, the bit corresponding to Bit14 in the bitmap field of the third entry can be set to 0 (the initial value of each bit is 1). At this time, the value in the bitmap field can represent the data corresponding to the fingerprint information in the fingerprint field, and the address part below 64 bytes is within the range of 56 to 59 bytes (0x38 to 0x3b in hexadecimal). Further, suppose that another piece of data is written into the storage queue 330, and the address portion above 64Byte in the address of the data is the same as the address portion above 64Byte in the address of the first data, while the address portion below 64Byte in the address of the data is different from the address portion below 64Byte in the address of the first data. Assume that the address portion below 64Byte in the address of the data is 0X3E (in hexadecimal), which is converted to decimal as 62, corresponding to the address range of 60 to 63Byte corresponding to Bit15. At this time, the fingerprint information already exists in the third entry, then the bit corresponding to Bit15 in the bitmap field of the third entry is set to 1 (the initial value of each bit is 0) or 0 (the initial value of each bit is 1). Fig. 9 As shown, through the above setting logic, a maximum of 16 addresses can be stored in one entry.

[0161] Similarly, when the first fingerprint information is stored in the fourth entry, the address portion of the data corresponding to the first fingerprint information within 64 bytes is also obtained, the bit corresponding to the address portion in the bitmap field is calculated, and then the bit in the fourth entry is set to the first value.

[0162] In an embodiment of the present application, an entry can store fingerprint information of any address in an address range corresponding to a cache line granularity. That is to say, for an address range of a cache line granularity, the address portion of the address that is higher than the cache line granularity is the same, and accordingly, the fingerprint information calculated based on this address portion is also the same. That is to say, only through the fingerprint information, it is impossible to further distinguish the addresses in the address range of a cache line granularity. In this regard, in an embodiment of the present application, each entry can be divided into two fields, one of which is a fingerprint field for storing fingerprint information, and the other is a bitmap field, which contains N bits, and divides the address range of a cache line granularity into N small address ranges, each small address range corresponds to 1 bit, and the prediction circuit 320 stores the fingerprint information of the address of the first data in the first During the process of three entries, a small address range where the address portion of the first data that is lower than the cache line granularity is located can also be determined, and then the bit position in the bitmap field corresponding to the address portion of the first data that is lower than the cache line granularity is determined, and then the bit position is set to the first value. Through the above processing, the fingerprint information in an entry, combined with the bit position set to the first value in the bitmap field, can be used to indicate a smaller address range (cache line granularity / N address range) where the address of the data in the storage queue 330 or the storage buffer 340 is located, thereby further improving the accuracy of the address that can be indicated by the information cached in each entry, and addresses of N address ranges can be stored in one entry, thereby improving the accuracy of subsequent prediction of whether the loaded data exists in the storage queue 330 or the storage buffer 340, and saving storage resources.

[0163] In some embodiments, the prediction circuit 320 is further used to perform a hash calculation on the address portion of the second data that is higher than the cache line granularity in the address in response to the second data being removed from the storage buffer to obtain fingerprint information of the address of the second data; the prediction circuit 320 is further used to calculate the position of the fifth entry in the first cache and the position of the sixth entry in the second cache based on the address of the second data; the prediction circuit 320 is used to match the fingerprint information of the address of the second data with the fingerprint information in the fifth entry and the sixth entry respectively, and if the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry, remove the successfully matched fingerprint information.

[0164] For example, please refer to Fig.10 , which shows a schematic diagram of the structure of another prediction circuit involved in the embodiment of the present application. Fig.10As shown, the prediction circuit 320 may also include a fingerprint removal circuit 328, which is connected to the cache circuit 322, and the storage buffer 340 is also connected to the prediction circuit 320. For example, the storage buffer 340 is also directly or indirectly connected to the fingerprint calculation circuit 323, the first position calculation circuit 324, the second position calculation circuit 325, and the bit calculation circuit 327 in the prediction circuit 320; when the second data is removed from the storage buffer 340, the storage buffer 340 (or other circuit components outside the storage buffer 340) can send the address of the second data to the prediction circuit 320; the prediction circuit 320 calculates the fingerprint information of the address of the second data through the fingerprint calculation circuit 323 according to the address of the second data, and calculates the second position calculation circuit 324 through the first position calculation circuit 325. The fifth entry in the first cache 322a, and the sixth entry in the second cache 322b are calculated by the second position calculation circuit 325, the fingerprint removal circuit 328 matches the fingerprint information of the address of the second data with the fingerprint information in the fifth entry and the fingerprint information in the sixth entry respectively, if the fingerprint information of the address of the second data matches the fingerprint information in the fifth entry, the cache circuit 322 is triggered to remove the fingerprint information in the fifth entry, if the fingerprint information of the address of the second data matches the fingerprint information in the sixth entry, the cache circuit 322 is triggered to remove the fingerprint information in the sixth entry, if the fingerprint information of the address of the second data does not match the fingerprint information in the fifth entry and the fingerprint information in the sixth entry, the fingerprint information in the fifth entry and the fingerprint information in the sixth entry are not processed.

[0165] Through the scheme shown in the embodiment of the present application, the fingerprint information corresponding to the address of the data removed from the storage buffer can be removed from the prediction circuit 320 in a timely manner, thereby avoiding the prediction circuit from subsequently erroneously predicting that the second data is stored in the storage queue or storage buffer, thereby ensuring the accuracy of the prediction.

[0166] In some embodiments, the prediction circuit 320 is used to determine that the fingerprint information of the loaded data address successfully matches the fingerprint information in the first entry or the second entry when the fingerprint information of the loaded data address is the same as the fingerprint information in the first entry or the second entry, and the address range corresponding to the bits set to the specified value in the entry with the same fingerprint information includes the address portion of the loaded data address that is lower than the cache line granularity; the prediction circuit 320 is used to determine that the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry when the fingerprint information of the address of the second data is the same as the fingerprint information in the fifth entry or the sixth entry, and the address range corresponding to the bits set to the specified value in the entry with the same fingerprint information includes the address portion of the address of the second data that is lower than the cache line granularity.

[0167] In an embodiment of the present application, in a case where an entry includes a fingerprint field and a bitmap field, if, in the addresses of two data, the address portions above the cache line granularity are the same, and the address portions below the cache line granularity are different, then the fingerprint information of the two addresses is the same, and the bits corresponding to the address portions below the cache line granularity in the two addresses in the bitmap field may be different. At this time, the addresses of the two data can be distinguished by the bits of the first value in the bitmap field; in this regard, in an embodiment of the present application, in a prediction process, or in a fingerprint removal process, when matching the fingerprint information of an address with the fingerprint information in an entry in a cache circuit, in addition to checking the address In addition to checking whether the fingerprint information of the address is the same as the fingerprint information in the entry, it is also checked whether the bit in the bitmap field corresponding to the address portion below the cache line granularity of the address is the same as the bit set to the first value in the entry. If the fingerprint information of the address is the same as the fingerprint information in the entry, and the bit in the bitmap field corresponding to the address portion below the cache line granularity of the address is also the same as the bit set to the first value in the entry, it means that the address and the address of the data cached in the entry are within the same address range of cache line granularity / N (such as the above 4Byte), at this time, it can be considered that the fingerprint information of the address matches the fingerprint information in the entry successfully. In other words, the above scheme can match data addresses with cache line granularity / N as the address granularity, thereby reducing the amount of data represented by the address, improving the matching efficiency, and ensuring the accuracy of the address matching.

[0168] For example, in the prediction process, Figure 8As shown, the bit calculation circuit 327 further calculates the bit in the bitmap field corresponding to the address portion of the loaded data address that is lower than the cache line granularity, and sends the bit in the bitmap field corresponding to the address portion of the loaded data address that is lower than the cache line granularity to the fingerprint matching circuit 326. When the fingerprint matching circuit 326 matches the fingerprint information of the loaded data address with the fingerprint information in the first entry / second entry, in addition to checking whether the fingerprint information of the loaded data address is the same as the fingerprint information in the first entry / second entry, it also checks whether the bit in the bitmap field corresponding to the address portion of the loaded data address that is lower than the cache line granularity is the same as the bit set to the first value in the first entry / second entry. If the fingerprint information of the loaded data address is the same as the fingerprint information in the first entry / second entry, the fingerprint matching circuit 326 checks whether the bit in the bitmap field corresponding to the address portion of the loaded data address that is lower than the cache line granularity is the same as the bit set to the first value in the first entry / second entry. The same, and the bit in the bitmap field corresponding to the address portion of the loaded data address that is lower than the cache line granularity is also the same as the bit set to the first value in the first entry / second entry, then it is determined that the fingerprint information of the loaded data address successfully matches the fingerprint information of the address of the cached data in the first entry / second entry; accordingly, in the case where the second data is removed from the storage buffer, the bit calculation circuit 327 also calculates the bit in the bitmap field corresponding to the address portion of the second data address that is lower than the cache line granularity, and sends the bit in the bitmap field corresponding to the address portion of the second data address that is lower than the cache line granularity to the fingerprint removal circuit 328, so that the fingerprint removal circuit 328 matches the fingerprint information of the address of the second data with the fingerprint information in the fifth entry / sixth entry.

[0169] In some embodiments, the above-mentioned prediction circuit is used to set the bit corresponding to the address part of the address of the second data below the cache line granularity in the bitmap field of the entry where the successfully matched fingerprint information is located to a second value when the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry.

[0170] In an embodiment of the present application, in a case where an entry includes a fingerprint field and a bitmap field, and the bitmap field includes N bits, and each bit corresponds to an address range of cache line granularity / N, removing the fingerprint information corresponding to the address of a data from an entry in the cache circuit 322 may refer to restoring the value of the bit corresponding to the address portion of the address lower than the cache line granularity in the bitmap field of the entry to the initial second value. Optionally, if after restoring the value of the bit corresponding to the address portion of the address lower than the cache line granularity in the bitmap field of the entry to the initial second value, the values ​​of the various bits in the bitmap field of the entry are all the second values, the fingerprint information in the fingerprint field of the entry may also be removed.

[0171] For example, Fig. 9As an example, in the cache structure shown in Fig. 9 In the example, it is assumed that the second data and the first data are the same data. At this time, the third entry and the fifth entry are the same entry. When the second data is removed from the storage buffer 340, the fingerprint removal circuit 328 determines that the fingerprint information of the address of the second data successfully matches the fingerprint information of the third entry. At the same time, it is determined that the address portion of the address of the second data that is lower than the cache line granularity corresponds to the bit numbered Bit14 in the bitmap field of the third entry. At this time, the fingerprint removal circuit 328 can trigger the cache circuit 322 to restore the bit of Bit14 in the third entry to the initial value. At this time, if there are other bits with the first value in the bitmap field of the third entry (for example, in Fig. 9 In the example above, if the initial value of the bit is 0 and the value of the bit numbered Bit15 is 1), the cache circuit 322 keeps the fingerprint information in the fingerprint field in the third entry unchanged; on the contrary, if the values ​​of all bits in the bitmap field of the third entry are the initial values, the cache circuit 322 can remove the fingerprint information in the fingerprint field in the third entry.

[0172] Accordingly, the process of the prediction circuit 320 removing the first fingerprint information from the third entry may refer to removing the first fingerprint information from the fingerprint field of the third entry and setting each bit in the bitmap field of the third entry to the initial second value.

[0173] Similarly, the process of the prediction circuit 320 removing the second fingerprint information from the fourth entry may refer to removing the second fingerprint information from the fingerprint field of the fourth entry and setting each bit in the bitmap field of the fourth entry to the initial second value.

[0174] Among them, the above application Figures 5 to 10 The solution involved in the illustrated embodiment is a filtering prediction solution implemented based on the cuckoo filter principle. Optionally, in some other embodiments, prediction can also be implemented based on other filter algorithms. For example, the prediction of whether data exists in a storage queue or a storage buffer can be implemented based on the Bloom filter principle.

[0175] In some embodiments, the prediction circuit 320 is used to calculate multiple positions of the load data address in the target array through a Bloom filter algorithm, and when the values ​​of the multiple positions of the load data address in the target array are all specified values, determine that the data corresponding to the load instruction is predicted to exist in the storage queue or storage buffer.

[0176] For example, based on Figure 4 For the scheme shown, please refer to Fig.11 , which shows a schematic diagram of the structure of a prediction circuit involved in an embodiment of the present application. Fig.11 As shown, the prediction circuit 320 also includes a position calculation circuit 328 and a value checking circuit 329, and the cache circuit 322 includes a third cache 322c, in which a target array is cached. For an address (such as the above-mentioned load data address), the position calculation circuit 328 calculates the load data address through multiple hash algorithms in the Bloom filter algorithm, and can obtain multiple positions (such as 3 positions) corresponding to the load data address in the target array, and indicates the calculated 3 positions to the third cache 322c; the third cache 322c can read the values ​​of the three positions in the target array, and send the read values ​​of the three positions to the value checking circuit 329. If the value checking circuit 329 checks that the values ​​of the three positions are all specified values ​​(for example, the initial value of each position in the target array can be 0, and the specified value can be 1, or the initial value of each position in the target array can be 1, and the specified value can be 0), it is determined that the data corresponding to the predicted load instruction exists in the storage queue or storage buffer.

[0177] Through the above scheme, it is only necessary to calculate that an address corresponds to multiple positions in the target array and check whether the values ​​of the multiple positions are all specified values ​​to complete the prediction. The prediction process is relatively simple and the prediction efficiency is high.

[0178] In some embodiments, the prediction circuit 320 is also used to respond to the third data being written into the storage queue 330 by calculating the addresses of the third data at multiple locations in the target array through a Bloom filter algorithm, and setting the values ​​of the addresses of the third data at multiple locations in the target array to specified values.

[0179] For example, Fig.11 As shown, the storage queue 330 is also connected to the prediction circuit 320. Specifically, the storage queue 330 can be connected to the position calculation circuit 328 in the prediction circuit 320. When the third data is written into the storage queue 330, the storage queue 330 sends the address of the third data to the position calculation circuit 328. The position calculation circuit 328 calculates the address of the third data through multiple hash algorithms in the Bloom filter algorithm, and can obtain the address of the third data corresponding to multiple positions (such as 3 positions) in the target array, and indicate the calculated 3 positions to the third cache 322c; the third cache 322c can set the values ​​of these three positions to specified values.

[0180] Based on the above examples, please refer to Fig.12 , which shows a schematic diagram of a load storage unit provided by an exemplary embodiment of the present application, such as Fig.12As shown, the load storage unit further includes: a load reservation station 360 and a data merging circuit 370; the load reservation station 360 is connected to the address calculation circuit 310, the storage queue 330, the storage buffer 340 and the data cache 350 are respectively connected to the data merging circuit 370, and the data merging circuit 370 is also connected to the load reservation station; the load reservation station 360 is used to send a load instruction to the address calculation circuit; the storage queue 330 and the storage buffer 340 are used to predict that the data corresponding to the load instruction exists in the storage queue when the prediction circuit 320 predicts that the data corresponding to the load instruction exists in the storage queue Or in the case of a storage buffer, the queried data is sent to a data merging circuit 370; the data merging circuit 370 is used to merge the data sent by the storage queue 330 and the storage buffer 340, and perform an exception detection on the merged data, and when a data exception is detected, send an exception instruction to the load reservation station 360; the load reservation station 360 is used to resend the load instruction to the address calculation circuit 310; the prediction circuit 320 is used to trigger a query of the data corresponding to the load instruction in the data cache 350 based on the resent load instruction.

[0181] For example, the prediction circuit 320 is used to trigger a query of the data corresponding to the load instruction in the storage queue 330 , the storage buffer 340 , and the data cache 350 based on the reissued load instruction.

[0182] In some embodiments, the load reservation station 360 is used to resend the load instruction to the address calculation circuit and set the value of the specified flag bit in the resent load instruction to the specified flag value; the prediction circuit 320 is used to trigger the query of the data corresponding to the load instruction in the data cache 350 when the value of the specified flag bit in the resent load instruction is the specified flag value.

[0183] For example, based on Figure 6 For the scheme shown, please refer to Fig.13 , which shows a schematic diagram of the structure of another prediction circuit involved in the embodiment of the present application. Fig.13As shown, before the fingerprint calculation circuit 323, the first position calculation circuit 324, and the second position calculation circuit 325, a flag bit checking circuit 321 is also included, and the input end of the flag bit checking circuit 321 is connected to the output end of the address calculation circuit 310, and the output end of the flag bit checking circuit 321 is respectively connected to the fingerprint calculation circuit 323, the first position calculation circuit 324, the second position calculation circuit 325 and the data cache 350; the address calculation circuit 310 sends the loaded data address to the flag bit checking circuit 321, and the flag bit checking circuit 321 checks the value of the specified flag bit in the loaded data address. If the specified flag bit is is a specified flag value (such as 1), the data cache 350 is directly triggered to query the data corresponding to the load instruction; for example, when the flag check circuit 321 checks that the value of the specified flag is the specified flag value, the load data address can be sent to the data cache 350, and the load data address will not be sent to the fingerprint calculation circuit 323, the first position calculation circuit 324 and the second position calculation circuit 325; conversely, if the value of the specified flag is not the specified flag value, the load data address can be sent to the fingerprint calculation circuit 323, the first position calculation circuit 324 and the second position calculation circuit 325 for subsequent prediction process.

[0184] Through the above scheme, for a certain address, when the prediction circuit 320 predicts incorrectly, the data merge circuit 370 can trigger the load reservation station 360 to reissue the load instruction. Correspondingly, when the prediction circuit 320 receives the reissued load instruction, it can directly trigger the data cache 350 to perform data query, thereby ensuring the accuracy of the data query and avoiding the situation where data cannot be loaded due to prediction errors.

[0185] The solution shown in the above embodiment of this application can improve CPU performance and reduce CPU power consumption on the product side. Fig.14 , which shows a schematic diagram of the load access pipeline involved in this application. Fig.14 As shown, based on the solution shown in the above embodiment of the present application, if the predictor predicts that the data has hit in SQ or SB, there is no need to access Dcache. If the prediction is wrong, it will be found that the acquired data is incomplete in the step of merging data, and it will be fed back to Load RS to notify the instruction to re-issue and execute. At the second issuance after the prediction error, Dcache is forced to be accessed, so there will be no error that the data cannot be loaded after the prediction error.

[0186] Please refer to Fig.15 , which shows a schematic diagram of inserting a new address into a predictor involved in this application. Fig.15As shown, the system designed in the embodiment of the present application uses cacheline (cache line) 64B as the granularity, and fingerprint bucket 1 (Bucket1, corresponding to the above-mentioned first cache 322a) and fingerprint bucket 2 (Bucket2, corresponding to the above-mentioned second cache 322b) have 16 entries respectively. Therefore, the fingerprint (fingerprint information) can be obtained by hashing the address part higher than 64B, and the address part higher than 64B is calculated through Pos1=hash() function or Pose2=Pos1 xor hash(f(x)) function to obtain the specific entry position pointing to the Bucket. Buckets in this application are stored in the form of addr:bitmap. As Fig.15 As shown, the addr of a Bucket entry in the embodiment of the present application can correspond to 16 bitmaps, which can cover an address range of 16*4B. Compared with the original cuckoo filter structure, more addresses can be stored.

[0187] In this application, one bit of the bitmap represents a 4-Byte data. If the data written by the store instruction is 2Byte, it also occupies one bit. If it is 8B, it needs to occupy two bits.

[0188] When an instruction is issued from the Store reservation station, its memory address is inserted into the predictor. Assuming that the width of the written data is 4 bytes, the insertion method is as follows: Figure 8 Assume that the address is 0x20000f74f8 (100000000000000000011110111010011111000), first divide it into two parts according to the cacheline granularity. Take 64B cacheline as an example. The address above 64B is 0x20000f74c0 (10000000000000000011110111010011000000), and the part within 64B is 0x38 (111000).

[0189] 0x20000f74c0 is used for hash operation. Hash calculation is performed on 0x20000f74c0 (calculated based on fp()) to obtain its fingerprint. If the fingerprint is 0x36, 0x20000f74c0 is calculated to obtain its insertion position. The calculation formula is Pos1 = hash (0x20000f74c0). For example, if it is 0x7, the fingerprint 0x36 is first tried to be inserted into entry7 of bucket1. If there is no conflict in entry7 of bucket1 during insertion, it is inserted. If there is a conflict, try to insert it into the position of Pose2 = Pos1 xor hash (f (x)) of bucket2. At this time, the insertion is not completed yet, and the bitmap needs to be set. Since the offset of address 0x20000f74f8 is 0x38, after processing with 4B as the granularity, it corresponds to bit14 of 16 bits. Therefore, bitmap 14 of entry7 of bucket1 is set (set to 1), and the insertion is completed.

[0190] Please refer to Fig.16 , which shows another schematic diagram of inserting a new address into a predictor involved in the present application. Fig.16 As shown in the figure, if the new address 0x00000839f0 is inserted, the bucket1 position obtained after hash calculation is also entry7, then the original fingerprint 0x36 and the corresponding bitmap need to be kicked out, and the new fingerprint 0xf and bitmap 12 need to be inserted into entry7. The kicked out fingerprint and bitmap need to be recalculated to obtain the new insertion position Pos2 = Pose1 xor hash (f (x)) = 7xor hash (0x36) = 11, so the 0x36 fingerprint and bit

[14] are inserted into entry 11 in bucket2.

[0191] Please refer to Fig.17 , which shows a schematic diagram of the address in the query predictor involved in this application. Fig.17 As shown in the figure, if the address 0x20000f74f8 is accessed when the load instruction is executed, the predictor is queried. Similarly, after processing the address, pos1 (entry 7) and pos2 (entry 11) and fingerprint 0x36 are obtained. At the same time, pos1 and pos2 are queried to find that the fingerprint of entry7 in bucket1 does not match, but the fingerprint in entry11 of bucket2 matches, so the address hits. At this time, when accessing the address 0x20000f74f8, there is no need to access the dcache.

[0192] In order to ensure the accuracy of the predictor, after the Store instruction is written from SBuffer to Dcache, it will be deleted from bucket1 and bucket2. The deletion process is similar to the above and will not be repeated here.

[0193] After data analysis and statistics, about 16% of memory access instructions can obtain complete data from SQ or SB. Therefore, after using this application, assuming that the predictor prediction accuracy is 90% (according to historical design experience, 95% is easily achieved), it can reduce the total 16%*90%=14.4% of Load instructions accessing Dcache. Compared with the original solution, it can reduce Dcache access conflicts and reduce Dcache power consumption by about 15%, thereby improving performance and reducing overall power consumption.

[0194] Please refer to Fig.18 , which shows a flow chart of an instruction processing method involved in an exemplary embodiment of the present application. Fig.18 As shown, the method can be performed by a load storage unit, and the load storage unit can be as shown in Figures 3 to 5 as well as Fig.12 Any of the load storage units described above. Fig.18 As shown, the method may include the following steps:

[0195] Step 1801, calculate the load data address corresponding to the load instruction through the address calculation circuit, and send the load data address to the prediction circuit.

[0196] Step 1802: predict whether the data corresponding to the load instruction exists in the storage queue or storage buffer based on the load data address through the prediction circuit.

[0197] Step 1803 , when the prediction circuit predicts that the data corresponding to the load instruction exists in the storage queue or the storage buffer, triggering a query of the data corresponding to the load instruction in the storage queue and the storage buffer.

[0198] In some embodiments, the method further includes: triggering a query of the data corresponding to the load instruction in the storage queue, storage buffer and data cache by the prediction circuit when it is predicted that the data corresponding to the load instruction does not exist in the storage queue or storage buffer.

[0199] In some embodiments, the prediction circuit includes a cache circuit, and the cache circuit is used to store fingerprint information of the address of the data in the storage queue and the storage buffer;

[0200] In some embodiments, the prediction circuit predicts whether the data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address, including:

[0201] The fingerprint information of the load data address is calculated by the prediction circuit, and the fingerprint information of the load data address is matched with the fingerprint information stored in the cache circuit. When the fingerprint information of the load data address matches the fingerprint information stored in the cache circuit successfully, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or storage buffer.

[0202] In some embodiments, the cache circuit includes a first cache and a second cache; the first cache and the second cache each include a plurality of entries;

[0203] The above prediction circuit predicts whether the data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address, including:

[0204] Calculating, by the prediction circuit, a position of a first entry in the first cache and a position of a second entry in the second cache based on the load data address;

[0205] The fingerprint information of the load data address is matched with the fingerprint information in the first entry and the second entry respectively through the prediction circuit. When the fingerprint information of the load data address successfully matches the fingerprint information in the first entry or the second entry, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or the storage buffer.

[0206] In some embodiments, the fingerprint information of the loaded data address calculated by the prediction circuit includes:

[0207] The prediction circuit performs hash calculation on the address portion of the loaded data address that is higher than the cache line granularity to obtain fingerprint information of the loaded data address.

[0208] In some embodiments, the above-mentioned calculating the position of the first entry in the first cache and the position of the second entry in the second cache based on the load data address by the prediction circuit includes:

[0209] By using a prediction circuit, based on a first position function of a cuckoo filter, a portion of an address of a loaded data address that is higher than a cache line granularity is calculated to obtain a position of a first entry;

[0210] The prediction circuit calculates the address portion of the loaded data address that is higher than the cache line granularity based on the second position function of the cuckoo filter to obtain the position of the second entry.

[0211] In some embodiments, the above method further comprises:

[0212] In response to the first data being written into the storage queue, a prediction circuit performs a hash calculation on an address portion of the first data that is higher than the cache line granularity to obtain fingerprint information of the address of the first data;

[0213] By using a prediction circuit, based on a first position function of a cuckoo filter, calculating an address portion of the address of the first data that is higher than a cache line granularity, to obtain a position of a third entry in the first cache;

[0214] The fingerprint information of the address of the first data is stored in the third entry through the prediction circuit.

[0215] In some embodiments, the above method further comprises:

[0216] Removing, by the prediction circuit, the first fingerprint information from the third entry in response to the first fingerprint information already existing in the third entry;

[0217] By using the prediction circuit, based on the second position function of the cuckoo filter, calculating the address portion of the data corresponding to the first fingerprint information that is higher than the cache line granularity, to obtain the position of the fourth entry in the second cache;

[0218] In response, by the prediction circuit, the first fingerprint information is stored in the fourth entry.

[0219] In some embodiments, the above method further comprises:

[0220] By the prediction circuit, in response to the second fingerprint information already existing in the fourth entry, the second fingerprint information is removed from the fourth entry.

[0221] In some embodiments, the entry includes a fingerprint field and a bitmap field; the bitmap field includes N bits, each bit corresponds to an address range of cache line granularity / N; the above method further includes:

[0222] Through the prediction circuit, when the fingerprint information of the address of the first data is stored in the third entry, it is determined that the address portion of the first data that is lower than the cache line granularity corresponds to the target bit in the bitmap field, and the target bit in the third entry is set to the first value.

[0223] In some embodiments, the above method further comprises:

[0224] In response to the second data being removed from the storage buffer, performing a hash calculation on an address portion of the second data that is higher than the cache line granularity in the address of the second data by the prediction circuit to obtain fingerprint information of the address of the second data;

[0225] By the prediction circuit, the position of the fifth entry in the first cache and the position of the sixth entry in the second cache are calculated based on the address of the second data;

[0226] The fingerprint information of the address of the second data is matched with the fingerprint information in the fifth entry and the sixth entry respectively through the prediction circuit. If the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry, the successfully matched fingerprint information is removed.

[0227] In some embodiments, the above-mentioned matching the fingerprint information of the address of the second data with the fingerprint information in the fifth entry and the sixth entry respectively by the prediction circuit includes:

[0228] Through the prediction circuit, when the fingerprint information of the address of the second data is the same as the fingerprint information in the fifth entry or the sixth entry, and the address range corresponding to the bits set to the specified value in the entry with the same fingerprint information includes the address part of the address of the second data that is lower than the cache line granularity, it is determined that the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry.

[0229] In some embodiments, the above-mentioned removing the successfully matched fingerprint information by the prediction circuit when the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry includes: setting the bit of the address portion of the address of the second data below the cache line granularity in the bitmap field of the entry where the successfully matched fingerprint information is located to a second value by the prediction circuit when the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry.

[0230] In some embodiments, the prediction circuit predicts whether the data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address, including:

[0231] Through the prediction circuit, multiple positions of the load data address in the target array are calculated based on the Bloom filter algorithm. When the values ​​of the multiple positions of the load data address in the target array are all specified values, it is determined that the data corresponding to the load instruction is predicted to exist in the storage queue or storage buffer.

[0232] In some embodiments, the above method further comprises:

[0233] Through the prediction circuit, in response to the third data being written into the storage queue, multiple locations of the address of the third data in the target array are calculated through the Bloom filter algorithm, and the values ​​of the multiple locations of the address of the third data in the target array are set to specified values.

[0234] In some embodiments, the load store unit further comprises: a load reservation station and a data merge circuit;

[0235] The load reservation station is connected to the address calculation circuit, the storage queue, the storage buffer and the data cache are respectively connected to the data merging circuit, and the data merging circuit is also connected to the load reservation station;

[0236] The above method further includes:

[0237] Sending a load instruction to the address calculation circuit via the load reservation station;

[0238] Through the storage queue and the storage buffer, when the prediction circuit predicts that the data corresponding to the load instruction exists in the storage queue or the storage buffer, the queried data is sent to the data merging circuit;

[0239] Merging the data sent by the storage queue and the storage buffer through the data merging circuit, performing an abnormality detection on the merged data, and sending an abnormality instruction to the load reservation station when the data abnormality is detected;

[0240] Reissue the load instruction to the address calculation circuit via the load reservation station;

[0241] Through the prediction circuit, based on the reissued load instruction, a query of the data corresponding to the load instruction in the data cache is triggered.

[0242] In some embodiments, reissuing the load instruction to the address calculation circuit by loading the reservation station includes:

[0243] reissuing the load instruction to the address calculation circuit through the load reservation station, and setting the value of the specified flag bit in the reissued load instruction to the specified flag value;

[0244] The above prediction circuit triggers querying the data corresponding to the load instruction in the data cache based on the reissued load instruction, including:

[0245] The prediction circuit is used to trigger a query of the data cache for the data corresponding to the load instruction when the value of the designated flag bit in the reissued load instruction is the designated flag value.

[0246] The solutions shown in the above embodiments of the present application can be applied to a processor. Specifically, the present application also provides a processor, which includes at least one load storage unit shown in the above embodiments.

[0247] On the other hand, the present application further provides a computer device, which includes at least one processor, and the processor includes at least one load storage unit as shown in the above embodiments.

[0248] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0249] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A load storage unit, characterized in that: The load storage unit includes: an address calculation circuit, a prediction circuit, a storage queue and a storage buffer; The address calculation circuit is connected to the prediction circuit, and the prediction circuit is respectively connected to the storage queue, the storage buffer and the data cache; The address calculation circuit is used to calculate the load data address corresponding to the load instruction and send the load data address to the prediction circuit; The prediction circuit is used to predict whether the data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address; The prediction circuit is further configured to trigger a query of the data corresponding to the load instruction in the storage queue and the storage buffer when it is predicted that the data corresponding to the load instruction exists in the storage queue or the storage buffer.

2. The load storage unit according to claim 1, characterized in that: The prediction circuit is further used to trigger a query of the data corresponding to the load instruction in the storage queue, the storage buffer and the data cache when it is predicted that the data corresponding to the load instruction does not exist in the storage queue or the storage buffer.

3. The load storage unit according to claim 1 or 2, characterized in that: The prediction circuit includes a cache circuit, and the cache circuit is used to store fingerprint information of addresses of data in the storage queue and the storage buffer; The prediction circuit is used to calculate the fingerprint information of the load data address, match the fingerprint information of the load data address with the fingerprint information stored in the cache circuit, and when the fingerprint information of the load data address matches the fingerprint information stored in the cache circuit successfully, determine and predict that the data corresponding to the load instruction exists in the storage queue or the storage buffer.

4. The load storage unit according to claim 3, characterized in that: The cache circuit comprises a first cache and a second cache; the first cache and the second cache respectively comprise a plurality of entries; The prediction circuit is used to calculate the position of the first entry in the first cache and the position of the second entry in the second cache based on the load data address; The prediction circuit is used to match the fingerprint information of the load data address with the fingerprint information in the first entry and the second entry respectively, and when the fingerprint information of the load data address successfully matches the fingerprint information in the first entry or the second entry, determine and predict that the data corresponding to the load instruction exists in the storage queue or the storage buffer.

5. The load storage unit according to claim 4, characterized in that: The prediction circuit is used to perform hash calculation on the address portion of the loaded data address that is higher than the cache line granularity to obtain fingerprint information of the loaded data address.

6. The load storage unit according to claim 4, characterized in that: The prediction circuit is used to calculate the address portion of the load data address that is higher than the cache line granularity based on the first position function of the cuckoo filter to obtain the position of the first entry; The prediction circuit is used to calculate the address portion of the load data address that is higher than the cache line granularity based on the second position function of the cuckoo filter to obtain the position of the second entry.

7. The load storage unit according to claim 4, characterized in that: The prediction circuit is further configured to, in response to the first data being written into the storage queue, perform a hash calculation on an address portion of the first data that is higher than a cache line granularity, to obtain fingerprint information of the address of the first data; The prediction circuit is further used to calculate the address portion of the first data that is higher than the cache line granularity through the first position function of the cuckoo filter to obtain the position of the third entry in the first cache; The prediction circuit is further configured to store fingerprint information of the address of the first data into the third entry.

8. The load-store unit according to claim 7, characterized in that: The prediction circuit is further configured to remove the first fingerprint information from the third entry in response to the first fingerprint information already existing in the third entry; The prediction circuit is further used to calculate the address portion of the data corresponding to the first fingerprint information that is higher than the cache line granularity through the second position function of the cuckoo filter to obtain the position of the fourth entry in the second cache; The prediction circuit is further configured to store the first fingerprint information into the fourth entry.

9. The load storage unit according to claim 8, characterized in that: The prediction circuit is further configured to remove the second fingerprint information from the fourth entry in response to the second fingerprint information already existing in the fourth entry.

10. The load storage unit according to claim 7, characterized in that: The entry includes a fingerprint field and a bitmap field; the bitmap field includes N bits, each bit corresponds to an address range of cache line granularity / N; N is an integer greater than or equal to 2; The prediction circuit is further used to determine, when the fingerprint information of the address of the first data is stored in the third entry, that the address portion of the address of the first data that is lower than the cache line granularity corresponds to the target bit in the bitmap field, and set the target bit in the third entry to a first value.

11. The load storage unit according to claim 10, characterized in that: The prediction circuit is further configured to, in response to the second data being removed from the storage buffer, perform a hash calculation on an address portion of the second data that is higher than a cache line granularity to obtain fingerprint information of the address of the second data; The prediction circuit is further configured to calculate a position of a fifth entry in the first cache and a position of a sixth entry in the second cache based on an address of the second data; The prediction circuit is used to match the fingerprint information of the address of the second data with the fingerprint information in the fifth entry and the sixth entry respectively, and if the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry, remove the successfully matched fingerprint information.

12. The load-store unit according to claim 11, characterized in that: The prediction circuit is configured to determine that the fingerprint information of the load data address successfully matches the fingerprint information in the first entry or the second entry when the fingerprint information of the load data address is the same as the fingerprint information in the first entry or the second entry, and the address range corresponding to the bits set to the specified value in the entry with the same fingerprint information includes the address portion of the load data address that is lower than the cache line granularity; The prediction circuit is used to determine that the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry when the fingerprint information of the address of the second data is the same as the fingerprint information in the fifth entry or the sixth entry, and the address range corresponding to the bits set to the specified value in the entries with the same fingerprint information includes the address part of the address of the second data that is lower than the cache line granularity.

13. The load storage unit according to claim 12, characterized in that: The prediction circuit is used to set the bits of the address portion of the address of the second data that is lower than the cache line granularity in the bitmap field of the entry where the successfully matched fingerprint information is located to a second value when the fingerprint information of the address of the second data successfully matches the fingerprint information in the fifth entry or the sixth entry.

14. The load storage unit according to claim 1 or 2, characterized in that: The prediction circuit is used to calculate multiple positions of the load data address in the target array based on the Bloom filter algorithm, and when the values ​​of the multiple positions of the load data address in the target array are all specified values, determine and predict that the data corresponding to the load instruction exists in the storage queue or the storage buffer.

15. The load storage unit according to claim 14, characterized in that: The prediction circuit is also used to respond to the third data being written into the storage queue, calculate the addresses of the third data at multiple locations in the target array through the Bloom filter algorithm, and set the values ​​of the addresses of the third data at multiple locations in the target array to the specified values.

16. The load-store unit according to claim 1 or 2, characterized in that: The load storage unit also includes: a load reservation station and a data merging circuit; The load reservation station is connected to the address calculation circuit, the storage queue, the storage buffer and the data cache are respectively connected to the data merging circuit, and the data merging circuit is also connected to the load reservation station; The load reservation station is used to send the load instruction to the address calculation circuit; The storage queue and the storage buffer are used to send the queried data to the data merging circuit when the prediction circuit predicts that the data corresponding to the load instruction exists in the storage queue or the storage buffer; The data merging circuit is used to merge the data sent by the storage queue and the storage buffer, perform abnormality detection on the merged data, and send an abnormal instruction to the load reservation station when a data abnormality is detected; The load reservation station is used to resend the load instruction to the address calculation circuit; The prediction circuit is used to trigger a query in the data cache for data corresponding to the load instruction based on the reissued load instruction.

17. A method for processing an instruction, characterized in that: The method is performed by a load storage unit according to any one of claims 1 to 16, and the method comprises: Calculating the load data address corresponding to the load instruction through the address calculation circuit, and sending the load data address to the prediction circuit; Predicting, by the prediction circuit, whether the data corresponding to the load instruction exists in the storage queue or the storage buffer based on the load data address; When the prediction circuit predicts that the data corresponding to the load instruction exists in the storage queue or the storage buffer, a query is triggered in the storage queue and the storage buffer for the data corresponding to the load instruction.

18. A processor, characterized in that: The processor comprises at least one load-store unit according to any one of claims 1 to 16.

19. A computer device, characterized in that: The computer device comprises at least one processor, and the processor comprises at least one load-store unit according to any one of claims 1 to 16.

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