Data processing system, method, device, storage medium and computer program product for a database

Abstract

The present application relates to a data processing system, method, device, storage medium and computer program product for a database. The system includes a first FPGA, a first GPU, a CPU and a memory. Among them, the first FPGA is used to obtain a target operation instruction for the database, send the target operation instruction to the first GPU, and read first data required to execute the target operation instruction from the memory and / or the database; the first GPU is used to predict the required data of the first FPGA according to the target operation instruction and the previous operation instruction of the target operation instruction, and feedback the required data to the CPU; the CPU is used to determine target data according to the required data, obtain the target data from the database, and write the target data into the memory. Using the system provided by the present application can improve the operation efficiency for the database.

Description

Technical Field

[0001] This application relates to the field of data processing, and particularly to a data processing system, method, device, storage medium, and computer program product for a database. Background Art

[0002] In scenarios where a database needs to process a large number of high-concurrency requests, database performance becomes particularly important. If the data processing method of the database is not optimized, a series of situations such as slow storage, response latency, and even database crashes may occur, seriously affecting the security and stability of the database and causing problems in the business system. Therefore, there is a need to provide a solution that can improve the efficiency of database operations. Summary of the Invention

[0003] Based on this, in view of the above technical problems, it is necessary to provide a data processing system, method, device, storage medium, and computer program product for a database.

[0004] In a first aspect, this application provides a data processing system for a database. The system includes a first FPGA, a first GPU, a CPU, and a memory. Among them,

[0005] The first FPGA is configured to obtain a target operation instruction for the database, send the target operation instruction to the first GPU, and read first data required to execute the target operation instruction from the memory and / or the database.

[0006] The first GPU is configured to predict the required data of the first FPGA according to the target operation instruction and the previous operation instruction of the target operation instruction, and feedback the required data to the CPU.

[0007] The CPU is configured to determine target data according to the required data, obtain the target data from the database, and write the target data into the memory.

[0008] In one embodiment, the reading of the first data required to execute the target operation instruction from the memory and / or the database includes:

[0009] Reading the first data required to execute the target operation instruction from the memory, and in the case where the first data does not exist in the memory, reading the first data from the database.

[0010] In one embodiment, the first FPGA is further configured to, when obtaining multiple operation instructions for the database, determine a first target operation instruction from the multiple operation instructions, perform a merging process on each of the first target operation instructions to obtain a merged instruction, and use the merged instruction and the instructions in the multiple operation instructions other than the first target operation instruction as the target operation instructions.

[0011] In one embodiment, there are multiple pieces of demand data, and the demand data has a corresponding predicted call order; determining the target data according to the demand data includes:

[0012] Determine the historical prediction accuracy rates of the first GPU for each of the predicted call orders, and determine a target predicted call order from each of the predicted call orders according to the historical prediction accuracy rates;

[0013] Use the demand data corresponding to the target predicted call order as the target data.

[0014] In one embodiment, the demand data is predicted by a data prediction model;

[0015] The CPU is further configured to, within an accuracy evaluation period, for any one of the predicted call orders, determine the historical prediction accuracy rate corresponding to the predicted call order according to the target demand data corresponding to the predicted call order and the actual demand data corresponding to each of the target demand data by the first FPGA;

[0016] The CPU is further configured to, when the historical prediction accuracy rates corresponding to the predicted call orders do not meet the preset accuracy requirements, feedback each of the actual demand data to the first GPU;

[0017] The first GPU is further configured to adjust the data prediction model according to each of the actual demand data.

[0018] In one embodiment, the first FPGA is further configured to, when the target operation instruction is a storage instruction, generate a data table for the data to be stored, determine the time feature and data feature of the data to be stored, generate a two-dimensional hash index value of the data table according to the time feature and the data feature, and store the two-dimensional hash index value in a two-dimensional hash index table for the database.

[0019] In one embodiment, the system further includes a second FPGA;

[0020] The first FPGA is further configured to determine first data required to execute the target operation instruction according to the target operation instruction, and send a first data retrieval request to the second FPGA based on the first data;

[0021] The second FPGA is configured to retrieve original data corresponding to the first data from the memory and / or the database according to the first data retrieval request, perform decompression and / or decryption processing on the original data to obtain the first data, and send the first data to the first FPGA.

[0022] In one embodiment, the system further includes a second GPU;

[0023] The first FPGA is further configured to determine the complexity of the target operation instruction, and send the target operation instruction to the second GPU when the complexity is greater than a complexity threshold;

[0024] The second GPU is configured to execute the target operation instruction sent by the first FPGA.

[0025] In a second aspect, the present application further provides a data processing method for a database. The data processing system for the database includes a first FPGA, a first GPU, a CPU, and a memory. The first FPGA reads first data required to execute a target operation instruction for the database from the memory and / or the database. The method is applied to the first GPU and includes:

[0026] Receiving the target operation instruction sent by the first FPGA;

[0027] Predicting required data of the first FPGA according to the target operation instruction and a previous operation instruction of the target operation instruction;

[0028] Feeding back the required data to the CPU, so that the CPU determines target data according to the required data, obtains the target data from the database, and writes the target data into the memory.

[0029] In a third aspect, the present application further provides a data processing device for a database. The data processing system for the database includes a first FPGA, a first GPU, a CPU, and a memory. The first FPGA reads first data required to execute a target operation instruction for the database from the memory and / or the database. The device is applied to the first GPU and includes:

[0030] A receiving module, configured to receive the target operation instruction sent by the first FPGA;

[0031] A prediction module, configured to predict the demand data of the first FPGA according to the target operation instruction and the previous operation instruction of the target operation instruction;

[0032] A feedback module, configured to feedback the demand data to the CPU, so that the CPU determines target data according to the demand data, obtains the target data from the database, and writes the target data into the memory.

[0033] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium has a computer program stored thereon, and when the computer program is executed by a processor, the above-mentioned method is implemented.

[0034] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the above-mentioned method is implemented.

[0035] For the above-mentioned data processing system, method, device, storage medium and computer program product for the database, according to the currently executed operation instruction and the previous operation instruction that has been executed before, predict the data that needs to be retrieved from the database subsequently, and determine the target data that needs to be written into the memory with a higher read / write rate from the predicted demand data, so that the required target data can be read from the memory when the operation instruction is executed subsequently, improving the efficiency of operating the database. At the same time, the embodiments of the present application adopt a heterogeneous computing mode, use the GPU with stronger processing ability for a large amount of data to predict the demand data, use the FPGA with better performance for specific tasks to execute the operation instruction, and use the CPU with stronger performance for complex control and task scheduling to execute the step of writing the target data into the memory, which can further improve the execution efficiency of the above steps, and thus can also further improve the efficiency of operating the database. Description of the Drawings

[0036] Figure 1 It is a schematic diagram of a data processing system for a database in an embodiment;

[0037] Figure 2 It is a schematic flowchart of a CPU evaluating whether to adjust the data prediction model in an embodiment;

[0038] Figure 3 It is a schematic diagram of a database storage structure in an embodiment;

[0039] Figure 4 It is a schematic diagram of a data processing system for a database in an embodiment;

[0040] Figure 5 It is a schematic diagram of a data processing system for a database in an embodiment;

[0041] Figure 6 A schematic diagram of a data processing system for a database in an embodiment;

[0042] Figure 7 A flowchart of a data processing method for a database in an embodiment;

[0043] Figure 8 A flowchart of a data processing apparatus for a database in an embodiment. Detailed implementation manners

[0044] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] In one embodiment, as Figure 1 shown, a data processing system for a database is provided, which is characterized in that the system includes a first FPGA, a first GPU, a CPU and a memory. The first FPGA is used to obtain a target operation instruction for the database, send the target operation instruction to the first GPU, and read first data required to execute the target operation instruction from the memory and / or the database; the first GPU is used to predict required data of the first FPGA according to the target operation instruction and the previous operation instruction of the target operation instruction, and feed back the required data to the CPU; the CPU is used to determine target data according to the required data, obtain the target data from the database, and write the target data into the memory; wherein, the read / write rate of the memory is greater than the read / write rate of the database.

[0046] In the embodiments of the present application, the target operation instruction is an instruction for operating on a database. A device that needs to operate on the database can send the target operation instruction to a data processing system for the database. After the system processes the target operation instruction, it performs the operation specified by the target operation instruction on the database. The data processing system for the database consists of a first FPGA (Field Programmable Gate Array), a first GPU (Graphics Processing Unit), a CPU (Central Processing Unit), and a memory (which can be any memory with a read / write speed greater than that of the database, such as DDR memory (Double Data Rate Synchronous Dynamic Random Access Memory), DRAM (Dynamic Random Access Memory), etc., and specifically can be determined by the storage medium used by the database that needs to be operated). The first FPGA is mainly used to execute the target operation instruction, the first GPU is mainly used to run the model for predicting demand data, the CPU is mainly used to control the first FPGA and the first GPU, and to execute other functions required during the operation on the database. The first FPGA, the first GPU, and the CPU can communicate with each other. Both the first FPGA and the CPU can be connected to the memory through a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) bus and share the same memory space.

[0047] After the first FPGA receives the target operation instruction, it reads the first data required to execute the target operation instruction and sends the target operation instruction to the first GPU. For example, when the target operation instruction is to read data from a data table, the first data required to execute the target operation instruction is the data table to be read. When the target operation instruction is to merge two tables, the first data required to execute the target operation instruction is the two tables to be merged. In one embodiment, the first FPGA can receive multiple operation instructions at one time. When obtaining multiple operation instructions for the database, the first FPGA determines the first target operation instruction (that is, each operation instruction that can be merged) from the multiple operation instructions, performs a merge process on each first target operation instruction to obtain a merge instruction, and uses the merge instruction and the instructions other than the first target operation instruction in the multiple operation instructions as the target operation instruction. For example, when the operation instruction is an SQL instruction, the read operations for different tables can be merged into one SQL statement, and the insert operations for different tables can also be merged into one SQL statement. After all the operation instructions that can be merged are merged into a merge instruction, the first FPGA uses the merge instruction and other unmerged operation instructions as the target operation instructions respectively.

[0048] The first FPGA can retrieve the first data in the database and the memory simultaneously. Since the first GPU has predicted the required data that the first FPGA may need when executing the operation instruction before, and the CPU reads the data predicted by the first GPU from the database and writes it into the memory, there is a high probability that the first data exists in the memory. In the case where the first GPU's prediction is incorrect, the first data may not exist in the memory, or only part of the first data exists. In one embodiment, the first FPGA can read the first data required to execute the target operation instruction from the memory, and when the first data does not exist in the memory, read the first data from the database. In another embodiment, if the first FPGA reads the second data (the second data is part of the first data) from the memory, it determines the third data that needs to be read from the memory based on the first data and the second data, and reads the third data from the database, so as to obtain all the first data required for the first FPGA to execute the target operation instruction.

[0049] After the first FPGA reads the first data, it executes the target operation instruction. The first FPGA also sends the target operation instruction to the first GPU, so that the first GPU can predict the required data for the first FPGA to execute the next operation instruction according to the previous operation instruction and the target operation instruction. The previous operation instruction refers to each operation instruction executed by the first FPGA before executing the target operation instruction. Specifically, how many previously executed operation instructions are used as the previous operation instruction can be determined according to the input required by the prediction model used by the first GPU. The required data can be the data required for the first FPGA to execute the subsequent 1 or N operation instructions.

[0050] Since the types of operations that the device for operating the external database needs to perform are usually fixed, there is a regularity in the order of data calls by the external device. The first GPU can predict the required data based on this regularity. For example, if the current operation of the device that needs to operate the external database is to calculate the average call duration of users in a certain area last year and then write the average call duration into another table, the order in which the device issues operation instructions is generally as follows: first, read the users in a certain area and their corresponding IDs from the data table storing user information, then, according to the user IDs, read the call durations corresponding to these user IDs from the call duration data tables for each month last year, calculate the average call duration, and finally, call the data table storing the average call duration and write the calculated average call duration into this table. Therefore, after the first GPU sequentially receives the operation instructions to read user IDs, the operation instructions to read call durations from the call duration data table for January last year, and the operation instructions to read call durations from the call duration data table for February last year, it can predict that the next operation instructions will most likely require the call duration data tables for March to December last year based on these operation instructions. The first GPU can use a trained data prediction model to predict the required data for the system in the future. The various previous operation instructions can be combined into an instruction sequence in the order in which the first GPU receives them, and the instruction sequence is input into the data prediction model to obtain the required data. If the required data is the data required for the first FPGA to execute N operation instructions, the required data output by the model can be a data sequence, where each required data is arranged in the order of predicted call (predicted call order). If the predicted call order of the required data is 1, it means that the model predicts that the first operation instruction to be executed by the first FPGA later will call this required data, and so on. Since the first GPU makes a prediction of the required data every time it obtains a target operation instruction, when predicting N required data at a time, the required data with a predicted call order of n in the previous prediction and the required data with a predicted call order of n - 1 in the current prediction are the required data predicted by the model for the same operation instruction. The embodiments of the present application do not specifically limit the structure of the data prediction model, and any model that can predict subsequent data on the sequence based on the data sequence is applicable to the embodiments of the present application. For example: bidirectional recurrent network, recurrent neural network, etc.

[0051] After the first GPU predicts the demand data, it sends the demand data to the CPU. The CPU can determine the target data that actually needs to be loaded into the memory from the demand data. For example, in the case where some of the demand data already exists in the memory, the CPU can use the data in the demand data other than the data that already exists in the memory as the target data. In one embodiment, the CPU determines the remaining storage space of the memory. When the total data size of the demand data is less than or equal to the size of the remaining storage space, all the demand data is used as the target data. Or when the total data size of the demand data is greater than the remaining storage space, the demand data is used as the target data in the order from near to far according to the predicted call order until the total amount of the target data reaches the size of the remaining storage space. In the process of using the demand data as the target data, the CPU can calculate whether the data volume size of the target data will exceed the size of the remaining storage space before using each demand data as the target data. If not, the demand data can be used as the target data. If so, the CPU does not use the demand data as the target data and terminates the process of sequentially using the demand data as the target data.

[0052] In another embodiment, the CPU determines the historical prediction accuracy rate of the first GPU according to the actual call data and the corresponding demand data for each execution of the operation instruction by the first FPGA, and determines the number of target data according to the historical prediction accuracy rate, such that the number of target data is proportional to the historical prediction accuracy rate, and uses the number of demand data of the target data with the closest predicted call order in the demand data as the target data. This is to ensure that in the case of a low historical prediction accuracy rate, only a small amount of data in the database is written into the memory, avoiding the situation where a large amount of data that the first FPGA actually does not need to use occupies the memory space. In the case where the historical prediction accuracy rate is lower than the threshold, the CPU can also retrain and adjust the data prediction model used by the first GPU according to the data actually called by the first FPGA each time and the data predicted by the first GPU that the first FPGA needs to call.

[0053] In another embodiment, the CPU is further configured to determine the historical prediction accuracy of the first GPU for each predicted call order respectively, and determine a target predicted call order from each predicted call order according to the historical prediction accuracy; and use the demand data corresponding to the target predicted call order as the target data. In the embodiments of the present application, the CPU can determine the historical prediction accuracy for each predicted call order respectively. Generally speaking, the data prediction model has a higher prediction accuracy for relatively recent predicted call orders and a lower prediction accuracy for relatively distant predicted call orders. A historical prediction accuracy threshold can be preset, and the predicted call order with a historical prediction accuracy greater than the historical prediction accuracy threshold is used as the target predicted call order, and the demand data corresponding to the target predicted call order in the demand data is used as the target data, so as to achieve the effect of avoiding a large amount of data that the first FPGA actually does not need to use from occupying the memory space as well.

[0054] In one embodiment, as Figure 2 shown, the CPU is further configured to, within an accuracy evaluation period, for any predicted call order, determine the historical prediction accuracy of the predicted call order according to the respective target demand data corresponding to the predicted call order and the actual demand data of the first FPGA corresponding to each target demand data; the CPU is further configured to, when the historical prediction accuracies corresponding to the respective predicted call orders do not meet the preset accuracy requirements, feedback each actual demand data to the first GPU; the first GPU is further configured to adjust the data prediction model according to each actual demand data. In the embodiments of the present application, the CPU collects the actual demand data actually called by the first FPGA when executing each target operation instruction within an accuracy evaluation period. The above data can be fed back from the first FPGA to the CPU. After an accuracy evaluation period ends, the CPU determines, for each predicted call order, the target demand data corresponding to the predicted call order among all the demand data predicted by the first GPU during this period, and determines the actual demand data corresponding to the target demand data. According to whether the target demand data matches the actual demand data, the historical prediction accuracy of the predicted call order is determined. If the historical accuracy of the data prediction model within an accuracy evaluation period does not meet the preset accuracy requirements (the specific requirements can be set by those skilled in the art according to actual needs. For example, an accuracy threshold can be set for each predicted call order respectively, and the preset accuracy requirements can be set such that the historical prediction accuracies of at least a preset proportion of the predicted call orders are greater than the corresponding thresholds, or set such that the historical prediction accuracies of the m predicted call orders closest to the predicted call order are greater than the corresponding thresholds, etc.), then the CPU can send the actual demand data to the first GPU so that the first GPU retrains the data prediction model according to the actual demand data corresponding to each target demand data to improve the prediction accuracy of the first GPU.

[0055] In one embodiment, the CPU determines the frequency at which each target data in the memory is called. For any target data, when the frequency at which the target data is called is less than the frequency threshold, the CPU deletes the target data from the memory. That is, the CPU can determine which target data should be deleted based on the frequency at which the first FPGA uses each target data in the memory, thereby releasing the space of the memory.

[0056] In one embodiment, the first FPGA is further configured to generate a data table for the data to be stored when the target operation instruction is a storage instruction, determine the time characteristics and data characteristics of the data to be stored, generate a two-dimensional hash index value of the data table according to the time characteristics and data characteristics, and store the two-dimensional hash index value in the two-dimensional hash index table for the database.

[0057] In the embodiments of the present application, the data tables in the database can be managed through the two-dimensional hash index table. When data needs to be stored in the database, the first FPGA can extract the time characteristics (such as the date, month, or year when the data to be stored is generated) and data characteristics (such as the type and source area of the data to be stored) of the data to be stored, generate a two-dimensional hash index value of the data table where the data to be stored is located according to the time characteristics and data characteristics, and store the index value in the two-dimensional hash index table. Subsequently, when the user inputs the time characteristics and data characteristics of the data to be stored, the system can calculate the two-dimensional hash index value of the data table that the user needs to search according to these two characteristics, and find the storage location of the data table corresponding to the two-dimensional hash index value from the two-dimensional hash index table, so as to quickly find the data table where the data to be stored is located from the database. As Figure 3 shown, it is the storage structure of the database when the data characteristic is the source area of the data to be stored.

[0058] In one embodiment, after the data to be stored is written into the newly generated data table for the data to be stored, the first FPGA writes the data table into the memory. The CPU can monitor whether the data table in the memory meets a preset condition. When the data table meets the preset condition, the CPU writes the data table into the database. This is because when an external device stores data, it usually writes to a certain data table continuously for multiple times. Therefore, the data table can be temporarily stored in the memory as an in-memory table to facilitate the first FPGA to call the data table when storing data. The preset condition can be set by the external device and transmitted to the CPU. For example, when the requirement of the external device is to write the data of each month into the same table, if the data to be stored transmitted by the external device changes from the data of a certain month to the data of the next month, the CPU can consider that the data of a certain month has been transmitted, convert the data table corresponding to the data of a certain month into a pre-stored table, and then write the pre-stored table into the storage device where the database is located when the condition for storing the pre-stored table in the database is also met.

[0059] In one embodiment, the CPU determines the service type corresponding to the data to be stored, and determines the number of database connections and the database storage engine according to the service type. The external device may transmit the service type to the CPU. The maximum number of database connections corresponding to the service type and the database storage engine corresponding to the service type may be pre-stored in the CPU. According to the pre-stored data above, the number of connections to the database is set according to the maximum number of database connections, and the storage engine used when performing a storage operation on the database is set according to the database storage engine corresponding to the service type. For example, in the case where the database is a MySQL database, the storage engines supported by the MySQL database may include InnoDB or MyISAM. The InnoDB storage engine is suitable for the resource configuration library, supports transactions, row-level locks, and foreign keys. The MyISAM storage engine is suitable for the historical query library, has a high insertion and query speed, but does not support transactions and foreign keys. Technical personnel can pre-determine the storage engine corresponding to the service type according to the characteristics of the service, and the CPU then selects InnoDB or MyISAM as the storage engine used when writing data into the database.

[0060] In one embodiment, as Figure 4 shown, the system further includes a second FPGA. The first FPGA is further configured to determine the first data required to execute the target operation instruction according to the target operation instruction, and send a first data retrieval request to the second FPGA based on the first data; the second FPGA is configured to retrieve the original data corresponding to the first data from the memory and / or the database according to the first data retrieval request, perform decompression and / or decryption processing on the original data to obtain the first data, and send the first data to the first FPGA.

[0061] In the embodiment of the present application, since the data in the database may be compressed or encrypted, a second FPGA may be set to specifically perform decompression or decryption processing on the first data. In this case, the first FPGA may be programmed as an FPGA dedicated to executing operation instructions, and the second FPGA may be programmed as an FPGA dedicated to decompressing or decrypting data, so as to utilize the characteristic that the FPGA has strong single-task execution ability and further improve the efficiency of operating the database. After determining the first data, the first FPGA sends the first data to be retrieved to the second FPGA. The second FPGA is responsible for reading the compressed or encrypted original data corresponding to the first data from the memory or the database, performing decompression or decryption processing on the original data to obtain the first data, and returning the first data to the first FPGA, so that the first FPGA can execute the target operation instruction according to the first data.

[0062] In one embodiment, as Figure 5As shown in the figure, the system further includes a second GPU; the first FPGA is further configured to determine the complexity of the target operation instruction, and when the complexity is greater than the complexity threshold, send the target operation instruction to the second GPU; the second GPU is configured to execute the target operation instruction sent by the first FPGA. In the embodiments of the present application, a second GPU can be set in the system to accelerate the processing of complex operation instructions. The complexity can be determined according to the number of the first data required by the target operation instruction or the length of the target operation instruction. The more the number of the first data required by the target operation instruction and the longer the length of the target operation instruction, the higher the complexity of the operation instruction. When the complexity of the target operation instruction is greater than the threshold, the first FPGA forwards the target operation instruction to the second GPU, and the second GPU performs execution processing on the target operation instruction. The second GPU can also send the target operation instruction to the first GPU so that the first GPU predicts the required data according to the target operation instruction, and can also send a first data retrieval request to the second FPGA so that the second FPGA sends the decompressed or decrypted first data to the second GPU.

[0063] In one embodiment, as Figure 6 shown, the memory is a DDR memory, and the system further includes a DMA (Direct Memory Access) controller and a Nand-flash memory. The CPU is further configured to obtain the target operation instruction and write the target operation instruction into the DDR memory through the DMA controller and the Nand-flash memory. Both the first FPGA and the CPU can read and write data from the DDR memory.

[0064] In one embodiment, as Figure 7 shown, a data processing method for a database is provided. In the embodiments of the present application, this method is described by taking the first GPU in the data processing system for the database as an example, including: Figure 1 receiving the target operation instruction sent by the first FPGA;

[0065] Step 702, receiving the target operation instruction sent by the first FPGA;

[0066] Step 704, predicting the required data of the first FPGA according to the target operation instruction and the previous operation instruction of the target operation instruction;

[0067] Step 706, feeding back the required data to the CPU so that the CPU determines the target data according to the required data, obtains the target data from the database, and writes the target data into the memory.

[0068] In the embodiment of the present application, after the first GPU receives the target operation instruction for the database sent by the first FPGA, it can predict the required data for the subsequent execution instructions of the system based on the target operation instruction and the previous operation instruction of the target operation instruction, and send the required data to the CPU, so that the CPU can determine the target data actually needed to be written into the memory according to the required data, obtain the target data from the database, and write the target data into the memory, so that when the subsequent operation instruction is executed, the first FPGA can obtain the first data required by the operation instruction from the memory instead of the database, thereby accelerating the operation speed for the database. The specific execution manners of each step can refer to the relevant descriptions of the foregoing embodiments, and the embodiments of the present application will not be elaborated herein.

[0069] The data processing method for the database provided by the embodiment of the present application predicts the data to be retrieved from the database subsequently by the GPU according to the currently executed operation instruction and the previous operation instruction that has been executed, so that the CPU can determine the target data that needs to be written into the memory with a higher read-write rate from the predicted required data, so that when the subsequent operation instruction is executed, the FPGA can read the required target data from the memory, improving the efficiency of operating the database.

[0070] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the indications of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0071] Based on the same inventive concept, the embodiment of the present application further provides a data processing device for the database for implementing the above-mentioned data processing method for the database. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the data processing device for the database provided below can refer to the limitations on the data processing method for the database in the foregoing text, and will not be elaborated herein.

[0072] In one embodiment, as Figure 8As shown, a data processing device 800 for a database is provided. The data processing system for the database includes a first FPGA, a first GPU, a CPU, and a memory. The first FPGA reads first data required to execute target operation instructions for the database from the memory and / or the database. The device is applied to the first GPU and includes: a receiving module 802, a prediction module 804, and a feedback module 806, where:

[0073] The receiving module 802 is configured to receive the target operation instructions sent by the first FPGA;

[0074] The prediction module 804 is configured to predict the required data of the first FPGA according to the target operation instructions and the previous operation instructions of the target operation instructions;

[0075] The feedback module 806 is configured to feedback the required data to the CPU, so that the CPU determines target data according to the required data, obtains the target data from the database, and writes the target data into the memory.

[0076] In the data processing device for the database provided by the embodiments of the present application, the GPU predicts the data that needs to be retrieved from the database subsequently according to the currently executed operation instructions and the previous operation instructions that have been executed, so that the CPU can determine the target data that needs to be written into the memory with a higher read / write rate from the predicted required data, so that the FPGA can read the required target data from the memory when executing the operation instructions subsequently, improving the efficiency of operating the database.

[0077] Each module in the above device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or be independent of it, or can be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0078] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0079] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0080] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data that have been authorized by the user or fully authorized by all parties.

[0081] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0082] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0083] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A data processing system for a database, characterized in that: The system includes a first FPGA, a first GPU, a CPU and a memory, wherein: The first FPGA is used to obtain a target operation instruction for a database, send the target operation instruction to the first GPU, and read first data required to execute the target operation instruction from the memory and / or the database; The first GPU is used to predict the required data of the first FPGA according to the target operation instruction and the preceding operation instruction of the target operation instruction, and feed the required data back to the CPU; The CPU is used to determine target data according to the demand data, obtain the target data from the database, and write the target data into the memory.

2. The system according to claim 1, characterized in that The step of reading the first data required for executing the target operation instruction from the memory and / or the database includes: The first data required for executing the target operation instruction is read from the memory, and when the first data does not exist in the memory, the first data is read from the database.

3. The system according to claim 1, characterized in that The first FPGA is also used to determine a first target operation instruction from the multiple operation instructions when multiple operation instructions for the database are obtained, merge the first target operation instructions to obtain a merged instruction, and use the merged instruction and the instructions in the multiple operation instructions except the first target operation instruction as the target operation instruction.

4. The system according to claim 1, characterized in that There are multiple demand data, and the demand data have a corresponding prediction call order; and determining the target data according to the demand data includes: Determine the historical prediction accuracy of the first GPU for each of the prediction call sequences, and determine a target prediction call sequence from each of the prediction call sequences according to the historical prediction accuracy; The demand data corresponding to the target prediction calling sequence is used as the target data.

5. The system according to claim 4, characterized in that The demand data is obtained by prediction through a data prediction model; The CPU is further configured to determine, within an accuracy evaluation cycle, for any of the predicted call sequences, a historical prediction accuracy corresponding to the predicted call sequence according to each target demand data corresponding to the predicted call sequence and actual demand data of the first FPGA corresponding to each target demand data; The CPU is further configured to feed back each of the actual demand data to the first GPU when the historical prediction accuracy corresponding to each of the prediction call sequences does not meet a preset accuracy requirement; The first GPU is further configured to adjust the data prediction model according to each of the actual demand data.

6. The system according to claim 1, characterized in that The first FPGA is also used to generate a data table for the data to be stored when the target operation instruction is a storage instruction, and determine the time characteristics and data characteristics of the data to be stored, generate a two-dimensional hash index value of the data table according to the time characteristics and the data characteristics, and store the two-dimensional hash index value in the two-dimensional hash index table for the database.

7. The system according to claim 1, characterized in that The system also includes a second FPGA; The first FPGA is further used to determine first data required to execute the target operation instruction according to the target operation instruction, and send a first data retrieval request to the second FPGA based on the first data; The second FPGA is used to retrieve the original data corresponding to the first data from the memory and / or the database according to the first data retrieval request, decompress and / or decrypt the original data to obtain the first data, and send the first data to the first FPGA.

8. The system according to claim 1, characterized in that The system also includes a second GPU; The first FPGA is further used to determine the complexity of the target operation instruction, and send the target operation instruction to the second GPU if the complexity is greater than a complexity threshold; The second GPU is used to execute the target operation instruction sent by the first FPGA.

9. A data processing method for a database, characterized in that: The data processing system for a database includes a first FPGA, a first GPU, a CPU, and a memory. The first FPGA reads first data required to execute a target operation instruction for the database from the memory and / or the database. The method is applied to the first GPU and includes: Receiving the target operation instruction sent by the first FPGA; Predicting required data of the first FPGA according to the target operation instruction and a preceding operation instruction of the target operation instruction; The demand data is fed back to the CPU, so that the CPU determines the target data according to the demand data, obtains the target data from a database, and writes the target data into a memory.

10. A data processing device for a database, characterized in that: The data processing system for a database includes a first FPGA, a first GPU, a CPU and a memory, wherein the first FPGA reads first data required to execute a target operation instruction for the database from the memory and / or the database, and the device is applied to the first GPU, including: A receiving module, used for receiving the target operation instruction sent by the first FPGA; A prediction module, configured to predict the required data of the first FPGA according to the target operation instruction and a preceding operation instruction of the target operation instruction; The feedback module is used to feed back the demand data to the CPU, so that the CPU determines the target data according to the demand data, obtains the target data from the database, and writes the target data into the memory.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 9 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to claim 9 are implemented.

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