Display device

Abstract

A display device includes a pixel including a pixel driving circuit and a light emitting element, a sensor including a sensor driving circuit and a sensing element, and a display panel in which a display area is defined. The display device includes a display area including a first area and a second area, and a sensor driving circuit connected to the sensing element and including a reset transistor including a gate electrode receiving a reset control signal, the reset control signal includes a first reset control signal and a second reset control signal different from the first reset control signal, and the first reset control signal is supplied to the reset transistor disposed in the first region. And the second reset control signal is supplied to the reset transistor disposed in the second region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0075786, filed on Jun. 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device, and more particularly, to a display device capable of detecting illuminance for each display panel position. Background Art

[0004] The display device displays an image to provide information to the user or provides various functions capable of organically communicating with the user, such as a function of sensing the user's input. Recent display devices also include a function for detecting information provided by the user (e.g., biometric information). In addition, recent display devices include a function for detecting ambient brightness. That is, the display device includes a sensor for detecting fingerprints, and / or the illumination method for identifying user information includes a capacitive method for detecting a capacitance change generated between electrodes, an optical method for detecting incident light using an optical sensor, and an ultrasonic method for detecting vibrations using a piezoelectric material or the like. Summary of the invention

[0005] Embodiments of the present disclosure provide a display device capable of detecting illuminance for each display panel position.

[0006] In an embodiment of the present disclosure, a display device includes: a pixel including a pixel driving circuit and a light-emitting element; a sensor including a sensor driving circuit and a sensing element; and a display panel having a display area defined therein, wherein the display area includes a first area and a second area adjacent to the first area, the sensor driving circuit is electrically connected to the sensing element and includes a reset transistor, the reset transistor includes a gate electrode for receiving a reset control signal, the reset control signal includes a first reset control signal and a second reset control signal different from the first reset control signal, and the first reset control signal is provided to the reset transistor disposed in the first area, and the second reset control signal is provided to the reset transistor disposed in the second area.

[0007] In an embodiment, the sensor may include a plurality of sensors, and the plurality of sensors may include a first sensor disposed in the first area and a second sensor disposed in the second area.

[0008] In an embodiment, the first sensor may sense a fingerprint, and the second sensor may sense illumination.

[0009] In an embodiment, the second area may include a first sensing area and a second sensing area spaced apart from the first sensing area in a predetermined direction, and a falling time point of the second reset control signal provided to the first sensing area may be different from a falling time point of the second reset control signal provided to the second sensing area.

[0010] In an embodiment, the second reset control signal provided to the second sensing region may be delayed by a first interval than the second reset control signal provided to the first sensing region.

[0011] In an embodiment, the second region may further include a third sensing region, the third sensing region being spaced apart from the first sensing region in the predetermined direction, the second sensing region being interposed between the first sensing region and the third sensing region. The second reset control signal provided to the third sensing region may be delayed by a second interval than the second reset control signal provided to the first sensing region. The second interval may be longer than the first interval.

[0012] In an embodiment, the reset transistor may further include a first electrode receiving a reset voltage and a second electrode connected to the first sensing node. The sensor driving circuit of the second sensor may further include: an amplifying transistor including a first electrode receiving a sensing driving voltage, a second electrode connected to the second sensing node, and a gate electrode connected to the first sensing node; and an output transistor including a first electrode connected to the second sensing node, a second electrode connected to a readout line, and a gate electrode receiving an output control signal.

[0013] In an embodiment, the output control signal may be provided during an output interval. A first reset interval does not overlap with the output interval, the second reset control signal provided to the first sensing region is provided in the first reset interval, and a second reset interval overlaps with the output interval, the second reset control signal provided to the second sensing region is provided in the second reset interval.

[0014] In an embodiment, the output interval may include a first output interval and a second output interval in succession. The second sensor outputs a signal corresponding to a first illuminance of the first sensing area during the first output interval, and the second sensor outputs a signal corresponding to a second illuminance of the second sensing area during the second output interval.

[0015] In an embodiment, the display device may further include: a driving circuit driving the display panel, and the driving circuit may detect external brightness based on one of the first illuminance and the second illuminance.

[0016] In an embodiment, the display panel may further include a plurality of data lines electrically connected to the pixels. The drive circuit may include a data driver that outputs data signals to the plurality of data lines. The data driver may operate in a blanking interval in which the data signals are not output to the plurality of data lines and in an effective interval in which the data signals are output to the plurality of data lines.

[0017] In an embodiment, the first reset interval may overlap with the blanking interval, and the second reset interval may overlap with the active interval.

[0018] In an embodiment, a pulse width of the second reset control signal may be narrower than a pulse width of the first reset control signal.

[0019] In an embodiment, a display device includes: a pixel including a pixel driving circuit and a light-emitting element; a sensor including a sensor driving circuit and a sensing element; and a display panel in which a display area is defined, wherein the display area includes a first area and a second area adjacent to the first area, the second area includes a first sensing area and a second sensing area spaced apart from the first sensing area in a predetermined direction, the sensor driving circuit is electrically connected to the sensing element and includes a reset transistor, the reset transistor includes a gate electrode receiving a reset control signal, and a falling time point of the reset control signal provided to the first sensing area is different from a falling time point of the reset control signal provided to the second sensing area.

[0020] In an embodiment, the sensor may include a plurality of sensors, and the plurality of sensors may include a first sensor disposed in the first area and a second sensor disposed in the second area. The first sensor may sense a fingerprint, and the second sensor may sense illumination.

[0021] In an embodiment, the first sensor may receive light during a first light receiving interval, and the second sensor may receive light during a second light receiving interval shorter than the first light receiving interval.

[0022] In an embodiment, the reset control signal provided to the second sensing region may be delayed by a first interval than the reset control signal provided to the first sensing region.

[0023] In an embodiment, the second region may further include a third sensing region, the third sensing region being spaced apart from the first sensing region in the predetermined direction, the second sensing region being interposed between the first sensing region and the third sensing region. The reset control signal provided to the third sensing region may be delayed by a second interval than the reset control signal provided to the first sensing region. The second interval may be longer than the first interval.

[0024] In an embodiment, the reset transistor may further include a first electrode receiving a reset voltage and a second electrode connected to a first sensing node. The sensor drive circuit may include: an amplifying transistor including a first electrode receiving a sensing drive voltage, a second electrode connected to a second sensing node, and a gate electrode connected to the first sensing node; and an output transistor including a first electrode connected to the second sensing node, a second electrode connected to a readout line, and a gate electrode receiving an output control signal.

[0025] In an embodiment, the output control signal may be provided during an output interval.The reset control signal provided to the first sensing region may not overlap with the output interval, and the reset control signal provided to the second sensing region may overlap with the output interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other embodiments, advantages and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0027] Figure 1 is a perspective view showing an embodiment of a display device according to the present disclosure.

[0028] Figure 2 is a cross-sectional view of an embodiment of a display device according to the present disclosure.

[0029] Figure 3 is a block diagram of an embodiment of a display device according to the present disclosure.

[0030] Figure 4A is an equivalent circuit diagram of an embodiment of a pixel and a sensor according to the present disclosure.

[0031] Figure 4B is a cross-sectional view of an embodiment of a display panel according to the present disclosure.

[0032] Figure 5 is a plan view showing an embodiment of a display area of ​​a display panel according to the present disclosure.

[0033] Fig. 6A is a waveform diagram for describing an embodiment of the operation of the first sensor according to the present disclosure.

[0034] Figure 6B is the image acquired by the first sensor.

[0035] Fig. 7A is a waveform diagram for describing an embodiment of the operation of the second sensor according to the present disclosure.

[0036] Figure 7B is the image acquired by the second sensor.

[0037] Figure 8 is a flowchart illustrating an embodiment of a method of driving a display device according to the present disclosure. DETAILED DESCRIPTION

[0038] In this specification, the statement that a first component (or region, layer, part, portion, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is disposed between the first component and the second component.

[0039] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effectiveness of describing the technical content. The expression "and / or" includes one or more combinations that the related components can define.

[0040] Although the terms "first", "second", etc. can be used to describe various components, the components should not be interpreted as being limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. As used herein, unless the context clearly indicates otherwise, a singular form may also include a plural form.

[0041] In addition, the terms "below", "beneath", "on", "over" and the like are used to describe the relationship between components shown in the drawings. Conceptually relative terms are described based on the directions shown in the drawings.

[0042] It will also be understood that the terms "comprising", "including", "having", etc. specify the presence of stated features, numbers, steps, operations, elements, components, or a combination thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or a combination thereof.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted as an idealized or overly formal meaning.

[0044] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0045] Figure 1 is a perspective view showing an embodiment of a display device DD according to the present disclosure. Figure 2 is a cross-sectional view of an embodiment of a display device DD according to the present disclosure.

[0046] Reference Figure 1 and Figure 2 The display device DD may be a mobile phone, a tablet computer, a car navigation system, a game console, or a wearable device, but is not limited thereto. Figure 1 An embodiment in which the display device DD is a smartphone is shown.

[0047] In addition, although in the embodiment Figure 1 , a rigid type display device DD having a bar form is shown, but the present disclosure is not particularly limited thereto. In an embodiment, for example, the display device DD may be a foldable, rollable, or slidable display device DD.

[0048] An upper surface of the display device DD may be defined as a display surface IS, and the display surface IS may have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface IS.

[0049] Hereinafter, a normal direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, the meaning of "when viewed from above the plane" may refer to "when viewed in the third direction DR3". That is, the plane may be parallel to a surface defined by the first direction DR1 and the second direction DR2.

[0050] The display surface IS may be divided into a transparent area TA and a frame area BZA. The transparent area TA may be an area in which the image IM is displayed. The user visually perceives the image IM through the transparent area TA. In the present embodiment, the transparent area TA is shown in the shape of a quadrilateral whose vertices are rounded. However, this is explained as an example. The transparent area TA may have various shapes, such as a rectangle, a circle, or a square, and may not be limited to a specific embodiment.

[0051] The border area BZA is adjacent to the transparent area TA. The border area BZA may have a predetermined color. The border area BZA may surround the transparent area TA. Therefore, the shape of the transparent area TA may be substantially defined by the border area BZA. However, this is explained as an example. The border area BZA may be provided only adjacent to one side of the transparent area TA or may be omitted.

[0052] The display device DD can sense external input applied from the outside. The external input may include various types of inputs provided from the outside of the display device DD. In an embodiment, in addition to contact with a part of the body such as the user's hand US_F, for example, the external input may include an external input (e.g., hovering) applied when the user's hand US_F is close to the display device DD or adjacent to the display device DD within a predetermined distance. In addition, the external input may be provided in various types, such as force, pressure, temperature, or light. The external input may be provided by a separate device, such as an active pen or a digital pen. In addition, the display device DD may detect biometric information of the user provided from the outside or measure the brightness of the surrounding environment.

[0053] The exterior of the display device DD may be composed of a window WM and a housing EDC. In an embodiment, the window WM and the housing EDC may be coupled to each other, and other components of the display device DD (such as a display module DM) may be accommodated therein.

[0054] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent material. In an embodiment, the window WM may include, for example, glass or plastic. The window WM may include a multilayer structure or a single-layer structure. In an embodiment, for example, the window WM may include a plurality of plastic films bonded by an adhesive or may have a glass substrate and a plastic film bonded by an adhesive.

[0055] The housing EDC may include a relatively high rigidity material. In an embodiment, for example, the housing EDC may include glass, plastic, or metal, or may include a plurality of frames and / or plates composed of any combination thereof. The housing EDC may stably protect the components of the display device DD accommodated in the internal space from external impacts. Although not shown, a battery module for supplying power required for the overall operation of the display device DD may be provided between the display module DM and the housing EDC.

[0056] Reference Figure 2 , the display device DD may include a display module DM, an adhesive layer AL, and a window WM, and the display module DM may include a display panel DP and an upper functional layer UFL.

[0057] The display panel DP may be a component that basically generates the image IM (see Figure 1). The display panel DP may be a light-emitting display panel. In an embodiment, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro light-emitting diode ("micro-LED") display panel, or a nano-LED display panel. Hereinafter, description will be made under the condition that the display panel DP is an organic light-emitting display panel.

[0058] The display panel DP may include a base layer BL, a pixel layer PXL, and an encapsulation layer TFE. The display panel DP in the embodiment of the present disclosure may be a flexible display panel or a rigid display panel. In the embodiment, for example, the display panel DP may be a foldable display panel folded around a folding axis, a rollable display panel at least partially rolled around a rotation axis, or a slidable display panel.

[0059] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and the like.

[0060] The pixel layer PXL may be disposed on the base layer BL. The pixel layer PXL may include a circuit layer DP_CL and an element layer DP_ED.

[0061] The circuit layer DP_CL may be disposed between the base layer BL and the element layer DP_ED. The circuit layer DP_CL may include at least one insulating layer and a circuit element. Below, the insulating layer included in the circuit layer DP_CL is also referred to as an "intermediate insulating layer". The intermediate insulating layer may include at least one intermediate inorganic film and at least one intermediate organic film.

[0062] The circuit elements may include: a pixel driving circuit PDC (refer to Figure 4A ), which includes a plurality of pixels PX (refer to Figure 3 ) in each; and the sensor drive circuit O_SD (reference Figure 4A ), which includes a plurality of sensors FX for recognizing external information (refer to Figure 3 ) in each of them. The circuit layer DP_CL may also include a circuit connected to the pixel driving circuit PDC (refer to Figure 4A ) and / or sensor drive circuit O_SD (refer to Figure 4A In the embodiment of the present disclosure, the plurality of sensors FX may include a first sensor FX1 (refer to Figure 5 ) and a second sensor FX2 for sensing illumination (refer to Figure 5 ), which will be described in detail later.

[0063] The element layer DP_ED may include a light emitting element ED included in each of the plurality of pixels PX (refer to Figure 4A ) and a photodetector OPD (refer to Figure 4A ). In an embodiment of the present disclosure, the photodetector OPD may be a photodiode, for example, an organic photodiode. The photodetector OPD may be a sensor that senses light reflected by the user's fingerprint or reacts to light. Figure 4B The circuit layer DP_CL and the element layer DP_ED are described in detail.

[0064] The encapsulation layer TFE encapsulates the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc., but is not particularly limited thereto. The organic film may include an organic material and may protect the element layer DP_ED from foreign objects such as dust particles.

[0065] The upper functional layer UFL may be disposed on the display panel DP. The upper functional layer UFL may be formed on the display panel DP through a continuous process, but the present disclosure is not limited thereto.

[0066] The upper functional layer UFL may include a sensor layer for detecting coordinates of an external input and an anti-reflection layer for reducing the reflectivity of external light incident from the outside. The sensor layer may be disposed on the display panel DP, and the anti-reflection layer may be disposed on the sensor layer. However, the present disclosure is not limited thereto. In an embodiment, for example, the upper functional layer UFL may include a sensor layer alone or an anti-reflection layer alone.

[0067] The anti-reflection layer may include a color filter, a black matrix, and a planarization layer. The color filter may have a predetermined arrangement. In an embodiment, for example, the color filter may be arranged in consideration of the color of the light emitted from the pixels included in the display panel DP. In another embodiment, the anti-reflection layer may include a black matrix and a reflection control layer. The reflection control layer may selectively absorb light reflected from the display panel DP and / or the inside of the electronic device or light of a predetermined wavelength band from the display panel DP and / or the incident light from the outside of the electronic device. In another embodiment, the anti-reflection layer may be a polarizing film.

[0068] The display device DD in the embodiment of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the upper functional layer UFL through the adhesive layer AL. The adhesive layer AL may include an optically clear adhesive ("OCA"), an optically clear resin ("OCR"), or a pressure sensitive adhesive ("PSA").

[0069] Figure 3 is a block diagram of an embodiment of a display device DD according to the present disclosure.

[0070] Reference Figure 3 The display device DD may include a display panel DP, a panel driver (or referred to as a driving circuit) and a driving controller 100. In an embodiment of the present disclosure, the panel driver includes a data driver 200, a scan driver 300, an emission driver 350, a voltage generator 400 and a sensor controller 500.

[0071] The display panel DP may include a transparent area TA (refer to Figure 1 ) corresponding to the display area DA and the frame area BZA (refer to Figure 1 ) corresponds to the non-display area NDA.

[0072] The display panel DP may include a plurality of pixels PX disposed in the display panel DP and a plurality of sensors FX disposed in the display panel DP. In an embodiment of the present disclosure, each of the plurality of sensors FX may be disposed between two adjacent pixels PX. The plurality of pixels PX and the plurality of sensors FX may be alternately disposed in the first direction DR1 and the second direction DR2. However, the present disclosure is not limited thereto. Two or more pixels PX may be disposed between two sensors FX adjacent to each other in the first direction DR1 among the plurality of sensors FX, or two or more pixels PX may be disposed between two sensors FX adjacent to each other in the second direction DR2 among the plurality of sensors FX.

[0073] The display panel DP may further include initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1, DL2, ... and DLm, and readout lines RL1, RL2, ... and RLh. Here, n, m and h may each be a natural number greater than 0.

[0074] Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and emission control lines EML1 to EMLn may extend in the second direction DR2. Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and emission control lines EML1 to EMLn may be arranged to be spaced apart from each other in the first direction DR1. Data lines DL1 to DLm and readout lines RL1 to RLh may extend in the first direction DR1 and may be arranged to be spaced apart from each other in the second direction DR2.

[0075] The plurality of pixels PX may be electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. In an embodiment, for example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, the number of scan lines connected to each pixel PX is not limited thereto and may be changed.

[0076] A plurality of sensors FX are electrically connected to readout lines RL1 to RLh, respectively. One sensor FX may be electrically connected to one scan line, for example, one write scan line among write scan lines SWL1 to SWLn. However, the present disclosure is not limited thereto. The number of scan lines connected to each sensor FX may be variable.

[0077] In an embodiment of the present disclosure, the number of readout lines RL1 to RLh may correspond to half the number of data lines DL1 to DLm. However, the present disclosure is not limited thereto. In an alternative embodiment, the number of readout lines RL1 to RLh may correspond to 1 / 4 or 1 / 8 of the number of data lines DL1 to DLm.

[0078] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates the image data signal DATA by converting the data format of the image signal RGB according to the interface specification with the data driver 200. The driving controller 100 outputs the first control signal SCS, the second control signal ECS, the third control signal DCS and the fourth control signal RCS.

[0079] The data driver 200 receives the third control signal DCS and the image data signal DATA from the driving controller 100. The data driver 200 converts the image data signal DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm to be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0080] The scan driver 300 receives a first control signal SCS from the drive controller 100. The scan driver 300 may output a scan signal to the scan line in response to the first control signal SCS. In an embodiment, for example, in response to the first control signal SCS, the scan driver 300 may output an initialization scan signal to the initialization scan lines SIL1 to SILn, and output a compensation scan signal to the compensation scan lines SCL1 to SCLn. In addition, in response to the first control signal SCS, the scan driver 300 may output a write scan signal to the write scan lines SWL1 to SWLn, and may output a black scan signal to the black scan lines SBL1 to SBLn.

[0081] The scan driver 300 may be disposed in the non-display area NDA of the display panel DP. However, the present disclosure is not particularly limited thereto. In an embodiment, for example, at least a portion of the scan driver 300 may be disposed in the display area DA.

[0082] The emission driver 350 may be disposed in the non-display area NDA of the display panel DP. The emission driver 350 receives the second control signal ECS from the drive controller 100. The emission driver 350 may output the emission control signal to the emission control lines EML1 to EMLn in response to the second control signal ECS. In an alternative embodiment, the scan driver 300 may be connected to the emission control lines EML1 to EMLn. In this case, the emission driver 350 may be omitted, and the scan driver 300 may output the emission control signal to the emission control lines EML1 to EMLn.

[0083] The voltage generator 400 may generate voltages required for the operation of the display panel DP. In an embodiment, the voltage generator 400 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, and a reset voltage Vrst.

[0084] The sensor controller 500 may provide the first and second reset control signals GR and GR_L1 , GR_L2 , and GR_L3 to the display panel DP through separate lines different from each other.

[0085] The first reset control signal GR may be provided to the display panel DP through the first reset control line RCL1. The second reset control signals GR_L1, GR_L2, and GR_L3 may be provided to the display panel DP through the second reset control line RCL2.

[0086] The second reset control signals GR_L1, GR_L2, and GR_L3 may include a (2-1)th reset control signal GR_L1, a (2-2)th reset control signal GR_L2, and a (2-3)th reset control signal GR_L3. The (2-1)th reset control signal GR_L1, the (2-2)th reset control signal GR_L2, and the (2-3)th reset control signal GR_L3 may be provided to different areas of the display area DA, respectively. This will be described later.

[0087] The sensor controller 500 may receive a fourth control signal RCS from the driving controller 100. The sensor controller 500 may receive sensing signals from the readout lines RL1 to RLh in response to the fourth control signal RCS. The sensor controller 500 may process the sensing signals received from the readout lines RL1 to RLh and may provide the processed detection signal S_FS to the driving controller 100.

[0088] Figure 4A : is an equivalent circuit diagram of an embodiment of a pixel PXij and a sensor FXdj according to the present disclosure. Here, i may be a natural number greater than 0 and equal to or less than m, and j may be a natural number greater than 0 and equal to or less than n.

[0089] Figure 4A An equivalent circuit diagram of one pixel PXij among a plurality of pixels PX is shown (see Figure 3 ). The circuit structure of the pixel PXij will be described below. The plurality of pixels PX have the same structure as each other, and therefore, detailed descriptions related to other pixels PX will be omitted to avoid redundancy. In addition, as an example, Figure 4A Shown in Figure 3 1 is an equivalent circuit diagram of one sensor FXdj among the plurality of sensors FX shown in FIG. 1 . The circuit structure of the sensor FXdj will be described below. The plurality of sensors FX have the same structure as each other, and therefore, detailed descriptions related to the other sensors FX will be omitted to avoid redundancy.

[0090] Reference Figure 3 and Figure 4A , also refer to Figure 1 , the pixel PXij can be connected to the i-th data line DLi among the data lines DL1 to DLm, the j-th initialization scan line SILj among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj among the compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj among the write scan lines SWL1 to SWLn, the j-th black scan line SBLj among the black scan lines SBL1 to SBLn, and the j-th emission control line EMLj among the emission control lines EML1 to EMLn.

[0091] The pixel PXij includes a light emitting element ED and a pixel driving circuit PDC. The light emitting element ED may be a light emitting diode. In an embodiment of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic emission layer, but the present disclosure is not particularly limited thereto.

[0092] The pixel driving circuit PDC includes first, second, third, fourth and fifth transistors T1, T2, T3, T4 and T5, first and second emission control transistors ET1 and ET2, and one capacitor Cst.

[0093] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be a transistor having a low temperature polycrystalline silicon ("LTPS") semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be a transistor having an oxide semiconductor layer. In an embodiment, for example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be LTPS transistors.

[0094] In detail, the display device DD (see Figure 1 ) may include a semiconductor layer including or consisting of polysilicon with relatively high reliability, and thus a high-resolution display device may be realized. Since the carrier mobility of the oxide semiconductor is relatively high and the leakage current of the oxide semiconductor is low, the voltage drop is not significant even if the driving time is long. That is, even during low-frequency driving, the color of the image does not change significantly due to the voltage drop. This means that low-frequency driving is possible. As described above, because the leakage current of the oxide semiconductor is small, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 may be implemented with an oxide semiconductor, thereby preventing the leakage current from flowing into the gate electrode and reducing power consumption.

[0095] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be P-type transistors, and the remaining transistors of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 may be N-type transistors. In an embodiment, for example, the first transistor T1, the second transistor T2, and the fifth transistor T5, and the first emission control transistor ET1 and the second emission control transistor ET2 are P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0096] The configuration of the pixel driving circuit PDC according to the present disclosure is not limited to Figure 4A The embodiment shown. Figure 4A The pixel driving circuit PDC shown in is only an example, and the configuration of the pixel driving circuit PDC may be modified and implemented. In an embodiment, for example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 and the first emission control transistor ET1 and the second emission control transistor ET2 may be a P-type transistor or an N-type transistor.

[0097] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can send the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal SBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a value similar to that input to the display device DD (refer to Figure 3 )’s image signal RGB corresponding to the voltage level.

[0098] The first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT1 and VINT2 to the pixels PXij, respectively.

[0099] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 may include a first electrode connected to the first driving voltage line VL1 via a first emission control transistor ET1, an anode AE ​​connected to the light emitting element ED via a second emission control transistor ET2 (refer to Figure 4B ) and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the capacitor Cst. The first transistor T1 may receive a data signal Di transmitted through the i-th data line DLi according to a switching operation of the second transistor T2, and then may supply a driving current Id to the light emitting element ED.

[0100] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 may be turned on according to a write scan signal SWj transmitted through the j-th write scan line SWLj, and then may transmit an i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0101] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 may be turned on according to the j-th compensation scan signal SCj transmitted through the j-th compensation scan line SCLj, and then the third electrode and the second electrode of the first transistor T1 may be connected. In this case, the first transistor T1 may be diode-connected.

[0102] The fourth transistor T4 is connected between the first initialization voltage line VL3 to which the first initialization voltage VINT1 is applied and the first node N1. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT1 is applied, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line SILj. The fourth transistor T4 is turned on according to the jth initialization scan signal SIj transmitted through the jth initialization scan line SILj. The fourth transistor T4 thus turned on transmits the first initialization voltage VINT1 to the first node N1, so that the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1) is initialized.

[0103] The first emission control transistor ET1 may include a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0104] The second emission control transistor ET2 may include a first electrode connected to the second electrode of the first transistor T1, an anode AE ​​connected to the light emitting element ED (refer to Figure 4B ) and a second electrode (eg, a gate electrode) connected to a j-th emission control line EMLj.

[0105] The first emission control transistor ET1 and the second emission control transistor ET2 may be simultaneously turned on according to the jth emission control signal EMj transmitted through the jth emission control line EMLj. The first driving voltage ELVDD applied through the turned-on first emission control transistor ET1 may be compensated by the diode-connected first transistor T1 and then may be transmitted to the light emitting element ED.

[0106] The fifth transistor T5 may include a first electrode connected to a second initialization voltage line VL4 transmitting a second initialization voltage VINT2, a second electrode connected to a second electrode of the second emission control transistor ET2, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line SBLj. The voltage level of the second initialization voltage VINT2 may be lower than or equal to the voltage level of the first initialization voltage VINT1.

[0107] As described above, one end of the capacitor Cst is connected to the third electrode of the first transistor T1, and the opposite end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The voltage level of the second driving voltage ELVSS may be lower than the voltage level of the first driving voltage ELVDD.

[0108] The sensor FX may be connected to the dth readout line RLd among the readout lines RL1 to RLh, the jth write scan line SWLj (or output control line), and the reset control line RCL. Here, d is a natural number greater than 0 and equal to or less than h.

[0109] The sensor FX may include a photodetector OPD (or referred to as a sensing element) and a sensor driving circuit O_SD.

[0110] The photodetector OPD may be a photodiode. In an embodiment of the present disclosure, the photodetector OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. The anode AE1 (refer to Figure 4B ) can be connected to the first sensing node SN1. The cathode CE of the photodetector OPD (refer to Figure 4B ) can be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS. Figure 4A In the embodiment, the sensor FXdj includes one photodetector OPD, but is not particularly limited thereto. In the embodiment, the sensor FXdj may include z photodetectors connected in parallel. Here, "z" may be, for example, an integer of 2 or more.

[0111] The sensor driving circuit O_SD may include three transistors ST1 to ST3. The three transistors ST1 to ST3 may include a reset transistor ST1, an amplifying transistor ST2, and an output transistor ST3. At least one of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be an oxide semiconductor transistor. In an embodiment of the present disclosure, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifying transistor ST2 and the output transistor ST3 may be LTPS transistors. However, the present disclosure is not limited thereto. In an embodiment, for example, at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifying transistor ST2 may be an LTPS semiconductor transistor.

[0112] In addition, some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and the other transistors may be N-type transistors. In an embodiment of the present disclosure, the amplifying transistor ST2 and the output transistor ST3 may be P-type transistors, and the reset transistor ST1 may be an N-type transistor. However, the present disclosure is not limited thereto. In an embodiment, for example, all transistors ST1, ST2, and ST3 may be N-type transistors or P-type transistors.

[0113] Reference Figure 3 and Figure 4A , also refer to Figure 1 The reset transistor ST1 may include a first electrode connected to the third initialization voltage line VL5 to receive the reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode receiving the reset control signal RST. The third electrode may also be referred to as a “gate electrode”.

[0114] A second electrode of the reset transistor ST1 may be electrically connected to the photodetector OPD.

[0115] The reset transistor ST1 may reset the potential of the first sensing node SN1 to a reset voltage Vrst in response to a reset control signal RST. The reset control signal RST may be a signal provided by a reset control line RCL. The reset control signal RST may include a first reset control signal GR and second reset control signals GR_L1, GR_L2, and GR_L3. The reset control line RCL may include a first reset control line RCL1 and a second reset control line RCL2 different from the first reset control line RCL1. The first reset control signal GR may be provided to the first reset control line RCL1. The second reset control signals GR_L1, GR_L2, and GR_L3 may be provided to the second reset control line RCL2. That is, the first reset control signal GR and the second reset control signals GR_L1, GR_L2, and GR_L3 may be signals provided by different reset control lines RCL1 and RCL2.

[0116] The amplifier transistor ST2 may include a first electrode receiving a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplifier transistor ST2 may be turned on according to the potential of the first sensing node SN1, and the sensing drive voltage SLVD may be applied to the second sensing node SN2. In an embodiment of the present disclosure, the sensing drive voltage SLVD may correspond to the first drive voltage ELVDD and one of the first initialization voltage VINT1 and the second initialization voltage VINT2. When the sensing drive voltage SLVD is the first drive voltage ELVDD, the first electrode of the amplifier transistor ST2 may be electrically connected to the first drive voltage line VL1. When the sensing drive voltage SLVD is the first initialization voltage VINT1, the first electrode of the amplifier transistor ST2 may be electrically connected to the first initialization voltage line VL3; when the sensing drive voltage SLVD corresponds to the second initialization voltage VINT2, the first electrode of the amplifier transistor ST2 may be electrically connected to the second initialization voltage line VL4.

[0117] The output transistor ST3 may include a first electrode connected to the second sensing node SN2, a second electrode connected to the dth readout line RLd, and a third electrode receiving an output control signal. The output transistor ST3 may transmit the readout signal FSd to the dth readout line RLd in response to the output control signal. The output control signal may be the jth write scan signal SWj (or referred to as the jth output control signal) supplied through the jth write scan line SWLj. That is, the output transistor ST3 may receive the jth write scan signal SWj supplied from the jth write scan line SWLj as the output control signal.

[0118] The reset interval may be defined as a rising interval (i.e., a high level interval) of the reset control line RCL. When a reset control signal RST having a relatively high level is supplied through the reset control line RCL, the reset transistor ST1 may be turned on. In an alternative embodiment, when the reset transistor ST1 includes a P-channel metal oxide semiconductor ("PMOS") transistor or is composed of a P-channel metal oxide semiconductor ("PMOS") transistor, during the reset interval, a reset control signal RST having a relatively low level may be supplied to the reset control line RCL. During the reset interval, the first sensing node SN1 may be reset to a potential corresponding to the reset voltage Vrst. In an embodiment of the present disclosure, the reset voltage Vrst may have a voltage level lower than the voltage level of the second drive voltage ELVSS.

[0119] The photodetector OPD of the sensor FX may be exposed to light during the emission interval of the light emitting element ED. In an alternative embodiment, the photodetector OPD of the sensor FX may be exposed to light by external light. The voltage of the first sensing node SN1 may maintain the reset voltage Vrst in the reset interval, and as the photodetector OPD is exposed to light, the voltage of the first sensing node SN1 may gradually transition to the second driving voltage ELVSS. The amplifying transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the amount of charge of the first sensing node SN1 input to the third electrode of the amplifying transistor ST2.

[0120] During the output interval, a j-th write scan signal SWj having a relatively low level may be supplied to the output transistor ST3 through the j-th write scan line SWLj. When the output transistor ST3 is turned on in response to the j-th write scan signal SWj having a relatively low level, a read signal Fsd corresponding to the current flowing through the amplifying transistor ST2 may be output to the d-th read line RLd.

[0121] The sensor controller 500 receiving the readout signal FSd may generate a detection signal S_FS by processing the readout signal FSd, and provide the detection signal S_FS to the driving controller 100. The driving controller 100 may obtain an image based on the detection signal S_FS. Relevant details will be given later.

[0122] Figure 4B is a cross-sectional view of an embodiment of a display panel DP according to the present disclosure.

[0123] Reference Figure 4A and Figure 4B , the display panel DP may include a base layer BL, a circuit layer DP_CL disposed on the base layer BL, a device layer DP_ED, and an encapsulation layer TFE.

[0124] At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be composed of multiple layers. A plurality of inorganic layers may constitute barrier layers BR1 and BR2 and / or a buffer layer BFL, which will be described later. The barrier layers BR1 and BR2 and the buffer layer BFL may be selectively provided.

[0125] The barrier layers BR1 and BR2 can prevent foreign matter from entering from the outside. The barrier layers BR1 and BR2 may include a silicon oxide layer and a silicon nitride layer. A plurality of silicon oxide layers and a plurality of silicon nitride layers may be provided, and the plurality of silicon oxide layers and the plurality of silicon nitride layers may be alternately stacked.

[0126] The buffer layer BFL may be disposed on the barrier layers BR1 and BR2. The buffer layer BFL improves the bonding force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0127] The first semiconductor pattern may be disposed on the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. In an embodiment, for example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. In an embodiment, for example, the first semiconductor pattern may include low temperature polycrystalline silicon.

[0128] Figure 4B Only a portion of the first semiconductor pattern disposed on the buffer layer BFL is shown, and another portion of the first semiconductor pattern may also be disposed in another portion of the first semiconductor pattern in another region. The first semiconductor pattern may be arranged throughout the pixel according to a predetermined rule. The electrical properties of the first semiconductor pattern may vary depending on whether it is doped. The first semiconductor pattern may include a first region with relatively high electrical conductivity and a second region with relatively low electrical conductivity. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a doped region doped with a P-type dopant, and the N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region or may be a region doped at a concentration lower than that of the first region.

[0129] The conductivity of the first region may be higher than that of the second region, and the first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to an active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active region of a transistor, another portion of the semiconductor pattern may be a source region or a drain region of the transistor, and another portion of the semiconductor pattern may be a connecting electrode or a connecting signal line.

[0130] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with a plurality of pixels in common and may cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 may be a silicon oxide layer having a single layer. The insulating layer of the circuit layer DP_CL described later and the first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials, but is not limited thereto.

[0131] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 may be a part of the metal pattern. The third electrode G1 of the first transistor T1 may overlap with the channel portion A1 of the first transistor T1. The third electrode G1 of the first transistor T1 may act as a mask in the process of doping the first semiconductor pattern. The third electrode G1 may include titanium (Ti), silver (Ag), an alloy including or consisting of silver (Ag), molybdenum (Mo), an alloy including or consisting of molybdenum (Mo), aluminum (Al), an alloy including or consisting of aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide ("ITO"), and indium zinc oxide ("IZO"), but is not particularly limited thereto.

[0132] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the third electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In the present embodiment, the second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0133] The upper electrode UE and the second back metal layer BMC2 may be disposed on the second insulating layer 20. The upper electrode UE may overlap the third electrode G1. The upper electrode UE may be a portion of the metal pattern. A portion of the third electrode G1 and the upper electrode UE overlapping a portion of the third electrode G1 may define a capacitor Cst (refer to Figure 4A ). In an embodiment of the present disclosure, the second insulating layer 20 may be replaced with an insulating pattern. In this case, the upper electrode UE may be disposed on the insulating pattern, and the upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0134] The second back metal layer BMC2 may be disposed to correspond to a lower portion of the oxide thin film transistor (eg, the third transistor T3 ). The second back metal layer BMC2 may receive a constant voltage or signal.

[0135] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE and the second back metal layer BMC2. The third insulating layer 30 may have a single layer or a multi-layer structure. In an embodiment, the third insulating layer 30 may have a multi-layer structure including, for example, a silicon oxide layer and a silicon nitride layer.

[0136] The second semiconductor pattern may be disposed on the third insulating layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions distinguished from each other according to whether the metal oxide is reduced. The region in which the metal oxide is reduced (hereinafter referred to as the "reduction region") has a higher conductivity than the region in which the metal oxide is not reduced (hereinafter referred to as the "non-reduction region"). The reduction region may be substantially used as a source / drain or a signal line of a transistor. The non-reduction region actually corresponds to an active region (alternatively, a semiconductor region or a channel) of a transistor. In other words, a portion of the second semiconductor pattern may be an active region of a transistor, another portion of the second semiconductor pattern may be a source region or a drain region of a transistor, and another portion of the second semiconductor pattern may be a connecting electrode or a connecting signal line.

[0137] The first electrode S3, the channel portion A3, and the second electrode D3 of the third transistor T3 may be formed by the second semiconductor pattern. The first electrode S3 and the second electrode D3 include a metal reduced from a metal oxide semiconductor. When viewed in a cross-sectional view, the first electrode S3 and the second electrode D3 may extend from the channel portion A3 in opposite directions to each other.

[0138] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may overlap with the plurality of pixels in common and may cover the second semiconductor pattern. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0139] The third electrode G3 of the third transistor T3 may be disposed on the fourth insulating layer 40. The third electrode G3 may be a part of the metal pattern. The third electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3. The third electrode G3 may act as a mask in the process of doping the second semiconductor pattern. In an embodiment of the present disclosure, the fourth insulating layer 40 may be replaced by an insulating pattern.

[0140] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the third electrode G3. The fifth insulating layer 50 may be an inorganic layer.

[0141] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 penetrating the first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50.

[0142] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The organic layer may include a general polymer such as polystyrene ("PS"); benzocyclobutene ("BCB"); polyimide; hexamethyldisiloxane ("HMDSO"); polymethyl methacrylate ("PMMA"); a polymer derivative having a phenol group; an acrylic polymer; an imide-based polymer; an acryl ether polymer; an amide-based polymer; a fluorine-based polymer; a p-xylene-based polymer; a vinyl alcohol-based polymer; or a combination thereof, but is not particularly limited thereto.

[0143] The second connection electrode CNE20 may be disposed on the sixth insulating layer 60. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a second contact hole CH2 passing through the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and may cover the second connection electrode CNE20. The seventh insulating layer 70 may be an organic layer.

[0144] The first electrode layer may be disposed on the circuit layer DP_CL. The pixel defining layer PDL may be formed on the first electrode layer. The first electrode layer may include an anode AE ​​of the light emitting element ED and an anode AE1 of the photodetector OPD. The anode AE ​​of the light emitting element ED and the anode AE1 of the photodetector OPD may be disposed on the seventh insulating layer 70. The anode AE ​​of the light emitting element ED may be connected to the second connection electrode CNE20 through a third contact hole CH3 passing through the seventh insulating layer 70.

[0145] A first film opening PDL-OP1 and a second film opening PDL-OP2 may be defined in the pixel defining layer PDL. The first film opening PDL-OP1 may expose at least a portion of the anode AE ​​of the light emitting element ED. The second film opening PDL-OP2 may expose at least a portion of the anode AE1 of the photodetector OPD.

[0146] In an embodiment of the present disclosure, the pixel defining layer PDL may further include a black material. The pixel defining layer PDL may further include a black organic dye / pigment such as carbon black or aniline black. The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may further include a liquid-proof organic material.

[0147] like Figure 4BAs shown in , the emission area PXA and the non-emission area NPXA adjacent to the emission area PXA may be defined in the display panel DP. The non-emission area NPXA may surround the emission area PXA. In the illustrated embodiment, the emission area PXA may be defined to correspond to a portion of the anode AE ​​exposed by the first film opening PDL-OP1. In an embodiment, the sensing area SA and the non-sensing area NSA adjacent to the sensing area SA may be further defined in the display panel DP.

[0148] The emission layer EL may be disposed on the anode AE ​​of the light emitting element ED. The emission layer EL may be disposed in an area corresponding to the first film opening PDL-OP1. The emission layer EL may generate light of a predetermined color. Although the patterned emission layer EL has been described as an example in the illustrated embodiment, one emission layer may be commonly disposed in a plurality of emission areas. In this case, the emission layer may generate white light or blue light. In addition, the emission layer may have a multilayer structure called "series".

[0149] The emission layer EL may include a relatively low molecular weight organic material or a relatively high molecular weight organic material as a light emitting material. In an alternative embodiment, the emission layer EL may include a quantum dot material as a light emitting material. The core of the quantum dot may be selected from II-VI compounds, III-V compounds, IV-VI compounds, IV elements, IV compounds, and any combination thereof.

[0150] The cathode CE may be disposed on the emission layer EL. In an embodiment of the present disclosure, the cathode CE may be commonly disposed in the emission region PXA, the non-emission region NPXA, and the non-pixel region NPA. The pixel PX may not be disposed in the non-pixel region NPA.

[0151] The circuit layer DP_CL may further include a sensor driving circuit O_SD. For ease of description, a reset transistor ST1 of the sensor driving circuit O_SD is shown. The first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1 may be formed by a second semiconductor pattern. The first electrode STS1 and the second electrode STD1 may include a metal reduced from a metal oxide semiconductor. The fourth insulating layer 40 may be provided to cover the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1. The third electrode STG1 of the reset transistor ST1 may be provided on the fourth insulating layer 40. The third electrode STG1 may also be referred to as a gate electrode STG1. In the illustrated embodiment, the third electrode STG1 may be a part of a metal pattern. The third electrode STG1 of the reset transistor ST1 may overlap with the channel portion STA1 of the reset transistor ST1.

[0152] In an embodiment of the present disclosure, the reset transistor ST1 may be disposed in the same layer as the third transistor T3. That is, the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1 may be formed by the same process as the first electrode S3, the channel portion A3, and the second electrode D3 of the third transistor T3. The third electrode STG1 of the reset transistor ST1 may be formed simultaneously with the third electrode G3 of the third transistor T3 by the same process. Although not shown separately, the first electrode and the second electrode of the amplifying transistor ST2 and the output transistor ST3 of the sensor driving circuit O_SD may be formed by the same process as the first electrode S1 and the second electrode D1 of the first transistor T1. The reset transistor ST1 and the third transistor T3 may be formed in the same layer by the same process. Therefore, there is no need to form an additional process for the reset transistor ST1, thereby improving process efficiency and reducing costs.

[0153] The element layer DP_ED may further include a photodetector OPD.

[0154] The photodetector OPD may include an anode AE1, a photoelectric conversion layer RL, and a cathode CE. The anode AE1 of the photodetector OPD may be disposed in the same layer as the anode AE ​​of the light emitting element ED. That is, the anode AE1 may be disposed on the circuit layer DP_CL and may be formed simultaneously by the same process as the anode AE ​​of the light emitting element ED.

[0155] The second film opening PDL-OP2 of the pixel defining layer PDL may expose at least a portion of the anode AE1. The photoelectric conversion layer RL may be disposed on the anode AE1 exposed by the second film opening PDL-OP2. The photoelectric conversion layer RL may include an organic photosensitive material. The cathode CE may be disposed on the photoelectric conversion layer RL. Each of the anode AE1 and the cathode CE may receive an electrical signal. The anode AE1 and the cathode CE may receive signals different from each other. Therefore, a predetermined electric field may be formed between the anode AE1 and the cathode CE. The photoelectric conversion layer RL generates an electrical signal corresponding to light incident on the sensor.

[0156] The charges generated in the photoelectric conversion layer RL may change the electric field between the anode AE1 and the cathode CE. The amount of charge generated by the photoelectric conversion layer RL may vary depending on whether light is incident on the photodetector OPD, the amount of light incident on the photodetector OPD, or the intensity of light incident on the photodetector OPD. Therefore, the electric field formed between the anode AE1 and the cathode CE may vary. The photodetector OPD according to the present disclosure may obtain information about a user's fingerprint or information about illumination by changing the electric field between the anode AE1 and the cathode CE.

[0157] The encapsulation layer TFE is disposed on the element layer DP_ED. The encapsulation layer TFE includes at least one inorganic layer or at least one organic layer. In an embodiment of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer inserted between the two inorganic layers. In an embodiment of the present disclosure, the thin film encapsulation layer may include a plurality of inorganic layers and a plurality of organic layers stacked alternately.

[0158] The encapsulated inorganic layer can protect the light emitting element ED and the photodetector OPD from moisture or oxygen, and the encapsulated organic layer can protect the light emitting element ED and the photodetector OPD from foreign objects such as dust particles. The encapsulated inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc., but is not particularly limited thereto. The encapsulated organic layer may include an acrylic-based organic layer, and is not particularly limited thereto.

[0159] Figure 5 FIG. 1 is a diagram showing a display panel DP (refer to FIG. 1 ) according to the present disclosure. Figure 2 ) is a plan view of an embodiment of a display area DA.

[0160] Reference Figure 5 , also refer to Figure 3 , the display area DA may include a first area AA1, a second area AA2, and a third area AA3. The second area AA2 may be disposed adjacent to the first area AA1 in a direction opposite to the second direction DR2. The third area AA3 may be disposed adjacent to the first area AA1 in the second direction DR2. That is, the second area AA2, the first area AA1, and the third area AA3 may be sequentially arranged in the second direction DR2. The first area AA1 may be disposed between the second area AA2 and the third area AA3.

[0161] The second area AA2 may include a first sensing area SA1, a second sensing area SA2, and a third sensing area SA3 sequentially arranged in the first direction DR1. The second sensing area SA2 may be disposed adjacent to the first sensing area SA1 in the first direction DR1. The third sensing area SA3 may be disposed adjacent to the second sensing area SA2 in the first direction DR1.

[0162] Despite Figure 5 , the second area AA2 is shown to include the first sensing area SA1, the second sensing area SA2, and the third sensing area SA3, but in the embodiment of the present disclosure, the third area AA3 in which the second sensor FX2 is disposed in the display area DA may also include the first sensing area SA1, the second sensing area SA2, and the third sensing area SA3. That is, the second area AA2 and the third area AA3 may have a symmetrical shape, with the first area AA1 interposed between the second area AA2 and the third area AA3.

[0163] Reference Figure 3 , Figure 4A and Figure 5 , the first sensor FX1 may be disposed in the first area AA1. The reset transistor ST1 of the first sensor FX1 may be connected to the first reset control line RCL1. The first reset control signal GR may be provided to the first sensor FX1. That is, the first reset control line RCL1 may be connected to the sensor FX1 disposed in the first area AA1.

[0164] The second sensor FX2 may be disposed in the second area AA2. The reset transistor ST1 of the second sensor FX2 may be connected to the second reset control line RCL2. Second reset control signals GR_L1, GR_L2, and GR_L3 may be provided to the second sensor FX2. That is, the second reset control line RCL2 may be connected to the sensor FX2 disposed in the second area AA2. In addition, the second reset control line RCL2 may be connected to the sensor FX2 disposed in the third area AA3.

[0165] The (2-1)th reset control signal GR_L1 may be provided to the first sensing area SA1. The (2-2)th reset control signal GR_L2 may be provided to the second sensing area SA2. The (2-3)th reset control signal GR_L3 may be provided to the third sensing area SA3.

[0166] In an embodiment, for example, the second reset control line RCL2 may include a (2-1)th control line, a (2-2)th control line, and a (2-3)th control line. The (2-1)th control line may be connected to the second sensor FX2 disposed in the first sensing area SA1, the (2-2)th control line may be connected to the second sensor FX2 disposed in the second sensing area SA2, and the (2-3)th control line may be connected to the second sensor FX2 disposed in the third sensing area SA3. The (2-1)th reset control signal GR_L1 may be provided to the (2-1)th control line, the (2-2)th reset control signal GR_L2 may be provided to the (2-2)th control line, and the (2-3)th reset control signal GR_L3 may be provided to the (2-3)th control line.

[0167] It should be noted that this is an illustrative embodiment, and the connection relationship of the second reset control line RCL2 in the embodiment of the present disclosure is not limited thereto. In the embodiment, for example, the second reset control line RCL2 can provide the (2-1)th reset control signal GR_L1, the (2-2)th reset control signal GR_L2, and the (2-3)th reset control signal GR_L3 in a time-division manner.

[0168] Although referenced Figure 5The second sensor FX2 disposed in the second area AA2 is described, but the third area AA3 may have a symmetrical configuration with the second area AA2, the first area AA1 is interposed between the second area AA2 and the third area AA3, and may have the same configuration of wiring connection relationship as the second area AA2.

[0169] The arrangement relationship of the first area AA1, the second area AA2 and the third area AA3 in the embodiment of the present disclosure may be changed according to the position setting. In the embodiment, for example, the third area AA3 may be omitted, and a plurality of first areas AA1 may be provided. The second area AA2 may be arranged between the plurality of first areas AA1.

[0170] Fig. 6A FX1 is a waveform diagram for describing an embodiment of the operation of the first sensor FX1 according to the present disclosure. Figure 6B is the image acquired by the first sensor FX1. Specifically, Fig. 6A is used to describe the operation of the first sensor FX1 for sensing a fingerprint, and Figure 6B is based on Fig. 6A The first area AA1 (refer to Figure 5 ). Fingerprint sensing may be performed only on an area where a touch occurs when the first sensor operates.

[0171] Reference Figure 3 , Figure 5 and Fig. 6A When the user executes a predetermined application, when the corresponding application is an application that expects to verify user authentication information, the display device DD may display a screen for user authentication. The first sensor FX1 may sequentially enter a reset interval, a light receiving interval (or a first light receiving interval), and an output interval, which will be described in detail below.

[0172] When the user attempts an input, the first enable signal R_EN1 may rise. The first enable signal R_EN1 may be a signal provided from the driving controller 100 to the sensor controller 500, but is not particularly limited thereto.

[0173] When the first enable signal R_EN1 rises, the first reset control signal GR may rise. In an embodiment, for example, the first reset control signal GR may be generated by a combination of the first enable signal R_EN1 and the vertical synchronization signal Vsync. However, the present disclosure is not limited thereto. The first reset control signal GR may be generated only by the first enable signal R_EN1, or may be generated by a combination of the first enable signal R_EN1 and another control signal (e.g., a data enable signal DE).

[0174] The data enable signal DE may operate in blanking intervals BS1-1 and BS2-1 in which data signals are not supplied to the plurality of data lines DL1 to DLm and in an active interval AS in which data signals are supplied to the plurality of data lines DL1 to DLm. The data enable signal DE may have one blanking interval BS1-1 or BS2-1 and one active interval AS repeated at a predetermined cycle. Fig. 6A In the present invention, for convenience of description, the blanking intervals BS1-1 and BS2-1 are shown as a first blanking interval BS1-1 and a second blanking interval BS2-1.

[0175] After activating the first enable signal R_EN1, the first reset control signal GR may be activated at the first rising time point of the vertical synchronization signal Vsync and disabled at the second rising time point. That is, the first reset control signal GR may rise in the first blanking interval BS1-1 after the first enable signal R_EN1 has risen, and fall in the second blanking interval BS2-1.

[0176] In this case, the interval in which the first reset control signal GR has a relatively high level may also be referred to as a rising interval. Fig. 6A It is described that the rising interval of the first reset control signal GR corresponds to one cycle of the vertical synchronization signal Vsync, but in an embodiment, the rising interval of the first reset control signal GR may correspond to two cycles of the vertical synchronization signal Vsync.

[0177] Before the user's input attempt occurs, the first sensor FX1 may remain in the state of the idle interval. As in one embodiment of the present disclosure, when the rising time point of the first enable signal R_EN1 is not included in the first blanking interval BS1-1, the first sensor FX1 may have a wake-up interval between the rising time point of the first enable signal R_EN1 and the first blanking interval BS1-1. However, when the rising time point of the first enable signal R_EN1 is included in the first blanking interval BS1-1, the wake-up interval may be omitted, and the first sensor FX1 may enter the reset interval RS immediately after the idle interval.

[0178] The reset interval RS may be defined as an interval in which the first reset control signal GR is provided. The first reset control signal GR may have a first pulse width PW1. During the reset interval RS, the first sensor FX1 may be reset by receiving the first reset control signal GR. The first reset control signal GR may be commonly provided to the plurality of first sensors FX1 to simultaneously reset the plurality of first sensors FX1. That is, the first reset control signal GR may simultaneously reset the plurality of first sensors FX1 disposed in the first area AA1.

[0179] When the reset interval RS ends in the second blanking interval BS2-1, the first sensor FX1 may receive the first light to collect information provided by the user within a predetermined interval (ie, a light receiving interval). The first light may be received from the user's hand US_F (refer to FIG. 1 ) disposed in the first area AA1. Figure 1 )The light output by the pixels PX in the overlapping area.

[0180] Generally, biometric information can be measured in the middle area of ​​the display area DA. Therefore, the first area AA1 in which the first sensor FX1 for sensing the biometric information of the user is provided can be provided in the central area of ​​the display area DA. However, this is an illustrative embodiment, and the arrangement relationship of the first area AA1, the second area AA2, and the third area AA3 in the embodiment of the present disclosure is not limited thereto. In the embodiment, for example, the third area AA3 can be omitted, and a plurality of first areas AA1 can be provided. The second area AA2 can be provided between the plurality of first areas AA1.

[0181] In an embodiment, the light receiving interval is an interval for ensuring a signal difference between ridges and valleys of a fingerprint based on light reflected from the ridges and valleys of the fingerprint among the first light, and the length of the light receiving interval may be 100 milliseconds (ms), for example. However, the length of the light receiving interval is not particularly limited thereto.

[0182] After a predetermined time has passed from the light receiving interval, the first sensor FX1 may output a readout signal via the readout lines RL1 to RLh in response to the write scan signals SW1 to SWn (or referred to as output control signals) during the output interval. The length of the output interval may be 32 ms, but is not particularly limited thereto. The output interval may be a portion of the light receiving interval for receiving light.

[0183] During the output interval, the sensor controller 500 may receive a readout signal corresponding to the first image IM1 corresponding to the first area AA1 from the first sensor FX1 disposed in the first area AA1 .

[0184] When the output interval ends, the first sensor FX1 may switch to a state of an idle interval. The sensor controller 500 may generate a detection signal S_FS by processing the received readout signal, and provide the detection signal S_FS to the drive controller 100 in response to the first detection enable signal S_FS_EN1. When the actual input ends (for example, when the user's touch or fingerprint recognition ends), the relevant application may end the collection interval based on the detection signal S_FS and enter a processing interval for processing user information.

[0185] The driving controller 100 may output the first image IM1 based on the detection signal S_FS. The driving controller 100 may perform an operation of comparing with biometric information of the user based on the fingerprint image of the first image IM1.

[0186] Fig. 7A FX2 is a waveform diagram for describing an embodiment of the operation of the second sensor FX2 according to the present disclosure. Figure 7B is the image acquired by the second sensor FX2. Specifically, Fig. 7A for describing the operation of the second sensor FX2 for sensing illumination, and Figure 7B The second area AA2 (refer to Figure 5 ) or the third area AA3 (refer to Figure 5 ) Fig. 7A The second image IM2 is obtained by the operation of Fig. 7A In the description of Fig. 6A The described components are denoted by the same reference numerals, and thus, additional description will be omitted to avoid redundancy.

[0187] Reference Figure 3 , Figure 4A , Figure 5 , Fig. 7A and Figure 7B , the second sensor FX2 may be used to sense the illumination. In an embodiment, for example, the second sensor FX2 may be operated to measure the ambient brightness during a predetermined period. A plurality of second sensors FX2 may be provided, and the plurality of second sensors FX2 may sequentially enter the reset intervals RS1, RS2, and RS3 and the output intervals SS1, SS2, and SS3. The reset intervals RS1, RS2, and RS3 may include a first reset interval RS1, a second reset interval RS2, and a third reset interval RS3. The output intervals SS1, SS2, and SS3 may include a first output interval SS1, a second output interval SS2, and a third output interval SS3. This will be described in detail below.

[0188] In the case of sensing a fingerprint, a relatively low illumination area in which the sensing area is covered by the user's hand may be used to sense the illumination difference between the ridges and valleys of the fingerprint. In an embodiment, when sensing a fingerprint, for example, a first illumination range of less than 10 lux may be used. The ambient brightness may have a second illumination range wider than the first illumination range. Therefore, it is necessary to sense a second illumination range wider than the illumination range when sensing a fingerprint to measure the illumination. In an embodiment, for example, the second illumination range may be greater than or equal to 0 lux and less than or equal to 100,000 lux.

[0189] When the ambient brightness is to be measured, the second enable signal R_EN2 may rise. The second enable signal R_EN2 may be a signal provided from the driving controller 100 to the sensor controller 500, but is not particularly limited thereto.

[0190] The data enable signal DE may operate in blanking intervals BS1-2, BS2-2, and BS3-2 in which data signals are not supplied to the plurality of data lines DL1 to DLm, and active intervals AS1 and AS2 in which data signals are supplied to the plurality of data lines DL1 to DLm. Fig. 7A , for convenience of description, the blanking intervals BS1-2, BS2-2, and BS3-2 are illustrated as the first blanking interval BS1-2, the second blanking interval BS2-2, and the third blanking interval BS3-2, and the effective intervals AS1 and AS2 are illustrated as the first effective interval AS1 and the second effective interval AS2.

[0191] When the second enable signal R_EN2 rises, the second reset control signals GR_L1, GR_L2, and GR_L3 may rise. The second reset control signals GR_L1, GR_L2, and GR_L3 may include a (2-1)th reset control signal GR_L1, a (2-2)th reset control signal GR_L2, and a (2-3)th reset control signal GR_L3. The (2-1)th reset control signal GR_L1, the (2-2)th reset control signal GR_L2, and the (2-3)th reset control signal GR_L3 may rise sequentially.

[0192] During the first reset interval RS1, the (2-1)th reset control signal GR_L1 may be provided. The (2-1)th reset control signal GR_L1 may have a second pulse width PW2. The second pulse width PW2 may be greater than the first reset control signal GR (refer to Fig. 6A ) of the first pulse width PW1 (refer to Fig. 6A ) is narrow. The (2-1)th reset control signal GR_L1 may rise and fall in the first blanking interval BS1-2 after the second enable signal R_EN2 is activated. It should be noted that this is an illustrative embodiment, and the rising time point of the (2-1)th reset control signal GR_L1 in the embodiment of the present disclosure is not limited thereto. In an embodiment, for example, the falling time point t1 of the (2-1)th reset control signal GR_L1 may exist in the first blanking interval BS1-2, and the rising time point of the (2-1)th reset control signal GR_L1 may be provided after the second enable signal R_EN2.

[0193] That is, the first reset interval RS1 may overlap the first blanking interval BS1-2. The falling time point t1 of the (2-1)th reset control signal GR_L1 may be provided between the first blanking interval BS1-2 and the first active interval AS1. The (2-1)th reset control signal GR_L1 may be provided to the second sensor FX2 provided in the first sensing area SA1.

[0194] During the first reset interval RS1 , the second sensor FX2 disposed in the first sensing area SA1 may be reset by receiving the (2-1)th reset control signal GR_L1 .

[0195] When the illumination is sensed by the ambient brightness, a portion of the light receiving interval in the embodiment of the present disclosure may be omitted (refer to Fig. 6A ). Thus, a phenomenon in which the second sensor FX2 is saturated due to receiving excessive light and thus cannot receive data required for illuminance sensing can be prevented. In an embodiment, in the operation of the second sensor FX2, the light receiving interval may include only an interval overlapping with the output interval, for example.

[0196] The second area AA2 and the third area AA3 in which the second sensor FX2 for measuring the ambient brightness is provided may be provided in the peripheral area of ​​the display area DA. However, this is an illustrative embodiment, and the arrangement relationship of the first area AA1, the second area AA2, and the third area AA3 in the embodiment of the present disclosure is not limited thereto. In an embodiment, the third area AA3 may be omitted, and a plurality of first areas AA1 may be provided. For example, the second area AA2 may be provided between a plurality of first areas AA1.

[0197] According to the present disclosure, even when the second sensor FX2 in a predetermined area cannot sense the ambient brightness due to, for example, an object or a user's hand, the display device DD can easily sense the ambient brightness using the second sensor FX2 in another area. In an embodiment, for example, when the second area AA2 is covered, the ambient brightness can be sensed using the second sensor FX2 disposed in the third area AA3, and the illuminance can be sensed based on the ambient brightness. Therefore, a display device DD with improved reliability can be provided.

[0198] After the first reset interval RS1, the second sensor FX2 may output a readout signal through the readout lines RL1 to RLh in response to the write scan signals SW1 to SWn during the output interval. The first reset interval RS1 may not overlap with the output interval.

[0199] During the first output interval SS1, the sensor controller 500 may receive a readout signal corresponding to the first image area IA1 corresponding to the first sensing area SA1 from the second sensor FX2 disposed in the first sensing area SA1. That is, during the first output interval SS1, the second sensor FX2 may output a signal corresponding to the first illuminance of the first sensing area SA1. In an embodiment, for example, the image of the first image area IA1 may display the first illuminance.

[0200] During the second reset interval RS2, the (2-2)th reset control signal GR_L2 may be provided. The (2-2)th reset control signal GR_L2 may rise and fall in the second effective interval AS2 after the (2-1)th reset control signal GR_L1 is provided. That is, the second reset interval RS2 may overlap the second effective interval AS2. The (2-2)th reset control signal GR_L2 may be provided to the second sensor FX2 disposed in the second sensing area SA2.

[0201] The falling time point t2 at which the (2-2)th reset control signal GR_L2 falls may be set between the first output interval SS1 and the second output interval SS2. The falling time point t1 of the (2-1)th reset control signal GR_L1 provided to the first sensing area SA1 may be different from the falling time point t2 of the (2-2)th reset control signal GR_L2 provided to the second sensing area SA2. In an embodiment, for example, the falling time point t2 of the (2-2)th reset control signal GR_L2 may be set between the falling time point t1 of the (2-1)th reset control signal GR_L1 and the falling time point t3 of the (2-3)th reset control signal GR_L3, which will be described below.

[0202] The (2-2)th reset control signal GR_L2 may be delayed by a first interval ITV1 from the (2-1)th reset control signal GR_L1. The first interval ITV1 may be an interval from a falling time point t1 of the (2-1)th reset control signal GR_L1 to a falling time point t2 of the (2-2)th reset control signal GR_L2.

[0203] During the second reset interval RS2, the second sensor FX2 disposed in the second sensing area SA2 may be reset by receiving the (2-2)th reset control signal GR_L2. The second reset interval RS2 may overlap with the output interval.

[0204] During the second output interval SS2, the sensor controller 500 may receive a readout signal corresponding to the second image area IA2 corresponding to the second sensing area SA2 from the second sensor FX2 disposed in the second sensing area SA2. That is, during the second output interval SS2, the second sensor FX2 may output a signal corresponding to the second illumination of the second sensing area SA2. In an embodiment, for example, the image of the second image area IA2 may display the second illumination.

[0205] During the third reset interval RS3, the (2-3)th reset control signal GR_L3 may be provided. After the (2-2)th reset control signal GR_L2 has been provided, the (2-3)th reset control signal GR_L3 may rise and fall while being spaced apart from the (2-2)th reset control signal GR_L2. The (2-3)th reset control signal GR_L3 may be provided to the second sensor FX2 disposed in the third sensing area SA3.

[0206] The falling time point t3 at which the (2-3)th reset control signal GR_L3 falls may be set between the second output interval SS2 and the third output interval SS3. The falling time point t2 of the (2-2)th reset control signal GR_L2 supplied to the second sensing area SA2 may be different from the falling time point t3 of the (2-3)th reset control signal GR_L3 supplied to the third sensing area SA3.

[0207] The (2-3)th reset control signal GR_L3 may be delayed from the (2-1)th reset control signal GR_L1 by a second interval ITV2. The second interval ITV2 may be an interval from a falling time point t1 of the (2-1)th reset control signal GR_L1 to a falling time point t3 of the (2-3)th reset control signal GR_L3. The second interval ITV2 may be longer than the first interval ITV1.

[0208] During the third reset interval RS3, the second sensor FX2 disposed in the third sensing area SA3 may be reset by receiving the (2-3)th reset control signal GR_L3. The third reset interval RS3 may overlap with the output interval.

[0209] During the third output interval SS3, the sensor controller 500 may receive a readout signal corresponding to the third image area IA3 corresponding to the third sensing area SA3 from the second sensor FX2 disposed in the third sensing area SA3. That is, during the third output interval SS3, the second sensor FX2 may output a signal corresponding to the third illuminance of the third sensing area SA3. In an embodiment, for example, the image of the third image area IA3 may display the third illuminance.

[0210] The driving controller 100 may acquire the second image IM2 by combining the readout signals corresponding to the first image area IA1, the second image area IA2, and the third image area IA3, respectively. The driving controller 100 may detect the external brightness based on at least one of the first illuminance of the first image area IA1, the second illuminance of the second image area IA2, and the third illuminance of the third image area IA3. That is, the display device DD may acquire the second image IM2 by sensing the illuminance according to the position of the display panel DP through the second sensor FX2. The display device DD may detect the illuminance based on the second image IM2.

[0211] Unlike the present disclosure, when the same sensor FX is used for both fingerprint sensing and illumination sensing, a gradient image can be acquired by a deviation in the length of the light receiving interval according to the position during illumination sensing. In this case, when the external brightness is low, the external brightness is detected at the bottom of the image of the sensor FX in which sufficient light is set, and when the external brightness is high, the external brightness is detected at the top of the image of the sensor FX in which excess light is received and not saturated, and important illumination sensing data can be sensed only for a predetermined position in the display area DA according to the illumination. That is, when the predetermined position is covered, the reliability of illumination sensing may be reduced. However, according to the present disclosure, the second sensor FX2 can be used to sense the illumination according to the position of the panel. The second reset control signals GR_L1, GR_L2 and GR_L3 can be applied to the first sensing area SA1, the second sensing area SA2 and the third sensing area SA3, respectively. In this way, the display device DD can acquire the second image IM2. The display device DD can sense the illumination using at least one of the first image area IA1, the second image area IA2 and the third image area IA3 of the second image IM2. In an embodiment, for example, even when at least one of the first sensing area SA1, the second sensing area SA2, and the third sensing area SA3 is covered by an external object or a user's hand, the display device DD can sense illuminance corresponding to external brightness using another of the first sensing area SA1, the second sensing area SA2, and the third sensing area SA3. Therefore, a display device DD with improved reliability can be provided.

[0212] Figure 8 FIG. 1 is a diagram showing a driving display device DD (see FIG. Figure 1 ) is a flowchart of an embodiment of a method.

[0213] Reference Figure 3 , Figure 5 , Fig. 7A , Figure 7B and Figure 8, the display device DD may measure the illuminance of the first sensing area SA1 using the second sensor FX2 disposed in the first sensing area SA1 (S100). The display device DD may measure the illuminance of the second sensing area SA2 using the second sensor FX2 disposed in the second sensing area SA2 (S200). The display device DD may measure the illuminance of the third sensing area SA3 using the second sensor FX2 disposed in the third sensing area SA3 (S300).

[0214] The driving controller 100 may acquire a second image IM2 by combining the illuminances measured in the first sensing area SA1, the second sensing area SA2, and the third sensing area SA3 (S400). The second image IM2 may also be referred to as a sensing image IM2. The second image IM2 may include a first image area IA1 measured in the first sensing area SA1, a second image area IA2 measured in the second sensing area SA2, and a third image area IA3 measured in the third sensing area SA3.

[0215] The driving controller 100 may detect illuminance based on the acquired sensing image IM2 ( S500 ).

[0216] According to the present disclosure, the second reset control signals GR_L1, GR_L2 and GR_L3 may be applied to the first sensing area SA1, the second sensing area SA2 and the third sensing area SA3, respectively. By this, the display device DD may acquire the second image IM2. The display device DD may sense the illuminance using at least one of the first image area IA1, the second image area IA2 and the third image area IA3 of the second image IM2. In an embodiment, for example, even when at least one of the first sensing area SA1, the second sensing area SA2 and the third sensing area SA3 is covered by an external object or a user's hand, the display device DD may sense the illuminance corresponding to the external brightness using another of the first sensing area SA1, the second sensing area SA2 and the third sensing area SA3. That is, the display device DD may detect the appropriate illuminance based on the sensing image IM2 acquired by measurement. Therefore, regardless of the external environment, the illuminance may be sensed for each display panel position, thereby improving the efficiency of illuminance measurement. Therefore, a display device DD with improved reliability may be provided.

[0217] According to the above-described embodiment, even when the second sensor in a predetermined area cannot sense the ambient brightness due to, for example, an object or a user's hand, the display device can still easily sense the ambient brightness using the second sensor in another area. In an embodiment, when the first area is covered, the ambient brightness can be sensed using the second sensor provided in the second area, and the illuminance can be sensed based on the ambient brightness. Therefore, a display device with improved reliability can be provided.

[0218] Although the preferred embodiments of the present disclosure are described above, it should be understood by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims. Therefore, the technical scope of the present invention is not limited to the detailed description of this specification, but should be defined by the claims.

[0219] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, in, The display device comprises: Pixels, including pixel driving circuits and light-emitting elements; Sensors, including: Sensor driving circuit, including: A reset transistor, comprising a gate electrode receiving a reset control signal, wherein the reset control signal comprises: a first reset control signal; and a second reset control signal, different from the first reset control signal; and a sensing element electrically connected to the sensor driving circuit; and A display panel, wherein a display area is defined in the display panel, and the display area includes: Region 1; and a second area, adjacent to the first area, The first reset control signal is provided to the reset transistor disposed in the first region, and the second reset control signal is provided to the reset transistor disposed in the second region.

2. The display device according to claim 1, in, The sensor includes a plurality of sensors, and The plurality of sensors include a first sensor disposed in the first area and a second sensor disposed in the second area.

3. The display device according to claim 2, in, The second area includes a first sensing area and a second sensing area spaced apart from the first sensing area in a predetermined direction, and The falling time point of the second reset control signal provided to the first sensing region is different from the falling time point of the second reset control signal provided to the second sensing region.

4. The display device according to claim 3, in, The second reset control signal provided to the second sensing region is delayed by a first interval compared to the second reset control signal provided to the first sensing region.

5. The display device according to claim 4, in, The second region further includes a third sensing region, the third sensing region is spaced apart from the first sensing region in the predetermined direction, and the second sensing region is between the first sensing region and the third sensing region. wherein the second reset control signal provided to the third sensing region is delayed by a second interval compared to the second reset control signal provided to the first sensing region, and The second interval is longer than the first interval.

6. The display device according to claim 3, in, The reset transistor further includes a first electrode receiving a reset voltage and a second electrode connected to the first sensing node. Wherein, the sensor driving circuit of the second sensor further includes: an amplifying transistor including a first electrode receiving a sensing driving voltage, a second electrode connected to a second sensing node, and a gate electrode connected to the first sensing node; and The output transistor includes a first electrode connected to the second sensing node, a second electrode connected to a readout line, and a gate electrode receiving an output control signal.

7. The display device according to claim 6, in, providing the output control signal during an output interval, wherein a first reset interval does not overlap with the output interval, the second reset control signal provided to the first sensing region is provided in the first reset interval, and A second reset interval overlaps with the output interval, and the second reset control signal provided to the second sensing area is provided in the second reset interval.

8. The display device according to claim 7, in, The output interval includes a first output interval and a second output interval that are consecutive, and The second sensor outputs a signal corresponding to a first illuminance of the first sensing area during the first output interval, and the second sensor outputs a signal corresponding to a second illuminance of the second sensing area during the second output interval.

9. The display device according to claim 8, in, The display device further comprises: A driving circuit drives the display panel, The driving circuit detects external brightness based on one of the first illuminance and the second illuminance.

10. The display device according to claim 9, in, The display panel further includes a plurality of data lines electrically connected to the pixels, The driving circuit includes a data driver that outputs data signals to the plurality of data lines, and The data driver operates in a blanking interval in which the data signal is not output to the plurality of data lines and in an effective interval in which the data signal is output to the plurality of data lines.

Images