Eight-neighbor local interconnect Ising model computing device and method based on dirty bit transfer

Abstract

The present invention discloses an eight-neighbor local interconnected Ising model calculation device and method based on dirty bit transfer, the device comprises: an SRAM storage array module, each SRAM storage subarray comprises an XOR value row and a plurality of spin rows, each spin node is used to store a spin value, a dirty bit and a spin interaction coefficient between adjacent spin nodes, and the dirty bit is used to mark whether the spin value changes when it is updated; a random pulse module is used to generate a random signal and control the random flipping of the spin state; a read-write module is used to write and read the SRAM; a calculation logic circuit is used to calculate the addition and XOR operations required for the Ising model update and control the reading and writing of the SRAM, and a dirty bit register is also provided to control the calculation of the local search item according to the state of the dirty bit register. The present invention can significantly enhance the ability to handle complex problems, improve execution efficiency, and reduce the energy loss of system updates.

Description

Technical Field

[0001] The present invention relates to the technical field of computing systems, and in particular to an eight-neighbor local interconnection Ising model computing device and method based on dirty bit transfer. Background Art

[0002] With the continuous growth of computing demand, traditional computing systems based on the von Neumann architecture are facing performance bottlenecks, especially when dealing with large-scale parallel computing tasks. In order to improve computing efficiency and reduce energy consumption, new computing architectures such as in-memory computing and neuromorphic computing are being explored. As a new computing model, the Ising architecture combines the characteristics of in-memory computing and neuromorphic computing, and realizes information processing by simulating the physical interaction of the Ising model. The emergence of the Ising architecture provides an efficient and energy-saving solution for processing complex large-scale parallel computing tasks.

[0003] The traditional local interconnect Ising architecture based on SRAM in-memory computing has the following problems:

[0004] 1. When the traditional local interconnected Ising architecture based on SRAM in-memory computing calculates the local search item of a spin node, even if the spin state of the adjacent spin node has not changed, the system will still perform a complete product-sum operation, that is, regardless of whether the adjacent spins have changed, the local search item of each spin will be recalculated, and the product sum of the spin values ​​of all adjacent spin nodes and the corresponding interaction coefficients will be recalculated, and the result will be accumulated with the external magnetic field coefficient, which will inevitably lead to a waste of computing resources. When the spin state has not changed, such repeated calculations increase a lot of unnecessary energy consumption.

[0005] 2. In the traditional locally interconnected Ising architecture, each spin node is only interconnected with the four spin nodes above, below, left, and right. This low interconnected structure limits the full exchange of information between spins, which in turn limits the model's ability to handle complex problems and cannot fully capture the correlations between a wider range of spin nodes. The interaction between spins is the basis of the physical process in the Ising model, and models with low interconnection cannot effectively simulate the full picture of these interactions. In addition, in a low-interconnected structure, changes in the spin state cannot be quickly and completely propagated to the entire system, which will also reduce the efficiency of the model. Summary of the invention

[0006] The technical problem to be solved by the present invention is: in response to the technical problems existing in the prior art, the present invention provides an eight-neighbor local interconnected Ising model calculation device and method based on dirty bit transfer, which has a simple implementation method, high efficiency, low energy consumption, and high resource utilization, and can significantly enhance the ability to handle complex problems, improve execution efficiency, and reduce the energy loss of system updates.

[0007] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0008] An eight-neighbor local interconnected Ising model computing device based on dirty bit transfer, comprising:

[0009] An SRAM storage array module, comprising a plurality of SRAM storage sub-arrays, each of the SRAM storage sub-arrays comprising an XOR value row and a plurality of spin rows;

[0010] Each of the spin rows includes a plurality of spin nodes, each of the spin nodes is interconnected with eight spin nodes, namely, upper, lower, left, right, upper left, upper right, lower left, and lower right, each spin node is used to store a spin value, a partial sum, a dirty bit, and a spin interaction coefficient between adjacent spin nodes, the dirty bit is used to mark whether the spin value of the spin node changes at each spin update, and the XOR value row includes a plurality of XOR value nodes for storing XOR values ​​between adjacent spin values ​​and corresponding interaction coefficients;

[0011] A random pulse module is used to generate a random signal to provide a probability flipping process of the Ising model to control the random flipping of the spin state;

[0012] A read / write module is used to write and read data in the SRAM storage array module;

[0013] A calculation logic circuit, used for calculating the addition and XOR operations required for updating the Ising model and controlling the reading and writing of the SRAM;

[0014] The calculation logic circuit is also provided with a dirty bit register for temporarily storing the dirty bit of the adjacent spin node. When the local search item is calculated bit by bit, the calculation of the local search item is controlled according to the state of the dirty bit register, wherein the local search item calculation of the spin node is performed only when it is determined that the spin state has been updated according to the dirty bit in the dirty bit register, and the corresponding spin value is updated according to the sign bit of the local search item calculated last.

[0015] Furthermore, the low bit of each XOR value node also includes a temporary storage bit for temporarily storing the dirty bit and spin value of the adjacent spin node. When all the spin nodes in a row write the dirty bit or spin value into the temporary storage bit, the dirty bit or spin value is read out and stored in the calculation logic circuit.

[0016] Furthermore, the SRAM storage array module adopts a staggered storage method to store the spin nodes of the next subarray in the free cells of the previous subarray, and controls the update of the spin value by setting a valid bit.

[0017] Furthermore, the calculation logic circuit includes a multiplexer, a read-write module WD, a sensitive amplifier module, an addition module, and a control module connected in sequence, respectively. The multiplexer is used to obtain the spin value and dirty bit of the adjacent spin node and store them in the temporary storage bit of the XOR value node, and select the result of the XOR calculation, the sum and carry of the addition calculation, and write them back to the XOR value node and the partial sum unit of the spin node in the SRAM storage array module through the read-write module WD. The sensitive amplifier module is used to control the reading of the storage value of the corresponding SRAM storage cell, or perform an AND operation and a NOR operation on the two storage cells and then perform an XOR operation and a bitwise addition operation on the values ​​in the two storage structures through the addition module. The control module is used to control the writing of the selection result of the multiplexer back to the SRAM, or control the sensitive amplifier module to read the SRAM.

[0018] Furthermore, the sensitive amplifier module includes two sensitive amplifiers SA. When a single word line is turned on, the sensitive amplifier SA reads the storage value of the corresponding SRAM storage unit. When two word lines are turned on, the sensitive amplifier SA performs an AND operation and a NOR operation on the two storage units, and performs an XOR operation and a bitwise addition operation on the values ​​in the two storage structures through the addition module.

[0019] Furthermore, the control module includes a read-write control circuit for controlling the read-write module WD, a valid bit register V for identifying whether the currently read spin node is valid, and a dirty bit register T for identifying whether the spin value of the adjacent spin node has been modified, and the read-write control circuit is respectively connected to the valid bit register V and the dirty bit register T; the read-write control circuit includes a NAND gate, a first AND gate, a second AND gate and a third AND gate, the input ends of the NAND gate are respectively connected to the COL_WRI_EN signal and the COL_WRI_SEL signal, and the output end is connected to one input end of the first AND gate, the other input end of the first AND gate is connected to the output end of the third AND gate, and the first AND gate is connected to the output end of the third AND gate. The output end of an AND gate is respectively connected to the enable end of the read-write module WD and the sensitive amplifier module, one input end of the second AND gate is connected to the Ising_EN signal, and the other input end is connected to the output end of the valid bit register V, the output end of the second AND gate is connected to an input end of the third AND gate, and the other input end of the third AND gate is connected to the output end of the dirty bit register T, the COL_WRI_SEL signal is used to control whether the current update is an odd column or an even column, the COL_WRI_EN information is used to simultaneously control the writing of the odd and even columns, and the Ising_EN signal is used to control whether the SRAM is in the Ising calculation mode or the SRAM is in the storage mode.

[0020] Furthermore, the addition module includes a carry register C and a logic circuit. The sensitive amplifier module reads the spin value stored in the XOR value node, performs a logic operation through the logic circuit, and then outputs it to the carry register C, so that the input of the carry register C is S i is the spin value.

[0021] A control method for the eight-neighbor local interconnected Ising model computing device based on dirty bit transfer, comprising the following steps:

[0022] When performing Ising calculation, first read the valid bit of the spin node and store it in the valid bit register V; judge whether the spin node is valid according to the valid bit of the spin node; if it is judged to be invalid, that is, the spin node is empty, then control not to perform Ising calculation, control the read-write module not to write data back to SRAM, and control the addition module input for performing local search item calculation in the calculation logic circuit to be a constant value; if it is judged that the spin node is valid, that is, the spin node is not empty, continue to perform Ising calculation;

[0023] After reading the valid bit of the spin node, read the dirty bit of the adjacent spin node, and store the dirty bit of the adjacent spin node in the temporary bit of the XOR value node, and then read the dirty bit into the dirty bit register T; if it is judged according to the dirty bit value that the spin value of the spin node has not changed, then the input of the addition module used to perform the local search item calculation in the control calculation logic circuit is controlled to be a constant value, and at the same time, the dirty bit register also controls the read-write module not to write the calculation result back to the SRAM; if it is judged according to the dirty bit value that the spin value of the spin node has changed, then recalculate the XOR value of the spin value and the interaction coefficient, and control the addition module to perform staggered addition of the calculated XOR value and spin value with the stored local search item to complete the local search item calculation.

[0024] Furthermore, if the spin value of the spin node is determined to have changed according to the dirty bit value, the spin value Sj of the spin node is read and stored in the temporary storage bit of the XOR value node, and then the spin value Sj is executed. j and the corresponding interaction coefficient J ij XOR operation The order is from high to low. When the XOR operation of the last bit is completed, the result replaces the S in the temporary storage position. j ;

[0025] When performing the addition calculation of the XOR value and the partial sum, the adjacent spin value S is pre-set i Stored in the carry register C to add the spin value S i Fusion to In the superposition calculation with the local search term, the spin value S stored in the XOR value node is read i, and input the spin value into the addition module to obtain the input of the carry register C as To set the spin value S i Write into carry register C.

[0026] Furthermore, a spin node update step is included, including:

[0027] Each time, a neighboring spin node is taken as the current spin node, and the dirty bits of the upper, lower, left, right, upper left, upper right, lower left, and lower right neighboring spin nodes are read in sequence, and the dirty bits are temporarily stored in the temporary storage bit of the XOR value node, and the dirty bits are stored in the dirty bit register T;

[0028] Read the spin value of the current adjacent spin node, temporarily store the spin value in the temporary storage bit of the XOR value node, and store the spin value in the carry register C;

[0029] Determine whether the spin value has changed according to the dirty bit. If so, calculate the spin value s of the current adjacent spin node in order from high to low. j and the interaction coefficient J ij The XOR value between them is stored in the corresponding XOR value node, and the XOR value result in the XOR value node is compared with the local search item L i (t) Stagger the addition to complete the local search term calculation, otherwise the XOR operation is not performed and exit;

[0030] After completing the reading of all adjacent spin nodes, determine whether the random number rn is satisfied 0 >step(t), step(t) is the preset update step number, if yes, then the local search item L i (t) and the probability reversal term R i (t) perform addition operation, otherwise do not perform addition operation;

[0031] After the calculation is completed, the adjacent spin node uses the highest bit of the result as the new spin state to complete an update of the spin node.

[0032] Compared with the prior art, the advantages of the present invention are:

[0033] 1. In the locally interconnected Ising architecture of the present invention, each spin node is interconnected with eight spin nodes to form a highly interconnected structure, which can enhance the connection between spin nodes, more accurately capture the interaction between spins, significantly enhance the model's ability to handle complex problems, and better capture the correlation between a wider range of spin nodes, thereby improving the performance of the calculation.

[0034] 2. The present invention adds a dirty bit in each spin node to mark whether the spin state has changed. At the same time, a dirty bit register is set in the in-memory computing logic circuit to temporarily store the dirty bits of adjacent spin nodes, which is further used to control the calculation of local search items. When calculating the local search items of the spin nodes, it is possible to avoid repeatedly calculating the product sum of the spin values ​​of the adjacent spin nodes whose spin states have not changed and the corresponding interaction coefficients, thereby significantly reducing the computational burden of spin updates, improving execution efficiency, and reducing the energy consumption of system updates. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the structural principle of SRAM bit line calculation.

[0036] Figure 2 It is a schematic diagram of the structural principle of the Ising architecture based on bit-line computing to achieve local interconnection.

[0037] Figure 3 This is a schematic diagram of the structural principle of each CSRAM array.

[0038] Figure 4 It is a schematic diagram of the structural principle of the local interconnected Ising architecture of this embodiment.

[0039] Figure 5 It is a schematic diagram of the principle of storing the spin nodes in the storage unit of this embodiment.

[0040] Figure 6 Schematic diagram of the structural principle of the spin node in this embodiment.

[0041] Figure 7 It is a schematic diagram of the implementation process of a spin node update in this embodiment.

[0042] Figure 8 It is a schematic diagram of the implementation principle of performing XOR value and partial sum addition in the SRAM array in this embodiment.

[0043] Fig. 9 It is a schematic diagram of the structural principle of the even-numbered column bit line peripheral calculation logic circuit of the present embodiment.

[0044] Fig.10 It is a schematic diagram of the structural principle of the peripheral calculation logic circuit of the odd-numbered column bit lines of this embodiment. DETAILED DESCRIPTION

[0045] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0046] For ease of understanding, the technical background related to the present invention is first introduced.

[0047] The Ising model was originally used to describe the behavior of spin particles in magnetic materials, in which each spin particle is connected to its neighboring spin particles, and the spin state can be +1 or -1, indicating spin up or down. ij Represents spin s i and j The interaction strength between them. In the CMOS Ising system, the spin state is stored in the storage unit, "0" represents spin up, and "1" represents spin down. The CMOS Ising system consists of multiple spin nodes, which are connected to each other through data paths to transmit spin values. Each spin node contains a spin value s i , the interaction coefficient with the neighboring spins J ij .

[0048] The energy of the Ising model is composed of the interaction energy between spins and the energy of the external magnetic field. In order to find the lowest energy ground state, the system will perform a series of ground state search operations in parallel. The ground state is the state with the lowest energy of the system. The solution to the problem can be obtained through the final spin state. The ground state search includes local search and probability flipping. Probability flipping prevents the system from falling into the local optimum. During the local search, the spin adjusts its own state based on the relationship with other connected spins so that the local energy shown in formula (1) is lower.

[0049] E i (t)=-∑ ＜i，j＞ (J ij s j (t)+h i )s i (t) (1)

[0050] The spin state that makes the local energy of the spin node lower can be determined by calculating the local search term of the spin, which can be calculated according to formula (2) based on the state of the connected spins and the interaction coefficient with the current spin node:

[0051] L i (t) = ∑ ＜i，j＞ J ij s j (t)+h i (2)

[0052] In order to prevent falling into the local optimal solution in the process of searching for the ground state, a probability-based local search state update method, namely probability flipping, is further adopted. The probability flip factor R(i) is defined as follows:

[0053] R i (t) = δ(rn 0 -step(t))rn 1 (3)

[0054] When 0>step(t), the value of R(i) is rn 1 ; Otherwise, the value of R(i) is 0. 0 andrn 1 are two random numbers with a value range of rn 0 ∈(0, step final ),rn 1 ∈(-αΔE max (i) / 2, αΔE max (i) / 2). where αΔE max (i) / 2 represents the maximum energy difference, α is a constant, and step(t) and step final They represent the selectable update steps and the total iterative update steps respectively.

[0055] The next state of the spin is determined by the sum of the local search term and the probability flip term. If the sum is positive, the spin state is "+1", otherwise it is "-1". The next state of the spin is s i (t+1) can be obtained from formula (4):

[0056]

[0057] In the traditional local interconnected Ising architecture based on SRAM in-memory computing, in the state update calculation, if the state of the spin remains unchanged, the complete product-sum operation will still be performed to recalculate the local search items of the spin, that is, even if the spin state of the adjacent spin node has not changed, the system will still recalculate the local search items of the spin node. This unnecessary repeated calculation will consume a large amount of computing resources, resulting in a decrease in overall computing efficiency and a waste of computing resources. The present invention introduces the concept of "dirty bit transfer", and the dirty bit marks whether the spin value of the spin node changes at each spin update. The calculation of the local search item is controlled according to the state of the dirty bit. If the state of the spin remains unchanged, the local search items of the adjacent spin nodes do not need to be recalculated. If the state of the spin changes, the local search items of the adjacent spin nodes are updated accordingly.

[0058] Specifically, after the next state of each spin is determined, if the state has changed, the spin update dirty bit is set to "1", otherwise it is set to "0". When the spin update dirty bit is "0", the local search items of the neighboring spin nodes do not need to be updated. When the spin node update dirty bit is "1", the neighboring spin nodes can update the local search items according to formula (5).

[0059] L i (t+1)=L i (t)+2J ij s j (t+1) (5)

[0060] like Figure 1 As shown in Figure 1, in SRAM, when two word lines are activated, through the action of two sensitive amplifiers, the bit line output is presented as the logical AND result of the two storage cells, and the inverse bit line output is presented as the logical NOR result of the two storage cells. The Ising architecture calculation based on bit line calculation realizes local interconnection. The spin interaction coefficient and spin state are stored in the SRAM storage array, and the spin is updated using bit line calculation. Its overall structure is shown in Figure 1. Figure 2 As shown. The 64×64 CSRAM array is the main body of the entire structure. The inter-spin coefficients of the mapping problem and the spin state that ultimately represents the solution to the problem are stored in the CSRAM array. The row and column random pulse generator generates random pulses for random flipping of the spin state during the ground state search process to prevent the system state from being trapped in the local optimal trap. The read-write controller controls the loading of the interaction coefficients and spin state before the entire system is calculated, and controls the reading of the spin state after the calculation is completed to obtain the solution to the problem being solved. The update controller generates control signals for the entire calculation array during the iterative update of the spin. The random pulse controller generates control signals during the random flipping of the spin state.

[0061] The structure of each CSRAM array is as follows Figure 3 The structure shown in the figure includes 256×256 storage units to store interaction coefficients, spin values, and intermediate values ​​generated during the calculation process. 256 random units are used for probability flipping during the spin update process. The peripheral calculation logic further processes the calculation results generated by the bit line. The word line drive module controls the data writing and reading and the driving of the word line during the bit line calculation process. The control module generates control signals during the bit line calculation process. The value of the random unit changes with the level of the pulse generated by the random pulse generator during the spin update process. In order to save the overhead of the random pulse generator, the random units in the same column of the entire structure share a column random pulse, and the random units in the same row share a row random pulse. In addition, each random unit is divided into a multi-bit random number composed of several bit column random pulses and several bit row random pulses during the calculation process to participate in the probability flip calculation of the spin.

[0062] In the traditional locally interconnected Ising model, each spin node is only connected to the four spin nodes above, below, left, and right. This low interconnected structure will limit the full exchange of information between spins. At the same time, the interaction between spins is the basis of the physical process in the Ising model. Models with low interconnectedness cannot effectively simulate the full picture of these interactions. Changes in the spin state cannot be quickly and completely propagated to the entire system, which will also reduce the efficiency of the model. The present invention forms a novel locally interconnected Ising architecture with a high degree of interconnection by interconnecting each spin node with eight spin nodes, namely, upper, lower, left, right, upper left, upper right, lower left, and lower right. The architecture can significantly enhance the ability of the model in processing complex problems, so that it can better capture the correlation between a wider range of spin nodes, thereby improving the performance of the structure. A dirty bit is added to each spin node to mark whether the spin state has changed. At the same time, a dirty bit register is set in the in-memory computing logic circuit to temporarily store the dirty bit of the adjacent spin node, which is then used to control the calculation of the local search item. During the calculation process, the system first checks the state of the dirty bit register. If the dirty bit register indicates that the adjacent spin state has not changed, the system will bypass the recalculation of the node and reuse the previous calculation results. Only when the dirty bit register shows that the spin state has been updated, the system performs the necessary product-sum operation, which can greatly reduce unnecessary computing resources, overcome efficiency bottlenecks, and effectively improve computing efficiency and energy utilization.

[0063] like Figure 4 As shown, the eight-neighbor local interconnected Ising model computing device based on dirty bit transfer in this embodiment includes:

[0064] An SRAM storage array module includes a plurality of SRAM storage sub-arrays, each of which includes an XOR value row and a plurality of spin rows;

[0065] Each spin row includes a plurality of spin nodes, each spin node is interconnected with eight spin nodes, namely, upper, lower, left, right, upper left, upper right, lower left, and lower right, each spin node is used to store a spin value, a partial sum, a dirty bit, and a spin interaction coefficient between adjacent spin nodes, the dirty bit is used to mark whether the spin value of the spin node changes at each spin update, and the XOR value row includes a plurality of XOR value nodes for storing XOR values ​​between adjacent spin values ​​and corresponding interaction coefficients;

[0066] A random pulse module is used to generate a random signal to provide a probability flipping process of the Ising model to control the random flipping of the spin state;

[0067] A read / write module is used to write and read data in the SRAM storage array module;

[0068] A calculation logic circuit, used for calculating the addition and XOR operations required for updating the Ising model and controlling the reading and writing of the SRAM;

[0069] The calculation logic circuit is also provided with a dirty bit register for temporarily storing the dirty bits of adjacent spin nodes. When the local search item is calculated bit by bit, the calculation of the local search item is controlled according to the state of the dirty bit register, wherein the local search item calculation of the spin node is performed only when it is determined that the spin state has been updated according to the dirty bit in the dirty bit register, and the corresponding spin value is updated according to the sign bit of the local search item calculated last.

[0070] This embodiment adopts the above-mentioned Ising architecture based on dirty bit transfer, and each spin node is interconnected with eight spin nodes, namely, upper, lower, left, right, upper left, upper right, lower left, and lower right, to form a highly local interconnected Ising architecture, which can enhance the connection between spin nodes, so as to more accurately capture the correlation between a wider range of spin nodes, and significantly enhance the ability of the model in dealing with complex problems. In addition, due to the more comprehensive interconnection, the risk of falling into the local optimal trap can be effectively reduced when solving optimization problems, and the possibility of finding the global optimal solution can be increased. The local optimal trap problem is that the next state of the spin determined by the local search can make the local energy of the spin node lower, but for the entire system, the overall energy of the system is easily trapped in the local optimal trap, so that the global optimal solution cannot be found. At the same time, the calculation of the local search item is controlled by reading the dirty bit of the adjacent spin node. Only when the dirty bit register shows that the spin state has been updated, the system performs the necessary product and sum operations, which can greatly reduce unnecessary computing resources and improve computing efficiency and energy utilization.

[0071] In the above structure of the present embodiment, a random signal is generated by a random pulse module, and is involved in the probability flipping process of the Ising model, which can avoid the Ising model from falling into the trap of the local optimal solution and promote the search for the global optimal solution. The read-write module is used to write and read the SRAM. When two storage cells are read at the same time, the read-write module will output the AND value and the NOR value of the two cells, and provide them to the calculation logic circuit for addition and XOR operations. At the same time, the read-write module also needs to write the calculation results of the calculation logic circuit into the SRAM. When the width of the adjacent spin interaction coefficient is 6 bits, a 256-row SRAM subarray contains 4 spin rows, 1 XOR value row and 1 reserved row. Among them, the spin row is used to store information related to the spin, and the XOR value row is used to store the XOR value of the adjacent spin value and the corresponding interaction coefficient, as well as to temporarily store the spin value and dirty bit of the adjacent spin node.

[0072] In the locally interconnected Ising architecture, in order to obtain the latest state information of the connected spin nodes during spin update, adjacent spin nodes cannot perform state update at the same time. This embodiment adopts a staggered storage method so that adjacent spin nodes are not stored in the same row, so that the spin structures in the same row can be updated at the same time.

[0073] like Figure 5 As shown, in order to reduce the storage area wasted by misaligned storage, in each storage sub-array of the SRAM storage array module of this embodiment, the spin node of the next sub-array is stored in the free cell of the previous sub-array, and the update of the spin value is controlled by setting a valid bit, which can make full use of the storage cells, reduce the storage area wasted by misaligned storage, improve storage efficiency, and reduce cost and complexity.

[0074] like Figure 6 As shown, the information stored in the spin node includes: 1) neighboring spin interaction coefficients; 2) partial sum; 3) dirty bit; 4) valid bit; 5) spin value. Since each spin is connected to 8 spins, namely, upper, lower, left, right, upper left, upper right, lower left, and lower right, each spin node needs to store 8 neighboring spin interaction coefficients. The spin node is updated by storing dirty bits based on dirty bit transfer. Therefore, it is necessary to store the partial sum in the spin node to avoid repeated calculations. At the same time, a dirty bit is required to record whether the spin value of the spin node has changed during this spin update. The valid bit is used to control the update of the spin value. The spin value is updated only when the spin node is valid. Due to the use of staggered storage, there may be spin nodes that do not store spin values ​​when the row is updated. Therefore, a valid bit is set to control whether the spin value is updated. Each spin node also needs to store spin values ​​to provide them to neighboring spin nodes for calculation of local search items.

[0075] Since the adjacent spin storage positions of the odd and even column spin nodes are inconsistent, the timings of reading the dirty bits and spin values ​​of the adjacent spin nodes are different. In this embodiment, the low bit of the XOR value node is used as a temporary storage bit to temporarily store the dirty bits and spin values ​​of the adjacent spin nodes. After all the spin nodes in a row write the dirty bits or spin values ​​into the temporary storage bit, the dirty bits or spin values ​​are read out and stored in the calculation logic circuit.

[0076] In SRAM, the storage cell uses "0" to represent the spin value "+1" and "1" to represent the spin value "-1", so J in formula (2) ij s j (t) value is J ij or -J ij , let the spin value in the storage unit be μ j (t), then μ j(t)∈{0,1}. Therefore, the calculation formula of the local search term can be converted into an XOR calculation and an addition operation, and the calculation is performed in the complement operation mode. The specific formula is as follows:

[0077]

[0078] Similarly, when considering the optimization based on dirty bit transfer, if the neighboring spin value does not change, there is no need to recalculate the local search term of the spin and the interaction coefficient of the neighboring spin, and formula (5) can be converted into another form.

[0079] The specific formula is as follows:

[0080]

[0081] At the beginning of an Ising calculation, the partial sum is initially used to store the external magnetic field coefficient h i After calculating and storing the local search term, there is no need to repeatedly calculate the external magnetic field coefficient h i , so there is no need to store the external magnetic field coefficient h i In addition, the neighboring spin values ​​are stored in advance at the end of the XOR value node, and the XOR calculation of the neighboring spin coefficient and the neighboring spin value is from high to low, and the lowest bit is replaced after the calculation of the lowest bit.

[0082] like Figure 7 As shown, the steps of executing a spin node update in this embodiment are as follows:

[0083] 1) Each time an adjacent spin node is read as the current spin node, the dirty bits of the upper, lower, left, right, upper left, upper right, lower left, and lower right adjacent spin nodes are read in sequence, the dirty bits are temporarily stored in the temporary storage bit of the XOR value node, and the dirty bits are stored in the dirty bit register T.

[0084] 2) Read the spin value of the adjacent spin node, temporarily store the spin value in the temporary storage bit of the XOR value node, and store the spin value in the carry register C.

[0085] 3) Determine whether the spin value has changed based on the dirty bit. If the dirty bit is "1", it indicates that the spin value has changed. Then, the spin value s of the adjacent spin node needs to be calculated in order from high to low. j and the interaction coefficient J i XOR value of x and add the result to the local search term L i (t) Offset addition, since the spin value sj is stored in register C in advance, it is equivalent to calculation formula 2: ). If the dirty bit is "0", indicating that the spin value has not changed, the XOR operation and subsequent operations are not performed.

[0086] 4) If the random number rn0 >step(t), where step(t) is the preset update step number, then the local search term Li(t) and the probability flip term R i (t) performs addition operation, otherwise, does not perform addition operation.

[0087] 5) After the calculation is completed, the highest bit of the result is used as the new state of the spin. If the new state is consistent with the original state, the dirty position is "0", if the new state is inconsistent with the original state, the dirty position is "1".

[0088] This embodiment implements spin node update based on dirty bit transfer. When calculating the local search items of the spin nodes, it can avoid repeatedly calculating the sum of the products of the spin values ​​and the corresponding interaction coefficients of those adjacent spin nodes whose spin states have not changed, thereby significantly reducing the computational burden of spin update, improving the execution efficiency of the algorithm, and greatly reducing the energy consumption of system update.

[0089] In the computing system of the Ising architecture, by repeatedly executing the above steps, the system continuously updates the spin state within a limited number of iterations, and this process will eventually converge to a stable state, and the spin state read at this time is the solution to the problem. When performing Ising calculations in this embodiment, the XOR value of the adjacent spin value and the corresponding interaction coefficient is first calculated, and then the XOR value and the partial sum are added bit by bit. The XOR calculation is implemented by the bit line, the inverse bit line and the NOR gate. When the two word lines are turned on, the bit line outputs the AND result of the two storage cells, and the inverse bit line outputs the NOR result of the two storage cells. The two results are input into the NOR gate to implement the XOR operation of the two storage cells, thereby obtaining the XOR value.

[0090] like Figure 8 As shown, this embodiment performs addition of XOR values ​​and partial sums in the SRAM array in a bit-serial manner, and stores the carry after each bit-by-bit calculation so that the carry of the lower bit can be read in the next bit-by-bit calculation. It can be seen from formula (7) that the Ising calculation based on adjacent spin update can be simplified to 2J ij or -2J ij and the addition of the partial sums, while 2J ij or -2J ij You can use J ij or -J ij It is obtained by shifting, and Jij or -Jij can be realized by the XOR operation. Therefore, when calculating the addition of the XOR value and the partial sum, it is only necessary to shift the XOR value and the partial sum to realize the addition operation of the partial sum, that is, to calculate the XOR value from the second to last bit of the partial sum.

[0091] In this embodiment, when calculating the addition of the partial sum and the XOR value, since the bit width of the partial sum is smaller than the bit width of the interaction coefficient, the XOR value needs to be sign-extended. Since the bitwise addition method is adopted, when calculating the highest bit of the partial sum, it is only necessary to add the highest bit of the partial sum to the sign bit of the XOR value.

[0092] The structure of the calculation logic circuit in this embodiment is as follows Fig. 9 , 10 As shown, Fig. 9 The corresponding bit line calculation logic circuit is even-numbered. Fig.10 Corresponding to the odd-numbered column bit line calculation logic circuit, since the odd and even columns are updated in time-sharing, the odd-numbered column bit line peripheral calculation logic circuit is different from the even-numbered column bit line peripheral calculation logic circuit. When COLWRI_EN is "1" and COLWRI_SEL is "1", data is written to the odd column, so an inverter is set at the COL_WRI_SEL input in the odd-numbered column bit line calculation logic circuit.

[0093] like Fig. 9 , 10 As shown, the calculation logic circuit in this embodiment includes a multiplexer, a read-write module WD, a sensitive amplifier module, an addition module, and a control module connected in sequence, respectively. The multiplexer is used to obtain the spin value and dirty bit of the adjacent spin node and store them in the temporary storage bit of the XOR value node, and select the result of the XOR calculation, the sum and carry of the addition calculation, and write them back to the XOR value node and the partial sum unit of the spin node in the SRAM storage array module through the read-write module WD. The sensitive amplifier module is used to control the reading of the storage value of the corresponding SRAM storage cell, or perform an AND operation and a NOR operation on the two storage cells and then perform an XOR operation and a bitwise addition operation on the values ​​in the two storage structures through the addition module. The control module is used to control the writing of the selection result of the multiplexer back to the SRAM, or control the sensitive amplifier module to read the SRAM.

[0094] In this embodiment, the control module includes a read-write control circuit for controlling the read-write module WD, a valid bit register V for identifying whether the currently read spin node is valid, and a dirty bit register T for identifying whether the spin value of the adjacent spin node has been modified. The read-write control circuit is connected to the valid bit register V and the dirty bit register T respectively; the read-write control circuit includes a NAND gate, a first AND gate, a second AND gate and a third AND gate, the input ends of the NAND gate are respectively connected to the COL_WRI_EN signal and the COL_WRI_SEL signal, and the output end is connected to one input end of the first AND gate, and the other input end of the first AND gate is connected to the output end of the third AND gate. The output end of the first AND gate is connected to the enable end of the read-write module WD and the sensitive amplifier module respectively, one input end of the second AND gate is connected to the Ising_EN signal, and the other input end is connected to the output end of the valid bit register V, the output end of the second AND gate is connected to an input end of the third AND gate, and the other input end of the third AND gate is connected to the output end of the dirty bit register T, the COL_WRI_SEL signal is used to control whether the current update is the odd column or the even column, and the COL_WRI_EN information is used to control the writing of the odd and even columns at the same time to realize the alternating update of the odd and even columns. When COL_WRI_EN is "0", the data written in the odd and even columns is not distinguished. The Ising_EN signal is used to control whether the SRAM is in the Ising calculation mode or the SRAM is in the storage mode.

[0095] Specifically, when COL_WRI_EN is "1" and COL_WRI_SEL is "0", the data is written into the even columns. When COL_WRI_EN is "1" and COL_WRI_SEL is "1", the data is written into the odd columns, and the SRAM working mode is controlled by the Ising_EN signal. If Ising_EN is "1", it means that the SRAM is in the Ising calculation mode, and if Ising_EN is "0", it means that the SRAM is in the storage mode. The control module controls whether Write writes the result back to the SRAM through the above signals, and controls whether the sensitive amplifier SA reads the stored value in the SRAM into the addition module.

[0096] like Fig. 9As shown, each column has an in-memory calculation circuit. The logic circuit uses a multiplexer to obtain the spin value and dirty bit of the adjacent spin node, and stores these values ​​in the temporary storage bit of the XOR node. The multiplexer is also used to select the result of the XOR calculation and the sum and carry of the addition calculation, and then write the data back to the XOR node and the partial sum unit of the spin node of the SRAM through the read-write module WD. When reading the adjacent spin value, the adjacent spin value may be stored in other SRAM sub-arrays and adjacent SRAM column units. To this end, the multiplexer is provided with Su, Sd, Sul, Sur, Sdl, and Sdr for reading the adjacent SRAM array, and for reading the spin values ​​of the upper, lower, upper left, upper right, lower left, and lower left respectively when the adjacent spin and the current spin are not stored on the same SRAM array, Su is connected to the bit line of the SRAM column unit of the SRAM array corresponding to the upper left of the current column, and Sul is connected to the bit line of the SRAM column unit of the SRAM array corresponding to the upper left of the current column, wherein Sul, Sur, and Su are required to be used when the current spin is the first spin at the top of the column, and Sd, Sdl, and Sdr are required to be used when the current spin is the first spin at the bottom of the column. For example, when the current spin is the first spin at the top of the column, the upper spin node of the spin is not stored in the SRAM array, but is stored in the adjacent SRAM array, and at this time, the adjacent SRAM array needs to be read through Su, and since Su is connected to the bit line BL of the adjacent SRAM array, the spin value of the adjacent spin node can be read out. When the current spin is not the first spin at the top of the column, the upper spin node of the spin and the current spin node are stored in the same column SRAM, and the value of the spin node can be directly read through the bit line. At the same time, Sl and Sr are also provided for reading left spin, right spin, upper left spin, upper right spin, lower left spin, and lower right spin when the adjacent spin and the current spin are stored in the same array of SRAM. Sl and Sr are connected to the bit lines of the adjacent SRAM column units in the same SRAM array. Sl is connected to the bit lines of the left SRAM array. When the SRAM works normally, the bit line can output the value of the storage unit on the column. If the left spin, upper left spin, and lower left spin are all stored in the left SRAM column, they can all be read through the bit line, that is, the left spin, upper left spin, and lower left spin can be obtained through Sl, and correspondingly, Sr can read the right spin, upper right spin, and lower right spin.

[0097] In this embodiment, the sensitive amplifier module includes two sensitive amplifiers SA and has two working modes. When a single word line is turned on, the sensitive amplifier SA reads the storage value of the corresponding SRAM storage unit. When two word lines are turned on, the sensitive amplifier SA performs an AND operation and a NOR operation on the two storage units, and performs an XOR operation and a bitwise addition operation on the values ​​in the two storage structures through the addition module.

[0098] In this embodiment, the addition module includes a carry register C and a logic circuit. The sensitive amplifier module reads the spin value stored in the XOR value node, performs a logic operation through the logic circuit, and then outputs it to the carry register C, so that the input of the carry register C is S i is the spin value.

[0099] The control method of the eight-neighbor local interconnected Ising model computing device based on dirty bit transfer in this embodiment includes the following steps:

[0100] Step 1: When performing Ising calculation, first read the valid bit of the spin node and store it in the valid bit register V. If the valid bit is "0", it means that the spin node is empty and the Ising calculation is not performed. Therefore, the WD is controlled not to write the data back to the SRAM, and the sensitive amplifier SA is controlled to set the input of the addition module to a constant value of "1", thereby preventing the level of each gate circuit in the addition module from flipping to achieve power consumption reduction. On the contrary, if the valid bit is "1", it means that the spin node is valid and the Ising calculation needs to continue.

[0101] Step 2: After completing the reading of the valid bit of the spin node, read the dirty bit of the adjacent spin node, and store the dirty bit of the adjacent spin node in the temporary bit of the XOR node, and then read the dirty bit into the dirty bit register T, and use the dirty bit value to determine whether the spin value has changed during the previous round of spin update. If the dirty bit value is "0", the output of the sensitive amplifier SA is controlled to be always 1, that is, the input of the addition module is always 1, thereby preventing the level of each gate circuit in the addition module from flipping, thereby achieving the effect of reducing power consumption. At the same time, the dirty bit register also controls Write not to write the calculation result back to SRAM. If the dirty bit value is "1", the XOR value of the spin value and the interaction coefficient is recalculated, and the XOR value and the spin value are staggered and added with the stored local search item. Among them, when the dirty bit value of the adjacent spin node is "1", the spin value S of the spin node needs to be read. j , and store it in the temporary bit of the XOR unit, and then perform the spin value Sj and the corresponding interaction coefficient J ij XOR operation The order is from high to low. When the XOR operation of the last bit is completed, the result replaces the S in the temporary storage position. j .

[0102] Step 3: When performing the addition calculation of the XOR value and the partial sum, the adjacent spin value S is pre-calculated. i Stored in the carry register C to convert the spin value S i Fusion to In the superposition calculation with the local search term, the spin value S stored in the XOR value node is read i , and input the spin value into the addition module, the input of the carry register C can be obtained as Therefore, the spin value S i Write into carry register C.

[0103] It is understandable that the above method of this embodiment can be executed by a single device, such as a computer or server, etc., and can also be applied to a distributed scenario and completed by multiple devices in cooperation with each other. In the case of a distributed scenario, one of the multiple devices can only execute one or more steps in the above method of this embodiment, and multiple devices interact to complete the above method. The processor can be implemented in the form of a general-purpose CPU, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, etc., for executing related programs to implement the above method of this embodiment. The memory can be implemented in the form of a read-only memory ROM, a random access memory RAM, a static storage device, and a dynamic storage device. The memory can store an operating system and other applications. When the above method of this embodiment is implemented by software or firmware, the relevant program code is stored in the memory and called and executed by the processor.

[0104] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. An eight-neighbor local interconnected Ising model computing device based on dirty bit transfer, characterized in that: include: An SRAM storage array module, comprising a plurality of SRAM storage sub-arrays, each of the SRAM storage sub-arrays comprising an XOR value row and a plurality of spin rows; Each of the spin rows includes a plurality of spin nodes, each of the spin nodes is interconnected with eight spin nodes, namely, upper, lower, left, right, upper left, upper right, lower left, and lower right, each spin node is used to store a spin value, a partial sum, a dirty bit, and a spin interaction coefficient between adjacent spin nodes, the dirty bit is used to mark whether the spin value of the spin node changes at each spin update, and the XOR value row includes a plurality of XOR value nodes for storing XOR values ​​between adjacent spin values ​​and corresponding interaction coefficients; A random pulse module is used to generate a random signal to provide a probability flipping process of the Ising model to control the random flipping of the spin state; A read / write module is used to write and read data in the SRAM storage array module; A calculation logic circuit, used for calculating the addition and XOR operations required for updating the Ising model and controlling the reading and writing of the SRAM; The calculation logic circuit is also provided with a dirty bit register for temporarily storing the dirty bit of the adjacent spin node. When the local search item is calculated bit by bit, the calculation of the local search item is controlled according to the state of the dirty bit in the dirty bit register, wherein the local search item calculation of the spin node is performed only when it is determined that the spin state has been updated according to the dirty bit in the dirty bit register, and the corresponding spin value is updated according to the sign bit of the local search item calculated last.

2. The eight-neighbor local interconnected Ising model computing device based on dirty bit transfer according to claim 1, characterized in that: The low bit of each XOR value node also includes a temporary storage bit for temporarily storing the dirty bit and spin value of the adjacent spin node. When all spin nodes in a row write the dirty bit or spin value into the temporary storage bit, the dirty bit or spin value is read out and stored in the calculation logic circuit.

3. The eight-neighbor local interconnected Ising model computing device based on dirty bit transfer according to claim 1, characterized in that: The SRAM storage array module adopts a staggered storage mode to store the spin nodes of the next subarray in the idle cells of the previous subarray, and controls the update of the spin value by setting a valid bit.

4. The eight-neighbor local interconnected Ising model computing device based on dirty bit transfer according to claim 1, characterized in that: The calculation logic circuit includes a multiplexer, a read / write module WD, a sensitive amplifier module, an addition module, and a control module connected in sequence, respectively. The multiplexer is used to obtain the spin value and dirty bit of the adjacent spin node and store them in the temporary storage bit of the XOR value node, and select the result of the XOR calculation, the sum and carry of the addition calculation, and write them back to the XOR value node and the partial sum unit of the spin node in the SRAM storage array module through the read / write module WD. The sensitive amplifier module is used to control the reading of the storage value of the corresponding SRAM storage unit, or perform an AND operation and a NOR operation on the two storage units and then perform an XOR operation and a bitwise addition operation on the values ​​in the two storage structures through the addition module. The control module is used to control the writing of the selection result of the multiplexer back to the SRAM, or control the sensitive amplifier module to read the SRAM.

5. The eight-neighbor local interconnected Ising model computing device based on dirty bit transfer according to claim 4, characterized in that: The sensitive amplifier module includes two sensitive amplifiers SA. When a single word line is turned on, the sensitive amplifier SA reads the storage value of the corresponding SRAM storage unit. When two word lines are turned on, the sensitive amplifier SA performs an AND operation and a NOR operation on the two storage units, and performs an XOR operation and a bitwise addition operation on the values ​​in the two storage structures through the addition module.

6. The eight-neighbor local interconnected Ising model computing device based on dirty bit transfer according to claim 4, characterized in that: The control module includes a read-write control circuit for controlling a read-write module WD, a valid bit register V for identifying whether a currently read spin node is valid, and a dirty bit register T for identifying whether a spin value of an adjacent spin node has been modified, and the read-write control circuit is connected to the valid bit register V and the dirty bit register T respectively; the read-write control circuit includes a NAND gate, a first AND gate, a second AND gate, and a third AND gate, the input ends of the NAND gate are respectively connected to a COL_WRI_EN signal and a COL_WRI_SEL signal, and the output end is connected to an input end of the first AND gate, the other input end of the first AND gate is connected to the output end of the third AND gate, and the first AND gate is connected to the output end of the third AND gate. The output ends of the gates are respectively connected to the enable ends of the read-write module WD and the sensitive amplifier module, one input end of the second AND gate is connected to the Ising_EN signal, and the other input end is connected to the output end of the valid bit register V, the output end of the second AND gate is connected to an input end of the third AND gate, and the other input end of the third AND gate is connected to the output end of the dirty bit register T, the COL_WRI_SEL signal is used to control whether the current update is the odd column or the even column, the COL_WRI_EN information is used to control the writing of the odd and even columns at the same time, and the Ising_EN signal is used to control whether the SRAM is in the Ising calculation mode or the SRAM is in the storage mode.

7. The eight-neighbor local interconnected Ising model computing device based on dirty bit transfer according to any one of claims 4 to 6, characterized in that: The addition module includes a carry register C and a logic circuit. The sensitive amplifier module reads the spin value stored in the XOR value node, performs a logic operation through the logic circuit, and then outputs it to the carry register C, so that the input of the carry register C is S i is the spin value.

8. A control method for the eight-neighbor local interconnected Ising model computing device based on dirty bit transfer as claimed in any one of claims 1 to 7, characterized in that the steps include: When performing Ising calculation, first read the valid bit of the spin node and store it in the valid bit register V; Judging whether the spin node is valid according to the valid bit of the spin node, if it is judged to be invalid, that is, the spin node is empty, then controlling not to perform Ising calculation, controlling the read-write module not to write data back to the SRAM, and controlling the input of the addition module used to perform the local search term calculation in the calculation logic circuit to be a constant value, if it is judged that the spin node is valid, that is, the spin node is not empty, continuing to perform Ising calculation; After reading the valid bit of the spin node, read the dirty bit of the adjacent spin node, and store the dirty bit of the adjacent spin node in the temporary storage bit of the XOR value node, and then read the dirty bit into the dirty bit register T; If it is judged according to the dirty bit value that the spin value of the spin node has not changed, the input of the addition module used to perform the local search item calculation in the control calculation logic circuit is controlled to be a constant value. At the same time, the dirty bit register also controls the read-write module not to write the calculation result back to the SRAM; if it is judged according to the dirty bit value that the spin value of the spin node has changed, the XOR value of the spin value and the interaction coefficient is recalculated, and the addition module is controlled to perform staggered addition of the calculated XOR value and spin value with the stored local search item to complete the local search item calculation.

9. The control method according to claim 8, characterized in that: If the spin value of the spin node is changed according to the dirty bit value, read the spin value S of the spin node j And store it in the temporary bit of the XOR value node, and then execute the spin value S j and the corresponding interaction coefficient J ij XOR operation The order is from high to low. When the XOR operation of the last bit is completed, the result replaces the S in the temporary storage position. j ; When performing the addition calculation of the XOR value and the partial sum, the adjacent spin value S is pre-set i Stored in the carry register C to convert the spin value S i Fusion to In the superposition calculation with the local search term, the spin value S stored in the XOR value node is read i , and input the spin value into the addition module to obtain the input of the carry register C as To set the spin value S i Write into carry register C.

10. The control method according to claim 8 or 9, characterized in that: Also included are the spin node update steps, including: Each time, a neighboring spin node is taken as the current spin node, and the dirty bits of the upper, lower, left, right, upper left, upper right, lower left, and lower right neighboring spin nodes are read in sequence, and the dirty bits are temporarily stored in the temporary storage bit of the XOR value node, and the dirty bits are stored in the dirty bit register T; Read the spin value of the current adjacent spin node, temporarily store the spin value in the temporary storage bit of the XOR value node, and store the spin value in the carry register C; Determine whether the spin value has changed according to the dirty bit. If so, calculate the spin value S of the current adjacent spin node in order from high to low. j and the interaction coefficient J ij The XOR value between them is stored in the corresponding XOR value node, and the XOR value result in the XOR value node is added to the local search item in a staggered manner to complete the local search item calculation, otherwise the XOR operation is not performed and exit; After completing the reading of all neighboring spin nodes, determine whether the random number rn0>step(t), where step(t) is the preset update step number. If so, the local search term and the probability flip term R are changed. i (t) perform addition operation, otherwise do not perform addition operation; After the calculation is completed, the adjacent spin node uses the highest bit of the result as the new spin state to complete an update of the spin node.

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