Electron source device and manufacturing method thereof, integrated circuit

Abstract

The present application provides an electron source device, a manufacturing method thereof, and an integrated circuit. The electron source device includes: a substrate 1; and an electron emission unit, wherein the electron emission unit includes: a low-potential source region 111, a channel region 222, a highly doped drain region 333, a gate 6, an electron acceleration layer 9, an insulating film 10, and a high-potential electron emitter conductive film 14. The highly doped drain region 333 is formed on the first main surface of the substrate 1, the channel region 222 is located below the highly doped drain region 333, the electron acceleration layer 9 is located on the surface of the highly doped drain region 333, and an insulating film 10 is provided between the electron acceleration layer 9 and the high-potential electron emitter conductive film 14. The gate 6 is located laterally outside the channel region 222, and the low-potential source region 111 is formed in the substrate 1, at least partially below the gate 6. The present application can improve electron emission efficiency, reduce resistance in the channel region, and improve the lifespan and electron emission stability of the electron source device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an electron source device, a manufacturing method thereof, and an integrated circuit. Background Art

[0002] With the development of the semiconductor microfabrication industry, the requirements for electron beam direct writing technology are becoming increasingly stringent, including ensuring the accuracy of fine graphics imaging and significantly improving the direct writing speed.

[0003] To meet this industry demand, multi-electron beam direct writing technology is rapidly developing and playing an irreplaceable role in the direct writing of fine patterns in integrated circuit chip manufacturing. Specifically, in semiconductor integrated circuit chip manufacturing, the imaging of high-tech node patterns (including patterns on photomasks and structural patterns at various device levels) requires both finer and more accurate direct writing, as well as high speed despite the dramatic increase in pattern data volume.

[0004] To accurately write fine patterns, the electron beam spot size must be reduced to facilitate precise scanning. While maintaining constant current density, reducing the electron beam spot size means reducing the electron beam current, which results in longer direct writing times. Furthermore, when the pattern size to be written is below tens of nanometers, the smaller the line width, the more significant the impact of shot noise becomes, severely impacting critical dimension uniformity and line edge roughness.

[0005] In order to ensure that the critical line width uniformity and line edge roughness of small line width graphics are sufficient to meet the product performance requirements, when writing graphics directly, the smaller the line width, the lower the sensitivity of the electron beam photoresist. As a result, the smaller the line width graphics, the greater the direct writing exposure required. This means that when the current density remains unchanged, the smaller the line width, the longer the direct writing time required. In order to improve the production capacity of electron beam direct writing equipment per unit time, a multi-electron beam direct writing machine that uses multiple electron beams to write simultaneously has become a necessary tool. In order to meet actual needs, the number of direct writing electron beams of a multi-electron beam direct writing machine needs to be around hundreds of thousands.

[0006] Currently, practical multi-electron beam direct writing systems generally use a single electron source, splitting a single source electron beam emitted from the source into multiple direct writing electron beams. To increase the current density of the direct writing electron beams, the total current of the source electron beams must be increased. However, increasing the total current of the source electron beams is difficult, and the increase in current density of each direct writing electron beam is limited. The best solution to these problems is to use a multi-source, multi-beam electron source device in which the current of each beam can be controlled.

[0007] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0008] Porous silicon prepared by photoelectrochemical etching can be applied to the preparation of electron sources. For example, single crystal silicon or columnar polycrystalline silicon materials can be used to prepare cold field emission electron sources. Figure 1 The porous silicon electron source structure and the voltage V applied across the porous silicon electron source structure PS Energy band diagram when .

[0009] like Figure 1 As shown in (a), when voltage Vps is applied to both ends of the electron source device, hot electrons are injected from the N-type silicon substrate into the broadband porous silicon region. The injected electrons are continuously accelerated by the electric field, reaching the top gold (Au) film via a quasi-ballistic transport mechanism, and then penetrating the Au film via a tunneling mechanism to be emitted into the vacuum. This is the cold-field electron emission current. Therefore, the porous silicon electron source device has the characteristics of high electron collimation, concentrated energy, and stable emission current. Utilizing semiconductor integrated circuit process technology and microelectromechanical system (MEMS) process technology, integrated porous silicon electron source devices can be fabricated to achieve multi-source and multi-beam capabilities.

[0010] The inventors of this application have found that the existing porous silicon electron source devices have the following problems: Figure 1 The problem with the high resistance of the N-type silicon substrate shown in (b) is that as electron source devices become smaller, the resistance of the N-type silicon substrate increases. When voltage Vps is applied across the electron source device, most of the Vps falls on this high resistance, generating unnecessary Joule heating, degrading the device's characteristics and causing damage, seriously shortening its lifespan.

[0011] To address the above-mentioned problems, or at least similar problems, embodiments of the present application provide an electron source device, a manufacturing method thereof, and an integrated circuit. In the electron source device of the present application, when the metal oxide semiconductor (MOS) field-effect transistor formed around the active region is turned on, electrons can be directly supplied from the low-potential source region to the electron acceleration layer, thereby improving electron emission efficiency and reducing the resistance of the channel region, thereby resolving the heating problem caused by high resistance and improving the lifespan and electron emission stability of the electron source device. Furthermore, this facilitates the mass production of uniform electron source devices using advanced microelectromechanical systems (MEMS) processes.

[0012] According to one aspect of an embodiment of the present application, an electron source device is provided, wherein the transistor device includes:

[0013] a substrate 1; and

[0014] electron emission unit,

[0015] The electron emission unit includes:

[0016] low potential source region 111, channel region 222, highly doped drain region 333, gate 6, electron acceleration layer 9, insulating film 10 and high potential electron emitter conductive film 14,

[0017] in,

[0018] The highly doped drain region 333 is formed on the first main surface of the substrate 1.

[0019] The channel region 222 is located at the lower side of the highly doped drain region 333.

[0020] The electron acceleration layer 9 is located on the surface of the highly doped drain region 333.

[0021] The insulating film 10 is provided between the electron acceleration layer 9 and the high potential electron emitter conductive film 14.

[0022] The gate 6 is located laterally outside the channel region 222 . The low potential source region 111 is formed in the substrate 1 and is at least partially located below the gate 6 .

[0023] According to another aspect of an embodiment of the present application, a method for manufacturing an electron source device is provided, for manufacturing the electron source device described in the above embodiment, the method comprising:

[0024] A highly doped drain region 333, a channel region 222, and a low potential source region 111 are formed in a substrate 1, wherein the highly doped drain region 333 is formed on the first main surface of the substrate 1, the channel region 222 is located below the highly doped drain region 333, and the low potential source region 111 is at least partially located laterally outside the channel region 222 and at least partially located below the channel region 222;

[0025] forming an electron acceleration layer 9 on the surface of the highly doped drain region 333;

[0026] Forming gate insulating films 4, 5 and a gate 6 in sequence on the lateral outer side of the channel region 222; and

[0027] An insulating film 10 and a high-potential electron emitter conductive film 14 are sequentially formed on the surface of the electron acceleration layer 9 .

[0028] The beneficial effects of this application are as follows: in the electron source device of this application, when the metal oxide semiconductor (MOS) field effect transistor formed around the active region is turned on, electrons can be directly supplied from the low-potential source region to the electron acceleration layer, thereby improving electron emission efficiency, reducing the resistance of the channel region, solving the problem of heat generation caused by high resistance, and improving the lifespan and electron emission stability of the electron source device. In addition, it facilitates the mass production of electron source devices with good uniformity using advanced micro-electromechanical systems (MEMS) processes.

[0029] With reference to the following description and accompanying drawings, specific embodiments of the present application are disclosed in detail, indicating the manner in which the principles of the present application can be employed. It should be understood that the embodiments of the present application are not limited in scope. Within the spirit and scope of the appended claims, the embodiments of the present application include many variations, modifications and equivalents.

[0030] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0031] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0033] Figure 1 is a porous silicon electron source structure and an energy band diagram when a voltage is applied across the porous silicon electron source structure;

[0034] Figure 2 is a schematic diagram of the electron source device of the present application;

[0035] Figure 3 is a schematic diagram of a method for manufacturing an electron source device of the present application;

[0036] Figures 4 to 26 Schematic diagram of the device structure in each step of the manufacturing method of the electron source device 100. DETAILED DESCRIPTION

[0037] The above and other features of the present application will become apparent through the following description with reference to the accompanying drawings. In the description and the accompanying drawings, specific embodiments of the present application are disclosed in detail, which illustrate some embodiments in which the principles of the present application can be adopted. It should be understood that the present application is not limited to the described embodiments. On the contrary, the present application includes all modifications, variations and equivalents that fall within the scope of the appended claims.

[0038] In the description of the various embodiments of the present application, for the convenience of description, the direction parallel to the first main surface of the substrate is called "horizontal", the direction perpendicular to the first main surface of the substrate is called "longitudinal", and the dimension in the "longitudinal" direction can be called "height" or "thickness"; in the "longitudinal", the direction from the first main surface of the first substrate to the channel region is called the "up" direction, and the opposite direction to the "up" direction is the "down" direction.

[0039] It should be noted that the above-mentioned “up” direction and “down” direction are only for the convenience of explanation and do not limit the orientation or posture of the electron source device of the present application during manufacture or use.

[0040] An embodiment of the present application provides an electron source device.

[0041] Figure 2 This is a schematic diagram of the electron source device of this application. Figure 2 As shown, the electron source device 100 includes: a substrate 1; and an electron emission unit. The electron source emission unit includes: a low potential source region 111, a channel region 222, a highly doped drain region 333, a gate 6, an electron acceleration layer 9, an insulating film 10, and a high potential electron emitter conductive film 14.

[0042] like Figure 2 As shown, a highly doped drain region 333 is formed on a first surface (e.g., an upper surface) of a substrate 1; a channel region 222 is located below the highly doped drain region 333; an electron acceleration layer 9 is located on the surface of the highly doped drain region 333; an insulating film 10 is disposed between the electron acceleration layer 9 and the high-potential electron emitter conductive film 14; and a gate 6 is located laterally outside the channel region 222. A low-potential source region 111 is formed in the substrate 1 and is at least partially located below the gate 6. For example, the low-potential source region 111 is located laterally outside the channel region 222 and below the gate 6.

[0043] like Figure 2 As shown, the electron source device 100 further includes: a low-voltage back metal electrode 12 , which is provided on the second main surface (eg, the lower surface) of the substrate 1 .

[0044] In at least one embodiment, the substrate 1 may be, for example, an N-type silicon substrate. The channel region 222 may be, for example, an undoped silicon epitaxial layer or an undoped columnar polysilicon layer. The impurity concentration of the low potential source region 111 and / or the highly doped drain region 333 is 5×10 19 cm -3 The thickness of the high-potential electron emitter conductive film 14 is 0.1 to 10 nm, and the material is one or more of a metal, a conductive compound, and a conductive two-dimensional material. The thickness of the gate 6 is equal to or greater than the thickness of the channel region 222. The material of the gate 6 is a highly doped semiconductor material or a metal material.

[0045] like Figure 2 As shown, a gate insulating film may be provided between the channel region 222 and the gate 6, and the gate 6 is electrically connected to the gate electrode 11. The thickness of the gate insulating film is 1 to 30 nm. The material of the gate insulating film is silicon dioxide and / or silicon nitride. For example, the gate insulating film includes a silicon dioxide (SiO2) film 4 and a silicon nitride (Si3N4) film 5. In addition, the gate insulating film may also extend laterally between the low potential source region 111 and the gate 6.

[0046] The channel region 222 is shaped like a cylinder, a cube, or a cuboid. The lateral dimension of the channel region 222 (e.g., the diameter of the cylinder, the side length of the cube, or the short side length of the cuboid) is 0.05 to 30 μm, and the longitudinal dimension of the channel region 222 (e.g., the height) is 0.5 to 7 μm.

[0047] In at least one embodiment, the material of the electron acceleration layer 9 can be porous silicon or porous polycrystalline silicon. The electron acceleration layer 9 can have multiple independent semiconductor grains, with an insulating medium of predetermined thickness between adjacent semiconductor grains, and the insulating medium includes, for example, silicon oxide SiO2. The thickness of the electron acceleration layer 9 is 0.1 to 5 μm, and the characteristic size of the semiconductor grains is 1 to 50 nm; the predetermined thickness of the insulating medium is, for example, 0.3 to 2 nm. Under the isolation of the insulating medium, adjacent semiconductor grains form a semiconductor grain chain structure with an insulating layer, and the direction of the semiconductor grain chain structure is perpendicular to the first main surface of the substrate 1.

[0048] like Figure 2 As shown, the electron source device 100 may further include a silicon dioxide (SiO2) film 7 and a silicon nitride (Si3N4) film 8. The silicon dioxide (SiO2) film 7 and the silicon nitride (Si3N4) film 8 are vertically stacked and formed between the gate 6 and the electron emitter metal lead 13, wherein the electron emitter metal lead 13 is electrically connected to the high potential electron emitter conductive film 14.

[0049] In the present application, the channel region 222, the gate insulating film, the gate 6, the low potential source region 111, and the highly doped drain region 333 form a MOS field effect transistor having a vertical channel. The gate 6, for example, is a gate all around (GAA) structure that laterally surrounds the sidewalls of the channel region 222.

[0050] The working principle of the electron source device 100 of the present application is as follows.

[0051] When a voltage V is applied between the electron emitter metal lead 13 and the back metal electrode 12 PS (For example, the electron emitter metal lead 13 is at a positive voltage and the back metal electrode 12 is at a ground or negative voltage), hot electrons are injected from the low potential source region 111 into the channel region 222, and the electrons are transported to the highly doped drain region 333 (for example, a highly doped N-type silicon drain region) under the action of the electric field, and injected into the electron acceleration layer 9. The injected electrons are accelerated by the electric field and transported to the high potential electron emitter conductive film 14 by a quasi-ballistic transport mechanism, and tunnel through the conductive film and are emitted into the surrounding space (for example, vacuum). When a positive voltage VG is applied to the gate metal electrode 11, the gate 6 (for example, n + By turning on (ON) the n-channel MOS field-effect transistor on the side wall of the active area, electrons can be directly supplied from the low-potential source region 111 to the highly doped drain region 333, thereby reducing the resistance of the channel region 222 and allowing Vps to effectively fall on the electron acceleration layer 9, thereby solving the heating problem, improving the life of the electron source device and the electron emission efficiency, and adjusting VG can also control the emission current.

[0052] Because the electron source device of this application is based on a planar cold-field electron emission mechanism and quasi-ballistic electron emission, the emitted electrons have minimal energy chromatic aberration, stable performance, and a long service life. Furthermore, it is easy to manufacture using MEMS technology, resulting in excellent device uniformity, a compact size, and the ability to be integrated, enabling the realization of multi-source, multi-beam electron source devices.

[0053] An embodiment of the present application further provides an integrated circuit, which may include at least one electron source device 100 .

[0054] The embodiment of the present application also provides a method for manufacturing an electron source device, which is used to manufacture the electron source device 100 .

[0055] Figure 3 is a schematic diagram of the manufacturing method of the electron source device, such as Figure 3 As shown, the manufacturing method includes:

[0056] 301, forming a highly doped drain region 333, a channel region 222, and a low potential source region 111, wherein the highly doped drain region 333 is formed on the first main surface of the substrate 1, the channel region 222 is located below the highly doped drain region 333, and the low potential source region 111 is at least partially located laterally outside the channel region 222 and at least partially located below the channel region 222;

[0057] 302. Forming an electron acceleration layer 9 on the surface of the highly doped drain region 333;

[0058] 303 , forming a gate insulating film and a gate 6 in sequence on the lateral outer side of the channel region 222 ; and

[0059] 304 . An insulating film 10 and a high-potential electron emitter conductive film 14 are sequentially formed on the surface of the electron acceleration layer 9 .

[0060] In addition, the method also includes: vertically stacking a silicon dioxide (SiO2) film 7 and a silicon nitride (Si3N4) film 8 on the surface of the gate 6; forming an electron emitter metal lead 13 on the surface of the silicon nitride (Si3N4) film 8; forming a gate metal electrode 11 and a back metal electrode 12, etc.

[0061] For descriptions of materials and dimensions involved in each step, reference may be made to the relevant descriptions of the electron source device 100 .

[0062] In some embodiments of operation 302, the step of forming the electron acceleration layer 9 includes:

[0063] 3021. Growing an undoped silicon epitaxial layer on the surface of the substrate 1, and forming an N-type silicon region on the top of the undoped silicon epitaxial layer;

[0064] 3022. Perform photoelectrochemical etching on the N-type silicon region formed on the top to form porous silicon; and

[0065] 3023. Perform a passivation process on the porous silicon to form a nanocrystalline grain chain structure containing an insulating layer.

[0066] In some other embodiments of operation 302, the step of forming the electron acceleration layer 9 includes:

[0067] 3021a. Growing an undoped columnar polysilicon layer on the surface of the substrate, and forming an N-type polysilicon region on top of the columnar polysilicon layer;

[0068] 3022a, performing photoelectrochemical etching on the N-type polysilicon region formed on the top to form porous polysilicon; and

[0069] 3023a. Perform a passivation process on the porous polycrystalline silicon to form a nanocrystalline grain chain structure containing an insulating layer.

[0070] The manufacturing method of the electron source device according to the embodiment of the present application is described below with reference to specific examples.

[0071] The specific process methods listed in the following examples are only examples, and the present application is not limited thereto.

[0072] Figures 4 to 26 1 is a schematic diagram of the device structure of each step of the manufacturing method of the electron source device 100. Figures 4 to 26 As shown, the manufacturing method of the electron source device 100 includes the following steps (1) to (21):

[0073] (1) Figure 4 As shown, a P-type (100) silicon substrate is prepared as the substrate 1, and its resistivity is 0.01 to 0.5 Ωcm.

[0074] (2) Figure 5 As shown, an active area photoresist pattern 1000 is formed by photolithography, and the shape of the pattern is circular (with a diameter of 0.05 to 30 μm), or positive (with a side length of 0.05 to 30 μm), or rectangular (with a short side length of 0.05 to 30 μm). Figure 6 is a schematic diagram of the active area photoresist pattern 1000, showing examples such as circle, square, and rectangle.

[0075] (3) Figure 7 As shown, reactive ion etching (RIE) or other methods are used to etch P-type silicon 1 around active area photoresist pattern 100, forming a stepped structure 102. Step 102 has a height of 1 to 15 μm. After etching, the photoresist is removed using oxygen plasma or sulfuric acid and hydrogen peroxide, forming an island active area 101 in the shape of a cylinder, cube, or cuboid.

[0076] (4) Figure 8 As shown, a silicon dioxide (SiO2) film 103 is deposited by low pressure chemical vapor deposition (LPCVD) method, and its thickness is 200-300 nm.

[0077] (5) Figure 9 As shown, the silicon dioxide (SiO2) film 103 is etched by RIE method to form sidewall (Sidewall) SiO2 film 104, and bare silicon surfaces 105 and 106 are formed at the same time.

[0078] (6) Figure 10 As shown, a highly doped N-type source region (i.e., a low potential source region) 111 is prepared by ion implantation or thermal diffusion, and a highly doped N-type region 33 with a thickness of 0.1 to 3 μm is formed on the top of the active region, and a channel region 222 is formed at the same time.

[0079] The doping elements of the highly doped N-type source region 111 and the highly doped N-type region 33 are group V elements such as phosphorus, antimony, and arsenic, and the implantation dose is 2x10 15 cm 2 above.

[0080] If ion implantation is used for doping, an annealing process at a temperature above 600°C is performed after the ion implantation. The annealing atmosphere is either forming gas (a mixture of hydrogen and nitrogen) or 100% nitrogen. The thickness of the highly doped N-type source region 111 and the highly doped N-type region 33 can be controlled by adjusting the annealing temperature and time. If thermal diffusion is used for doping, the thickness of the highly doped N-type source region 111 and the highly doped N-type region 33 can be controlled by adjusting the diffusion temperature and time.

[0081] (7) Figure 11 As shown, after the annealing is completed, a wet etching method (for example, using HF solution) is used to completely etch the SiO2 film on the side walls of the active area 101 and the back side of the P-type silicon substrate 1 to form bare silicon side walls 107 and the back side 108 of the bare silicon substrate.

[0082] (8) Figure 12 As shown, a silicon dioxide (SiO2) film 4 is deposited by LPCVD method with a thickness of 1 to 10 nm, followed by a silicon nitride (Si3N4) film 5 with a thickness of 1 to 10 nm.

[0083] (9) Figure 13 As shown, using LPCVD method, n + The thickness of the polysilicon film is greater than the height 101 of the active area.

[0084] Then, a chemical mechanical polishing (CMP) method is used to planarize the top layer of the active area 101, the nitride (Si 3 N 4 ) silicon film 5 .

[0085] Then use RIE method to etch n + Polysilicon, forming n + The polysilicon gate 6 also forms a step structure 109 with a depth of 0.03 to 2.8 μm.

[0086] n +The structure of the polysilicon gate 6 is a Gate all around (GAA) structure, and the top of the polysilicon gate 6 is higher than the bottom of the highly doped N-type silicon region 33 .

[0087] (10) Figure 14 As shown, a silicon dioxide (SiO2) film 7 is deposited using LPCVD to a thickness greater than the height of step 103. CMP is then used to planarize the film down to the silicon nitride film 5 on top of the active region 101. A silicon nitride (Si3N4) film 8 is then deposited using LPCVD to a thickness of 20 to 50 nm.

[0088] (11) Figure 15 As shown, a photoresist is used to protect the surface, and the silicon nitride (Si3N4) film, silicon dioxide (SiO2) film, polysilicon film, and other multi-layer films on the back are removed by RIE to form a bare silicon backside 110. The surface photoresist is then removed by oxygen plasma or sulfuric acid plus hydrogen peroxide.

[0089] (12) Figure 16 As shown, an opening pattern 111 is formed on the top of the active area 101 using a photolithography method, and other areas are protected by a photoresist 112.

[0090] (13) Figure 17 As shown, RIE is used to etch silicon nitride (Si3N4) films 8 and 5 down to the surface of silicon dioxide (SiO2) film 4. A diluted hydrofluoric acid (DHF) solution is then used to etch silicon dioxide (SiO2) film 4, exposing the highly doped N-type silicon surface 113. The surface photoresist is then removed using oxygen plasma or a method such as sulfuric acid and hydrogen peroxide.

[0091] (14) Figure 18 As shown, a porous silicon layer 114 is prepared by photoelectrochemical etching with a thickness of 0.01 to 2.7 μm. Under the porous silicon layer 114, a highly doped N-type silicon drain region 333 with a thickness of more than 50 nm is left.

[0092] (15) Figure 19As shown, thermal oxidation or electrochemical oxidation (ECO) is used to oxidize the nano-silicon grains in the porous silicon to grow a 1-2 nm thick oxide layer (SiO2) on the surface. Then, high pressure water vapor annealing (HWA) and super critical rinse and dry (SCRD) are immediately performed to form a porous silicon electron acceleration layer 9. The porous silicon electron acceleration layer 9 is composed of nano-silicon grain chains with a 1-2 nm thick oxide film (SiO2) formed on the surface. The direction of the nano-silicon grain chains is perpendicular to the surface of the silicon substrate, as shown in FIG. Figure 20 shown.

[0093] (16) Figure 21 As shown, an insulating film 10 having a thickness of 1 to 2 nm is deposited on the surface of the porous silicon electron acceleration layer 9 by atomic layer deposition (ALD). (If the oxide layer in step 15 is thick enough (2 nm or more), this insulating film may not be used.) The insulating film material is at least one of the following: SiO2, ZrO2, Si3N4, HfO2, Al2O3, etc.

[0094] (17) Figure 22 As shown, a contact hole pattern is formed by photolithography, a silicon nitride (Si3N4) film 8 is etched by RIE, and a silicon dioxide (SiO2) film 7 is etched by RIE or wet etching to expose n + Contact holes 115 are formed on the surface of the polysilicon. Then, the surface photoresist is removed by using an oxygen plasma method or a method such as sulfuric acid and hydrogen peroxide.

[0095] (18) Figure 23 As shown, an Al metal film is deposited by sputtering to a thickness greater than the thickness of the silicon nitride (Si3N4) film 8 plus the thickness of the silicon dioxide (SiO2) film 7. Subsequently, a gate lead electrode pattern is formed by photolithography, and a gate metal electrode 11 is formed by RIE or wet etching. The surface photoresist is then removed by oxygen plasma.

[0096] (19) Figure 24 As shown, the surface is protected with photoresist, and the backside is etched using RIE and wet etching to form a bare silicon surface. An Al metal film is then deposited by sputtering to form a backside metal electrode 12 with a thickness of 100 to 300 nm. The surface photoresist is then removed using an oxygen plasma process. Next, the substrate is annealed for 30 minutes at 450 to 500°C in a forming gas (a mixture of hydrogen and nitrogen) atmosphere to form an ohmic contact.

[0097] (20) Figure 25 As shown, photolithography, sputtering (or evaporation) and lift-off methods are used to prepare the electron emitter metal lead 13. The metal film material and its thickness are Au / Cr=200-300 / 10nm, or Au / Ti=200-300 / 10nm.

[0098] (21) Figure 26 As shown, the high potential electron emitter conductive film 14 is prepared by photolithography, sputtering (or evaporation) and lift-off method. The high potential electron emitter conductive film material and its thickness are Au / Ti≤10 / 1nm, or Au / Cr≤10 / 1nm, or single atomic layer graphene film.

[0099] The present application has been described above in conjunction with specific embodiments. However, those skilled in the art should understand that these descriptions are merely illustrative and are not intended to limit the scope of protection of the present application. Those skilled in the art may make various modifications and variations to the present application based on the spirit and principles of the present application, and such modifications and variations are also within the scope of the present application.

Claims

1. An electron source device, characterized in that: The electron source device comprises: a substrate (1); and electron emission unit, The electron emission unit includes: a low potential source region (111), a channel region (222), a highly doped drain region (333), a gate (6), an electron acceleration layer (9), an insulating film (10) and a high potential electron emitter conductive film (14), in, The highly doped drain region (333) is formed on the first main surface of the substrate (1), The channel region (222) is located at the lower side of the highly doped drain region (333), The electron acceleration layer (9) is located on the surface of the highly doped drain region (333), The insulating film (10) is provided between the electron acceleration layer (9) and the high-potential electron emitter conductive film (14). The gate (6) is located laterally outside the channel region (222), The low potential source region (111) is formed in the substrate (1) and is at least partially located below the gate (6).

2. The electron source device according to claim 1, wherein The electron source device further includes: A low-voltage back metal electrode (12) is provided on the second main surface of the substrate (1).

3. The electron source device according to claim 1, wherein The electron acceleration layer (9) comprises a plurality of semiconductor crystal grains which are independent of each other, and an insulating medium of a predetermined thickness is provided between adjacent semiconductor crystal grains, wherein the insulating medium comprises silicon oxide (SiO2).

4. The electron source device according to claim 3, wherein The thickness of the electron acceleration layer (9) is 0.1 to 5 μm, and the characteristic size of the semiconductor grains is 1 to 50 nm.

5. The electron source device according to claim 3, wherein The predetermined thickness of the insulating medium is 0.3 to 2 nm. Under the isolation of the insulating medium, the adjacent semiconductor grains form a semiconductor grain chain structure with an insulating layer, and the direction of the semiconductor grain chain structure is perpendicular to the first main surface of the substrate.

6. The electron source device according to claim 1, wherein The thickness of the high-potential electron emitter conductive film (14) is 0.1-10 nm, and the material is one or more of metal, conductive compound, and conductive two-dimensional material.

7. The electron source device according to claim 1, wherein A gate insulating film (4, 5) is provided between the channel region (222) and the gate (6), Furthermore, the gate insulating film (4, 5) extends laterally between the low potential source region (111) and the gate (6). The gate (6) is electrically connected to the gate electrode (11).

8. The electron source device according to claim 7, wherein The shape of the channel region (222) is a cylinder, a cube, or a cuboid. The channel region (222) has a lateral dimension of 0.05 to 30 μm and a longitudinal dimension of 0.5 to 7 μm.

9. The electron source device according to claim 7, wherein The impurity concentration of the low potential source region (111) and / or the highly doped drain region (333) is 5×10 19 cm -3 above.

10. The electron source device according to claim 7, wherein The lateral size of the gate insulating film (4, 5) is 1 to 30 nm, The gate insulating film (4, 5) is made of silicon dioxide and / or silicon nitride.

11. The electron source device according to claim 1, wherein The thickness of the gate (6) is equal to or greater than the thickness of the channel region (222), and the material of the gate (6) is a highly doped semiconductor material or a metal material.

12. An integrated circuit, characterized in that: The integrated circuit comprises at least one electron source device according to any one of claims 1 to 11.

13. A method for manufacturing an electron source device, for manufacturing the electron source device according to any one of claims 1 to 11, characterized in that: The method comprises: A highly doped drain region (333), a channel region (222), and a low potential source region (111) are formed in a substrate (1), wherein the highly doped drain region (333) is formed on a first main surface of the substrate (1), the channel region (222) is located below the highly doped drain region (333), and the low potential source region (111) is at least partially located laterally outside the channel region (222) and at least partially located below the channel region (222); forming an electron acceleration layer (9) on the surface of the highly doped drain region (333); forming a gate insulating film (4, 5) and a gate (6) in sequence on the lateral outer side of the channel region (222); and An insulating film (10) and a high-potential electron emitter conductive film (14) are sequentially formed on the surface of the electron acceleration layer (9).

14. The method for manufacturing an electron source device according to claim 13, wherein: The steps of forming the electron acceleration layer (9) include: Growing an undoped silicon epitaxial layer on the surface of the substrate, and forming an N-type silicon region on top of the undoped silicon epitaxial layer; Performing photoelectrochemical etching on the N-type silicon region formed on the top to form porous silicon; and A passivation process is performed on the porous silicon to form a nano-crystal grain chain structure containing an insulating layer.

15. The method for manufacturing an electron source device according to claim 13, wherein: The steps of forming the electron acceleration layer (9) include: growing an undoped columnar polysilicon layer on the surface of the substrate, and forming an N-type polysilicon region on top of the columnar polysilicon layer; Performing photoelectrochemical etching on the N-type polysilicon region formed on the top to form porous polysilicon; and A passivation process is performed on the porous polycrystalline silicon to form a nanocrystalline grain chain structure containing an insulating layer.

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