A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, comprising the steps of: providing a device layer; forming a dielectric layer above the device layer; and forming a field plate above the dielectric layer, wherein the field plate comprises a first field plate layer and a second field plate layer, the first field plate layer comprises a silicon layer and a silicon oxide layer connected to the periphery of the silicon layer, at least a part of the upper surface of the silicon oxide layer extends in a slant direction away from the silicon layer, and the second field plate layer comprises a first metal and a second metal connected to the periphery of the first metal, and the extending direction of the second metal is consistent with the extending direction of the upper surface of the silicon oxide layer. The manufacturing method forms a laminated field plate comprising the first field plate and the second field plate layer, and the second field plate layer comprises the second metal extending in a slant direction, so that the field plate has a slant field plate structure, the high electric field modulation capability of the field plate is realized while the high dielectric breakdown voltage is maintained, the high working performance and the high reliability are combined, and the overall process steps are compatible with the existing process.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit devices and manufacturing technology, and relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In recent years, with the progress of material science, gallium nitride material has been widely used in power management, wireless communication and many other fields due to its superior physical properties. However, when the GaN-based high electron mobility transistor (HEMT) is working, there is an electric field concentration phenomenon at the edge of the gate close to the drain side, which increases the gate leakage current and easily leads to dielectric breakdown, so that the voltage resistance advantage of gallium nitride material cannot be maximized.

[0003] In order to improve the breakdown characteristics of gallium nitride devices, a common way is to use a field plate structure to improve the breakdown and other performances of gallium nitride devices. The field plate refers to a layer of structure (for example, a metal plate) covering the surface of the gallium nitride device, which is isolated from the device surface by a dielectric layer, and can reduce the local excessive electric field by modulating the electric field. However, in actual application, it is found that there is still a sharp peak of electric field at the edge of the field plate (equivalent to the phenomenon of electric field concentration on the side of the original gate towards the drain, which is eliminated due to the setting of the field plate, but a new electric field concentration effect is generated at the edge of the field plate), the problem of sharp end discharge still exists, which still affects the performance of the device.

[0004] Further in order to alleviate the problem of field plate sharp end discharge, the following technical means can be used to improve or alleviate: 1) increasing the thickness of the dielectric layer below the field plate to alleviate the dielectric breakdown problem, but this way will cause the undesired decrease of the original modulation electric field ability of the field plate; 2) using a multi-layer field plate structure, and the multi-layer field plate is staggered in a stepped manner, but this way will increase the difficulty of device manufacturing process, and also will cause the problem of uneven wafer surface affecting the subsequent process; 3) using an inclined field plate, which is complex and not easy to mass produce; 4) floating field plate, which still has the problem of edge electric field sharp peak and is easy to break down. That is, the technical means currently used either cannot effectively solve the problem of local electric field concentration, or will introduce new problems or weaken the electric field regulation ability that the field plate structure can originally achieve, or the process is complicated and not easy to mass produce.

[0005] Therefore, how to provide a semiconductor device and a manufacturing method thereof to effectively improve the problem of electric field concentration without increasing the process difficulty and complexity has become an important technical problem to be solved by those skilled in the art.

[0006] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and facilitating the understanding of the skilled in the art. The above technical scheme cannot be considered as known to the skilled in the art only because it is described in the background section of the present application. SUMMARY

[0007] In view of the above-mentioned disadvantages of the prior art, the present application aims to provide a semiconductor device and a manufacturing method thereof, which can effectively improve the field plate edge electric field concentration phenomenon, or increase the process complexity and is not easy to mass-produce.

[0008] To achieve the above object and other related objects, the present application provides a manufacturing method of a semiconductor device, comprising the following steps:

[0009] providing a device layer;

[0010] forming a dielectric layer above the device layer;

[0011] forming a field plate above the dielectric layer, the field plate comprising a first field plate layer and a second field plate layer, the first field plate layer being located between the dielectric layer and the second field plate layer, wherein the first field plate layer comprises a silicon layer and a silicon oxide layer, the silicon oxide layer being connected to the periphery of the silicon layer and at least a part of the upper surface of the silicon oxide layer extending along an inclined direction away from the silicon layer, the second field plate layer comprising a first metal and a second metal, the second metal being connected to the periphery of the first metal and the extending direction of the second metal being consistent with the extending direction of the upper surface of the silicon oxide layer.

[0012] Optionally, forming a field plate above the dielectric layer comprises the following steps:

[0013] sequentially forming a silicon base layer and a metal base layer above the dielectric layer, the metal base layer covering the upper surface of the silicon base layer and the end surface of the silicon base layer in the horizontal direction being exposed;

[0014] performing an oxidation treatment to oxidize the edge part of the silicon base layer into a silicon oxide layer, the un-oxidized part of the silicon base layer constituting the silicon layer, and the part of the metal base layer above the edge part constituting the second metal based on the formation of the silicon oxide layer.

[0015] Optionally, the temperature range of the oxidation treatment is 600-900℃, the time of the oxidation treatment is less than or equal to 30min, and the method of the oxidation treatment comprises at least one of dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, plasma oxidation, photochemical oxidation and electrochemical oxidation.

[0016] Optionally, the length of the silicon oxide layer is equal to the thickness of the silicon layer.

[0017] Optionally, the thickness of the silicon oxide layer increases in the direction in which the silicon layer points to the silicon oxide layer, or the thickness of the silicon oxide layer first increases and then remains unchanged.

[0018] Optionally, the material of the silicon layer includes at least one of amorphous silicon and polycrystalline silicon, the thickness of the silicon layer ranges from 5 to 20 nm, and the forming method of the silicon layer includes at least one of CVD, PVD and ALD; the second field plate layer includes at least one of a single metal material layer, a composite metal material layer and a stacked metal material layer, the material of the second field plate layer includes at least one of Al, Ni, W, Ti, Au, Ag, TiN, TiW and TaN, the thickness of the second field plate layer ranges from 50 to 200 nm, and the forming method of the second field plate layer includes at least one of CVD, PVD and ALD.

[0019] Optionally, the material of the medium layer includes at least one of SiN, SiO, SiON, AlN and Al2O3, the thickness of the medium layer ranges from 50 to 150 nm, and the forming method of the medium layer includes at least one of PECVD, SACVD, PVD and ALD.

[0020] Optionally, the device layer includes, from bottom to top, a substrate, a transition layer, a channel layer, a barrier layer and a gate structure, wherein the substrate includes at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate and a diamond substrate, the transition layer includes at least one of an AlN nucleation layer, a multi-quantum well buffer layer, an Al composition gradient buffer layer and a GaN buffer layer, the thickness of the transition layer ranges from 1 to 10 μm, the barrier layer includes at least one of an Al x Ga 1-x N (0≤x≤1) layer and an In y Al 1-y N (0≤y≤1) layer, the thickness of the barrier layer ranges from 10 to 25 nm, and the gate structure includes at least one of a P-type GaN gate, a P-type Al z Ga 1-z N (0≤z≤1) gate, a metal gate and a metal / insulator / semiconductor gate, and the thickness of the gate ranges from 50 to 150 nm.

[0021] The application further provides a semiconductor device, including:

[0022] a device layer;

[0023] a medium layer above the device layer;

[0024] A field plate is located above the dielectric layer, and the field plate comprises a first field plate layer and a second field plate layer, and the first field plate layer is located between the dielectric layer and the second field plate layer. The first field plate layer comprises a silicon layer and a silicon oxide layer, and the silicon oxide layer is connected to the periphery of the silicon layer, and at least part of the upper surface of the silicon oxide layer extends in a slanting direction away from the silicon layer. The second field plate layer comprises a first metal and a second metal, and the second metal is connected to the periphery of the first metal, and the extending direction of the second metal is consistent with the extending direction of the upper surface of the silicon oxide layer.

[0025] Optionally, the length of the silicon oxide layer is equal to the thickness of the silicon layer.

[0026] As described above, the method for manufacturing the semiconductor device of the present application forms a field plate comprising a first field plate layer and a second field plate layer, and the second field plate layer comprises a second metal extending in a slanting direction, thereby realizing a local slanting field plate structure. The high electric field modulation capability of the field plate is realized while maintaining a high dielectric breakdown voltage, and high work performance and high reliability are achieved. In addition, the thickness of the silicon oxide layer is increased during the process of oxidizing silicon into silicon oxide, and the metal is slanted due to mechanical action, thereby obtaining a second metal similar to a slanting field plate without additional process steps. The overall process is simple and easy to implement, and is basically compatible with the existing process. Compared with the traditional improvement method, the advantages are outstanding, and the method is suitable for mass production. The semiconductor device of the present application has a field plate structure comprising a first field plate layer and a second field plate layer, and the second field plate layer comprises a second metal extending in a slanting direction at the edge. The high electric field modulation capability is realized while maintaining a high breakdown voltage and high reliability. The overall structure is simple and low in cost, and is suitable for popularization and application. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A local cross-sectional schematic diagram of the structure obtained after providing a device layer in the method for manufacturing the semiconductor device of the present application is shown.

[0028] Figure 2 A local cross-sectional schematic diagram of the structure obtained after forming a dielectric layer in the method for manufacturing the semiconductor device of the present application is shown.

[0029] Figure 3 A local cross-sectional schematic diagram of the structure obtained after forming a silicon initial layer and a metal initial layer in the method for manufacturing the semiconductor device of the present application is shown.

[0030] Figure 4 A local cross-sectional schematic diagram of the structure obtained after forming a silicon base layer and a metal base layer in the method for manufacturing the semiconductor device of the present application is shown.

[0031] Figure 5 A local cross-sectional schematic diagram of the structure obtained after forming a field plate in the method for manufacturing the semiconductor device of the present application is shown.

[0032] Figure 6 is shown Figure 5 a first enlarged view of a partial region thereof.

[0033] Figure 7 is shown Figure 5 a second enlarged view of a partial region thereof.

[0034] Reference Signs List

[0035] 10 device layer

[0036] 11 substrate

[0037] 12 transition layer

[0038] 13 channel layer

[0039] 14 barrier layer

[0040] 15 gate structure

[0041] 20 dielectric layer

[0042] 30 silicon initial layer

[0043] 31 silicon base layer

[0044] 310 first field plate layer

[0045] 311 silicon layer

[0046] 312 silicon oxide layer

[0047] 40 metal initial layer

[0048] 41 metal base layer

[0049] 410 second field plate layer

[0050] 411 first metal

[0051] 412 second metal

[0052] 50 field plateDETAILED DESCRIPTION

[0053] The present application is herein described, by way of example only, with the assistance of specific details to facilitate a comprehensive understanding of the application by those skilled in the art. The application can be practiced in ways different from those specifically set forth herein without departing from the spirit of the present application. The description herein of the various aspects of the application is specifically made in reliance upon the teachings of the drawings, which form a part of the detailed description.

[0054] Reference Signs List Figures 1 to 7It is to be noted that the drawings provided in the embodiments merely schematically illustrate the basic concept of the present application, and thus only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and ratio of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0055] Embodiment One

[0056] The embodiment provides a semiconductor device manufacturing method, including the following steps.

[0057] S1: providing a device layer;

[0058] S2: forming a dielectric layer above the device layer;

[0059] S3: forming a field plate above the dielectric layer, the field plate including a first field plate layer and a second field plate layer, the first field plate layer being located between the dielectric layer and the second field plate layer, wherein the first field plate layer includes a silicon layer and a silicon oxide layer, the silicon oxide layer being connected to the periphery of the silicon layer and at least part of the upper surface of the silicon oxide layer extending in a slant direction away from the silicon layer, the second field plate layer including a first metal and a second metal, the second metal being connected to the periphery of the first metal and the extension direction of the second metal being consistent with the extension direction of the upper surface of the silicon oxide layer.

[0060] First, referring to Figure 1 , step S1 is performed to provide a device layer 10.

[0061] As an example, the device layer 10 includes, from bottom to top, a substrate 11, a transition layer 12, a channel layer 13, a barrier layer 14 and a gate structure 15, the barrier layer 14 and the channel layer 13 forming a heterojunction to form a two-dimensional electron gas. In a specific example, step S1 includes the following steps: providing a substrate 11, epitaxially growing the transition layer 12, the channel layer 13 and the barrier layer 14 on the substrate 11 in sequence; and forming a gate structure 15 above the barrier layer 14. In addition, although not shown in the drawings, the device layer 10 also includes structures such as source metal and drain metal arranged on both sides of the gate structure 15.

[0062] Further, the substrate 11 includes at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate and a diamond substrate, and the substrate 11 in the embodiment is a silicon substrate.

[0063] Further, the transition layer 12 includes at least one of an AlN nucleation layer, a multiple quantum well (MQW) buffer layer, an Al composition graded buffer layer, and a GaN buffer layer, and the thickness of the transition layer 12 ranges from 1 to 10 μm, including but not limited to 2 μm, 5 μm, and 8 μm. In the present embodiment, the transition layer 12 is a GaN buffer layer.

[0064] Further, the channel layer 13 includes GaN, and the thickness of the channel layer ranges from 300 to 1200 nm, including but not limited to 500 nm and 1000 nm.

[0065] Further, the barrier layer 14 includes at least one of an Al x Ga 1-x N (0≤x≤1) layer and an In y Al 1-y N (0≤y≤1) layer, and the thickness of the barrier layer 14 ranges from 10 to 25 nm, including but not limited to 13 nm, 18 nm, and 22 nm. In the present embodiment, the barrier layer 14 is an Al 0.2 Ga 0.8 N (i.e., x=0.2), and the thickness thereof is 15 nm.

[0066] Further, the gate structure 15 includes at least one of a P-type GaN gate, a P-type Al z Ga 1-z N (0≤z≤1) gate, a metal gate, and a metal / insulator / semiconductor (MIS) gate, and the thickness of the gate ranges from 50 to 150 nm, including but not limited to 75 nm, 95 nm, and 125 nm. In the present embodiment, the gate structure 15 is a P-type GaN gate, and the thickness thereof is 100 nm.

[0067] It should be noted that when the semiconductor device includes a HEMT device, the device layer includes a plurality of structure layers as described above, and in other embodiments, when the semiconductor device is another type of device (e.g., a MOS device), etc., a field plate structure can also be used to modulate the internal electric field, i.e., the semiconductor device of the present embodiment includes but is not limited to a HEMT device.

[0068] Next, referring to Figure 2 , a step S2 is performed to form a dielectric layer 20 above the device layer 10.

[0069] As an example, the material of the dielectric layer 20 includes at least one of SiN, SiO (i.e. silicon oxide, including silicon dioxide), SiON, AlN and Al2O3, the thickness of the dielectric layer 20 ranges from 50 to 150 nm, including but not limited to 75 nm, 100 nm and 125 nm, the forming method of the dielectric layer 20 includes at least one of PECVD, SACVD, PVD and ALD, and in the embodiment, the material of the dielectric layer 20 is SiN, the thickness of the dielectric layer 20 is 50 nm, and the dielectric layer 20 is formed by PECVD. It should be noted that, in the case where the field plate 50 of the embodiment is not provided, the thickness of the dielectric layer generally needs to be kept above a certain value (e.g. 150 to 250 nm) to avoid the dielectric breakdown problem caused by the local electric field concentration at the edge of the gate or the edge of the field plate 50, while in the embodiment, the device is provided with the field plate 50 having the above structure, the thickness of the dielectric layer 20 can be relatively thin and the breakdown problem is not easy to occur, while the field plate 50 has good electric field regulation capability.

[0070] Next, referring to Figures 3 to 5 , a step S2 is performed to form a field plate 50 above the dielectric layer 20, the field plate 50 including a first field plate layer 310 and a second field plate layer 410, the first field plate layer 310 being located between the dielectric layer 20 and the second field plate layer 410, wherein the first field plate layer 310 includes a silicon layer 311 and a silicon oxide layer 312, the silicon oxide layer 312 being connected to the periphery of the silicon layer 311 (equivalent to the silicon oxide layer 312 being located at the edge of the first field plate layer 310), and at least a part of the upper surface of the silicon oxide layer 312 extends obliquely away from the silicon layer 311 (i.e. forms an acute angle with the horizontal plane), the second field plate layer 410 including a first metal 411 and a second metal 412, the second metal 412 being connected to the periphery of the first metal 411 (equivalent to the second metal 412 being located at the edge of the second field plate layer 410), and the extension direction of the second metal 412 is consistent with the extension direction of the upper surface of the silicon oxide layer 312.

[0071] Specifically, the field plate structure in the embodiment has a first metal similar to a conventional field plate and a second metal similar to an inclined field plate, wherein the obliquely extending second metal is arranged at the periphery of the first metal, which is equivalent to tilting the edge part of the conventional field plate where the electric field is easy to concentrate as an inclined field plate, and the distribution of the electric field lines is changed by the arrangement of the second metal to reduce the electric field concentration degree, thereby avoiding the occurrence of the electric field concentration problem at the edge of the field plate, and without increasing the thickness of the dielectric layer below the field plate, the dielectric breakdown problem is avoided, the voltage withstanding performance and reliability of the device are improved, and the application prospect is expanded. In addition, Figure 5The second metal is locally enlarged to fully show the inclined extension of the second metal. In fact, in order to ensure that the field plate structure can avoid the problem of electric field concentration at the edge, the length of the second metal needs to be much smaller than the length of the first metal (for example, the length ratio is less than 1 / 30), that is, the second metal is located at the edge terminal position of the field plate and belongs to the edge part of the second field plate layer. In the field plate of the embodiment, the first metal is the main structure for modulating the electric field in the field plate, and the second metal is the auxiliary structure for adjusting the edge electric field line distribution in the field plate.

[0072] It should be noted that, since the field plate structure extending from one side of the gate electrode to the other side of the gate electrode is exemplarily illustrated in the embodiment, the gate electrode is formed above the barrier layer and the upper surface is obviously higher than the upper surface of the barrier layer. In the case where the thickness of the dielectric layer needs to be strictly limited to ensure good electric field modulation effect of the field plate, the upper surface of the dielectric layer is not completely parallel to the upper surface of the barrier layer by using a relatively thick dielectric layer to compensate for the surface flatness, which makes it necessary to have a height difference between the part above the gate electrode and the part on both sides of the gate electrode in the same structure layer. At this time, the part above the gate electrode is also considered to extend in the horizontal direction, only the height is different. That is, in the field plate structure of the embodiment, in addition to the inclined extension of the second metal, the silicon layer and the first metal also extend in the horizontal direction.

[0073] As an example, forming the field plate 50 above the dielectric layer 20 includes the following steps:

[0074] As shown in Figure 3 and Figure 4 , the silicon base layer 31 and the metal base layer 41 are formed above the dielectric layer 20, the metal base layer 41 covers the upper surface of the silicon base layer 31, and the end surface of the silicon base layer 31 in the horizontal direction is exposed;

[0075] Further, forming the silicon base layer 31 and the metal base layer 41 above the dielectric layer 20 includes the following steps:

[0076] As shown in Figure 3 , the silicon initial layer 30 and the metal initial layer 40 are sequentially formed above the dielectric layer 20;

[0077] As shown in Figure 4 , a photoresist layer (not shown) is formed above the metal initial layer 40, and the photoresist layer is subjected to photolithography to form an etching window (not shown) exposing at least a part of the upper surface of the metal initial layer 40. The position and pattern of the initial field plate (i.e., the structure composed of the silicon base layer and the metal base layer) are defined by the photolithography step;

[0078] Etching is performed on the photoresist layer after photolithography to expose at least a portion of the upper surface of the dielectric layer 20, so as to form a silicon base layer 31 based on the silicon initial layer 30 and a metal base layer 41 based on the metal initial layer 40 (i.e., etching away a portion of the metal initial layer 40 and a portion of the silicon initial layer 30, leaving the remaining silicon initial layer 30 as the silicon base layer 31, and the remaining metal initial layer 40 as the metal base layer 41). The horizontal end face of the silicon base layer 31 is exposed to facilitate subsequent oxidation processing.

[0079] like Figure 5 As shown, an oxidation process is performed to oxidize the edge portion of the silicon base layer 31 into a silicon oxide layer 312. The unoxidized portion of the silicon base layer 31 constitutes the silicon layer 311. The portion of the metal base layer 41 above the edge portion undergoes a tilting deformation based on the formation of the silicon oxide layer 312 to form the second metal 412. Correspondingly, the portion of the metal base layer 41 above the silicon layer 311 serves as the first metal 411. The first metal 41 and the second metal 412 together constitute the second field plate layer 410 (i.e., the edge portion of the metal base layer 41 is tilted to obtain the second field plate layer 410). It should be noted that "edge portion" is a relative concept. The degree of edge is adjusted based on the specific parameters of the oxidation process so that the structural parameters of the second metal (including length, tilt angle, morphology, etc.) meet the requirements for changing the electric field concentration.

[0080] As an example, the material of the silicon layer 311 includes at least one of amorphous silicon and polycrystalline silicon; the thickness of the silicon layer 311 ranges from 5 to 20 nm, including but not limited to 8 nm, 12 nm, and 18 nm; the formation method of the silicon layer 311 includes at least one of CVD, PVD, and ALD. Naturally, the above-mentioned parameters of the silicon initial layer 30 and the silicon base layer 31 are consistent with those of the silicon layer 311. In this embodiment, the material of the silicon layer 311 is amorphous silicon, the thickness of the silicon layer 311 is 10 nm, and it is formed by PECVD.

[0081] It should be noted that the silicon layer 311 in the embodiment cannot be made of single crystal silicon, because the deposition temperature of single crystal silicon film is as high as 1200 °C, and in the growth process, the already formed structure layers such as GaN buffer layer and dielectric layer in the device layer are easily damaged by heat, which will affect the actual working performance of the device. Therefore, when selecting the material for making the silicon layer 311, a material with a deposition temperature less than or equal to 900 °C or lower should be used, for example, polycrystalline silicon (deposition temperature is relatively low, 580-680 °C) or amorphous silicon (deposition temperature can be as low as room temperature). Of course, the silicon layer 311 can also be made of other materials with a deposition temperature that meets the above temperature condition. Because the thickness of the silicon layer 311 needs to meet the condition that after the oxidation treatment process, the part of the second field plate layer 410 located above the silicon layer 311 (i.e. the first metal) can be tilted at a certain angle compared with the part of the second field plate layer 410 located above the silicon layer 311 (i.e. the second metal) to improve the local electric field concentration phenomenon at the edge, therefore, after many tests, verification and adjustment, the above thickness range of the silicon layer 311 is summarized.

[0082] As an example, the second field plate layer 410 includes at least one of a single metal material layer (a single structure layer including only one kind of metal or metal compound), a composite metal material layer (a single structure layer including multiple kinds of metal or metal compound) and a stacked metal material layer (including at least two layers of structure, each layer of structure has the same or different material and each layer of material can be single or multiple). In the embodiment, the second field plate layer 410 is a single metal material layer.

[0083] Further, the material of the second field plate layer 410 includes at least one of Al, Ni, W, Ti, Au, Ag, TiN, TiW and TaN, the thickness of the second field plate layer 410 ranges from 50 to 200 nm, including but not limited to 90 nm, 130 nm and 180 nm; the forming method of the second field plate layer 410 includes at least one of CVD, PVD and ALD, and the above parameters of the metal initial layer 40 and the metal base layer 41 are consistent with the second field plate layer 410. In the embodiment, the material of the second field plate layer 410 is TiN, the thickness of the second field plate layer 410 is 80 nm and the second field plate layer 410 is formed by PVD. The material of the second field plate layer 410 is preferably a metal or a metal compound that is not easy to be oxidized under high temperature conditions (≥600°C), such as Au, Ag, TiN and the like, because in the subsequent oxidation process to oxidize the edge of the silicon base layer 31 into the silicon oxide layer 312, the metal base layer 41 is also in an oxidation environment, if a reactive metal is used, it is very likely to be undesirably oxidized and lose or weaken its basic electric field modulation ability as a field plate, or an additional step is needed to remove the metal oxide after the oxidation of the metal base layer to obtain the second field plate layer 410, which will increase the process cost. Of course, if the process cost is not considered and only the electric field regulation effect of the field plate structure itself is considered, Al, Ni and the like can also be used to make the second field plate layer 410, and in order to ensure that the structure of the second field plate layer 410 meets the needs of electric field regulation, a barrier layer can be used to wrap the second field plate layer 410 to avoid its surface being exposed to the oxidation environment to avoid metal oxidation reaction, or a relatively thick metal initial layer is formed and is exposed to the oxidation environment, and after the oxidation process is completed, the surface metal oxide layer is etched or corroded to leave the unoxidized part as the second field plate layer 410, which is not limited here, and the material and thickness of the second field plate layer can be selected based on actual needs.

[0084] As an example, the temperature of the oxidation process ranges from 600 to 900°C, including but not limited to 680°C, 750°C and 820°C; the time of the oxidation process is less than or equal to 30 min, including but not limited to 10 min, 18 min and 25 min; the method of the oxidation process includes at least one of dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, plasma oxidation, photochemical oxidation and electrochemical oxidation. The temperature and time of the oxidation process are reasonably selected based on the inclination degree and topography requirements of the pre-formed second metal 412, and more preferably, the edge (i.e. the surface in the horizontal direction) of the silicon base layer 31 is completely oxidized, and in the embodiment, the oxidation process is high-temperature oxidation at 900°C, which can improve the oxidation rate.

[0085] As an example, the length of the silicon oxide layer 312 (i.e. the oxidation depth, Figure 6 is adjusted by the process parameters of the oxidation process, and more preferably, please refer to Figure 6 , the length of the silicon oxide layer 312 is equal to the thickness of the silicon layer 311 (indicated by t in Figure 6 ).

[0086] Specifically, in the present embodiment, since the structure of the second metal 412 corresponds to the structure of the silicon oxide layer 312, and the thickness of the dielectric layer 20 under the field plate 50 is limited, if the length of the silicon oxide layer 312 is too large (i.e. the oxidation depth is too deep), the proportion of the second metal 412 is too large (causing the part of the second field plate layer that is inclined to be located not only at the edge terminal position but also at the main body position), and in the process of device operation, since the second metal 412 is under the silicon oxide layer 312 and the dielectric layer 20, the overall thickness of the field plate dielectric is relatively thick, which causes the problem of weakening the electric field modulation capability, and if the length of the silicon oxide layer 312 is too small, the size of the second metal 412 is relatively small, and the local inclination of the second field plate layer 410 is not enough to effectively improve the electric field concentration problem, therefore, it is preferred that the length of the silicon oxide layer 312 is equal to the thickness of the silicon layer 311. Since the morphology (especially the cross-sectional morphology) and size of the second metal 412 in the field plate structure are directly related to the morphology and size of the silicon oxide layer 312, and the silicon oxide layer 312 is obtained by oxidation at the edge of the silicon base layer 31 and is directly related to the thickness of the silicon base layer 31 (consistent with the thickness of the silicon layer 311), therefore, based on the "length of the silicon oxide layer is equal to the thickness of the silicon layer", the suitable size range of the second metal 412 is limited (i.e. the vertical projection length of the second metal 412 is equal to the thickness of the silicon layer 311), within the above-mentioned suitable size range, the second metal 312 only belongs to the field plate edge terminal structure, and the field plate structure can reduce or avoid the occurrence of the electric field concentration problem at the edge of the field plate and will not deteriorate other working performance of the device.

[0087] In an example, as shown in Figure 6 , a first kind of enlarged schematic view of the partial region (the region shown by the dashed line box) in Figure 5 , in the direction of the silicon layer 311 pointing to the silicon oxide layer 312, the thickness of the silicon oxide layer 312 first increases and then remains unchanged, i.e. the part of the silicon oxide layer 312 higher than the silicon layer 311 (the area above the dashed line in Figure 6 ) in the vertical cross-section in the width direction of the gate structure 14 is trapezoidal, so that the second metal 412 first presents an inclined shape and then presents a platform shape, at this time, the inclined part of the second metal 412 plays a similar technical effect as the traditional inclined field plate, and due to the existence of the silicon oxide layer 312, even though the platform part is located at the most edge, but due to the existence of the silicon oxide layer 312 below, it will not cause the breakdown problem of the dielectric layer 20 below.

[0088] In another example, referring to Figure 7 , a second enlarged view of a local area (the area shown by the dashed line) in Figure 5 , the thickness of the silicon oxide layer 312 increases in the direction in which the silicon layer 311 points to the silicon oxide layer 312, i.e., the part of the silicon oxide layer 312 that is higher than the silicon layer 311 (the area above the dashed line in Figure 7 ) is triangular in vertical cross-section in the width direction of the gate structure 14, so that the second metal 412 is overall inclined, and the second metal 412 can play the electric field regulating effect of a conventional inclined field plate without increasing the process complexity. The above two thickness variation trends of the silicon oxide layer 312 are adjusted by the ratio of the vertical oxidation speed to the horizontal oxidation speed during oxidation of the silicon base layer. When the horizontal oxidation speed is slower than the vertical oxidation speed, the side surface silicon material of the silicon base layer is completely consumed and oxidized into silicon oxide, and the oxidation depth in the horizontal direction still does not meet the actual needs and continues to be oxidized, at which time the thickness of the silicon oxide at the edge no longer changes and is platform-shaped, as shown in Figure 6 ; and when the horizontal oxidation speed is faster than the horizontal oxidation speed, the side surface silicon material of the silicon base layer is completely consumed and oxidized into silicon oxide at the same time, and the oxidation depth in the horizontal direction also meets the actual needs and stops continuing to be oxidized, as shown in Figure 7 .

[0089] It should be noted that although the present embodiment takes the example of extending the field plate from one side of the gate to the other side of the gate for example, in fact, the position of the field plate can extend from above the gate to between the gate and the drain, can be located between the gate and the source, and can be distributed in multiple positions. In addition, from the perspective of electrical connection, the field plate can be a contact field plate (for example, a source field plate, a gate field plate, or a drain field plate) or a floating field plate (not connected to any electrode and in a floating state), which is not mandatory.

[0090] Specifically, the manufacturing method of the present embodiment first manufactures an initial stacked field plate structure of the silicon base layer and the metal base layer, and then oxidizes the edge of the silicon base layer to convert it into a silicon oxide layer. In the process of growing silicon oxide from silicon, on the one hand, the thickness of the silicon oxide layer increases compared to the thickness of the silicon base layer. For example, in the case of converting silicon into silicon dioxide, about 0.44 unit thickness of silicon is consumed for every unit thickness of silicon dioxide grown, i.e., about 23 nm of silicon dioxide is formed after 10 nm of amorphous silicon is oxidized, which causes the part of the metal base layer (i.e., the second metal) attached to the corresponding position above the silicon base layer to be lifted up by the underlying silicon oxide layer and gradually deformed with the oxidation of the silicon oxide layer; on the other hand, the oxidizing agent diffuses from the edge of the silicon base layer to the inside during the oxidation process,Figure 6 The second metal presents a similar inclined morphology, and the part of the silicon base layer remaining after oxidation serves as a silicon layer and the partially inclined metal base layer serves as a second field plate layer, thereby forming a laminated field plate including the first field plate layer and the second field plate layer. The inclined structure of the second metal enables the overall field plate to produce a technical effect similar to that of an inclined field plate. In short, the manufacturing method has the following advantages:

[0091] 1) The edge region of the second field plate layer in the field plate structure (i.e., the second metal) is at least partially inclined, which is equivalent to forming a local inclined field plate structure at the edge of the field plate, effectively improving the regulation ability of the field plate on the electric field without causing the problem of edge electric field concentration;

[0092] 2) The field plate can be applied above a relatively thin dielectric layer to ensure good regulation ability of the field plate on the electric field, and the dielectric breakdown problem does not occur due to the thin dielectric layer, effectively improving the voltage resistance performance of the device and fully utilizing and exploiting the voltage resistance advantage of GaN material;

[0093] 3) The silicon oxide layer obtained by oxidizing the edge part of the silicon base layer as an additional structure of the dielectric layer increases the thickness of the dielectric at the edge of the field plate, which can ensure that the dielectric below the field plate is not broken down even in the case of a local strong electric field at the edge of the field plate, while avoiding the problem of parasitic capacitance caused by the multi-layer field plate, and only the structure of the local region is increased, which does not weaken the electric field regulation ability of the field plate itself;

[0094] 4) When the edge part of the silicon base layer is oxidized, the oxidation reaction gradually develops from the edge to the middle, and the length of the silicon oxide layer can be adjusted by setting the oxidation process (the longer the oxidation time, the deeper the diffusion of oxygen elements into the interior of the silicon base layer, and the wider the area thickened due to oxidation), which has good controllability;

[0095] 5) The oxidation process is a self-aligned process that does not require steps such as photolithography and etching, and the process flow is simple and the process precision is easy to guarantee, with good repeatability and process stability;

[0096] 6) The overall process is simple and easy to implement, and can be fully compatible with existing device processes without the need to develop new processes or equipment, which is suitable for large-scale high-quality production.

[0097] The manufacturing method of the semiconductor device of the embodiment forms a silicon layer-metal layer laminated field plate including a first field plate layer and a second field plate layer, and the second field plate layer includes a second metal extending in a slanting direction to form a locally slanted field plate structure. The field plate can achieve high electric field modulation capability while maintaining high dielectric breakdown voltage, and has high working performance and high reliability. In addition, the second metal with a slanted field plate structure is obtained without additional process steps by using the thickness increasing feature of silicon oxidation to silicon oxide to make the metal slant due to mechanical action. The overall process is simple and easy to implement, and is basically compatible with existing processes. Compared with traditional improvement methods, the advantages are outstanding, and is suitable for mass production.

[0098] Embodiment two

[0099] The application also provides a semiconductor device which can be manufactured by the manufacturing method of embodiment one or other suitable method. Please refer to Figure 5 , which shows a partial cross-sectional view of the device. The device includes a device layer 10, a dielectric layer 20 and a field plate 50.

[0100] Specifically, the dielectric layer 20 is located above the device layer 10, the field plate 50 is located above the dielectric layer 20, and the field plate 50 includes a first field plate layer 310 and a second field plate layer 410, and the first field plate layer 310 is located between the dielectric layer 20 and the second field plate layer 410. The first field plate layer 310 includes a silicon layer 311 and a silicon oxide layer 312, the silicon oxide layer 312 is connected to the periphery of the silicon layer 311, and at least part of the upper surface of the silicon oxide layer 312 extends in a slanting direction away from the silicon layer 311. The second field plate layer 410 includes a first metal 411 and a second metal 412, and the second metal 412 is connected to the periphery of the first metal 411, and the extension direction of the second metal 412 is consistent with the extension direction of the upper surface of the silicon oxide layer 312.

[0101] Specifically, the slanted appearance of the second metal 412 in the field plate 50 allows the field plate 50 to well regulate the electric field without causing local concentration of edge electric field. The silicon oxide layer 312 is used to assist in forming the special structure of the field plate 50, and also serves as an additional part of the dielectric layer 20 below the field plate 50 to improve the breakdown characteristics of the device without affecting the electric field modulation capability.

[0102] As an example, the device layer 10 includes a substrate 11, a transition layer 12, a channel layer 13, a barrier layer 14 and a gate structure 15 stacked in order from bottom to top, and the device layer 10 also includes source metal and drain metal structures arranged on both sides of the gate structure 15.

[0103] As an example, the length of the silicon oxide layer 312 is equal to the thickness of the silicon layer 311.

[0104] As an example, in the direction in which the silicon layer 311 points to the silicon oxide layer 312, the thickness of the silicon oxide layer 312 increases first and then remains unchanged.

[0105] The semiconductor device of the embodiment has a laminated field plate including a first field plate layer and a second field plate layer, and the second field plate layer includes a second metal extending obliquely at the edge, which has high breakdown voltage and high reliability while ensuring high electric field modulation capability, and has simple overall structure and low cost, and is suitable for popularization and application.

[0106] In summary, the manufacturing method of the semiconductor device of the embodiment forms a laminated field plate including a first field plate layer and a second field plate layer, and the second field plate layer includes a second metal extending obliquely to form a locally inclined field plate structure, which uses the field plate to achieve high electric field modulation capability while maintaining high dielectric breakdown voltage, and has high working performance and high reliability. In addition, the thickness of the metal is increased due to the mechanical effect during the process of oxidizing silicon to silicon oxide, and the second metal similar to the inclined field plate is obtained without additional process steps, and the overall process steps are simple and easy to implement, and are basically compatible with the existing process. Compared with the traditional improvement method, the advantages are outstanding, and it is suitable for mass production. The semiconductor device of the embodiment has a laminated field plate including a first field plate layer and a second field plate layer, and the second field plate layer includes a second metal extending obliquely at the edge, which has high breakdown voltage and high reliability while ensuring high electric field modulation capability, and has simple overall structure and low cost, and is suitable for popularization and application. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0107] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a device layer, wherein the device layer comprises a gate structure; forming a dielectric layer above the device layer; forming a field plate above the dielectric layer, wherein the field plate comprises a first field plate layer and a second field plate layer, the first field plate layer is located between the dielectric layer and the second field plate layer, the first field plate layer comprises a silicon layer and a silicon oxide layer, the silicon oxide layer is connected to the periphery of the silicon layer, and at least part of the upper surface of the silicon oxide layer extends in an oblique direction away from the silicon layer, the second field plate layer comprises a first metal and a second metal, the second metal is connected to the periphery of the first metal, and the extension direction of the second metal is consistent with the extension direction of the upper surface of the silicon oxide layer; wherein the periphery refers to the side of the silicon layer away from the gate structure in the extension direction of the silicon layer, the oblique extension refers to the oblique upward extension, and in the direction of the silicon layer pointing to the silicon oxide layer, the thickness of the silicon oxide layer increases or first increases and then remains unchanged, the silicon oxide layer is formed by oxidizing the edge of the silicon base layer of the silicon layer, and the second metal extends in the oblique direction following the silicon oxide layer.

2. The method of manufacturing a semiconductor device according to claim 1, wherein: The method for forming a field plate above the dielectric layer comprises the following steps: forming a silicon base layer and a metal base layer above the dielectric layer in sequence, the metal base layer covers the upper surface of the silicon base layer, and the end surface of the silicon base layer in the horizontal direction is exposed; performing an oxidation treatment to oxidize the edge part of the silicon base layer into a silicon oxide layer, the part of the silicon base layer that is not oxidized constitutes the silicon layer, and the part of the metal base layer above the edge part constitutes the second metal based on the formation of the silicon oxide layer.

3. The method of manufacturing a semiconductor device according to claim 2, wherein: The temperature range of the oxidation treatment is 600-900 ℃, the time of the oxidation treatment is less than or equal to 30 min, and the method of the oxidation treatment comprises at least one of dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, plasma oxidation, photochemical oxidation and electrochemical oxidation.

4. The method of fabricating a semiconductor device according to claim 2, wherein: The length of the silicon oxide layer is equal to the thickness of the silicon layer.

5. The method of fabricating a semiconductor device according to claim 1, wherein: The material of the silicon layer comprises at least one of amorphous silicon and polycrystalline silicon, the thickness of the silicon layer ranges from 5 nm to 20 nm, and the forming method of the silicon layer comprises at least one of CVD, PVD and ALD; the second field plate layer comprises at least one of a single metal material layer, a composite metal material layer and a laminated metal material layer, the material of the second field plate layer comprises at least one of Al, Ni, W, Ti, Au, Ag, TiN, TiW and TaN, the thickness of the second field plate layer ranges from 50 nm to 200 nm, and the forming method of the second field plate layer comprises at least one of CVD, PVD and ALD.

6. The method of fabricating a semiconductor device according to claim 1, wherein: The material of the dielectric layer comprises at least one of SiN, SiO, SiON, AlN and Al2O3, the thickness of the dielectric layer ranges from 50 nm to 150 nm, and the forming method of the dielectric layer comprises at least one of PECVD, SACVD, PVD and ALD.

7. The method of fabricating a semiconductor device according to Claim 1, wherein: The device layer comprises, from bottom to top, a substrate, a transition layer, a channel layer, a barrier layer and a gate structure, wherein the substrate comprises at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate and a diamond substrate, the transition layer comprises at least one of an AlN nucleation layer, a multi-quantum well buffer layer, an Al composition gradient buffer layer and a GaN buffer layer, the thickness of the transition layer ranges from 1 to 10 μm, the barrier layer comprises at least one of an Al x Ga 1-x N (0≤x≤1) layer and an In y Al 1-y N (0≤y≤1) layer, the thickness of the barrier layer ranges from 10 to 25 nm, the gate structure comprises at least one of a P-type GaN gate, a P-type Al z Ga 1-z N (0≤z≤1) gate, a metal gate and a metal / insulator / semiconductor gate, and the thickness of the gate ranges from 50 to 150 nm.

8. A semiconductor device, characterized by The method comprises the following steps: providing a device layer, wherein the device layer comprises a gate structure; forming a dielectric layer above the device layer; ​ A field plate is located above the dielectric layer, the field plate comprises a first field plate layer and a second field plate layer, the first field plate layer is located between the dielectric layer and the second field plate layer, wherein the first field plate layer comprises a silicon layer and a silicon oxide layer, the silicon oxide layer is connected to the periphery of the silicon layer and at least part of the upper surface of the silicon oxide layer extends in a slant direction away from the silicon layer, the second field plate layer comprises a first metal and a second metal, the second metal is connected to the periphery of the first metal and the extension direction of the second metal is consistent with the extension direction of the upper surface of the silicon oxide layer; wherein the periphery refers to the side of the silicon layer away from the gate structure along the extension direction of the silicon layer, the slant extension is upward slant extension, and in the direction of the silicon layer pointing to the silicon oxide layer, the thickness of the silicon oxide layer increases or first increases and then remains unchanged, the silicon oxide layer is formed by oxidizing the edge of the silicon base layer of the silicon layer, and the second metal follows the slant extension of the silicon oxide layer.

9. The semiconductor device of claim 8, wherein: The length of the silicon oxide layer is equal to the thickness of the silicon layer.

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