A vdmos trench type electric field modulation variable-doping terminal

Abstract

The utility model provides a kind of VDMOS trench type electric field modulation variable doping terminal, comprising: drift layer is located on the upside of silicon carbide substrate, P+ trap region, main knot, first field limiting ring, second field limiting ring and P+ area are equipped in drift layer, P+ trap region, main knot, first field limiting ring and second field limiting ring are sequentially connected, P+ area is located in one end of drift layer, and located in one side of second field limiting ring;Insulating layer underside is connected to P+ trap region, main knot, first field limiting ring, second field limiting ring, drift layer and P+ area respectively;The width of main knot is greater than the width of first field limiting ring, and the width of first field limiting ring is greater than the width of second field limiting ring;The depth of main knot is less than the depth of first field limiting ring, and the depth of first field limiting ring is less than the depth of second field limiting ring;Cut-off ring metal layer underside is connected to P+ area, solve the breakdown problem caused by electric field concentration, improve the reliability of device.

Description

Technical Field

[0001] This utility model relates to a VDMOS trench-type electric field modulation variable doping terminal. Background Technology

[0002] Silicon carbide VDMOS is a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, and power conversion. Based on the device structure design, the electric field concentration occurs at the edges of repeating cells due to the lateral distribution of the electric field, leading to breakdown at the device edges. Traditional cells use field-limiting ring structures with the same doping concentration to suppress this electric field concentration. However, because the doping concentration and spacing of the field-limiting rings are equal, the electric field intensity gradually decreases, and there are still differences in the electric field distribution. The risk of breakdown remains high in the region near the P+ well region. Utility Model Content

[0003] The technical problem to be solved by this invention is to provide a VDMOS trench-type electric field modulation variable doping terminal to solve the breakdown problem caused by electric field concentration and improve the reliability of the device.

[0004] In a first aspect, this utility model provides a VDMOS trench-type electric field modulation variable doping terminal, comprising:

[0005] silicon carbide substrate;

[0006] A drift layer is disposed on the upper side of the silicon carbide substrate. The drift layer contains a P+ well region, a main junction, a first field limiting ring, a second field limiting ring, and a P+ region. The P+ well region, the main junction, the first field limiting ring, and the second field limiting ring are connected in sequence. The P+ region is disposed at one end of the drift layer and is located on one side of the second field limiting ring.

[0007] An insulating layer, the lower side of which is connected to the P+ well region, the main junction, the first field limiting ring, the second field limiting ring, the drift layer, and the P+ region respectively; the width of the main junction is greater than the width of the first field limiting ring, and the width of the first field limiting ring is greater than the width of the second field limiting ring; the depth of the main junction is less than the depth of the first field limiting ring, and the depth of the first field limiting ring is less than the depth of the second field limiting ring.

[0008] A stop ring metal layer, the lower side of which is connected to the P+ region.

[0009] The advantages of this utility model are:

[0010] I. This utility model provides a high resistivity conductor layer on the top of the device terminal structure. When the drain is subjected to voltage, there is a voltage difference between the source metal layer and the cutoff ring metal layer. The high resistivity conductor layer makes the voltage evenly distributed in this region, thereby forming a uniformly distributed electric field under the insulating layer, suppressing the breakdown problem caused by the electric field concentration near the P+ well region.

[0011] II. This invention constructs a first P-type doped region, a second P-type doped region, and a third P-type doped region with gradually decreasing concentration, gradually decreasing width, and gradually increasing depth from the P+ well region to the stop ring metal layer. The first P-type doped region reduces the electric field strength at the interface with the P+ well region, the second P-type doped region reduces the electric field strength at the interface with the first P-type doped region, and the third P-type doped region reduces the electric field strength at the interface with the second P-type doped region and the drift layer.

[0012] Third, the depth of the first, second, and third P-type doped regions gradually increases in order to extend the interface with the strongest electric field intensity into the device interior, so as to avoid the electric field at the device surface affecting the electric field distribution near the cutoff ring metal layer and thus affecting the device reliability. Attached Figure Description

[0013] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0014] Figure 1 This is a schematic diagram of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention.

[0015] Figure 2 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 1 .

[0016] Figure 3 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 2 .

[0017] Figure 4 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 3 .

[0018] Figure 5 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 4 .

[0019] Figure 6 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 5 .

[0020] Figure 7This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 6 .

[0021] Figure 8 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 7 .

[0022] Figure 9 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 8 .

[0023] Figure 10 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 9 .

[0024] Figure 11 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 10 .

[0025] Figure 12 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 10 one.

[0026] Figure 13 This is a cross-sectional view of the process of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention. Figure 10 two. Detailed Implementation

[0027] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0030] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0031] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0032] like Figure 1 As shown, this application embodiment provides a VDMOS trench-type electric field modulation variable doping terminal, including:

[0033] Silicon carbide substrate 1; a drain metal layer 5 is provided on the lower side of silicon carbide substrate 1;

[0034] A drift layer 2 is disposed on the upper side of the silicon carbide substrate 1. The drift layer 2 contains a P+ well region 21, a main junction 22, a first field limiting ring 23, a second field limiting ring 24, and a P+ region 25. The P+ well region 21, the main junction 22, the first field limiting ring 23, and the second field limiting ring 24 are connected in sequence. The P+ region 25 is disposed at one end of the drift layer 2 and is located on one side of the second field limiting ring 24.

[0035] An insulating layer 3 has its lower surface connected to the P+ well region 21, the main junction 22, the first field limiting ring 23, the second field limiting ring 24, the drift layer 2, and the P+ region 25, respectively. The width of the main junction 22 is greater than the width of the first field limiting ring 23, and the width of the first field limiting ring 23 is greater than the width of the second field limiting ring 24. The depth of the main junction 22 is less than the depth of the first field limiting ring 23, and the depth of the first field limiting ring 23 is less than the depth of the second field limiting ring 24.

[0036] The stop ring metal layer 4 is connected to the P+ region 25 on its lower side; the source metal layer 7 is connected to the P+ region 25 and the drift layer 2.

[0037] In this embodiment, preferably, the main junction 22 includes a first P-type doped region 221 and a first P-type trench region 222, the first P-type doped region 221 being connected to the P+ well region 21, and the first P-type trench region 222 being disposed within the first P-type doped region 221; the first field limiting ring 23 includes a second P-type doped region 231 and a second P-type trench region 232, the second P-type trench region 232 being disposed within the second P-type doped region 231, and the second P-type doped region 231 being connected to the first P-type doped region 221; the second field limiting ring 24 includes a third P-type doped region 241 and a third P-type trench region 242, the third P-type trench region 242 being disposed within the third P-type doped region 241, and the third P-type doped region 241 being connected to the second P-type doped region 231.

[0038] The width of the first P-type groove region 222 is greater than the width of the second P-type groove region 232, and the width of the second P-type groove region 232 is greater than the width of the third P-type groove region 242.

[0039] The depth of the first P-type trench region 222 is less than the depth of the second P-type trench region 232, and the depth of the second P-type trench region 232 is less than the depth of the third P-type trench region 242.

[0040] The width of the first P-type doped region 221 is greater than the width of the second P-type doped region 231, and the width of the second P-type doped region 231 is greater than the width of the third P-type doped region 241.

[0041] The depth of the first P-type doped region 221 is less than the depth of the second P-type doped region 231, and the depth of the second P-type doped region 231 is less than the depth of the third P-type doped region 241.

[0042] In this embodiment, preferably, the doping concentration of the first P-type trench region 222 is greater than the doping concentration of the second P-type trench region 232, and the doping concentration of the second P-type trench region 232 is greater than the doping concentration of the third P-type trench region 242.

[0043] The doping concentration of the first P-type doped region 221 is greater than that of the second P-type doped region 231, and the doping concentration of the second P-type doped region 231 is greater than that of the third P-type doped region 241.

[0044] In this embodiment, preferably, the lower side surface of the first P-type doped region 221, the lower side surface of the second P-type doped region 231, and the lower side surface of the third P-type doped region 241 are all arc-shaped.

[0045] In this embodiment, preferably, the depth of the P+ region 25 is less than the depth of the first P-type doped region 221.

[0046] In this embodiment, preferably, it further includes a high resistivity conductor layer 6, the lower side of which is connected to the insulating layer 3, the left side of which is connected to the source metal layer 7, and the right side of which is connected to the cutoff ring metal layer 4.

[0047] In this embodiment, preferably, the thickness of the high resistivity conductor layer 6 is greater than the thickness of the insulating layer 3.

[0048] like Figures 1 to 13 As shown, the method for preparing the above-mentioned terminal includes the following steps:

[0049] Step 1: Epitaxial growth is performed on the upper side of silicon carbide substrate 1 to obtain drift layer 2;

[0050] Step 2: Form a barrier layer 8 above the drift layer 2, etch the barrier layer 8 to form a via, and implant ions to form a P+ well region 21 and a P+ region 25.

[0051] Step 3: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, and etch the drift layer 2 to form the first groove 26, the second groove 27 and the third groove 28.

[0052] Step 4: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, and etch the second groove 27 and the third groove 28 downwards.

[0053] Step 5: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, and etch the third groove 28 downwards;

[0054] Step 6: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a via, deposit silicon carbide material to form the first P-type trench region 222;

[0055] Step 7: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a via, deposit silicon carbide material to form the second P-type trench region 232;

[0056] Step 8: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a via, deposit silicon carbide material, and form the third P-type trench region 242.

[0057] Step 9: Remove the barrier layer 8 and reform the barrier layer 8. Set the temperature to 1200 degrees Celsius and the time to 80 minutes. Perform thermal diffusion redistribution on the first P-type trench region 222, the second P-type trench region 232, and the third P-type trench region 242 to form the first P-type doped region 221, the second P-type doped region 231, and the third P-type doped region 241. The main junction 22 includes the first P-type doped region 221 and the first P-type trench region 222. The first field limiting ring 23 includes the second P-type doped region 231 and the second P-type trench region 232. The second field limiting ring 24 includes the third P-type doped region 241 and the third P-type trench region 242. The P+ well region 21, the first P-type doped region 221, the second P-type doped region 231, and the third P-type doped region 241 are connected in sequence.

[0058] Step 10: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a via, and deposit the insulating layer 3.

[0059] Step 11: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a via, and deposit to form the source metal layer 7 and the stop ring metal layer 4.

[0060] Step 12: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a via, deposit and form a high resistivity conductor layer 6, and remove the barrier layer 8.

[0061] In another embodiment of this invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer is 5-9e16cm. -3 The doping concentration of the third P-type doped region 241 is 2-8e16cm. -3 The doping concentration of the second P-type doped region 231 is 0.8-5e17cm. -3 The doping concentration of the first P-type doped region 221 is 0.5-5e18cm.-3 The doping concentrations of P+ well region 21 and P+ region 25 are both 5-8e18cm. -3 The doping concentration of the third P-type trench region 242 is 2-8e17cm. -3 The doping concentration of the second P-type trench region 232 is 0.8-5e18cm. -3 The doping concentration of the first P-type doped region 221 is 0.5-5e19cm. -3 The insulating layer 3 can be made of silicon dioxide, the source metal layer 7 and the stop ring metal layer 4 can be made of one or more metals such as Al, Cu and Ni, and the high resistivity conductor layer 6 can be made of SIPOS material or low-doped polycrystalline silicon.

[0062] The doping concentrations of the silicon carbide substrate 1, drift layer 2, and p+ well region 21 are considered in the traditional design structure of planar gate silicon carbide VDMOS devices. The doping concentrations of the third P-type trench region 242, the second P-type trench region 232, and the first P-type trench region 222 are to form the corresponding concentrations of the third P-type doped region 241, the second P-type doped region 231, and the first P-type doped region 221 under thermal diffusion process conditions. The doping concentrations of the third P-type doped region 241, the second P-type doped region 231, and the first P-type doped region 221 are to form a distribution in which the P-type doping concentration gradually decreases from the P+ well region 21 to the first P-type doped region 221, the second P-type doped region 231, the third P-type doped region 241, and finally to the stop ring metal layer 4.

[0063] like Figure 1 As shown, d1 is 10 μm, d2 is 6 μm, d3 is 3 μm, w1 is 2 μm, w2 is 1 μm, and w3 is 0.5 μm. This is the width design after electric field distribution optimization matching the doping concentration and the distribution caused by thermal diffusion under trench doping conditions.

[0064] The depth of the P+ well region 21 is 1 μm, the depth of the first P-type doped region 221 is 1.5 μm, the depth of the second P-type doped region 231 is 2 μm, the depth of the third P-type doped region 241 is 3 μm, the depth of the third P-type trench region 242 is 2 μm, the depth of the second P-type trench region 232 is 1.2 μm, and the depth of the first P-type trench region 222 is 0.7 μm. This is to form a structure in which the depth of the P+ well region 21, the first P-type doped region 221, the second P-type doped region 231, and the third P-type doped region 241 gradually increases. The trench depth is to form doped regions of corresponding depths.

[0065] The doped region in the device terminal is fabricated by thermal diffusion. Because the trench is etched, the thermal diffusion depth of the device can be guaranteed. At the same time, compared with ion implantation, thermal diffusion causes less lattice damage to the device, and the device has higher reliability and stability.

[0066] The device has an insulating layer 3 with a thickness of 100 nm, a high resistivity conductor layer 6 with a thickness of 500 nm, and a source metal layer 7 and a cutoff ring metal layer 4 with a thickness of 600 nm each.

[0067] By setting a high resistivity conductor layer 6 on the top of the device terminal structure, when the drain is subjected to voltage, there is a voltage difference between the source metal layer 7 and the cutoff ring metal layer 4. The high resistivity conductor layer 6 makes the voltage evenly distributed in this region, thereby forming a uniformly distributed electric field under the insulating layer 3, suppressing the breakdown problem caused by the electric field concentration near the P+ well region 21.

[0068] From the P+ well region 21 toward the stop ring metal layer 4, a first P-type doped region 221, a second P-type doped region 231, and a third P-type doped region 241 are constructed with gradually decreasing concentration, gradually decreasing width, and gradually increasing depth. The first P-type doped region 221 reduces the electric field strength at the interface with the P+ well region 21, the second P-type doped region 231 reduces the electric field strength at the interface with the first P-type doped region 221, and the third P-type doped region 241 reduces the electric field strength at the interface with the second P-type doped region 231 and the drift layer 2.

[0069] The increasing depths of the first P-type doped region 221, the second P-type doped region 231, and the third P-type doped region 241 are intended to extend the interface with the strongest electric field intensity into the device, thereby preventing the electric field at the device surface from affecting the electric field distribution near the cutoff ring metal layer 4 and thus impacting device reliability.

[0070] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A VDMOS trench-type electric field modulation variable doping terminal, characterized in that: include: silicon carbide substrate; A drift layer is disposed on the upper side of the silicon carbide substrate. The drift layer contains a P+ well region, a main junction, a first field limiting ring, a second field limiting ring, and a P+ region. The P+ well region, the main junction, the first field limiting ring, and the second field limiting ring are connected in sequence. The P+ region is disposed at one end of the drift layer and is located on one side of the second field limiting ring. An insulating layer, the lower side of which is connected to the P+ well region, the main junction, the first field limiting ring, the second field limiting ring, the drift layer, and the P+ region respectively; the width of the main junction is greater than the width of the first field limiting ring, and the width of the first field limiting ring is greater than the width of the second field limiting ring; the depth of the main junction is less than the depth of the first field limiting ring, and the depth of the first field limiting ring is less than the depth of the second field limiting ring. A stop ring metal layer, the lower side of which is connected to the P+ region.

2. The VDMOS trench-type electric field modulation variable doping terminal as described in claim 1, characterized in that: The main junction includes a first P-type doped region and a first P-type trench region, the first P-type doped region being connected to the P+ well region, and the first P-type trench region being disposed within the first P-type doped region; the first field limiting ring includes a second P-type doped region and a second P-type trench region, the second P-type trench region being disposed within the second P-type doped region, and the second P-type doped region being connected to the first P-type doped region; the second field limiting ring includes a third P-type doped region and a third P-type trench region, the third P-type trench region being disposed within the third P-type doped region, and the third P-type doped region being connected to the second P-type doped region. The width of the first P-shaped trench area is greater than the width of the second P-shaped trench area, and the width of the second P-shaped trench area is greater than the width of the third P-shaped trench area; The depth of the first P-type trench region is less than the depth of the second P-type trench region, and the depth of the second P-type trench region is less than the depth of the third P-type trench region; The width of the first P-type doped region is greater than the width of the second P-type doped region, and the width of the second P-type doped region is greater than the width of the third P-type doped region; The depth of the first P-type doped region is less than the depth of the second P-type doped region, and the depth of the second P-type doped region is less than the depth of the third P-type doped region.

3. The VDMOS trench-type electric field modulation variable doping terminal as described in claim 2, characterized in that: The doping concentration of the first P-type trench region is greater than the doping concentration of the second P-type trench region, and the doping concentration of the second P-type trench region is greater than the doping concentration of the third P-type trench region. The doping concentration of the first P-type doped region is greater than that of the second P-type doped region, and the doping concentration of the second P-type doped region is greater than that of the third P-type doped region.

4. The VDMOS trench-type electric field modulation variable doping terminal as described in claim 2, characterized in that: The lower side surfaces of the first P-type doped region, the second P-type doped region, and the third P-type doped region are all arc-shaped.

5. The VDMOS trench-type electric field modulation variable doping terminal as described in claim 2, characterized in that: The depth of the P+ region is less than the depth of the first P-type doped region.

6. The VDMOS trench-type electric field modulation variable doping terminal as described in claim 1, characterized in that: It also includes a high resistivity conductor layer, the lower side of which is connected to the insulating layer.

7. The VDMOS trench-type electric field modulation variable doping terminal as described in claim 6, characterized in that: The thickness of the high resistivity conductor layer is greater than the thickness of the insulating layer.

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