Memory device and method of manufacturing the same

Abstract

A memory device includes cell plugs and an insulation pattern disposed on the cell plugs, the insulation pattern including openings respectively corresponding to the cell plugs. The memory device further includes a bit line disposed on the insulating pattern and a bit line contact disposed in the opening to couple the cell plug and the bit line, respectively. The memory device also includes a first air gap disposed between the bit lines. The memory device additionally includes a second air gap extending from the first air gap and surrounded by the bit line contact and the insulating pattern.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device including a bit line and a method of manufacturing the memory device. Background Art

[0002] The memory device may be a nonvolatile memory device in which the stored data is maintained even if the supplied power is cut off. The nonvolatile memory device may be classified into a two-dimensional (2D) structure or a three-dimensional (3D) structure according to the structure in which the memory cells are arranged. The memory cells of the nonvolatile memory device having a 2D structure may be arranged in a single layer on a substrate, while the memory cells of the nonvolatile memory device having a 3D structure may be vertically stacked on the substrate. Since the integration of the nonvolatile memory device having a 3D structure is higher than that of the nonvolatile memory device having a 2D structure, electronic devices using the nonvolatile memory device having a 3D structure are increasingly used. Summary of the invention

[0003] One embodiment of the present disclosure relates to a memory device. The memory device may include: a cell plug; an insulating pattern disposed on the cell plug and including openings respectively corresponding to the cell plugs; a bit line disposed on the insulating pattern; a bit line contact disposed in the opening to respectively connect the cell plug and the bit line; a first air gap disposed between the bit lines; and a second air gap extending from the first air gap and surrounded by the bit line contact and the insulating pattern.

[0004] One embodiment of the present disclosure relates to a method for manufacturing a memory device. The method may include: forming an insulating layer on a cell plug; etching a portion of the insulating layer to form an opening at least partially overlapping the cell plug; forming a first material layer to fill a corresponding lower portion of the opening; forming a lower sacrificial layer on the entire structure including the first material layer; forming a spacer pattern on the lower sacrificial layer to expose a portion of the lower sacrificial layer; etching the lower sacrificial layer exposed by the spacer pattern to form a sacrificial opening exposing a corresponding portion of the first material layer; filling the sacrificial opening with a second material layer; removing the lower sacrificial layer; and forming a capping layer on the second material layer to form an air gap between the second material layers and between the second material layer and the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0006] Figure 2 is a diagram illustrating a structure of a memory cell array according to one embodiment of the present disclosure.

[0007] Figure 3 is a diagram illustrating a structure of a memory device according to one embodiment of the present disclosure.

[0008] FIG. 4A to FIG. 4D is a diagram illustrating a structure of a memory device according to one embodiment of the present disclosure.

[0009] FIG. 5A to FIG. 5K is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0010] Figure 6 is a diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0011] Figure 7 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied. DETAILED DESCRIPTION

[0012] The specific structural or functional description of the embodiments of the present disclosure introduced in this specification or application is provided as an example to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in the specification or application.

[0013] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings so that those skilled in the art can practice the technical spirit of the present disclosure.

[0014] Some embodiments of the present disclosure are directed to a technology for simplifying a manufacturing process of a memory device including a bit line while improving performance of the memory device.

[0015] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0016] Reference Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0017] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include a plurality of memory cells in which data may be stored. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be coupled to each of the first to i-th memory blocks BLK1 to BLKi. A bit line BL may be commonly coupled to the first to i-th memory blocks BLK1 to BLKi.

[0018] Each of the first to i-th memory blocks BLK1 to BLKi may be implemented in a two-dimensional (2D) structure or a three-dimensional (3D) structure. Each of the memory blocks having a 2D structure may include memory cells arranged horizontally on a substrate. Each of the memory blocks having a 3D structure may include memory cells stacked vertically on a substrate. Although a memory block formed in a 3D structure is described in this embodiment for ease of description, this embodiment may also be applied to memory blocks each having a 2D structure.

[0019] According to the programming scheme, each memory cell can store 1 bit of data or 2 or more bits of data. For example, the scheme for storing 1 bit of data in one memory cell is called a single-level cell (SLC) scheme, and the scheme for storing 2 bits of data in one memory cell is called a multi-level cell (MLC) scheme. The scheme for storing 3 bits of data in one memory cell is called a three-level cell (TLC) scheme, and the scheme for storing 4 bits of data in one memory cell is called a quad-level cell (QLC) scheme. In addition, 5 or more bits of data can be stored in one memory cell.

[0020] The peripheral circuit 170 may perform a program operation to store data in the memory cell array 110, a read operation to output data stored in the memory cell array 110, and an erase operation to erase data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0021] The voltage generator 120 may generate various operation voltages Vop required for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0022] The programming voltage may be a voltage applied to a selected word line among the word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. The on-voltage may be applied to the drain selection line DSL or the source selection line SSL, and may be used to turn on the drain selection transistor or the source selection transistor. The off-voltage may be applied to the drain selection line DSL or the source selection line SSL, and may be used to turn off the drain selection transistor or the source selection transistor. For example, the off-voltage may be set to 0V.

[0023] The precharge voltage is a voltage higher than 0V and can be applied to the bit line during a read operation. The verification voltage can be used to determine whether the threshold voltage of the selected memory cell has increased to a verification operation of a target level. The verification voltage can be set to various levels according to the target level and can be applied to the selected word line. The read voltage can be applied to the selected word line during a read operation of the selected memory cell. For example, the read voltage can be set to various levels according to the programming scheme of the selected memory cell. The pass voltage can be a voltage applied to an unselected word line among the word lines WL during a programming or read operation, and can be used to turn on the memory cells connected to the unselected word lines. The erase voltage can be used to erase the memory cells included in the selected storage block, and can be applied to the source line SL.

[0024] The row decoder 130 may transmit the operation voltage Vop to the drain select line DSL, the word line WL, the source select line SSL, and the source line SL coupled to the memory block selected in response to the row address RADD. For example, the row decoder 130 may be coupled to the voltage generator 120 through the global line, and may be coupled to the first memory block BLK1 to the i-th memory block BLKi through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0025] The page buffer group 140 may include page buffers (not illustrated) respectively coupled to the first to i-th storage blocks BLK1 to BLKi. For example, the corresponding page buffers (not illustrated) may be coupled to the first to i-th storage blocks BLK1 to BLKi through the bit lines BL. During a read operation, the page buffers (not illustrated) may sense a current or voltage of a bit line that varies according to a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG, and may temporarily store the sensed data.

[0026] The column decoder 150 may be configured so that data is transmitted between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be coupled to the page buffer group 140 through the column line CL, and may send an enable signal through the column line CL. A page buffer (not illustrated) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0027] The input / output circuit 160 may receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 180, and may transmit data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0028] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, or a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 so that a program operation is performed on a storage block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 so that a read operation is performed on a storage block selected by the address and read data is output. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 so that an erase operation is performed on a selected storage block.

[0029] Figure 2 is a diagram illustrating a structure of a memory cell array according to one embodiment of the present disclosure.

[0030] Reference Figure 2 , the memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. The first to i-th memory blocks BLK1 to BLKi may be arranged to be spaced apart from each other in the Y direction. The first to i-th memory blocks BLK1 to BLKi may extend in the X direction.

[0031] The first to i-th memory blocks BLK1 to BLKi may be commonly coupled to the first to j-th bit lines BL1 to BLj. For example, the first to j-th bit lines BL1 to BLj may extend in the Y direction and may be arranged to be spaced apart from each other in the X direction. The first to j-th bit lines BL1 to BLj may each be coupled to the first to i-th memory blocks BLK1 to BLKi on the first to i-th memory blocks BLK1 to BLKi.

[0032] Figure 3 is a diagram illustrating a structure of a memory device according to one embodiment of the present disclosure.

[0033] Reference Figure 3, the i-th memory block BLKi may be separated from the adjacent memory blocks by the slit SI. For example, the slit SI may be positioned in the Y direction of the i-th memory block BLKi and may extend in the X direction. The i-th memory block BLKi may be adjacent to other memory blocks, with the slit SI interposed therebetween.

[0034] The i-th storage block BLKi may include a plurality of cell plugs CP. The cell plugs CP may be formed in a vertical direction (e.g., Z direction) from a substrate (not shown). The cell plugs CP may be formed in a plurality of rows. Each row may include cell plugs CP spaced apart from each other in the X direction. The plurality of rows may be spaced apart from each other in the Y direction. The centers of the cell plugs CP included in the odd rows and the centers of the cell plugs CP included in the even rows may be offset from each other.

[0035] Each of the cell plugs CP may include a cylindrical barrier layer BX, a charge capture layer CT formed along the inner wall of the barrier layer BX, a tunnel isolation layer TX formed along the inner wall of the charge capture layer CT, a channel layer CH formed along the inner wall of the tunnel isolation layer TX, and a core column CO formed in a cylindrical shape in a region surrounded by the channel layer CH. Each of the barrier layer BX and the tunnel isolation layer TX may be formed of an oxide layer (e.g., a silicon oxide layer). The charge capture layer CT may be formed of a nitride layer. The channel layer CH may be formed of a doped silicon layer. The core column CO may be formed of an insulating layer or a conductive layer. The barrier layer BX, the charge capture layer CT, the tunnel isolation layer TX, the channel layer CH, and the core column CO formed in the cell plug CP may extend in a vertical direction Z.

[0036] The first to j-th bit lines BL1 to BLj may be located on the i-th memory block BLKi. The first to j-th bit lines BL1 to BLj may be arranged to be spaced apart from each other in the X direction. In addition, each of the first to j-th bit lines BL1 to BLj may extend in the Y direction.

[0037] Each of the first to j-th bit lines BL1 to BLj may be coupled to at least one cell plug CP. For example, the first bit line BL1 may be coupled to the cell plugs CP included in the odd-numbered rows. Also, the second bit line BL2 may be coupled to the cell plugs CP included in the even-numbered rows.

[0038] Reference Figure 3 , the distance between adjacent bit lines BL (e.g., the first bit line BL1 and the second bit line BL2) in the X direction may be smaller than the distance between adjacent cell plugs CP in the X direction. As the distance between adjacent bit lines BL in the X direction decreases, the parasitic capacitance between the bit lines BL may increase. According to the present disclosure, the parasitic capacitance between the bit lines BL may be reduced by forming an air gap between the bit lines BL. FIG. 4A to FIG. 4D Describe the air gap.

[0039] FIG. 4A to FIG. 4D is a diagram illustrating a structure of a memory device according to one embodiment of the present disclosure. Figure 4A It is along Figure 3 A cross-sectional view taken along line AA'. Figure 4B It is shown Figure 4A FIG. 1 is a perspective view of the structure of the bit lines BL1 to BL3 and the upper bit line contacts UBC. Figure 4C is along with Figure 4A The plane view corresponds to the cross section taken along the line BB'. Figure 4D is along with Figure 4A The plane view corresponds to the cross section taken along the line CC'.

[0040] Reference Figure 4A and Figure 4B , the memory device 100 may include a cell plug CP, an insulating pattern IL on the cell plug CP, bit lines BL1, BL2, and BL3 on the insulating pattern IL, an air gap AG, and a bit line contact BC coupling the cell plug CP to the bit lines BL1 and BL3. The memory device 100 may also include a contact plug CC coupling each of the cell plugs CP to a corresponding one of the bit line contacts BC.

[0041] The memory device 100 may include cell plugs CP. Each cell plug CP may include a blocking layer BX, a charge trap layer CT, a tunnel isolation layer TX, a channel layer CH, and a pillar CO. The cell plug CP may penetrate the conductive layers CD and the interlayer insulating layers IIL alternately stacked in the Z direction.

[0042] An insulating layer ILL and contact plugs CC penetrating the insulating layer ILL may be formed on the cell plugs CP. The contact plugs CC may contact the cell plugs CP, respectively. The contact plugs CC may be electrically connected to the cell plugs CP.

[0043] The insulating pattern IL and the bit line contact BC may be formed on the cell plug CP. For example, the insulating pattern IL and the bit line contact BC may be positioned on the insulating layer ILL and the contact plug CC. The bit line contact BC may contact the contact plug CC, respectively. The bit line contact BC may be connected to the cell plug CP through the contact plug CC, respectively.

[0044] although Figure 4A It is shown that the cell plug CP is connected to the bit line contact BC through the contact plug CC, but this is only an example, and various different embodiments are possible. For example, the cell plug CP may be directly connected to the bit line contact BC. In addition, although Figure 4AIt is illustrated that the stem CO included in each cell plug CP contacts the contact plug CC, but the present disclosure is not limited thereto. For example, the cell plug CP may further include a cover layer formed on the stem CO, and the cover layer may contact the contact plug CC.

[0045] The insulating pattern IL may be formed on the cell plug CP. For example, the insulating pattern IL may contact the upper surface of the insulating layer ILL. In one embodiment, the insulating pattern IL may include openings OP corresponding to the cell plugs CP, respectively. The opening OP may be formed to correspond to the position of the cell plug CP. For example, at least a portion of the opening OP may overlap with the cell plug CP. Alternatively, at least a portion of the cell plug CP may overlap with the opening OP. In one embodiment, the opening OP may be formed to correspond to the position of the contact plug CC. At least a portion of the opening OP may overlap with the contact plug CC. The opening OP may expose at least a portion of the upper surface of the contact plug CC.

[0046] The bit lines BL1, BL2, and BL3 may be formed on the insulating pattern IL. Each of the bit lines BL1, BL2, and BL3 may extend in the Y direction. The bit lines BL1, BL2, and BL3 may be formed of molybdenum (Mo). The bit lines BL1, BL2, and BL3 may be formed as a single layer. For example, the bit lines BL1, BL2, and BL3 may not include a barrier metal or a metal seed layer. Therefore, compared with the case where the bit lines BL1, BL2, and BL3 are formed of copper (Cu) or tungsten (W), when the bit lines BL1, BL2, and BL3 are formed of molybdenum, the resistance of the bit lines BL1, BL2, and BL3 may be reduced.

[0047] The bit line contact BC may be formed in the opening OP. The bit line contact BC may couple the cell plugs CP to the bit lines BL1, BL2, and BL3, respectively. For example, the bit line contact BC may couple any one of the cell plugs CP to the first bit line BL1, and may couple another cell plug CP to the third bit line BL3.

[0048] Each of the bit line contacts BC may include an upper bit line contact UBC extending from each of the bit lines BL1 and BL3 and a lower bit line contact LBC making contact with a lower surface of the upper bit line contact UBC.

[0049] The upper bit line contact UBC may be integrally formed on each of the bit lines BL1, BL2, and BL3. The width of the upper bit line contact UBC in the X direction may be the same as the width of each of the bit lines BL1, BL2, and BL3 in the X direction. For example, the side surface of the upper bit line contact UBC in the X direction may extend from the side surface of each of the bit lines BL1, BL2, and BL3 in the X direction. In addition, the width of the upper bit line contact UBC in the Y direction may be the same as the width of each of the openings OP in the Y direction. For example, the side surface of the upper bit line contact UBC in the Y direction may be coplanar with the inner wall of each of the openings OP. Reference Figure 4B and Figure 4D , the side surface of the upper bit line contact UBC in the Y direction may contact the inner wall of the opening OP. In addition, the side surface of the upper bit line contact UBC in the X direction may be spaced apart from the inner wall of the opening OP. The second air gap AG2 may be formed between the side surface of the upper bit line contact UBC in the X direction and the inner wall of the opening OP.

[0050] The upper bit line contact UBC may be formed of molybdenum. Molybdenum is relatively higher in step coverage than copper or tungsten. Therefore, in the case of molybdenum filling, the incidence of gap filling defects in which a high aspect ratio structure (e.g., a structure in which the first bit line BL1 and the upper bit line contact UBC are integrally formed) is not sufficiently filled with metal may be reduced compared to copper or tungsten filling.

[0051] The lower bit line contact LBC may be formed of tungsten or copper. The lower bit line contact LBC may be wider than the upper bit line contact UBC. For example, the lower bit line contact LBC may have the same width as each opening OP. The lower bit line contact LBC may have a recessed shape compared to the upper surface of the insulating pattern IL. Since the lower bit line contact LBC has a recessed shape compared to the upper surface of the insulating pattern IL, the volume of the air gap AG may be increased.

[0052] The memory device 100 may further include a capping layer CAP covering the upper surfaces of the bit lines BL1, BL2, and BL3 and extending in a horizontal direction (e.g., an X direction and a Y direction). The capping layer CAP may also cover the upper surfaces of the bit lines BL1, BL2, and BL3 and at least some areas of the sidewalls of the bit lines BL1, BL2, and BL3. The capping layer CAP may be formed of an oxide layer. The capping layer CAP may be formed of a material having a low dielectric constant to reduce the capacitance between the bit lines BL1, BL2, and BL3.

[0053] The capping layer CAP may be formed of a material having a relatively low step coverage As the step coverage of the material forming the capping layer CAP decreases, the volume of the air gap AG may increase.

[0054] The memory device 100 may include an air gap AG. The air gap AG may include a first air gap AG1 between the bit lines BL1, BL2, and BL3 and a second air gap AG2 extending from the first air gap AG1 and surrounded by the bit line contact BC and the insulating pattern IL. The first air gap AG1 and the second air gap AG2 may extend from each other.

[0055] The first air gap AG1 may be surrounded by the capping layer CAP, the sidewalls of the bit lines BL1, BL2, and BL3, the upper surface of the insulating pattern IL, and the second air gap AG2. The first air gap AG1 may be surrounded by the capping layer CAP, the upper surface of the insulating pattern IL, and the second air gap AG2. Each of the first air gaps AG1 may partially overlap the insulating pattern IL. For example, the lower surface of each of the first air gaps AG1 may contact both the upper surface of the insulating pattern IL and the second air gap AG2.

[0056] The second air gap AG2 may be surrounded by the first air gap AG1, the sidewall of the upper bit line contact UBC, the inner wall of each opening OP, and the upper surface of the lower bit line contact LBC. Each of the second air gaps AG2 may be positioned in each opening OP together with the bit line contact BC. As the length of the lower bit line contact LBC in the Z direction decreases, the volume of the second air gap AG2 may increase.

[0057] Reference Figure 4C , each of the first air gaps AG1 may extend in a direction in which each of the bit lines BL1, BL2, and BL3 extends. For example, each of the first air gaps AG1 may extend in the Y direction. Each of the first air gaps AG1 may be positioned between the bit lines BL1, BL2, and BL3 to reduce parasitic capacitance between the bit lines BL1, BL2, and BL3.

[0058] Reference Figure 4D , two separate second air gaps AG21 and AG2r may be positioned in any one opening OP. For example, any one second air gap AG21 may be formed on one side of the upper bit line contact UBC, and another second air gap AG2r may be formed on the other side of the upper bit line contact UBC. The two second air gaps AG21 and AG2r positioned in one opening OP may be separated from each other by the upper bit line contact UBC. Figure 4A and Figure 4D , the first air gap AG1 positioned at opposite sides of the first bit line BL1 may extend to second air gaps AG21 and AG2r on opposite sides of an upper bit line contact UBC extending from the first bit line BL1, respectively.

[0059] The second air gap AG2 may be surrounded by the sidewalls of the upper bit line contacts UBC and the inner walls of the opening OP. Since the second air gap AG2 is positioned at a height corresponding to the upper bit line contacts UBC, parasitic capacitance between the upper bit line contacts UBC may be reduced.

[0060] FIG. 5A to FIG. 5K is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure. FIG. 5A to FIG. 5K It is along Figure 3 A cross-sectional view taken along line AA'.

[0061] Reference Figure 5A The cell plug CP may be formed to penetrate the stacked body ST. The first insulating layer ILL may be formed on the cell plug CP. In addition, the contact plug CC may be formed to penetrate the first insulating layer ILL. The contact plug CC may be formed to contact the cell plug CP.

[0062] The second insulating layer may be formed on the cell plug CP. For example, the second insulating layer may be formed on the first insulating layer ILL. A portion of the second insulating layer may be etched to form an insulating pattern IL. For example, a portion of the second insulating layer may be etched to form an opening OP for exposing the contact plug CC. The insulating pattern IL may include an opening OP at least partially overlapping the cell plug CP.

[0063] Reference Figure 5B , a first material layer M1 may be formed in the opening OP. The first material layer M1 may be formed to fill the opening OP. The first material layer M1 may be a conductive layer such as tungsten. For example, the first material layer M1 may be formed of the same material as the contact plug CC.

[0064] Reference Figure 5C , the first material layer M1 may be formed to fill the lower portion of the opening OP. For example, an etch back process may be performed to etch the portion of the first material layer M1 filled in the opening OP. When the portion of the first material layer M1 in the opening OP is etched, a portion of the inner wall of each opening OP may be exposed. When the portion of the first material layer M1 is etched, the first material layer M1 may have a concave shape compared to the upper surface of the insulating pattern IL. That is, the thickness of the first material layer M1 may be thinner than the thickness of the insulating pattern IL.

[0065] Reference Figure 5D , a lower sacrificial layer LSF may be formed on the entire structure including the first material layer M1. The lower sacrificial layer LSF may be formed to cover the first material layer M1 and the insulating pattern IL. The lower sacrificial layer LSF may fill the opening OP of the insulating pattern IL. The lower sacrificial layer LSF may be a polysilicon layer. An upper sacrificial layer USF may be formed on the lower sacrificial layer LSF. The upper sacrificial layer USF may be an amorphous carbon layer ACL.

[0066] Reference Figure 5E , a portion of the upper sacrificial layer USF may be etched to form an upper sacrificial pattern pUSF exposing a portion of the lower sacrificial layer LSF. The upper sacrificial pattern pUSF may be formed so as not to overlap with the opening OP of the insulating pattern IL. Assuming that the insulating pattern IL between the openings OP has a first width W1, the upper sacrificial pattern pUSF may have a second width W2 narrower than the first width W1.

[0067] Reference Fig. 5F , spacers SP may be formed along the surface of the upper sacrificial pattern pUSF and the surface of the lower sacrificial layer LSF. The spacers SP may be formed of a material having an etching selectivity different from that of the upper sacrificial pattern pUSF. For example, the spacers SP may be formed of an insulating material such as an oxide layer.

[0068] Reference Figure 5G , the spacer SP and a portion of the upper sacrificial pattern pUSF may be etched to form a spacer pattern pSP. For example, an etch back process may be performed to expose a portion of the lower sacrificial layer LSF and the upper sacrificial pattern pUSF. The etch back process may be performed by an anisotropic dry etching process. When the etch back process is performed on the entire structure formed with the spacer SP, the spacer SP formed in the horizontal direction (e.g., the X direction and the Y direction) may be removed. Therefore, the spacer SP formed along the Z direction on the side surface of the upper sacrificial pattern pUSF may remain as the spacer pattern pSP. The spacer pattern pSP may expose a portion of the lower sacrificial layer LSF on the lower sacrificial layer LSF.

[0069] Reference Figure 5H , an etching process may be performed to remove a portion of the lower sacrificial layer LSF exposed by the spacer pattern pSP. An anisotropic dry etching process may be performed as an etching process for removing a portion of the lower sacrificial layer LSF. When removing a portion of the lower sacrificial layer LSF, a lower sacrificial pattern pLSF including a sacrificial opening SOP exposing a portion of each first material layer M1 may be retained. While etching a portion of the lower sacrificial layer LSF using the spacer pattern pSP, the height of the spacer pattern pSP may be reduced.

[0070] Each of the sacrificial openings SOP included in the lower sacrificial pattern pLSF may expose a portion of the upper surface of each of the first material layers M1. In addition, each of the sacrificial openings SOP included in the lower sacrificial pattern pLSF may expose a portion of the upper surface of the insulating pattern IL. In the region where the upper surface of the insulating pattern IL is exposed while the lower sacrificial layer LSF is etched, the etching may be stopped at a height corresponding to the upper surface of the insulating pattern IL. In the region where the upper surface of each first material layer M1 is exposed through the opening OP while the lower sacrificial layer LSF is etched, the etching may be stopped at a height corresponding to the upper surface of each of the first material layers M1. Because the etching depth of the sacrificial openings SOP varies depending on the position on the insulating pattern IL, the etching may be performed as shown in FIG. Figure 4B and Figure 4D As shown, an upper bit line contact UBC is formed.

[0071] Reference Fig.5I , after forming the lower sacrificial pattern pLSF, the spacer pattern pSP may be removed.

[0072] The sacrificial opening SOP can be filled with the second material layer M2. Because the bit line and the upper bit line contact portion should be formed integrally in the sacrificial opening SOP, the aspect ratio of the sacrificial opening SOP can be increased. Therefore, the second material layer M2 used to fill the interior of the sacrificial opening SOP can be selected from a conductive material with a high step coverage. For example, the second material layer M2 can be formed of molybdenum. Because molybdenum has a high step coverage characteristic, even if the aspect ratio of the sacrificial opening SOP increases compared to the conventional case, the interior of the sacrificial opening SOP can be fully filled. In addition, each of the second material layers M2 can be formed by a single layer. When molybdenum with a high step coverage is used for the second material layer M2, the step of forming a barrier metal or a metal seed layer can be omitted before the step of filling the sacrificial opening SOP with the second material layer M2. Therefore, according to the present disclosure, the manufacturing process can be simplified compared to the case where a barrier metal or a metal seed layer is required. In addition, since the second material layer M2 positioned above the upper surface of the insulating pattern IL among the second material layers M2 filled in the sacrificial opening SOP becomes the bit lines BL1 to BL3 (see Figure 4A ), and the second material layer M2 positioned between the insulating patterns IL becomes the upper bit line contact UBC (see Figure 4A ), so the resistance between the bit line and the upper bit line contact can be reduced.

[0073] Reference Figure 5J, an etching process may be performed to remove the lower sacrificial pattern pLSF. For example, a dry etching process or a wet etching process may be performed on the lower sacrificial pattern pLSF having a higher etching selectivity than the second material layer M2, the insulating pattern IL, and the first material layer M1. When the lower sacrificial pattern pLSF is removed, the second material layer M2 may be exposed, and the first material layer M1 may also be exposed between the insulating patterns IL.

[0074] Reference Figure 5K , a capping layer CAP may be formed on the second material layer M2. The capping layer CAP may be formed of an insulating material having a low step coverage, so that an air gap AG is formed between the second material layers M2 and in the opening OP. The air gap AG may include a first air gap AG1 and a second air gap AG2 positioned below the first air gap AG1. The first air gap AG1 may be surrounded by the sidewalls of the second material layer M2 and the capping layer CAP. Alternatively, the first air gap AG1 may be surrounded by the capping layer CAP. In addition, the second air gap AG2 may be surrounded by the sidewalls of the second material layer M2, the inner walls of the opening OP, and the upper surface of the first material layer M1.

[0075] Figure 6 is a diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0076] Reference Figure 6 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0077] The controller 3100 may be coupled to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a program operation, a read operation, or an erase operation of the memory device 3200, or may control a background operation of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may run firmware for controlling the memory device 3200. In one example, the controller 3100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0078] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) based on a specific communication standard. In one embodiment, the controller 3100 can communicate with an external device through at least one of various communication standards such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-Express (PCI-E), an advanced technology attachment (ATA) protocol, a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), Firewire, a universal flash storage (UFS), WiFi, Bluetooth, and a non-volatile memory fast (NVMe) interface. In one embodiment, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0079] The memory device 3200 may include a plurality of memory cells and may be connected to Figure 1 The memory device 100 shown in FIG. 1 is configured in the same manner.

[0080] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a single semiconductor device, and then a memory card such as a Personal Computer Memory Card International Association (PCMCIA) card, a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC or eMMC), an SD card (SD, Mini SD, Micro SD or SDHC), or a Universal Flash Storage (UFS) may be formed.

[0081] Figure 7 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied.

[0082] Reference Figure 7 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0083] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. In one embodiment, the received signal may be a signal based on an interface of the host 4100 and the SSD 4200. For example, the signal may be defined by at least one of various interfaces, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WiFi, Bluetooth, and a non-volatile memory express (NVMe) interface.

[0084] Each of the plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Figure 1 The memory device 100 shown in FIG. 4 is configured in the same manner. The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0085] The auxiliary power supply 4230 may be coupled to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may be supplied with a power supply voltage from the host 4100 and may be charged. When the power supply from the host 4100 is not smoothly performed, the auxiliary power supply 4230 may provide a supply voltage of the SSD 4200. In one embodiment, the auxiliary power supply 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located in a mainboard and may provide auxiliary power to the SSD 4200.

[0086] The buffer memory 4240 may be used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, and a low power DDR (LPDDR) SDRAM, or a nonvolatile memory such as a ferroelectric RAM (FRAM), a resistive RAM (ReRAM), a spin transfer torque magnetic RAM (STT-MRAM), and a phase change RAM (PRAM).

[0087] According to the present disclosure, the resistance of a bit line and the parasitic capacitance between the bit lines can be reduced, and the manufacturing process of a memory device can be simplified.

[0088] CROSS-REFERENCE TO RELATED APPLICATIONS

[0089] This application claims the priority of Korean Patent Application No. 10-2023-0075462 filed in the Korean Intellectual Property Office on June 13, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: Unit plug; an insulating pattern disposed on the cell plug and including openings respectively corresponding to the cell plugs; a bit line, the bit line being disposed on the insulating pattern; a bit line contact portion disposed in the opening to respectively connect the cell plug and the bit line; a first air gap disposed between the bit lines; as well as A second air gap extends from the first air gap and is surrounded by the bit line contact and the insulation pattern.

2. The memory device according to claim 1, wherein: The bit line includes molybdenum Mo.

3. The memory device according to claim 1, wherein: Each of the bit line contacts comprises: an upper bit line contact extending from each of the bit lines; and A lower bit line contact portion contacts a lower surface of the upper bit line contact portion.

4. The memory device according to claim 3, wherein: The upper bit line contact includes molybdenum.

5. The memory device according to claim 3, wherein: The upper bit line contact has a width equal to a width of each of the bit lines.

6. The memory device according to claim 3, wherein: The upper bit line contact contacts a portion of an inner wall of each of the openings.

7. The memory device according to claim 3, wherein: The lower bit line contact fills a lower portion of each of the openings.

8. The memory device according to claim 3, wherein: Each of the second air gaps is surrounded by a corresponding one of the first air gaps, a side wall of the upper bit line contact, an inner wall of a corresponding one of the openings, and an upper surface of the lower bit line contact.

9. The memory device of claim 1, further comprising: A cover layer covers an upper surface of the bit line and extends in a horizontal direction.

10. The memory device according to claim 9, wherein: The capping layer is an oxide layer.

11. The memory device according to claim 9, wherein: The first air gap is surrounded by the capping layer, the sidewall of the bit line, an upper surface of the insulation pattern, and the second air gap.

12. The memory device according to claim 1, wherein: Each of the first air gaps partially overlaps the insulation pattern.

13. The memory device according to claim 1, wherein: Each of the first air gaps extends along a direction in which each of the bit lines extends.

14. The memory device according to claim 1, wherein: The bit line contact and the second air gap are positioned in the opening.

15. A method of manufacturing a memory device, the method comprising the steps of: forming an insulating layer on the cell plug; etching a portion of the insulating layer to form an opening at least partially overlapping the cell plug; forming a first material layer to fill corresponding lower portions of the openings; forming a lower sacrificial layer on the entire structure including the first material layer; forming a spacer pattern on the lower sacrificial layer to expose a portion of the lower sacrificial layer; etching the lower sacrificial layer exposed by the spacer pattern to form a sacrificial opening exposing a corresponding portion of the first material layer; filling the sacrificial opening with a second material layer; removing the lower sacrificial layer; as well as A cover layer is formed on the second material layers to form air gaps between the second material layers and between the second material layer and the opening.

16. The method according to claim 15, wherein: The step of forming the first material layer to fill the corresponding lower portion of the opening comprises: forming the first material layer in the opening; and A portion of each of the first material layers is etched to expose a portion of an inner wall of each of the openings.

17. The method according to claim 15, wherein: The step of forming the spacer pattern on the lower sacrificial layer comprises: forming an upper sacrificial layer on the lower sacrificial layer; etching a portion of the upper sacrificial layer to form an upper sacrificial pattern exposing a portion of the lower sacrificial layer; forming spacers on the upper sacrificial patterns; and A portion of the spacer and the upper sacrificial pattern are etched to form the spacer pattern.

18. The method according to claim 15, wherein: The second material layer includes molybdenum.

19. The method according to claim 18, wherein: The second material layer is formed as a single layer.

20. The method according to claim 15, wherein: The air gap is formed to include: a first air gap surrounded by a sidewall of the second material layer and the cover layer; and A second air gap is surrounded by a side wall of the second material layer, an inner wall of the opening, and an upper surface of the first material layer.

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