A diamond-based CMOS inverter and its fabrication method

Abstract

This invention belongs to the field of semiconductor device technology and discloses a diamond-based CMOS inverter and its fabrication method. The diamond-based CMOS inverter includes a diamond substrate, a single-crystal diamond thin film, a hydrogen-terminated region, a mesa isolation region, an n-type oxide semiconductor layer, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a first gate dielectric layer, a first gate electrode, a second gate dielectric layer, and a second gate electrode; the first drain electrode and the second drain electrode are metal-interconnected; the first gate electrode and the second gate electrode are also metal-interconnected. This invention combines p-type hydrogen-terminated diamond and n-type oxide semiconductor to fabricate a diamond-based CMOS inverter, effectively circumventing the current technical difficulty in realizing n-type MOS devices with diamond, fully leveraging the advantages of both diamond and n-type oxide semiconductor, and achieving a high-performance diamond-based monolithic integrated CMOS inverter.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a diamond-based CMOS inverter (Complementary Metal-Oxide-Semiconductor) and its fabrication method. Background Technology

[0002] With the application of first-generation semiconductor materials silicon and germanium in electronic devices, human technological life entered a period of rapid development. Driven by technological advancements and the demands of integrated circuit development, second-generation semiconductor materials gallium arsenide and third-generation semiconductor materials silicon carbide and gallium nitride were subsequently developed and utilized. Moore's Law requires the integration of more electronic devices within a unit area, leading to increasingly prominent problems such as heat dissipation, gate breakdown, and tunneling leakage current. To solve these problems, people have gradually turned their attention to emerging semiconductor materials.

[0003] Compared to other semiconductor materials, diamond possesses a wide bandgap, high mobility, high thermal conductivity, and large Johnson, Baliga, and Keyes quality factors, resulting in significantly superior electrical properties compared to other third-generation semiconductor materials. This makes diamond-based electronic devices superior in performance to those of other semiconductor electronic devices, while also maximizing the coverage of application areas in terms of output power and operating frequency. It is highly suitable for fabricating ultra-high frequency, ultra-high power, high-temperature resistant, and radiation-resistant electronic devices. Existing research indicates that electrons in the valence band of hydrogen-terminated diamond transfer to the lowest unoccupied molecular orbital (LOMO) of the adsorbed molecule, leading to the formation of a two-dimensional hole gas layer on the diamond surface, which can achieve 10-1 12 cm -2 ~10 14 cm -2 The surface carrier concentration, and 20cm 2 ·V -1 ·s -1 ~680cm 2 ·V -1 ·s -1 The carrier mobility is within a certain range, therefore it can be used to fabricate high-performance p-type field-effect transistors.

[0004] As a crucial component in logic circuit applications, inverter design has always been a research hotspot. Currently, diamond-based devices mainly employ normally-on / normally-off structures, also known as E / D logic inverters. However, E / D logic inverters suffer from depletion-mode components, leading to a significant increase in conduction current and energy waste. In applications, CMOS inverters have become the most popular technology due to their low power consumption, fast switching speed, high gain, and strong anti-interference capabilities. However, due to current technological limitations, the n-type doping of diamond materials has not yet met the requirements for electronic device applications, thus preventing the realization of diamond-based CMOS devices. Summary of the Invention

[0005] To address the shortcomings of the prior art, this invention provides a diamond-based CMOS inverter and its fabrication method.

[0006] The present invention provides a diamond-based CMOS inverter, comprising a diamond substrate, a single-crystal diamond thin film, a hydrogen-terminated region, a mesa isolation region, an n-type oxide semiconductor layer, a first source electrode, a first drain electrode, a first gate dielectric layer, a first gate electrode, a second source electrode, a second drain electrode, a second gate dielectric layer, and a second gate electrode.

[0007] It should be noted that, in order to overcome the shortcomings of existing technologies where n-type doped diamond materials are difficult to meet the requirements for use in electronic devices, this invention uses a diamond substrate as the base. This not only prepares the material for subsequent construction of voltage- and heat-resistant diamond-based CMOS devices, but also provides excellent heat dissipation for the overall CMOS inverter device structure. In some preferred embodiments of this invention, the diamond substrate used is a homogeneous or heterogeneous diamond substrate prepared by high-temperature high-pressure technology or vapor phase epitaxy, such as homogeneous epitaxial single-crystal diamond or heterogeneous epitaxial single-crystal diamond, including single-crystal diamond, to ensure the acquisition of a pure diamond substrate.

[0008] In some preferred embodiments of the present invention, a single-crystal diamond film is further disposed on the surface of the diamond substrate as a functional layer, that is, the single-crystal diamond film is used as the basis for fabricating diamond-based CMOS devices. To ensure that the single-crystal diamond film disposed on the surface of the diamond substrate can achieve the above-mentioned effects, in some preferred embodiments of the present invention, the thickness of the single-crystal diamond film is 50 nm to 5 mm.

[0009] In some preferred embodiments of the present invention, the single-crystal diamond film is obtained by deposition on the diamond substrate using chemical vapor deposition. Specifically, the resistivity of the single-crystal diamond film deposited by chemical vapor deposition in this invention is >100 MΩ·cm to ensure the insulating properties of the formed single-crystal diamond film. The root mean square surface roughness of the single-crystal diamond film of the present invention is ≤0.5 nm. The root mean square surface roughness is related to the carrier mobility of the p-type conductive channel in the hydrogen-terminated region. By controlling the root mean square surface roughness to ≤0.5 nm, it is beneficial to regulate the carrier mobility of the p-type conductive channel in the hydrogen-terminated region to 20 cm⁻¹. 2 / V·s~2500cm 2 / V·s. The full width at half maximum (FWHM) of the Raman curve of the single-crystal diamond thin film of this invention is ≤2cm. -1 The XRD rocking curve has a half-peak width of ≤30 arcsec, thus ensuring that the obtained single-crystal diamond thin film material is of electronic device grade.

[0010] The present invention further includes a hydrogen-terminated region on the single-crystal diamond film, which serves as a p-type conductive channel. To ensure that the hydrogen-terminated region on the single-crystal diamond film can be used as a p-type conductive channel, in some preferred embodiments of the present invention, the carrier concentration on the inner surface of the p-type conductive channel in the hydrogen-terminated region is 1 × 10⁻⁶. 12 cm -2 ~5×10 14 cm -2 The migration rate is 20cm. 2 / V·s~2500cm 2 / V·s. Furthermore, in some preferred embodiments of the present invention, the thickness of the hydrogen-terminated region is 1nm to 20nm.

[0011] The present invention further includes a mesa isolation region on the single-crystal diamond film, and the mesa isolation region is located around the hydrogen-terminated region to serve as an insulating layer for electrical isolation between devices. In some preferred embodiments of the present invention, the mesa isolation region is oxygen-terminated diamond.

[0012] This invention further includes an n-type oxide semiconductor layer on the mesa isolation region to serve as an n-type conductive channel within which charge carriers migrate. To ensure the n-type oxide semiconductor layer achieves the aforementioned effects, in some feasible embodiments of this invention, the material of the n-type oxide semiconductor layer is any one or more of tin dioxide, zinc oxide, indium oxide, zirconium dioxide, indium tin oxide, aluminum zinc oxide, and indium gallium zinc oxide. In some feasible embodiments of this invention, when the n-type oxide semiconductor layer is disposed on the mesa isolation region, it is deposited using any one of electron beam evaporation, magnetron sputtering, metal-organic chemical vapor deposition, laser pulse deposition, atomic layer deposition, and sol-gel deposition.

[0013] Please see Figure 1 To construct a complete logic device, this invention provides a first source electrode and a first drain electrode at both ends of the n-type oxide semiconductor layer, both forming ohmic contacts with the n-type oxide semiconductor layer. A second source electrode and a second drain electrode are respectively provided at both ends of the hydrogen-terminated region, both forming ohmic contacts with the hydrogen-terminated region. The first and second drain electrodes are metal-interconnected, serving as the output of a CMOS inverter; the first and second gate electrodes are metal-interconnected, serving as the input of the CMOS inverter.

[0014] In some preferred embodiments of the present invention, the materials of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are all selected from any one or more of Au, Pd, Ir, Pt, and Ti, so as to achieve ohmic contact and reduce resistance.

[0015] To ensure the metal interconnection of the first drain electrode and the second drain electrode, and the metal interconnection of the first gate electrode and the second gate electrode, in some preferred embodiments of the present invention, the first drain electrode and the second drain electrode are metal interconnected through a first interconnect line, so that the first drain electrode and the second drain electrode are connected and have the same potential, thereby serving as the signal output of the CMOS inverter. The first gate electrode and the second gate electrode are metal interconnected through a second interconnect line, so that the first gate electrode and the second gate electrode are connected and have the same potential, thereby serving as the signal input of the CMOS inverter.

[0016] It should also be emphasized that the present invention further comprises a first gate dielectric layer on the n-type oxide semiconductor layer, which improves gate control and reduces gate leakage current. A first gate electrode is provided on the first gate dielectric layer to provide a gate voltage and regulate the n-type conductive channel current. The present invention further comprises a second gate dielectric layer on the hydrogen-terminated region, the second gate dielectric layer having the same function as the first gate dielectric layer. A second gate electrode is provided on the second gate dielectric layer, the second gate electrode having the same function as the first gate electrode.

[0017] In some feasible embodiments of the present invention, the materials of the first gate dielectric layer and the second gate dielectric layer are both selected from Al2O3, SiO2, and SiN. x One or more of HfO2 and MoO3 can be used to reduce leakage current.

[0018] In some feasible embodiments of the present invention, the materials of the first gate electrode and the second gate electrode are both selected from any one or more of Al, Zr, Hf and Mo.

[0019] The present invention discloses a method for fabricating a diamond-based CMOS inverter, comprising the following steps:

[0020] A diamond substrate is provided as the base.

[0021] A single-crystal diamond layer is deposited on the surface of the diamond substrate to form a single-crystal diamond film on the surface of the diamond substrate.

[0022] It should be noted that, in order to avoid impurities on the diamond substrate surface potentially affecting the quality and performance of the subsequently formed devices, the diamond substrate needs to be pretreated before forming the single-crystal diamond film. This pretreatment removes impurities from the diamond substrate surface and facilitates better bonding of the subsequent single-crystal diamond film to the diamond substrate surface. To ensure that the above effects can be achieved through pretreatment, in some feasible embodiments of the present invention, the pretreatment is carried out through the following steps: cleaning and drying the diamond substrate for later use, thus obtaining a clean diamond substrate.

[0023] To ensure the formation of a single-crystal diamond film on the diamond substrate surface, in some preferred embodiments of the present invention, chemical vapor deposition is used for preparation, and the specific steps are as follows: the diamond substrate is placed in the cavity of the chemical vapor deposition apparatus and a vacuum is drawn to ≤10. -1 After the pressure stabilizes, hydrogen gas is introduced at a flow rate of 100 sccm to 500 sccm. The microwave source is turned on and the power is slowly increased to 600 W to 1500 W. The hydrogen plasma atmosphere is maintained for 1 min to 2 h. The microwave source is then turned off, but the hydrogen gas flow is maintained until the sample cools to room temperature. The hydrogen gas is then turned off, and the sample is removed. Furthermore, the single-crystal diamond film deposited by chemical vapor deposition in this invention has been tested and found to have a resistivity ≥100 MΩ·cm, a root mean square surface roughness ≤0.5 nm, and a Raman curve half-peak width ≤2 cm. -1 The half-width at half maximum (FWHM) of the XRD (X-ray diffraction) rocking curve is ≤30 arcsec.

[0024] The single-crystal diamond film is hydrogenated to form a two-dimensional hole gas conductive layer on the surface of the single-crystal diamond film.

[0025] Using photolithography and etching techniques, a portion of the two-dimensional hole gas conductive layer is etched, while the unetched areas retain the characteristics of the two-dimensional hole gas conductive layer, forming hydrogen terminal regions; the etched areas form mesa isolation regions.

[0026] It should be noted that, in order to ensure that the formed hydrogen-terminated region can be used as a p-type conductive channel, the present invention preferably employs a hydrogenation process, in which hydrogen reacts with the carbon on the surface of the single-crystal diamond film, thereby transforming the carbon layer on the surface of the single-crystal diamond film into a hydrocarbon-terminated layer. That is, a two-dimensional hole gas conductive layer is formed in situ on the surface of the single-crystal diamond film. According to the actual required size of the hydrogen-terminated region, other areas are etched so that the unetched areas retain the characteristics of the two-dimensional hole gas conductive layer, forming a hydrogen-terminated region to serve as a p-type conductive channel; while the etched area is oxygen-terminated diamond, serving as a mesa isolation region to achieve electrical isolation between devices.

[0027] To ensure that a two-dimensional hole gas conductive layer can be formed on the surface of a single-crystal diamond film through hydrogenation, in some preferred embodiments of the present invention, the hydrogenation is carried out in a hydrogen plasma or hydrogen atmosphere, and the hydrogen flow rate is 50 sccm to 1000 sccm, so as to provide hydrogen through the hydrogen plasma or hydrogen atmosphere to achieve the above reaction.

[0028] To further ensure the formation of a two-dimensional hole gas conductive layer on the surface of a single-crystal diamond film via hydrogenation, in some preferred embodiments of the present invention, the reaction temperature of the hydrogenation treatment is 500℃~900℃. At this temperature, the carbon layer on the surface of the single-crystal diamond film is transformed into a hydrocarbon terminal layer by hydrogen plasma or hydrogen gas, thereby forming a two-dimensional hole gas conductive layer on the surface of the single-crystal diamond film. To ensure the formation of a two-dimensional hole gas conductive layer with a hydrocarbon terminal layer at this reaction temperature, in some preferred embodiments of the present invention, the reaction time of the hydrogenation treatment is 10s~2h. Furthermore, the carrier concentration of the two-dimensional hole gas conductive layer of the present invention (i.e., the carrier concentration inside the p-type conductive channel in the hydrogen terminal region) is 1×10⁻⁶. 12 cm -2 ~5×10 14 cm -2 The migration rate is 20cm. 2 / V·s~2500cm 2 / V·s.

[0029] It should be noted that, in order to facilitate the formation of the hydrogen terminal region and the mesa isolation region, in some preferred embodiments of the present invention, a mask method is used. That is, according to actual needs, a mask matching the actual required p-type channel size is selected to form the required photoresist pattern. Then, photolithography is used to etch the uncovered area of ​​the two-dimensional hole gas conductive layer so that the etched area forms the mesa isolation region, while the unetched area retains the characteristics of the two-dimensional hole gas conductive layer and forms the hydrogen terminal region.

[0030] To ensure that the two-dimensional hole gas conductive layer can be formed into hydrogen terminal regions and mesa isolation regions using a masking method combined with photolithography, in some preferred embodiments of the present invention, the following steps are employed:

[0031] Diamond substrates with a two-dimensional hole gas conductive layer on their surface were ultrasonically cleaned using acetone, isopropanol, and deionized water, and then dried for later use. Subsequently, a layer of photoresist was spin-coated onto the sample surface. The photoresist-coated diamond substrate was then baked at 85℃–95℃ for 60–120 s, followed by UV lithography exposure using a designed mask for 2 s–8 s, and development for 50 s–70 s, ensuring the photoresist only covers the p-type channels. Then, reactive ion etching was used to form mesa isolation regions. Finally, acetone was used to remove the photoresist from the sample surface, thus forming hydrogen-terminated and mesa isolation regions on the two-dimensional hole gas conductive layer, resulting in a diamond substrate with both hydrogen-terminated and mesa isolation regions on its surface. During etching, a plasma power of 30W–300W and a etching rate of 1 nm / min–1000 nm / min were used.

[0032] After depositing a protective layer on the hydrogen terminal region using deposition technology, an oxide layer is deposited on the surface of the sample with the protective layer deposited. An n-type channel pattern is then etched on the surface of the oxide layer to form an n-type oxide semiconductor layer, which serves as an n-type conductive channel.

[0033] It should be noted that, considering the entire sample surface is exposed to the preparation environment during deposition, this invention aims to prevent damage to the hydrogen terminal region during oxide layer deposition and sample processing. Therefore, a protective layer is first deposited on the hydrogen terminal region before the sample undergoes deposition. This process involves depositing an oxide layer on the surface of the sample with the protective layer, followed by etching to form an n-type channel pattern, and then removing the protective layer from the hydrogen terminal region. This achieves the deposition of an oxide layer only on the mesa isolation region. Considering that the deposited protective layer must not only protect the hydrogen terminal region to prevent accidental etching but also be easy to remove without damaging the region, in some preferred embodiments of this invention, the protective layer is selected from metals or dielectric materials, and its thickness is 130 nm to 170 nm. The metal can be gold, and the dielectric material can be SiO2 or Si3N4. It should be noted that when the protective layer on the hydrogen termination region is metal, there is no need to remove the protective layer; after etching an n-type channel pattern on the oxide layer surface, an n-type oxide semiconductor layer is formed. When the protective layer on the hydrogen termination region is a dielectric material, an n-type channel pattern is etched on the oxide layer surface, and the protective layer is removed to form an n-type oxide semiconductor layer. To ensure the removal of the protective layer, in some feasible embodiments of the present invention, cleaning is performed using I2 / KI solution, BOE (Buffered Oxide Etch), or hydrofluoric acid.

[0034] In some feasible embodiments of the present invention, when depositing a protective layer on the hydrogen terminal region and when depositing an oxide layer on the surface of the mesa isolation region, any one of electron beam evaporation physical vapor deposition, magnetron sputtering, metal-organic chemical vapor deposition, laser pulse deposition, atomic layer deposition, and sol-gel can be used for deposition.

[0035] In some preferred embodiments of the present invention, when a protective layer is deposited using electron beam evaporation physical vapor deposition, the protective layer deposited on the hydrogen terminal region is achieved through the following steps:

[0036] 1) A layer of photoresist is spin-coated onto the sample surface where hydrogen termination regions and mesa isolation regions are formed. The sample is then baked at 90℃~105℃ for 80s~100s. Ultraviolet lithography is then performed using a mask designed according to device performance requirements for 5s~6s, followed by development for 60s~80s to expose the hydrogen termination regions and achieve the pattern of the protective layer. The photoresist used is AZ5214 or RN246.

[0037] 2) Using EB-PVD deposition technology, a protective layer material with a thickness of 130nm to 170nm is deposited to complete the lift-off process, leaving only the dielectric layer in the area not covered by photoresist to form a protective layer on the hydrogen termination region.

[0038] To ensure that the formed oxide layer can be used as an n-type conductive channel, in some preferred embodiments of the present invention, the material of the deposited oxide layer can be selected according to actual needs, such as any one or more of SnO2, ZnO, In2O3, ZrO2, ITO, AZO and IGZO.

[0039] To further ensure that the formed oxide layer can be used as an n-type conductive channel, in some preferred embodiments of the present invention, the required n-type channel pattern is first etched onto the surface of the oxide layer according to actual needs, followed by annealing. Annealing improves the crystallinity of the oxide layer, thereby enhancing the carrier mobility performance of the n-type conductive channel and forming an n-type oxide semiconductor layer to meet the requirements for use as an n-type conductive channel material. In some preferred embodiments of the present invention, the annealing process uses either oxygen or argon in the annealing atmosphere, at a temperature of 300°C to 600°C, for a time of 1 min to 60 min.

[0040] Test results show that the carrier concentration of the n-type conductive channel in the n-type oxide semiconductor layer formed by the above method of the present invention is 1×10⁻⁶. 15 cm -3 ~1×10 20 cm -3 The migration rate is 1cm. 2 / V·s~500cm 2 / V·s.

[0041] A first source electrode and a first drain electrode are deposited at both ends of the n-type oxide semiconductor layer, so that both the first drain electrode and the second drain electrode form an ohmic contact with the n-type oxide semiconductor layer; a second source electrode and a second drain electrode are deposited at both ends of the hydrogen terminal region, so that both the second source electrode and the second drain electrode form an ohmic contact with the hydrogen terminal region, which is a p-type conductive channel.

[0042] It should be noted that the present invention preferably employs a mask method, that is, according to actual needs, a mask is selected that matches the size of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode, to form the required photoresist pattern, and then the corresponding first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are deposited respectively.

[0043] In some feasible embodiments of the present invention, the deposition of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode can be performed using any one of the following methods: electron beam evaporation, magnetron sputtering, metal-organic chemical vapor deposition, laser pulse deposition, atomic layer deposition, and sol-gel deposition. In some preferred embodiments of the present invention, electron beam evaporation technology is used for deposition.

[0044] It should also be noted that the first source electrode is grounded and the second source electrode is connected to the power supply voltage to form a complete logic device structure, so as to ensure that the CMOS inverter can work.

[0045] A first gate dielectric layer and a first gate electrode are sequentially deposited on an n-type oxide semiconductor layer, and a second gate dielectric layer and a second gate electrode are sequentially deposited on a hydrogen-terminated region.

[0046] A first interconnect line and a second interconnect line are formed on the sample surface using photolithography and deposition techniques, so as to realize the metal interconnection of the first drain electrode and the second drain electrode through the first interconnect line, and to realize the metal interconnection of the first gate electrode and the second gate electrode through the second interconnect line.

[0047] It should be noted that the present invention preferably employs a mask method, that is, according to actual needs, a mask is selected that matches the actual required dimensions of the first gate dielectric layer and the first gate electrode, the second gate dielectric layer and the second gate electrode, to form the required photoresist pattern, and then the corresponding first gate dielectric layer and the first gate electrode, the second gate dielectric layer and the second gate electrode are deposited respectively.

[0048] In some feasible embodiments of the present invention, the deposition of the first gate dielectric layer and the first gate electrode, the second gate dielectric layer and the second gate electrode can be performed using any one of the following methods: electron beam evaporation, magnetron sputtering, metal-organic chemical vapor deposition, laser pulse deposition, atomic layer deposition, and sol-gel deposition. In some preferred embodiments of the present invention, electron beam evaporation physical vapor deposition is used for deposition.

[0049] In some feasible embodiments of the present invention, the photolithography described in the present invention is any one of ultraviolet lithography, electron beam lithography, and stepper non-contact lithography.

[0050] Compared with the prior art, the present invention has the following advantages:

[0051] The diamond-based CMOS inverter of the present invention includes: a diamond substrate, a single-crystal diamond thin film, a hydrogen-terminated region, a mesa isolation region, an n-type oxide semiconductor layer, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a first gate dielectric layer, a first gate electrode, a second gate dielectric layer, and a second gate electrode. A single-crystal diamond thin film is disposed on the diamond substrate. The single-crystal diamond thin film has a hydrogen-terminated region and a mesa isolation region. An n-type oxide semiconductor layer is disposed on the mesa isolation region. A first source electrode and a first drain electrode are respectively disposed at both ends of the n-type oxide semiconductor layer. A second source electrode and a second drain electrode are respectively disposed at both ends of the hydrogen-terminated region. A first gate dielectric layer is disposed on the n-type oxide semiconductor layer. A second gate dielectric layer is disposed on the hydrogen-terminated region. A first gate electrode is disposed on the first gate dielectric layer. A second gate electrode is disposed on the second gate dielectric layer. The first drain electrode and the second drain electrode are metal-interconnected and serve as the output of the CMOS inverter; the first gate electrode and the second gate electrode are metal-interconnected and serve as the input of the CMOS inverter.

[0052] This invention effectively circumvents the current technical challenge of realizing n-type MOS devices (Metal-Oxide-Semiconductor Field-Effect Transistors) using diamond by combining p-type hydrogen-terminated diamond and n-type oxide semiconductor. It fully leverages the advantages of both diamond and n-type oxide semiconductor to achieve a high-performance diamond-based monolithically integrated CMOS inverter. Diamond has high carrier mobility, while n-type oxide semiconductor has high electron concentration and low resistivity. Monolithic integration reduces device spacing, ensuring the CMOS inverter has high switching speed, high gain, and low loss. Diamond has high thermal conductivity and strong radiation resistance, reducing device junction temperature, while n-type oxide semiconductor has good thermal stability. Therefore, this ensures the CMOS inverter can be used in high-temperature, high-radiation environments. This demonstrates the enormous potential of diamond in integrated circuit applications, playing multiple roles in digital system design, computer processors, and communication circuits, including logic gate implementation, clock signal driving, buffer amplifiers, signal inversion control, and digital signal processing. This promotes the development of digital circuit technology and provides an efficient and reliable working foundation for digital systems. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of the connection logic of the diamond-based CMOS inverter of the present invention. Figure 1 In the middle, M P It is a p-type enhancement device, M N It is an n-type enhancement-mode device, V DD This is the operating voltage, gnd is ground, V INIt is the input terminal and indicates that the first gate electrode and the second gate electrode are connected, V OUT It is the output terminal and indicates that the first drain electrode and the second drain electrode are connected.

[0054] Figure 2 A schematic flowchart of the fabrication method of the diamond-based CMOS inverter of the present invention.

[0055] Figure 3 This is a schematic diagram of the cross-sectional structure of a diamond-based CMOS inverter according to the present invention; Figure 3 In the diagram, there are: 1. Diamond substrate; 2. Single-crystal diamond thin film; 3. Hydrogen terminal region; 4. Mesa isolation region; 5. n-type oxide semiconductor layer; 6. First source electrode; 7. First drain electrode; 8. Second source electrode; 9. Second drain electrode; 10. First gate dielectric layer; 11. First gate electrode; 12. Second gate dielectric layer; 13. Second gate electrode; 14. First interconnect; 15. Second interconnect.

[0056] Figure 4 This is a top view of a diamond-based CMOS inverter according to the present invention. Detailed Implementation

[0057] The technical solutions in the embodiments of the present invention will be clearly and completely described below. It should be noted that in the following embodiments of the present invention, standard cleaning processes for diamond substrates in the art are used for cleaning; therefore, the specific cleaning steps will not be repeated, and those skilled in the art should know them. In the following embodiments of the present invention, the preparation process used to grow and form the diamond substrate is a conventional process in the art, as long as diamond substrate 1 can be formed; therefore, it will not be repeated, and those skilled in the art should know them. It should also be noted that, for the sake of concise expression, as shown in the English-Chinese comparison table in Table 1, the following substances or preparation methods in the following embodiments of the present invention are replaced with their corresponding English abbreviations.

[0058] Table 1. Chinese-English Translation Table

[0059]

[0060] The present invention discloses a diamond-based CMOS inverter, comprising: a diamond substrate 1; a single-crystal diamond thin film 2 disposed on the diamond substrate 1; a hydrogen termination region 3 disposed on the single-crystal diamond thin film 2 as a p-type conductive channel; a mesa isolation region 4 disposed on the single-crystal diamond thin film 2 and located around the hydrogen termination region 3; an n-type oxide semiconductor layer 5 disposed on the mesa isolation region 4 as an n-type conductive channel; a first gate dielectric layer 10 disposed on the n-type oxide semiconductor layer 5; and a first gate electrode 11 disposed on the first gate dielectric layer 10; a second gate dielectric layer 12 disposed on the hydrogen termination region 3, and a second gate dielectric layer 12 having a first gate electrode 11 disposed on the second gate dielectric layer 12. The invention comprises two gate electrodes 13; wherein, the n-type oxide semiconductor layer 5 has a first source electrode 6 and a first drain electrode 7 at its two ends, and the first gate dielectric layer 10 and the first gate electrode 11 are both located between the first source electrode 6 and the first drain electrode 7; the hydrogen-terminated region 3 has a second source electrode 8 and a second drain electrode 9 at its two ends, and the second gate dielectric layer 12 and the second gate electrode 13 are both located between the second source electrode 8 and the second drain electrode 9; the first drain electrode 7 and the second drain electrode 9 are metal-interconnected and serve as the output of the CMOS inverter; the first gate electrode 11 and the second gate electrode 13 are metal-interconnected and serve as the input of the CMOS inverter. This invention effectively circumvents the current technical difficulty of realizing n-type MOS devices using diamond by combining p-type hydrogen-terminated diamond (i.e., hydrogen-terminated region 3) and n-type oxide semiconductor (i.e., n-type oxide semiconductor layer 5), fully leveraging the advantages of both diamond and n-type oxide semiconductor, and realizing a high-performance diamond-based monolithic integrated CMOS inverter.

[0061] Furthermore, a portion of the first source electrode 6 and the first drain electrode 7 are both located on the mesa isolation region 4, and another portion is located on the n-type oxide semiconductor layer 5, for forming an ohmic contact; a portion of the second source electrode 8 and the second drain electrode 9 are both located on the mesa isolation region 4, and another portion is located on the hydrogen terminal region 3, for forming an ohmic contact; the second source electrode 8 and the second drain electrode 9 are not in contact with the second gate dielectric layer 12 and the second gate electrode 13; the first gate dielectric layer 10 is located on the first source electrode 6 and the first drain electrode 7 and is not in contact with the first gate electrode 11.

[0062] The present invention also provides a method for fabricating a diamond-based CMOS inverter, including the following embodiments.

[0063] Example 1

[0064] Please see Figure 2 This embodiment provides a diamond-based CMOS inverter, which is fabricated through the following steps:

[0065] Step 1, provide a diamond substrate 1 as the base:

[0066] 1.1) A diamond substrate 1 was grown using CVD technology.

[0067] 1.2) After cleaning the diamond substrate 1 grown by CVD technology, it is dried with nitrogen gas to obtain a clean diamond substrate 1, which is used as a substrate for later use.

[0068] Step 2: Epitaxially grow a single-crystal diamond layer on the surface of the diamond substrate 1 to form a single-crystal diamond thin film 2 on the surface of the diamond substrate 1.

[0069] Using MPCVD technology, a single-crystal diamond film 2 with a thickness of 2 μm was deposited on a cleaned diamond substrate 1 under the conditions of plasma power of 1.2 kW, chamber pressure of 100 Torr, and total gas flow rate of 500 sccm.

[0070] Furthermore, testing showed that the resistivity of the single-crystal diamond film 2 obtained in this embodiment was 120 MΩ·cm, the root mean square surface roughness was 0.4 nm, and the full width at half maximum (FWHM) of the Raman curve was 1.9 cm. -1 The half-peak width of the XRD rocking curve is 28 arcsec.

[0071] Step 3: The single-crystal diamond film 2 is subjected to hydrogenation treatment to form a two-dimensional hole gas conductive layer on the surface of the single-crystal diamond film 2.

[0072] Using MPCVD technology, the single-crystal diamond film 2 was hydrogenated for 20 minutes at a chamber temperature of 700℃ and a hydrogen flow rate of 100 sccm to form a two-dimensional hole gas conductive layer on the surface of the single-crystal diamond film 2.

[0073] Step 4: Using photolithography and etching techniques, a portion of the two-dimensional hole gas conductive layer is etched. The unetched areas retain the characteristics of the two-dimensional hole gas conductive layer, forming hydrogen terminal regions 3. The etched areas form mesa isolation regions 4.

[0074] 4.1) Clean the sample obtained in step 3 above with acetone, isopropanol and deionized water by ultrasonic cleaning, and then blow dry for later use.

[0075] 4.2) Spin-coat a layer of AZ5214 photoresist onto the sample surface obtained in 4.1) above, and then bake at 90°C for 90s to remove the photoresist solvent; then, use a mask designed according to the device performance requirements to perform ultraviolet lithography exposure for 5s, development for 60s, remove the exposed photoresist, and leave the mask area pattern.

[0076] 4.3) Using RIE etching, etching is performed under RIE etching process conditions of plasma power of 100W and rate of 500nm / min to form mesa isolation region 4 in the area where the two-dimensional hole gas conductive layer is not covered by photoresist. Finally, acetone is used to remove the photoresist on the sample surface to expose the unetched area that still retains the characteristics of the two-dimensional hole gas conductive layer, forming hydrogen terminal region 3.

[0077] Furthermore, testing showed that the two-dimensional hole gas surface density in the hydrogen terminal region 3 obtained in this embodiment is 1×10⁻⁶. 13 cm -2 The migration rate is 180cm. 2 / V·s.

[0078] Step 5: After depositing a protective layer on the hydrogen terminal region 3 using deposition techniques, an oxide layer is deposited on the sample surface with the protective layer:

[0079] 5.1) Spin-coat a layer of AZ5214 photoresist onto the sample surface obtained in 4.3) above, then bake at 90°C for 90s, perform ultraviolet lithography exposure for 5s using a mask designed according to the device performance requirements, develop for 60s, remove the exposed photoresist to expose the hydrogen terminal region 3, and realize the pattern of the protective layer.

[0080] 5.2) EB-PVD deposition technology was used, with a background vacuum of 5×10⁻⁶. -4 Under the condition of Pa, the electron beam current is set to 30mA, and a SiO2 layer with a thickness of 150nm is deposited to complete the lift-off process. Only the dielectric layer in the area not covered by photoresist is retained to form a protective layer on the hydrogen terminal region 3.

[0081] 5.3) A 220 nm thick In2O3 layer was deposited on the sample surface using radio frequency magnetron sputtering technology. In this embodiment, the sputtering conditions for radio frequency magnetron sputtering were: temperature 300 °C, sputtering power 300 W, deposition time 10 min, working pressure 0.6 Pa. A target material prepared by mixing In2O3, SnO2, and WO3 in a mass ratio of 90:9:1 was used as the In2O3 target to control the properties of the n-type oxide. The background vacuum was 10 Pa. -4 Pa, argon flow rate is 40 mL / min.

[0082] Step 6: An n-type channel pattern is etched on the surface of the oxide layer, and the protective layer on the hydrogen termination region is removed, thus forming the n-type oxide semiconductor layer 5. In this embodiment, the carrier concentration in the n-type conductive channel region of the obtained In2O3 layer is 10. 18 cm -3 The migration rate was 27.3 cm. 2 / V·s.

[0083] 6.1) After sputtering, the sample is allowed to cool naturally to room temperature. Then, a layer of AZ5214 photoresist is spin-coated onto the surface of the obtained sample. The single crystal diamond sample with the photoresist spin-coated is baked at 90°C for 90 seconds. According to the device performance requirements, a well-designed mask is used for ultraviolet lithography exposure for 5 seconds, followed by development for 60 seconds. The exposed photoresist is removed, leaving the mask area pattern.

[0084] 6.2) 150 nm SiO2 was deposited using EB-PVD technology, with a base vacuum of 5 × 10⁻⁶. -4 Pa, a lift-off process was performed in acetone solution to obtain a SiO2 mask pattern. Then the sample was placed in an etching machine for etching to remove the non-n-type conductive channel region In2O3, leaving only the n-type conductive channel region In2O3, thus obtaining the n-type oxide semiconductor layer 5.

[0085] 6.3) Immerse the sample obtained in step 6.2) above in BOE solution to remove the SiO2 layer formed in steps 6.2) and 5. Since the hydrogen-terminated region is conductive, while SiO2 is non-conductive, if the sample becomes conductive again in this region, it indicates that the SiO2 has been completely removed. Furthermore, in practice, it was found that a 150nm SiO2 layer can be completely etched away after immersion in BOE solution for 3 minutes.

[0086] Step 7: A first source electrode 6 and a first drain electrode 7 are deposited at both ends of the n-type oxide semiconductor layer 5, and a second source electrode 8 and a second drain electrode 9 are deposited at both ends of the hydrogen terminal region 3.

[0087] 7.1) Spin-coat a layer of AZ5214 photoresist onto the sample surface obtained in 6.3) above. Bake the single crystal diamond sample with the photoresist spin-coated at 90°C for 90 seconds. According to the device performance requirements, perform ultraviolet lithography exposure for 5 seconds using a pre-designed mask, followed by development for 60 seconds. Remove the exposed photoresist to expose the source and drain electrode areas.

[0088] 7.2) Electron beam evaporation technology is used, with a background vacuum of 5×10⁻⁶. -4 Under the condition of Pa, Au with a thickness of 150 nm is deposited at both ends of the n-type oxide semiconductor layer 5 to serve as the first source electrode 6 and the first drain electrode 7, respectively. At the same time, Au with a thickness of 150 nm is deposited at both ends of the hydrogen terminal region 3 to serve as the second source electrode 8 and the second drain electrode 9, respectively.

[0089] 7.3) Take out the sample deposited in 7.2) above, immerse it in acetone solution for 5 minutes to complete the lift-off process, so as to peel off the AZ5214 photoresist coated in 7.1) above, and obtain the first source electrode 6, the first drain electrode 7, the second source electrode 8 and the second drain electrode 9.

[0090] Step 8: A first gate dielectric layer 10 and a first gate electrode 11 are sequentially deposited on the n-type oxide semiconductor layer 5, while a second gate dielectric layer 12 and a second gate electrode 13 are sequentially deposited on the hydrogen termination region 3.

[0091] 8.1) Spin-coat a layer of AZ5214 photoresist onto the sample surface obtained in 7.3) above. Bake the single crystal diamond sample with the photoresist spin-coated at 90°C for 90 seconds. Perform ultraviolet lithography exposure for 5 seconds using a pre-designed mask according to the device performance requirements, followed by development for 60 seconds. Remove the exposed photoresist to obtain the gate dielectric layer pattern.

[0092] 8.2) EB-PVD technology is used, with a background vacuum of 3.7 × 10⁻⁶. -5 Under conditions of Pa and a current intensity of 20 mA, a 50 nm thick Al2O3 layer is first deposited on the n-type oxide semiconductor layer 5 as the first gate dielectric layer 10. Then, an Al layer is deposited on the formed Al2O3 layer to obtain the first gate electrode 11. Simultaneously, a 50 nm thick Al2O3 layer is first deposited on the hydrogen terminal region 3 as the second gate dielectric layer 12. Then, an Al layer is deposited on the formed Al2O3 layer to obtain the second gate electrode 13.

[0093] 8.3) Take out the sample deposited in step 8.2) above, immerse it in acetone solution for 5 minutes to peel off the AZ5214 photoresist coated in step 1) above, and obtain the first gate dielectric layer 10, the first gate electrode 11, the second gate dielectric layer 12 and the second gate electrode 13.

[0094] Step 9: Interconnect the first drain electrode 7 and the second drain electrode 9 with metal, and interconnect the first gate electrode 11 and the second gate electrode 13 with metal to form a logic device.

[0095] A layer of AZ5214 photoresist was spin-coated onto the surface of the sample obtained in 8.3) above. The single-crystal diamond sample with the photoresist spin-coated was baked at 90°C for 90 seconds. According to the device performance requirements, UV lithography exposure was performed using a designed mask for 5 seconds, followed by development for 60 seconds. The exposed photoresist was then removed to obtain the interconnect metal pattern. Electron beam evaporation technology was used, with a background vacuum of 5 × 10⁻⁶. -4Under the condition of Pa, Al metal interconnects are deposited, and the first drain electrode 7 and the second drain electrode 9 are interconnected through the first interconnect 14, and the first gate electrode 11 and the second gate electrode 13 are interconnected through the second interconnect 15, to obtain a diamond-based CMOS inverter.

[0096] Furthermore, the overall structure of the diamond-based CMOS inverter formed in this embodiment is as follows: Figure 3 and Figure 4 As shown.

[0097] Example 2

[0098] This embodiment provides a diamond-based CMOS inverter, which is fabricated through the following steps:

[0099] Step 1, provide a diamond substrate 1 as the base:

[0100] 1.1) A diamond substrate 1 was grown using HPHT technology.

[0101] 1.2) After cleaning the diamond substrate 1 grown by HPHT technology, it is dried with nitrogen gas to obtain a clean diamond substrate 1, which is used as a substrate for later use.

[0102] Step 2: Epitaxially grow a single-crystal diamond layer on the surface of the diamond substrate 1 to form a single-crystal diamond thin film 2 on the surface of the diamond substrate 1.

[0103] A single-crystal diamond layer 2 was deposited on a cleaned diamond substrate using MPCVD technology. The plasma power was 1 kW, the chamber pressure was 100 Torr, and the total gas flow rate was 500 sccm. The resulting single-crystal diamond film had a thickness of 1 μm, a resistivity of 100 MΩ·cm, a root mean square surface roughness of 0.5 nm, and a Raman curve half-width of 2 cm. -1 The half-peak width of the XRD rocking curve is 30 arcsec.

[0104] Step 3: The single-crystal diamond film 2 is subjected to hydrogenation treatment to form a two-dimensional hole gas conductive layer on the surface of the single-crystal diamond film 2.

[0105] The microwave plasma power was controlled to maintain a chamber temperature of 700℃ and a hydrogen flow rate of 150 sccm to hydrogenate the grown single-crystal diamond film 2 for 5 minutes, thereby forming a two-dimensional hole gas conductive layer on the surface of the single-crystal diamond film 2. The resulting two-dimensional hole gas conductive layer had an areal density of 2 × 10⁻⁶. 13 cm -2 The migration rate is 150cm. 2 / V·s.

[0106] Step 4: Using photolithography and etching techniques, a portion of the two-dimensional hole gas conductive layer is etched. The unetched areas retain the characteristics of the two-dimensional hole gas conductive layer, forming hydrogen terminal regions 3. The etched areas form mesa isolation regions 4.

[0107] 4.1) Clean the sample with acetone, isopropanol, and deionized water using ultrasonic cleaning, and then dry it for later use.

[0108] 4.2) Spin-coat a layer of RN246 photoresist onto the sample surface obtained in 4.1) above. Bake the spin-coated single-crystal diamond sample at 100°C for 90s to remove the photoresist solvent. Expose the sample to ultraviolet light for 5.5s using a pre-designed mask, bake it at 103°C for 100s, and develop it for 80s to remove the unexposed photoresist, leaving the mask area pattern.

[0109] 4.3) ICP etching is used to etch the sample surface under RIE etching conditions of plasma power of 100W and rate of 500nm / min to form mesa isolation region 4. Finally, acetone is used to remove the photoresist on the sample surface to expose the unetched area that still retains the characteristics of the two-dimensional hole gas conductive layer, forming hydrogen terminal region 3.

[0110] Step 5: After depositing a protective layer on the hydrogen terminal region 3 using deposition techniques, an oxide layer is deposited on the sample surface with the protective layer:

[0111] 5.1) Spin-coat a layer of RN246 photoresist onto the sample surface obtained in 4.3) above. Bake the single crystal diamond sample with the photoresist spin-coated at 100°C for 90s. Expose it to ultraviolet light for 5.5s using a pre-designed mask. Then bake it at 103°C for 100s and develop it for 80s. Remove the unexposed photoresist to expose the hydrogen terminal region 3, thus realizing the pattern of the protective layer.

[0112] 5.2) Using EB-PVD deposition technology, with a background vacuum of 5×10⁻⁶ -4 Under the condition of Pa, the electron beam current is set to 20mA, and a layer of Au with a thickness of 150nm is deposited to complete the lift-off process. Only the Au layer in the area not covered by photoresist is retained to form a protective layer on the hydrogen terminal region 3.

[0113] 5.3) Using atomic layer deposition (ALD), an 80 nm thick n-type Al-doped ZnO semiconductor layer was deposited on the sample surface. In this embodiment, the aluminum doping source was trimethylaluminum, the zinc source precursor was dimethylzinc, the oxygen source precursor was water, the deposition temperature was 200 °C, the chamber pressure was 0.2 Torr, and the Al doping content was 2.17%.

[0114] Step 6: An n-type channel pattern is etched on the surface of the oxide layer to form an n-type oxide semiconductor layer 5.

[0115] 6.1) After deposition, the sample was allowed to cool naturally to room temperature. Then, an RN246 photoresist layer was spin-coated onto the obtained sample surface. The single-crystal diamond sample with the photoresist coated was baked at 100℃ for 90s, exposed to ultraviolet light using a pre-designed mask for 5.5s, then baked at 103℃ for 100s, and developed for 80s. The unexposed photoresist was removed, leaving the mask area pattern. 100nm of SiO2 was deposited using EB-PVD with a base vacuum of 5×10⁻⁶. -4 Pa, after peeling, obtains the SiO2 mask pattern. Then the sample is placed in an etching machine for etching to remove the non-n-type conductive channel region ZnO, leaving only the n-type conductive channel region ZnO.

[0116] 6.2) Immerse the sample in BOE solution for 7 minutes to remove the SiO2 mask formed in 6.1) above.

[0117] 6.3) The annealed sample was placed in a rapid annealing furnace for annealing at 400℃ for 60s. The resulting ZnO thin film n-type conductive channel region had a carrier concentration of 4×10⁻⁶. 18 cm -3 The migration rate was 17.4 cm. 2 / V·s.

[0118] Step 7: Deposit and form the second source electrode, the second drain electrode, the second gate dielectric layer, and the second gate electrode respectively.

[0119] 7.1) Spin-coat a layer of RN246 photoresist onto the sample surface obtained in 6.3). Bake the single-crystal diamond sample with the photoresist spin-coated at 100°C for 90s. Expose it to ultraviolet light using a mask for 5.5s. Then bake it at 103°C for 100s and develop it for 80s. Remove the unexposed photoresist, leaving the mask area pattern. Use a KI / I2 aqueous solution to etch the Au layer at the dielectric layer position of the p-type device to obtain the second source electrode 8 and the second drain electrode 9.

[0120] 7.2) Using the mask described in 7.1), deposit 50 / 100 nm ZrO2 / Al at the gate dielectric layer of the p-type device using electron beam evaporation, with a base vacuum of 5 × 10⁻⁶. -4 Pa. The deposited diamond sample was removed, immersed in acetone solution for 5 min, and then peeled off to obtain the designed second gate dielectric layer 12 and second gate electrode 13.

[0121] Step 8: Deposit the first source electrode, the first drain electrode, the first gate dielectric layer, and the first gate electrode.

[0122] 8.1) Spin-coat a layer of RN246 photoresist onto the surface of the sample described in 7.2). Bake the spin-coated single-crystal diamond sample at 100°C for 90 seconds, perform UV lithography exposure using a pre-designed mask for 5.5 seconds, then bake at 103°C for 100 seconds, and develop for 80 seconds to obtain the source / drain electrode pattern. Deposit 150 nm of Au using electron beam evaporation with a base vacuum of 5 × 10⁻⁶. -4 Pa. The deposited diamond sample is removed, immersed in acetone solution for 5 min, and then peeled off to obtain the first source electrode 6 and the first drain electrode 7.

[0123] 8.2) Spin-coat a layer of RN246 photoresist onto the sample surface. Bake the spin-coated single-crystal diamond sample at 100℃ for 90s, perform UV lithography exposure using a pre-designed mask for 5.5s, then bake at 103℃ for 100s, and develop for 80s to obtain the gate electrode pattern. Deposit 50 / 100nm MoO3 / Mo using electron beam evaporation with a base vacuum of 5×10⁻⁶. - 4 Pa. The deposited diamond sample is removed, immersed in acetone solution for 5 min, and then peeled off to obtain the first gate dielectric layer 10 and the first gate electrode 11.

[0124] Step 9: Interconnect the first drain electrode 7 and the second drain electrode 9 with metal, and interconnect the first gate electrode 11 and the second gate electrode 13 with metal to form a logic device.

[0125] Interconnects of deposited Al metal are used to interconnect the first drain electrode 7 and the second drain electrode 9 through the first interconnect 14, and to interconnect the first gate electrode 11 and the second gate electrode 13 through the second interconnect 15, to obtain a diamond-based CMOS inverter.

[0126] The diamond-based CMOS inverter of this invention is fabricated by combining p-type hydrogen-terminated diamond (i.e., hydrogen-terminated region 3) and n-type oxide semiconductor. This effectively avoids the current technical difficulty of realizing n-type MOS devices with diamond, and fully leverages the advantages of both diamond and n-type oxide semiconductor to achieve a high-performance diamond-based monolithically integrated CMOS inverter. Diamond has high carrier mobility, while n-type oxide semiconductor has high conductive electron concentration and low resistivity. Monolithic integration reduces device spacing, ensuring that the CMOS inverter has high switching speed, high gain, and low loss. Diamond has high thermal conductivity and strong radiation resistance, reducing device junction temperature, while n-type oxide semiconductor has good thermal stability. Therefore, this ensures that the CMOS inverter can be used in high-temperature and high-radiation environments, demonstrating the great potential of diamond in integrated circuit applications.

[0127] Obviously, the above embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A diamond-based CMOS inverter, characterized in that, include: Diamond substrate (1); A single-crystal diamond thin film (2) is disposed on the diamond substrate (1); The hydrogen terminal region (3) is disposed on the single crystal diamond film (2) as a p-type conductive channel; The platform isolation area (4) is disposed on the single crystal diamond film (2) and is located around the hydrogen terminal area (3); An n-type oxide semiconductor layer (5) is disposed on the mesa isolation region (4) as an n-type conductive channel; A first gate dielectric layer (10) is disposed on an n-type oxide semiconductor layer (5); and a first gate electrode (11) is disposed on the first gate dielectric layer (10); A second gate dielectric layer (12) is disposed on the hydrogen terminal region (3); and a second gate electrode (13) is disposed on the second gate dielectric layer (12); The n-type oxide semiconductor layer (5) has a first source electrode (6) and a first drain electrode (7) at its two ends, and the first gate dielectric layer (10) and the first gate electrode (11) are located between the first source electrode (6) and the first drain electrode (7); the hydrogen terminal region (3) has a second source electrode (8) and a second drain electrode (9) at its two ends, and the second gate dielectric layer (12) and the second gate electrode (13) are located between the second source electrode (8) and the second drain electrode (9); the first drain electrode (7) and the second drain electrode (9) are interconnected by metal as the output of the CMOS inverter; the first gate electrode (11) and the second gate electrode (13) are interconnected by metal as the input of the CMOS inverter.

2. The diamond-based CMOS inverter as described in claim 1, characterized in that, The single-crystal diamond film (2) is obtained by epitaxy on the diamond substrate (1) using chemical vapor deposition; the hydrogen terminal region (3) is formed by hydrogenation treatment of the surface of the single-crystal diamond film (2).

3. The diamond-based CMOS inverter as described in claim 1, characterized in that, The carrier concentration inside the p-type conductive channel of the hydrogen terminal region (3) is 1×10⁻⁶. 12 cm -2 ~5×10 14 cm -2 The migration rate is 20cm. 2 / V·s~2500cm 2 / V·s, the thickness of the hydrogen terminal region (3) is 1nm to 20nm.

4. The diamond-based CMOS inverter as described in claim 1, characterized in that, The tabletop isolation area (4) is made of oxygen-terminated diamond.

5. The diamond-based CMOS inverter as described in claim 1, characterized in that, The n-type oxide semiconductor layer (5) is made of any one or more of tin dioxide, zinc oxide, indium oxide, zirconium dioxide, indium tin oxide, aluminum zinc oxide and indium gallium zinc oxide.

6. The diamond-based CMOS inverter as described in claim 1, characterized in that, The materials of the first source electrode (6), the first drain electrode (7), the second source electrode (8), and the second drain electrode (9) are all selected from one or more of Au, Pd, Ir, Pt, and Ti.

7. The diamond-based CMOS inverter as described in claim 1, characterized in that, The materials of the first gate dielectric layer (10) and the second gate dielectric layer (12) are both selected from Al2O3, SiO2, and SiN. x Any one or more of HfO2 and MoO3.

8. The diamond-based CMOS inverter as described in claim 1, characterized in that, The materials of the first gate electrode (11) and the second gate electrode (13) are selected from any one or more of Al, Zr, Hf and Mo.

9. A method for fabricating a diamond-based CMOS inverter according to any one of claims 1 to 8, characterized in that, Includes the following steps: A diamond substrate (1) is provided as the base; A single-crystal diamond layer is epitaxially grown on the surface of the diamond substrate (1) to form a single-crystal diamond film (2) on the surface of the diamond substrate (1); The single-crystal diamond film (2) is subjected to hydrogenation treatment to form a two-dimensional hole gas conductive layer on the surface of the single-crystal diamond film (2); Photolithography and etching techniques are used to etch a portion of the two-dimensional hole gas conductive layer. The unetched area retains the characteristics of the two-dimensional hole gas conductive layer to form a hydrogen terminal region (3). The etched area forms a mesa isolation region (4). After depositing a protective layer on the hydrogen terminal region (3) using deposition technology, an oxide layer is deposited on the sample surface with the protective layer to form an n-type oxide semiconductor layer (5); A first source electrode (6) and a first drain electrode (7) are formed at both ends of the n-type oxide semiconductor layer (5), and a second source electrode (8) and a second drain electrode (9) are deposited at both ends of the hydrogen terminal region (3). A first gate dielectric layer (10) and a first gate electrode (11) are sequentially deposited on an n-type oxide semiconductor layer (5), and a second gate dielectric layer (12) and a second gate electrode (13) are sequentially deposited on a hydrogen terminal region (3). The first drain electrode (7) and the second drain electrode (9) are interconnected by metal, and the first gate electrode (11) and the second gate electrode (13) are interconnected by metal to form a logic device.

10. The preparation method according to claim 9, wherein the hydrogenation treatment is carried out in a hydrogen plasma or a hydrogen atmosphere; The hydrogen flow rate in hydrogen plasma or hydrogen atmosphere is 50 sccm to 1000 sccm. The reaction temperature for the hydrogenation treatment is 500℃~900℃.

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