A GaN-based transistor and its manufacturing method and application

Abstract

The present invention discloses a GaN-based transistor and a manufacturing method and application thereof, belonging to the technical field of semiconductors. The GaN-based transistor comprises a substrate, an N-GaN layer, a U-GaN layer and an InGaN layer in sequence, and a source, a drain and a gate arranged on the InGaN layer; wherein the In component content of the InGaN layer is 1% to 2%; the InGaN layer has a P-type source region and a P-type drain region; the source and the drain are arranged on the P-type source region and the P-type drain region respectively, and the gate is arranged between the source and the drain and is spaced from the InGaN layer by a gate dielectric layer to construct a high-performance GaN pMOS device structure, and combined with a PN junction diode structure, realizes its application in GaN CMOS logic circuits. The manufacturing method of the present invention reduces the damage to the surface of the GaN device caused by ion implantation and activation, and improves the performance of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and in particular relates to a GaN-based transistor and a manufacturing method and application thereof. Background Art

[0002] As a third-generation semiconductor, GaN is the future development direction of solid-state microwave power devices and power electronic devices due to its advantages such as high electron saturation drift rate, wide bandgap, high temperature resistance, and high breakdown field strength. At present, the application structure of GaN in the power and RF industries is mainly GaN HEMT. The single structure cannot reflect the advantages of GaN devices in high frequency and high voltage. At present, the academic and industrial circles are basically studying n-channel devices. The realization of true GaN complementary logic integrated circuits requires p-channel devices, and it is difficult to realize high-performance p-channel devices. The existing p-channel device is mostly constructed by forming a p-type doped region in the n-GaN substrate, which has problems such as limited doping effect, low activation rate and material damage. It is difficult to form a GaN PMOS device structure with excellent performance, which limits the development and application of GaN CMOS logic circuits. Summary of the invention

[0003] In view of the deficiencies in the prior art, the present invention provides a GaN-based transistor and a manufacturing method and application thereof.

[0004] In order to achieve the above purpose, the technical solution of the present invention is:

[0005] A GaN-based transistor comprises, in order, a substrate, an N-GaN layer, a U-GaN layer and an InGaN layer, and a source electrode, a drain electrode and a gate electrode arranged on the InGaN layer; wherein the In component content of the InGaN layer is 1% to 2%; the InGaN layer has a P-type source region and a P-type drain region; the source electrode and the drain electrode are arranged on the P-type source region and the P-type drain region respectively, and the gate electrode is arranged between the source electrode and the drain electrode and is separated from the InGaN layer by a gate dielectric layer.

[0006] Optionally, the N-type doping concentration of the N-GaN layer is 1E18~3E19 cm -3 The thickness of the N-GaN layer is 1-5 μm, the thickness of the U-GaN layer is 2-4 μm, and the thickness of the InGaN layer is 200-400 nm.

[0007] Optionally, the intrinsic carrier concentration of the U-GaN layer is less than 5E17 cm -3 , the intrinsic carrier concentration of the InGaN layer outside the P-type source region and the P-type drain region is less than 1E17 cm -3 ; P-type source region and P-type drain region are doped with Mg, and the Mg doping concentration is 1E19~1E20 cm-3 .

[0008] Optionally, the channel length between the P-type source region and the P-type drain region is 200-1000 nm; the gate is located above the channel, with both ends exceeding the channel length by more than 0.5 μm and being more than 4 μm away from the source and drain.

[0009] Optionally, the gate dielectric layer is 10-30 nm thick; the gate dielectric layer material is an aluminum oxide layer, silicon nitride or silicon oxide.

[0010] Optionally, a back electrode is further included, wherein the back electrode is disposed on the etched mesa of the N-GaN layer and forms an ohmic contact with the N-GaN layer.

[0011] A method for manufacturing the above-mentioned GaN-based transistor comprises the following steps:

[0012] 1) Growing N-GaN layer, U-GaN layer and InGaN layer in sequence on the substrate;

[0013] 2) Forming a P-type source region and a P-type drain region in the InGaN layer through selective ion implantation and annealing activation;

[0014] 3) Depositing a gate dielectric layer and fabricating a P-type ohmic contact to form a source electrode and a drain electrode on the P-type source region and the P-type drain region, respectively;

[0015] 4) A gate is formed on the gate dielectric layer between the source and the drain.

[0016] Optionally, the growth temperature of the InGaN layer is greater than 800° C.; step 2) includes

[0017] 2.1) A first dielectric protective layer with a thickness of 20-40 nm is deposited on the InGaN layer, and Mg ions are selectively implanted with an energy of 15-40 KeV and an implantation dose of 1E13 cm -2 ~ 1E14 cm -2 ; forming a P-type source region and a P-type drain region in the InGaN layer, and then removing the first dielectric protective layer;

[0018] 2.2) A second dielectric protective layer with a thickness of 250-400 nm is deposited on the InGaN layer, and annealed in a nitrogen atmosphere at a temperature of 1100-1250° C. for 1-8 hours. After the annealing is completed, the second dielectric protective layer is removed.

[0019] Optionally, the first dielectric protection layer is SiN, and the second dielectric protection layer is a stack of 10-30 nm SiO2 and 250-350 nm SiN.

[0020] The In component content is 1%~2%, and more preferably about 1%-1.5%. A small amount of In can reduce the activation energy of Mg ion implantation in GaN, and the crystal quality of In-doped GaN at high temperature (800°C) is high. The annealing temperature of Mg-implanted GaN activation is reduced, and the activation efficiency is improved while ensuring the crystal quality, which can increase the mobility of pMOS and reduce the leakage of pMOS.

[0021] A semiconductor device, the epitaxial structure of which comprises a substrate, an N-GaN layer, a U-GaN layer and an InGaN layer in sequence, and is provided with a transistor region and a diode region, wherein the transistor region forms the above-mentioned GaN-based transistor; the InGaN layer in the diode region has an ion-implanted P-type junction region, a P electrode is provided on the P-type junction region, and an N electrode is provided on the etched table of the N-GaN layer in the diode region.

[0022] Optionally, a first dielectric layer is further provided on the diode region, and the first dielectric layer and the gate dielectric layer are provided on the same layer.

[0023] Optionally, the InGaN layer in the diode region also has at least one ion-implanted P-type field limiting ring region, and the P-type field limiting ring region is arranged outside the P-type junction region and the distance between the P-type junction region and the P-type junction region is 200~2000 nm; when it includes multiple P-type field limiting ring regions arranged at intervals, the distance between adjacent P-type field limiting ring regions is 200~1000 nm.

[0024] A method for manufacturing the semiconductor device as described above comprises:

[0025] 1) Grow N-GaN layer, U-GaN layer and InGaN layer in sequence on the substrate, and plan the transistor area and diode area;

[0026] 2) Forming a P-type source region, a P-type drain region and a P-type junction region in the InGaN layer through selective ion implantation and annealing activation, wherein the P-type source region and the P-type drain region are located in the transistor region, and the P-type junction region is located in the diode region;

[0027] 3) Depositing a dielectric layer and fabricating a P-type ohmic contact to form a source electrode and a drain electrode on the P-type source region and the P-type drain region, respectively, and forming a P electrode on the P-type junction region; wherein the dielectric layer serves as a gate dielectric layer in the transistor region and as a first dielectric layer in the diode region;

[0028] 4) performing mesa etching and fabricating an N-type ohmic contact on the etched mesa of the N-GaN layer to form an N electrode;

[0029] 5) A gate is formed on the gate dielectric layer between the source and the drain.

[0030] Furthermore, during the ion implantation in step 2), at least one P-type field limiting ring region is simultaneously formed outside the P-type junction region in the diode region.

[0031] An integrated circuit comprises the above-mentioned GaN-based transistor or the above-mentioned semiconductor device.

[0032] The beneficial effects of the present invention are:

[0033] Through ion implantation and epitaxial structure construction, a high-performance GaN pMOS device structure is produced and combined with a PN junction diode structure to realize its application in GaN CMOS logic circuits and can be applied to amplifiers and other fields.

[0034] The manufacturing method of the present invention improves the activation rate of GaN p-type selective doping while ensuring the reduction of annealing activation temperature, reduces the damage to the surface of GaN devices caused by ion implantation and activation, and improves the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic structural diagram of a GaN-based transistor of Example 1;

[0036] Figure 2(a) to Figure 2(f) A schematic diagram of the process of manufacturing a GaN-based transistor according to Example 1;

[0037] Figure 3 is a schematic structural diagram of a GaN-based transistor according to Example 2;

[0038] Figure 4 is a schematic structural diagram of a semiconductor device according to Embodiment 3;

[0039] Figure 5 is a schematic diagram of a top view of the semiconductor device of Example 3;

[0040] Figure 6(a) to Figure 6(g) A schematic diagram of the process of manufacturing a semiconductor device according to Embodiment 3;

[0041] Figure 7 This is an application circuit example of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION

[0042] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The various drawings of the present invention are only for illustration to make it easier to understand the present invention, and the specific proportions can be adjusted according to design requirements. The upper and lower relationships of the relative elements and the definitions of the front / back in the figures described in the text should be understood by those skilled in the art to refer to the relative positions of the components, so they can all be flipped to present the same components, which should all fall within the scope disclosed in this specification.

[0043] Example 1

[0044] refer to Figure 1 The GaN-based transistor of Example 1 has an epitaxial structure that includes a substrate 1, an N-GaN layer 2, a U-GaN layer 3 (an unintentionally doped GaN layer), and an InGaN layer 4, as well as a gate dielectric layer 5, a source S, a drain D, and a gate G disposed on the InGaN layer 4. The substrate 1 can be made of, for example, Si, SiC, sapphire, a self-supporting substrate, etc.; the N-type doping concentration of the N-GaN layer 2 is 1E18~3E19cm -3 , for example, in 5×10 18 cm -3 ~1×10 19 cm -3 The intrinsic carrier concentration of the U-GaN layer 3 is less than 5E17 cm -3 , more preferably, the intrinsic carrier concentration of the U-GaN layer 3 is less than 5E16 cm -3 , thickness 2~4μm; the intrinsic carrier concentration of InGaN layer 4 is less than 1E17 cm -3 , more preferably, the intrinsic carrier concentration of the InGaN layer 4 is less than 5E16 cm -3 , with a thickness of 200-400 nm and an In component content of 1%-2%, more preferably 1%-1.5%. The InGaN layer 4 has a P-type source region a and a P-type drain region b implanted with Mg ions, and the ion implantation dose is 1E13 cm -2 ~ 1E14 cm -2 The P-type source region a and P-type drain region b are doped with Mg, and the Mg doping concentration is 1E19~1E20 cm -3 The source S and the drain D are respectively arranged on the P-type source region a and the P-type drain region b and form ohmic contacts. The source S and the drain D are arranged opposite to each other. The gate G is arranged between the source S and the drain D and is separated from the InGaN layer 4 by a gate dielectric layer 5. The gate dielectric layer 5 is Al2O3 with a thickness of 10 to 30 nm.

[0045] The following references Figure 2(a) to Figure 2(f) A method for manufacturing the above-mentioned GaN-based transistor is described.

[0046] Referring to FIG. 2 (a), an N-GaN layer 2, a U-GaN layer 3 and an InGaN layer 4 are sequentially grown on a substrate 1 by an epitaxial growth process, wherein the growth temperature of the InGaN layer 4 is greater than 800°C, preferably 800-900°C, and a higher growth temperature is used to ensure the crystal growth quality of InGaN and reduce the incorporation of impurity defects, and the In component is preferably 1%-1.5%, and the thickness is 300 nm for example. The U-GaN layer 3 is provided to improve the breakdown performance of the pMOS and reduce the gate electron injection effect.

[0047] Referring to FIG2(b), a 30 nm thick SiN is deposited on the surface of the InGaN layer 4 by ICPCVD process as the first dielectric protection layer V1, and a P-type source region a and a P-type drain region b are formed by selective Mg ion implantation process, with an ion implantation energy of 15-40 KeV. For example, an ion implantation energy of 20 KeV and a dose of 6E13 cm -2 , the injection depth is the thickness of the InGaN layer 4, wherein the first dielectric protection layer V1 acts as a buffer. Under this condition, the damage to GaN is small, the defects generated are small, and the hole compensation after the p-type activation is small. The widths of the P-type source region a and the P-type drain region b are, for example, 100~200 μm, 150 μm for example, and the spacing, i.e., the channel length, is 200~1000 nm, 1 μm for example. The channel distance is shortened as much as possible on the basis of avoiding the short channel effect and considering the lithography accuracy. This is because the mobility of GaN holes is low, and the activation rate of injection activation is currently not as high as that of epitaxy. Shortening the distance enhances its gate control effect. The area selection process can be implemented in the form of a patterned shielding layer, etc. After the ion implantation is completed, the first dielectric protection layer V1 is removed.

[0048] Referring to Figure 2 (c), a 20 nm ALD-grown SiO2 and a 300 nm LPCVD-grown SiN stack are sequentially deposited on the surface of the InGaN layer 4 as the second dielectric protection layer V2, and annealed in a nitrogen atmosphere at a temperature of 1100-1250°C for 1-8 hours. The second dielectric protection layer V2 is used to protect GaN from being corroded and decomposed at high temperatures during annealing, and the removal process has little effect on GaN. A small amount of In doping in the InGaN layer 4 can reduce the activation energy of Mg ion implantation into GaN, thereby improving the activation efficiency while ensuring high crystal quality. For example, the annealing condition parameters are: temperature 1250°C, N2 atmosphere, time 1h, normal pressure. Under these conditions, the damage to the injected lattice can be effectively repaired and the holes can be activated. At the same time, this is also the highest temperature that GaN can withstand without decomposition under normal pressure, and has a high activation rate. In another embodiment, the annealing condition parameters are: 1100°C, N2 atmosphere, 8h, normal pressure. Under these conditions, the lower temperature and longer annealing time can reduce the damage to the surface caused by high temperature, repair the damage to the injected lattice and activate the holes. Thus, a high-performance semiconductor structure is obtained to meet the needs of the device. After the annealing process is completed, the second dielectric protective layer V2 is removed.

[0049] Referring to Figure 2 (d), a p-type ohmic contact is prepared, using Ni / Au=10 / 10 nm metal, annealing is performed in an oxygen atmosphere, the annealing temperature is 550°C, the annealing time is 10 min, and a source S and a drain D are formed on the P-type source region a and the P-type drain region b, respectively. On the side close to the channel, the edges of the source S and the drain D are retracted relative to the edges of the P-type source region a and the P-type drain region b to leave space for the gate.

[0050] Referring to Figure 2 (e), 20 nm Al2O3 is deposited as the gate dielectric layer 5 by the ALD process, the growth temperature is 350°C, and the Al source is synthesized by reaction with ozone. The gate dielectric layer 5 covers the surface of the source S and the drain D at the same time. In the subsequent process, holes can be selectively opened on the source S and the drain D as needed for external connection. Al2O3 is used as the gate dielectric layer to regulate the threshold of pMOS and as the gate dielectric of the MOS structure. In the process of mass production of devices on the wafer, the devices on the wafer can be isolated by insulation injection after this step. In other embodiments, the gate dielectric layer 5 can be silicon nitride or silicon oxide.

[0051] Referring to FIG2(f), a gate metal is evaporated on the gate dielectric layer 5 between the source S and the drain D, using Ni / Au=50 / 150nm, and annealed at 400°C for 5 minutes to reduce gate leakage, thereby forming a gate G and forming the final GaN p-MOS device. The two sides of the gate G exceed the channel length by more than 0.5μm and are more than 4μm away from the source S and the drain D. The two sides of the gate G overlap above the P-type source region a and the P-type drain region b, so that the gate's control over the channel is increased and the turn-on voltage is changed.

[0052] In addition, in other embodiments, the gate dielectric layer 5 may be deposited first, the gate dielectric layer 5 located above the P-type source region a and the P-type drain region b may be opened, and then the P ohmic contact may be prepared.

[0053] Example 2

[0054] refer to Figure 3 , the GaN-based transistor of Example 2 is different from Example 1 in that it also includes mesa etching, the etching depth reaches the surface of the N-GaN layer 2, and an N-type ohmic contact is made on the N-GaN layer 2 to form a back electrode 6, and the back electrode 6 serves as an n-type contact layer for regulating the threshold voltage, thereby preparing a triode device. The metal of the back electrode 6 is Ti / Al / Ni / Au=20 / 20 / 50 / 150 nm. Due to the heavy doping of the N-GaN layer 2, the N-type ohmic can form an ohmic contact without annealing. The steps of mesa etching and making the back electrode 6 can be performed before the preparation of the gate metal, or adjusted according to actual needs. The distance between the back metal 6 and the edge of the mesa etching is preferably 20~30 μm, which can achieve better regulation performance.

[0055] Example 3

[0056] refer to Figure 4 and Figure 5 The semiconductor device of Example 3 has an epitaxial structure which includes a substrate 1, an N-GaN layer 2, a U-GaN layer 3 and an InGaN layer 4 in sequence, and is provided with a transistor region A and a diode region B. The transistor formed in the transistor region is a pMOS transistor, and the diode formed in the diode region is a PN junction diode. The arrangement of the epitaxial structure is the same as that of Example 1, and a GaN-based transistor structure as in Example 1 is formed in the transistor region A. In the diode region, the InGaN layer 4 has an ion-implanted P-type junction region c and a P-type field limiting ring region d, the P-type field limiting ring region d is arranged outside the P-type junction region c, a P-electrode 7 is arranged on the P-type junction region c, and an N-electrode 8 is arranged on the etched table of the N-GaN layer 2 of the diode region B. The P-type junction region c and the P-type field limiting ring region d have, for example, the same ion implantation dose as the P-type source region a and the P-type drain region b, and the Mg ion implantation dose is 1E13 cm -2 ~ 1E14 cm -2 A first dielectric layer 9 is disposed on the InGaN layer 4 of the diode region B. The first dielectric layer 9 can be disposed on the same layer as the gate dielectric layer 5 .

[0057] The following references Figure 6(a) to Figure 6(g) A method for manufacturing the above-mentioned GaN-based transistor is described.

[0058] Referring to FIG6 (a), an N-GaN layer 2, a U-GaN layer 3 and an InGaN layer 4 are sequentially grown on a substrate 1 by an epitaxial growth process, wherein the growth temperature of the InGaN layer 4 is greater than 800°C, the In component is preferably 1% to 1.5%, and the thickness is 300 nm, for example. A transistor region A and a diode region B are planned.

[0059] Referring to FIG6(b), a 30 nm thick SiN is deposited on the surface of the InGaN layer 4 by ICPCVD process as the first dielectric protection layer V1, and a P-type source region a, a P-type drain region b, a P-type junction region c and a P-type field limiting ring region d are formed by selective Mg ion implantation process, and the ion implantation energy is 15-40 KeV. For example, the ion implantation energy is 20 KeV and the dose is 6E13 cm -2 , the implantation depth is the thickness of the InGaN layer 4. The P-type source region a and the P-type drain region b are located in the transistor region A, and the structure can refer to Example 1. The P-type junction region c and the P-type field limiting ring region d are located in the diode region B, wherein the spacing between the P-type junction region and the P-type field limiting ring region is 200~2000 nm. When there are multiple P-type field limiting ring regions d, the spacing between adjacent P-type field limiting ring regions d is 200~1000 nm. After the ion implantation is completed, the first dielectric protective layer V1 is removed.

[0060] Referring to FIG. 6 (c), a 20 nm ALD-grown SiO2 and a 300 nm LPCVD-grown SiN stack are sequentially deposited on the surface of the InGaN layer 4 as the second dielectric protective layer V2, and annealed in a nitrogen atmosphere at a temperature of 1100-1250°C and an annealing time of 1-8 hours. For example, the annealing condition parameters are: temperature 1250°C, N2 atmosphere, time 1 hour, and normal pressure. Under these conditions, the injection lattice damage can be effectively repaired and the holes can be activated. At the same time, this is also the highest temperature that GaN can withstand without decomposition under normal pressure, and has a high activation rate. In another embodiment, the annealing condition parameters are: 1100°C, N2 atmosphere, 8 hours, and normal pressure. Under these conditions, a lower temperature and a longer annealing time can reduce the damage to the surface caused by high temperature, repair the injection lattice damage, and activate the holes. After the annealing process is completed, the second dielectric protective layer V2 is removed.

[0061] Referring to FIG. 6 (d), a p-type ohmic contact is prepared using Ni / Au=10 / 10 nm metal, and annealing is performed in an oxygen atmosphere at a temperature of 550°C for 10 min. A source S and a drain D are formed on the P-type source region a and the P-type drain region b, respectively, and a P electrode 7 is formed on the P-type junction region c.

[0062] Referring to Fig. 6 (e), a 20 nm Al2O3 dielectric layer V3 is deposited by the ALD process, which serves as the gate dielectric layer 5 in the gate region of the transistor region A and as the first dielectric layer 9 on the surface of the InGaN layer 4 in the diode region B. The dielectric layer V3 covers the surfaces of the source S, the drain D and the P electrode 7 at the same time. In the subsequent process, holes can be selectively opened on the source S, the drain D and the P electrode 7 as needed to facilitate external connection.

[0063] Referring to FIG6(f), mesa etching is performed to a depth of the surface of the N-GaN layer 2, and an N-type ohmic contact is made on the etched mesa of the diode region B to form an N electrode 8. The metal is Ti / Al / Ni / Au=20 / 20 / 50 / 150 nm. Due to heavy doping, an N-type ohmic contact can be formed without annealing.

[0064] 6( g ), a gate metal is evaporated on the gate dielectric layer 5 between the source S and the drain D, using Ni / Au=50 / 150nm, and annealed at 400° C. for 5 min to reduce gate leakage, thereby forming a gate G.

[0065] In addition, according to actual needs such as device protection, a passivation layer can be added to the structure or on the surface of the structure. This is a conventional technology.

[0066] The semiconductor device mentioned above simultaneously prepares a pMOS transistor and a PN junction diode, arranges and connects the devices according to the circuit design, and can be used to combine and connect with other device structures to realize a GaN CMOS logic circuit.

[0067] The semiconductor device of the present invention can be applied to an integrated circuit. In an application circuit in which the integrated circuit includes both a triode and a diode, for example, Figure 7 In the XOR gate logic circuit, if the levels of the two inputs A and B are different, the output is a high level 1 and the transistor is turned on; if the levels of the two inputs A and B are the same, the output is a low level 0 and the transistor is not turned on.

[0068] The above embodiments are only used to further illustrate a GaN-based transistor and its manufacturing method and application of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention fall within the protection scope of the technical solution of the present invention.

Claims

1. A GaN-based transistor, characterized in that: The invention comprises, in order, a substrate, an N-GaN layer, a U-GaN layer and an InGaN layer, and a source electrode, a drain electrode and a gate electrode arranged on the InGaN layer; wherein the In component content of the InGaN layer is 1% to 2%; the InGaN layer has an ion-implanted P-type source region and an ion-implanted P-type drain region, and the intrinsic carrier concentration of the InGaN layer outside the P-type source region and the P-type drain region is less than 1E17 cm -3 The source and drain are respectively arranged on the P-type source region and the P-type drain region, and the gate is arranged between the source and the drain and is separated from the InGaN layer by a gate dielectric layer.

2. The GaN-based transistor according to claim 1, characterized in that: The N-type doping concentration of the N-GaN layer is 1E18~3E19cm -3 ; The thickness of the N-GaN layer is 1~5 μm, the thickness of the U-GaN layer is 2~4 μm, and the thickness of the InGaN layer is 200~400 nm.

3. The GaN-based transistor according to claim 1, characterized in that: The intrinsic carrier concentration of the U-GaN layer is less than 5E17 cm -3 The P-type source region and the P-type drain region are doped with Mg, and the Mg doping concentration is 1E19~1E20 cm -3 .

4. The GaN-based transistor according to claim 1, characterized in that: The channel length between the P-type source region and the P-type drain region is 200-1000 nm; the gate is located above the channel, with both ends exceeding the channel length by more than 0.5 μm and being more than 4 μm away from the source and drain.

5. The GaN-based transistor according to claim 1, characterized in that: The gate dielectric layer has a thickness of 10-30 nm; the gate dielectric layer material is an aluminum oxide layer, silicon nitride or silicon oxide.

6. The GaN-based transistor according to claim 1, characterized in that: The invention also includes a back electrode, which is arranged on the etched mesa of the N-GaN layer and forms an ohmic contact with the N-GaN layer.

7. A method for manufacturing a GaN-based transistor according to any one of claims 1 to 6, characterized in that: The following steps are involved: 1) Growing N-GaN layer, U-GaN layer and InGaN layer in sequence on the substrate; 2) Forming a P-type source region and a P-type drain region in the InGaN layer through selective ion implantation and annealing activation; 3) Depositing a gate dielectric layer and fabricating a P-type ohmic contact to form a source electrode and a drain electrode on the P-type source region and the P-type drain region, respectively; 4) A gate is formed on the gate dielectric layer between the source and the drain.

8. The method for manufacturing a GaN-based transistor according to claim 7, characterized in that: The growth temperature of the InGaN layer is greater than 800°C; step 2) comprises 2.1) A first dielectric protective layer with a thickness of 20-40 nm is deposited on the InGaN layer, and Mg ions are selectively implanted with an energy of 15-40 KeV and an implantation dose of 1E13 cm -2 ~ 1E14 cm -2 ; forming a P-type source region and a P-type drain region in the InGaN layer, and then removing the first dielectric protective layer; 2.2) A second dielectric protective layer with a thickness of 250-400 nm is deposited on the InGaN layer, and annealed in a nitrogen atmosphere at a temperature of 1100-1250 °C for 1-8 h. After the annealing is completed, the second dielectric protective layer is removed.

9. The method for manufacturing a GaN-based transistor according to claim 8, characterized in that: The first dielectric protection layer is SiN, and the second dielectric protection layer is a stack of 10-30 nm SiO2 and 250-350 nm SiN.

10. A semiconductor device, characterized in that: The epitaxial structure of the semiconductor device includes a substrate, an N-GaN layer, a U-GaN layer and an InGaN layer in sequence, and is provided with a transistor region and a diode region. The transistor region forms the GaN-based transistor according to any one of claims 1 to 6; the InGaN layer in the diode region has an ion-implanted P-type junction region, a P electrode is provided on the P-type junction region, and an N electrode is provided on the etched table of the N-GaN layer in the diode region.

11. The semiconductor device according to claim 10, wherein: A first dielectric layer is also disposed on the diode region, and the first dielectric layer and the gate dielectric layer are disposed on the same layer.

12. The semiconductor device according to claim 10, wherein: The InGaN layer in the diode region also has at least one P-type field limiting ring region implanted with ions, and the P-type field limiting ring region is arranged outside the P-type junction region and the distance between the P-type junction region and the P-type junction region is 200~2000 nm; when it includes multiple P-type field limiting ring regions arranged at intervals, the distance between adjacent P-type field limiting ring regions is 200~1000 nm.

13. A method for manufacturing a semiconductor device according to claim 10, characterized in that: 1) Grow N-GaN layer, U-GaN layer and InGaN layer in sequence on the substrate, and plan the transistor area and diode area; 2) Forming a P-type source region, a P-type drain region and a P-type junction region in the InGaN layer through selective ion implantation and annealing activation, wherein the P-type source region and the P-type drain region are located in the transistor region, and the P-type junction region is located in the diode region; 3) Depositing a dielectric layer and fabricating a P-type ohmic contact to form a source electrode and a drain electrode on the P-type source region and the P-type drain region, respectively, and forming a P electrode on the P-type junction region; in The dielectric layer serves as a gate dielectric layer in the transistor region and as a first dielectric layer in the diode region; 4) performing mesa etching and fabricating an N-type ohmic contact on the etched mesa of the N-GaN layer to form an N electrode; 5) A gate is formed on the gate dielectric layer between the source and the drain.

14. An integrated circuit, characterized in that: Comprising the GaN-based transistor according to claim 1 or the semiconductor device according to claim 10.

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