A topological circuit for a converter with a wide voltage range

Abstract

The present invention provides a topology circuit for a converter with a wide voltage range, characterized in that the specific structure includes: a half-bridge drive circuit and a QR control circuit; the half-bridge drive circuit includes a first transistor (Q1), a second transistor (Q2), a first DC blocking capacitor (C1), a second DC blocking capacitor (C2), a main transformer (T1), a first secondary-side rectifier diode (D2), a second secondary-side rectifier diode (D3), an energy storage inductor (L1), and a smoothing capacitor (C4); the QR control circuit includes a control chip (U1), the control chip U1 is connected to the half-bridge drive circuit and is externally connected to a measurement chip (U2). The topology circuit for a converter with a wide voltage range of the present invention can achieve the ability of ZVS soft switching while adjusting the wide voltage range, thereby improving the application range of the converter and expanding the adaptability of the topology circuit in applications.

Description

Technical Field

[0001] The invention relates to a topology circuit for a converter with a wide voltage range. Background Art

[0002] Quasi-resonant (QR) technology is typically used only in flyback topologies and their derivatives (such as boost and buck-boost). Its principle is that after the energy stored in the main transformer (energy storage inductor) is released and transferred within a cycle, the topological inductance and parasitic capacitance (primarily the MOS output junction capacitance (coss)) will generate a voltage oscillation between the drain and source of the topological switch MOS due to underdamping, with the bus voltage as the center line. The voltage valley of this oscillation is detected to trigger the MOS turn-on time for the next switching cycle, ensuring that the MOS turns on at the lowest drain-source voltage (Vds). This achieves a near-zero voltage turn-on (ZVS) effect, thereby reducing the voltage / current combined losses when the MOS turns on.

[0003] ZVS is a forced conduction technology that uses high-frequency plasma to create a high-current path, enabling current to flow from one device to another. In a ZVS system, a flyback transformer (often referred to as a ZVS transformer) is used to generate the high-frequency current. When power is input to the ZVS transformer, it generates a high-frequency, high-voltage sine wave. When this sine wave is applied to the two terminals of another circuit (often referred to as the "load circuit"), it generates high-frequency plasma, enabling current to flow from one terminal to the other.

[0004] ZVS technology can be used in many different applications, such as power tools, heaters, and lighting. Its advantage is that it can provide high current output while keeping the current flow efficient.

[0005] Because a flyback converter relies on an energy storage inductor to store energy during the Ton period of the switching cycle and then transfer and output energy during the Toff period, and because the transformer (inductor) flux operates only in the first quadrant (unidirectional magnetization), core utilization is low. These two factors determine that the flyback topology is only suitable for low-power converters.

[0006] Another common switching power supply topology, the half-bridge converter, is a derivative of the forward topology. Because this topology transfers energy throughout the entire switching cycle, both during the Ton and Toff periods, and the transformer's flux operates in bidirectional magnetization (first and third order), resulting in high core utilization, the half-bridge topology is often suitable for high-power converter designs. However, when using PWM (pulse-width modulation) control, traditional half-bridge topologies struggle to achieve ZVS (zero-voltage switching) to reduce switching losses in the switching elements. Dedicated ZVS half-bridge topologies, such as the common LLC (LLC) topology, can only be controlled using a fixed 50% duty cycle (PFM) frequency modulation (FFM). This PFM control has the obvious disadvantage of being unable to achieve a wide voltage regulation range. This significantly limits the LLC topology's application. Summary of the Invention

[0007] In view of this, the present invention provides a topology circuit for a converter with a wide voltage range, which realizes voltage adjustment in a wide voltage range and ZVS soft switching by combining QR technology and traditional board bridge technology.

[0008] The present invention provides a topology circuit for a converter with a wide voltage range, the specific structure of which includes:

[0009] A half-bridge drive circuit and a QR control circuit; the half-bridge drive circuit includes a first transistor Q1, a second transistor Q2, a first blocking capacitor C1, a second blocking capacitor C2, a main transformer T1, a first secondary-side rectifier diode D2, a second secondary-side rectifier diode D3, an energy storage inductor L1, and a smoothing capacitor C4; the first transistor Q1 and the second transistor Q2 are respectively connected to the same side of the main transformer T1 and are respectively set as the upper and lower tubes of the half-bridge drive circuit; the first blocking capacitor C1 and the second blocking capacitor C2 are respectively connected in parallel with the first transistor Q1 and the second transistor Q2; the first secondary-side rectifier diode D2 and the second secondary-side rectifier diode D3 are connected to the other side of the main transformer T1, and the energy storage inductor L1 and the smoothing capacitor C4 are connected in parallel to each other and in series on one side of the first secondary-side rectifier diode D2;

[0010] The QR control circuit includes a control chip U1, which is connected to the half-bridge drive circuit and is also externally connected to a measurement chip U2;

[0011] The measuring chip U2 is connected to the half-bridge driving circuit and the QR control circuit, samples and measures the PWM-P driving signal sent by the control chip U1, and sets a dead time Td.

[0012] Furthermore, isolation gate drivers are connected to the circuits of the first transistor Q1 and the second transistor Q2, respectively. The first driver U3 is connected to the first transistor Q1, and the second driver U4 is connected to the second transistor Q2.

[0013] Furthermore, the QR control circuit is provided with an open collector output OC1, which is externally connected to the output terminal.

[0014] Furthermore, the energy storage inductor L1 and the smoothing capacitor C4 are externally connected to the output end.

[0015] Furthermore, the control chip U1 outputs a single-ended driving signal PWM-P when in operation.

[0016] Furthermore, the measurement chip immediately sends out a pulse width signal H0 having the same width as the PWM-P signal after the dead time Td.

[0017] Furthermore, a bootstrap circuit is connected to the first driver U3 to provide an operating voltage for the first driver U3.

[0018] Furthermore, the bootstrap circuit includes a bootstrap resistor R5, a bootstrap diode D1 and a bootstrap capacitor C3; the three are connected in series and in parallel to the first driver U3.

[0019] Furthermore, the energy storage inductor L1 operates in an inductor current discontinuous mode.

[0020] Furthermore, the control chip U1 has a cycle skipping detection function, and can select the valley bottom of the damped oscillation at which to turn on according to the duty cycle and load conditions. Beneficial effects

[0021] According to the present invention, a topology circuit for a converter with a wide voltage range can achieve the capability of ZVS soft switching while adjusting the wide voltage range, thereby improving the application range of the converter and expanding the adaptability of the topology circuit in application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments are briefly introduced below.

[0023] The drawings described below only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0024] In the attached figure:

[0025] Figure 1 shows a circuit schematic diagram according to an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of a working signal waveform according to the present invention is shown;

[0027] Reference Signs List

[0028] Q1. First transistor, Q2. Second transistor, C1. First DC blocking capacitor, C2. Second DC blocking capacitor, T1. Main transformer, D2. First secondary-side rectifier diode, D3. Second secondary-side rectifier diode, L1. Energy storage inductor, C4. Smoothing capacitor, U1. Control chip, U2. Measurement chip, U3. First driver, U4. Second driver, R5

[0029] .Bootstrap resistor, D1.Bootstrap diode, C3.Bootstrap capacitor. DETAILED DESCRIPTION

[0030] In order to make the purpose, scheme and advantages of the technical solution of the present invention more clear, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of specific embodiments of the present invention. Unless otherwise specified, the terms used herein have the common meanings in the art. The same reference numerals in the drawings represent the same components.

[0031] like Figure 1 As shown, in one embodiment:

[0032] The present invention provides a topology circuit for a converter with a wide voltage range, comprising: a half-bridge drive circuit and a QR control circuit; the half-bridge drive circuit comprises a first transistor Q1, a second transistor Q2, a first DC blocking capacitor C1, a second DC blocking capacitor C2, a main transformer T1, a first secondary-side rectifier diode D2, a second secondary-side rectifier diode D3, an energy storage inductor L1, and a smoothing capacitor C4; the first transistor Q1 and the second transistor Q2 are respectively connected to the same side of the main transformer T1 and serve as the upper and lower transistors of the half-bridge drive circuit; the first DC blocking capacitor C1 and the second DC blocking capacitor C2 are respectively connected in parallel with the first transistor Q1 and the second transistor Q2; the first secondary-side rectifier diode D2 and the second secondary-side rectifier diode D3 are connected to the other side of the main transformer T1, the energy storage inductor L1 and the smoothing capacitor C4 are connected in parallel with each other and in series with one side of the first secondary-side rectifier diode D2;

[0033] The QR control circuit includes a control chip U1, which is connected to the half-bridge drive circuit and is also externally connected to a measurement chip U2;

[0034] The measurement chip U2 is connected to the half-bridge drive circuit and the QR control circuit, and uses a high-speed single-chip microcomputer (model AMP32F051K) to sample and measure the PWM-P drive signal sent by the control chip U1, and set a dead time Td.

[0035] Furthermore, isolation gate drivers are connected to the circuits of the first transistor Q1 and the second transistor Q2, respectively. The first driver U3 is connected to the first transistor Q1, and the second driver U4 is connected to the second transistor Q2.

[0036] Furthermore, the QR control circuit is provided with an open collector output OC1, which is externally connected to the output terminal.

[0037] Furthermore, the energy storage inductor L1 and the smoothing capacitor C4 are externally connected to the output end.

[0038] Furthermore, the control chip U1 outputs a single-ended driving signal PWM-P when in operation.

[0039] Furthermore, the measurement chip U2 immediately sends out a pulse width signal H0 having the same width as the PWM-P signal after the dead time Td.

[0040] Furthermore, a bootstrap circuit is connected to the first driver U3 to provide an operating voltage for the first driver U3.

[0041] Furthermore, the bootstrap circuit includes a bootstrap resistor R5, a bootstrap diode D1 and a bootstrap capacitor C3; the three are connected in series and in parallel to the first driver U3.

[0042] Furthermore, the energy storage inductor L1 operates in an inductor current discontinuous mode.

[0043] Furthermore, the control chip U1 has a cycle skipping detection function, and can select the valley bottom of the damped oscillation at which to turn on according to the duty cycle and load conditions.

[0044] The working principle of this embodiment is as follows Figure 2 As shown:

[0045] The phase of the pulse width PWM-P emitted by the control chip U1 in the QR circuit is in phase with the drive signal GL of the second transistor Q2 in the lower tube. This is to ensure that the second transistor Q2 is turned on first during startup. The primary chip power supply system P+12V is provided by the bootstrap resistor R5 and the bootstrap diode D1, which charges the bootstrap capacitor C3 through the lower tube circuit to establish the power supply VB required by the driver U3 of the upper tube.

[0046] ① At time T1: GL is high, and Q2 turns on. Because the drain potential VS before Q2 turns on is equal to the neutral voltage VZ, Q2 inevitably turns on under non-ZVS conditions. When Q2 turns on, D3 conducts, transferring energy to the output. At the same time, due to the transformer's primary winding magnetizing inductance, some energy is stored in the inductor, which is not transferred to the output.

[0047] At time T2: GL goes low, Q2 turns off, and the energy stored in the magnetizing inductor is released, causing the VS voltage to reverse. Due to the effect of the MOS's output capacitance (coss), the VS voltage reaches the bus voltage (VBus) after a brief charging period. The inductor energy continues to flow through the body diode of Q1 to the bus. At this point, Q1's drain-source voltage is clamped to a level equal to the body diode's forward voltage drop (VF), which is approximately zero voltage. T2 is programmed by U2 based on the magnetizing inductor and the MOS's coss parameters. This time is also referred to as the dead time (Td) mentioned above.

[0048] ③ At time T3: Because Q1's drain-source voltage VDS is zero, GH outputs a high level, achieving zero voltage turn-on (ZVS) for Q1. After Q1 turns on, D2 conducts, transferring energy to the output. Simultaneously, some energy is stored in the primary winding's magnetizing inductance, which is not transferred to the output.

[0049] ④ At time T4: GH outputs a low level, and Q1 turns off. Similarly, the inductor energy is released, the VS voltage reverses, and freewheeling current flows through the body diode of the lower transistor, Q2. If a dead time Td is set at time T4 and Q2 is turned on immediately afterward, the same as in conventional LLC control mode can be achieved, achieving zero voltage on both the upper and lower transistors. However, PWM modulation is required to achieve a wide voltage regulation rate. At time T4, the timing of Q1's turn-on is determined by the converter's input and output conditions and ultimately by the control loop. During this period, the valley detection mechanism of the QR control chip determines when Q1 will turn on in the next cycle.

[0050] Finally, it should be noted that when describing the positions of various components and the matching relationships between them, the present invention usually takes one / a pair of components as an example. However, those skilled in the art should understand that such positions, matching relationships, etc. are also applicable to other components / other pairs of components.

[0051] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention. The scope of protection of the present invention is determined by the appended claims.

Claims

1. A topology circuit for a converter with a wide voltage range, characterized in that: The specific structure includes: A half-bridge drive circuit and a QR control circuit; the half-bridge drive circuit comprises a first transistor (Q1), a second transistor (Q2), a first DC blocking capacitor (C1), a second DC blocking capacitor (C2), a main transformer (T1), a first secondary-side rectifier diode (D2), a second secondary-side rectifier diode (D3), an energy storage inductor (L1) and a smoothing capacitor (C4); the first transistor (Q1) and the second transistor (Q2) are respectively connected to the same side of the main transformer (T1) and are respectively set as the upper tube and the lower tube of the half-bridge drive circuit; the first DC blocking capacitor (C1) and the second DC blocking capacitor (C2) are respectively connected in parallel with the first transistor (Q1) and the second transistor (Q2); the first secondary-side rectifier diode (D2) and the second secondary-side rectifier diode (D3) are connected to the other side of the main transformer (T1), and the energy storage inductor (L1) and the smoothing capacitor (C4) are connected in parallel with each other and in series with one side of the first secondary-side rectifier diode (D2); The QR control circuit includes a control chip (U1), the control chip U1 is connected to the half-bridge drive circuit and is externally connected to a measurement chip (U2); The control chip (U1) outputs a single-ended drive signal PWM-P when in operation; The measuring chip (U2) is connected to the half-bridge driving circuit and the QR control circuit, samples and measures the PWM-P driving signal sent by the control chip (U1), and sets a dead time Td; The measuring chip (U2) immediately sends out a pulse width signal H0 having the same width as the PWM-P signal after the dead time Td.

2. A topology circuit for a converter with a wide voltage range according to claim 1, characterized in that: Isolation gate drivers are respectively connected to the circuits of the first transistor (Q1) and the second transistor (Q2), the first driver (U3) is connected to the first transistor (Q1), and the second driver (U4) is connected to the second transistor (Q2).

3. The topology circuit for a converter with a wide voltage range according to claim 1, characterized in that: The QR control circuit is provided with an open collector output (OC1) connected to the output terminal.

4. The topology circuit for a converter with a wide voltage range according to claim 1, characterized in that: The energy storage inductor (L1) and the smoothing capacitor (C4) are externally connected to the output end.

5. The topology circuit for a converter with a wide voltage range according to claim 2, characterized in that: The first driver (U3) is connected to a bootstrap circuit to provide an operating voltage for the first driver (U3).

6. The topology circuit for a converter with a wide voltage range according to claim 5, characterized in that: The bootstrap circuit comprises a bootstrap resistor (R5), a bootstrap diode (D1) and a bootstrap capacitor (C3); the three are connected in series and in parallel to the first driver U3.

7. The topology circuit for a converter with a wide voltage range according to claim 1, characterized in that: The energy storage inductor (L1) operates in an inductor current discontinuous mode.

8. The topology circuit for a converter with a wide voltage range according to claim 1, characterized in that: The control chip (U1) has a skip cycle detection function and can select the valley bottom of the damped oscillation at which it is turned on according to the duty cycle and load conditions.

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