Data low-latency transceiving method and apparatus, network device, and storage medium

Abstract

Embodiments of the present disclosure relate to a data low-latency transceiver method, device, network equipment and storage medium. The low-latency transceiver comprises: parsing a received message in a pipeline manner at a MAC layer of the low-latency transceiver to obtain a frame detection sequence of the received message; in response to the frame detection sequence being inconsistent with a check sequence, updating the frame detection sequence of the received message to a target sequence, and forwarding the updated received message; and the target sequence is different from at least one bit of the check sequence. In the embodiment, the message is parsed in the pipeline manner without forwarding the message after receiving the whole frame message, which can reduce the delay of forwarding the message and is conducive to meeting the needs of business scenarios.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of signal processing, and particularly relates to a data low-latency transceiving method and device, a network device and a storage medium. BACKGROUND

[0002] Some service scenarios require high data transmission efficiency, such as securities quantitative trading, and therefore require network devices such as low-latency switches.

[0003] Taking a low-latency switch as an example, the existing solution usually uses a Field-Programmable Gate Array (FPGA) to implement the low-latency switch.

[0004] In actual application, the FPGA device has a large message transceiving delay and cannot meet the requirements of the above service scenarios. SUMMARY

[0005] The present disclosure provides a data low-latency transceiving method and device, a network device and a storage medium to solve the problems of the related art.

[0006] According to a first aspect of an embodiment of the present disclosure, a data low-latency transceiving method is provided, which is suitable for a low-latency transceiver, and the method comprises the following steps.

[0007] The MAC layer of the low-latency transceiver adopts a Pipeline mode to analyze a received message, and obtains a frame detection sequence of the received message.

[0008] In response to the frame detection sequence being inconsistent with a check sequence, the frame detection sequence of the received message is updated to a target sequence, and the updated received message is forwarded; the target sequence is different from at least one bit of the check sequence.

[0009] Optionally, the method further comprises the following steps.

[0010] The updated received message is sent to a peer device after logical processing, and the peer device discards the updated received message when detecting the target sequence in the received message.

[0011] Optionally, the method further comprises the following steps.

[0012] The MAC layer of the low-latency transceiver adopts a Pipeline mode to process a sent message, and a preset control code is added to the sent message during the Pipeline mode processing, and a coded sent message is obtained.

[0013] Optionally, the method further comprises the following steps.

[0014] The scrambled sending message is processed to obtain a second length sending message;

[0015] The second length sending message is converted in length to obtain a first length sending message;

[0016] The first length sending message is processed logically to obtain a receiving message to be forwarded.

[0017] Optionally, the method further comprises:

[0018] The first length receiving message is obtained;

[0019] The receiving message is aligned with the message header according to the position information in the message header of the receiving message to obtain a second length receiving message; the second length is greater than the first length;

[0020] The second length receiving message is processed to obtain a data block type;

[0021] The message payload of the receiving message is obtained and forwarded according to the data block type.

[0022] According to a second aspect of the embodiments of the present disclosure, a data low latency transceiver device is provided, and the device comprises:

[0023] A detection sequence acquisition module is configured to parse a receiving message in a MAC layer of the low latency transceiver in a Pipeline mode to obtain a frame detection sequence of the receiving message;

[0024] An updated message acquisition module is configured to update the frame detection sequence of the receiving message to a target sequence and forward the updated receiving message in response to the frame detection sequence being inconsistent with a check sequence; the target sequence is different from at least one bit of the check sequence.

[0025] Optionally, the device further comprises:

[0026] An updated message forwarding module is configured to send the updated receiving message to a peer device after logical processing of the updated receiving message; the peer device discards the updated receiving message when the target sequence in the receiving message is detected.

[0027] Optionally, the device further comprises:

[0028] A code-added message acquisition module is configured to process a sending message in a MAC layer of the low latency transceiver in a Pipeline mode and add a preset control code to the sending message during the Pipeline mode processing to obtain a code-added sending message.

[0029] Optionally, the device further comprises:

[0030] The sending message obtaining module is configured to scramble the sending message after the adding of the code to obtain a sending message of a second length;

[0031] The sending message conversion module is configured to convert the length of the sending message of the second length to obtain a sending message of a first length.

[0032] The sending message processing module is configured to perform logical processing on the sending message of the first length to obtain a receiving message to be forwarded.

[0033] Optionally, the apparatus further comprises:

[0034] The receiving message obtaining module is configured to obtain a receiving message of a first length.

[0035] The receiving message alignment module is configured to align the message header and the receiving message according to the position information in the message header of the receiving message to obtain a receiving message of a second length; the second length is greater than the first length.

[0036] The receiving message scrambling module is configured to perform descrambling processing on the receiving message of the second length to obtain a data block type.

[0037] The message payload forwarding module is configured to obtain and forward the message payload of the receiving message according to the data block type.

[0038] According to a third aspect of the embodiments of the present disclosure, a network device is provided, comprising a processor and a memory.

[0039] The memory is configured to store a computer program executable by the processor.

[0040] The processor is configured to execute the computer program in the memory to implement the method according to any one of the first aspect.

[0041] According to a fourth aspect of the embodiments of the present disclosure, a non-transitory computer readable storage medium is provided, which can implement the method according to any one of the first aspect when a computer program executable in the storage medium is executed by a processor.

[0042] The technical solutions provided by the embodiments of the present disclosure can have the following beneficial effects:

[0043] The data low-latency transceiver method provided by the embodiment of the present disclosure can parse a received message in a Pipeline manner at a MAC layer of the low-latency transceiver to obtain a frame detection sequence of the received message; then, in response to the frame detection sequence being inconsistent with a check sequence, updating the frame detection sequence of the received message to a target sequence, and forwarding the updated received message; the target sequence is different from at least one bit of the check sequence. In this way, the message is parsed in the Pipeline manner in the embodiment, and the message does not need to be forwarded after the whole frame of the message is received, which can reduce the delay of forwarding the message, and is beneficial to meeting the needs of a service scenario.

[0044] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure, together with the description.

[0046] Figure 1 is a block diagram of a low-latency transceiver according to an exemplary embodiment.

[0047] Figure 2 is a block diagram of a PCS layer receiving message according to an exemplary embodiment.

[0048] Figure 3 is a block diagram of a receiving message in the related art.

[0049] Figure 4 is a block diagram of a PCS sending message according to an exemplary embodiment.

[0050] Figure 5 is a block diagram of a sending message in the related art.

[0051] Figure 6 is a flowchart of a data low-latency transceiver method according to an exemplary embodiment. DETAILED DESCRIPTION

[0052] The exemplary embodiments will be described in detail herein with reference to the accompanying drawings. The following description, with reference to the accompanying drawings, relates to specific embodiments so as to provide a thorough understanding of the present disclosure. However, those skilled in the art will recognize that the disclosure is not limited to these embodiments and can be practiced with modifications and changes within the scope and spirit of the present disclosure. Accordingly, the following detailed description is exemplary and explanatory in nature.

[0053] The embodiment of the present disclosure provides a data low-latency transceiving method, device, network equipment and storage medium. The data low-latency transceiving method can be applied to a low-latency transceiver, and the low-latency transceiver can be applied to network equipment. The network equipment can include, but is not limited to, a router, a switch or a server intelligent network card, etc. It can be understood that the low-latency transceiver and / or network equipment can be realized in a hardware manner, that is, by setting a circuit, the data low-latency transceiving method is realized by the circuit. The low-latency transceiver and / or network equipment can be realized in a software manner, that is, the data low-latency transceiving method is realized by a computer readable program.

[0054] For the convenience of understanding the scheme, the embodiment provides a logical architecture of a low-latency transceiver. Referring to Figure 1 The low-latency transceiver provided by the embodiment of the present disclosure includes a logic unit 11. The logic unit 11 is used for performing serial-parallel conversion processing and analog signal processing on original data to obtain a received message or a sent message.

[0055] In the embodiment, the original data refers to uncoded data. Considering that the original data is not coded, it is not necessary to set a buffer BUFFER, and the redundant operation pipeline (Pipeline) is removed, the delay of transceiving a message can be reduced, the low-latency transmission characteristic function is realized, and the demand of a service scenario is met.

[0056] In the embodiment, the logic unit 11 is used for reducing the latency in a physical medium attachment (PMA). Considering that the low-latency transceiver further includes a physical coding sublayer (PCS), the latency of the PCS layer can be reduced on the basis of reducing the latency in the PMA layer.

[0057] Continuing to refer to Figure 1 The low-latency transceiver further includes a synchronization module 12, a first conversion module 13 and a descrambling module 14. Wherein,

[0058] The synchronization module 12 is used for determining position information of a message header (Header) in a received message. The received message is sent to the synchronization module 12 by the logic unit 11, and the length of the received message is a first length, for example, the first length is 64 bits.

[0059] The first conversion module 13 is used for aligning the message header and the received message according to the position information of the message header to obtain a received message with a second length. The second length is greater than the first length, for example, the second length is 66 bits.

[0060] The descrambling module 14 is configured to descramble the second length of the received message to obtain a block type, and obtain a message payload of the received message according to the block type. The message payload is the content to be transmitted.

[0061] Taking the FPGA with a high-speed transceiver as an example, the FPGA is provided with a 64 / 66B encoding serial interface, i.e., a 10GBASE-R interface, which can support transmission of a data stream on an optical medium, and the speed of the data stream is 10 Gbit / s. When the first conversion module 13 is implemented by using the 10GBASE-R interface, 64B / 66B encoding is adopted, i.e., 64-bit data or control information is encoded into a 66-bit block for transmission, and the first two bits of the 66-bit block represent a message header. The message header is used for alignment of data of a receiving end and synchronization of a received data bit stream. In an example, the message header can include two types of "01" and "10", "01" indicates that the following 64 bits are all data, and "10" indicates that the following 64 bits are a combination of data and control information.

[0062] Continuing to refer to Figure 1 , the first conversion module 13 and the descrambling module 14 constitute a data path to transmit the content to be transmitted, i.e., the message payload. The synchronization module 12 bypasses the data path to constitute a control path, which is used to transmit an alignment instruction and the like used for alignment of the logic unit 11 and the first conversion module 13.

[0063] The logic unit 11 converts the received serial data into parallel data, i.e., the received message, and sends the received message to the first conversion module 13 and the synchronization module 12. The synchronization module 12 is configured to detect a message header in the received message. The message header can be located at any position of the received message, and the position of the message data can be determined only after the message header of the received message is determined.

[0064] It should be noted that there are 66 possible positions of the message header. The message header header occupies 2 bits, and appears once every 32 bits of data, at which time there is a 2-bit misalignment, so each round is 32 clock cycles. Assuming that the starting detection time is 0, the newly received 32-bit data is simultaneously matched with 66 modes. When the message header position of the newly received 32-bit data is 2'b01 or 2'b10, the mode matching is determined, and the matching value cnt+1 is output. If the mode matching is continuously matched for 64 times and the other modes are all failed, it is confirmed that the mode is the final alignment mode, and a synchronization valid flag Syn Valid is output as an alignment instruction for the first conversion module 13.

[0065] The first conversion module 13 outputs a 2-bit packet header and 64-bit data according to the position information of the packet header, so as to align the packet header and the received packet, and obtain a second length of the received packet, and realize the alignment from 64-bit data to 66-bit data. It can be understood that in the process of aligning the 2-bit packet header and the 64-bit data, there will be a situation of invalid data for one clock period every 33 clock periods, and the data will be delayed for 0-1 clock period to wait for the 64-bit data.

[0066] In an embodiment, the descrambling module 14 performs descrambling processing on the second length of the received packet output by the first conversion module 13. In an example, the descrambling module 14 can use a linear feedback shift register (LFSR) to generate a pseudo-random binary sequence (PRBS), which has the property of white noise. In this example, the generating polynomial of the PRBS sequence is represented as X58+X39+1, where X represents a delay unit in the shift register, the number represents the number of steps of delay, and "+" represents the XOR operation, that is, "X58" represents that the bit delayed for 58 steps is fed back to the input, "X39" represents that the bit delayed for 39 steps is fed back to the input, and "1" represents that there is a fixed bit (usually the lowest bit of the register) fed back to the input. In this example, the data block and the block type of the received packet can be obtained through decoding processing, and then the packet header (sop) and the packet trailer (eop) can be obtained according to the block type, that is, the packet payload can be obtained.

[0067] The above embodiment describes the scheme of reducing the delay of the received packet transmission by the PCS setting synchronization module 12, the first conversion module 13 and the descrambling module 14. In an embodiment, the delay of the received packet in the medium access control layer (MAC) can also be reduced. Continue to refer to Figure 1 The low-latency transceiver also includes an RX_MAC module 15 and a receiving processing module 16. Among them,

[0068] The RX_MAC module 15 is used to process the packet payload in a pipeline manner, and obtain a frame check sequence during the pipeline processing, and update the frame check sequence to a target sequence when the frame check sequence is inconsistent with a check sequence, so as to obtain an updated received packet.

[0069] It should be noted that the above frame check sequence (FCS) is a redundancy check method for detecting whether an error occurs in the transmission process of a data frame, is an application of cyclic redundancy check (CRC), and is usually attached at the end of the data frame. The process of obtaining the above frame check sequence can refer to related technologies. Moreover, the process of obtaining the check sequence can also refer to related technologies.

[0070] In an example, referring to Figure 2 During the Pipeline processing (about 2-3 clock cycles), the RX_MAC module 15 can obtain the FCS sequence; and the RX_MAC module 15 can calculate the check sequence according to the message payload. If the FCS sequence is consistent with the check sequence, it means that the message payload is correct; if the FCS sequence is inconsistent with the check sequence, it means that the message payload is incorrect. The RX_MAC module 15 can flip at least one bit in the check sequence to obtain the above target sequence. Since at least one bit of the target sequence is flipped compared with the check sequence, it is an abnormal sequence. Then the RX_MAC module 15 can replace the above FCS sequence with the above target sequence.

[0071] Referring to Figure 3 In related technologies, the received message is stored in the RX BUFFER until the end of the message is detected, and then the complete received message is verified. If the FCS sequence of the received message passes the verification, the complete received message is sent to the subsequent module; if the FCS sequence does not pass the verification, the message is discarded.

[0072] It can be known from the example solutions shown in Figure 2 and Figure 3 that the solution of the embodiment can forward the message without setting the BUFFER and without obtaining the entire message, so as to reduce the transmission delay. Or, in the solution of the embodiment, all messages are forwarded, and only the error message is marked, so as to reduce the delay caused by receiving the entire message.

[0073] It should be noted that the above embodiment describes the process of the RX_MAC module 15 processing the received message by the Pipeline method. In addition, the RX_MAC module 15 also has the functions of counting statistics or other message processing methods, which can be set according to specific scenes, and the corresponding solutions fall within the protection scope of the present disclosure.

[0074] The above embodiment describes the receiving process from receiving the message from the FPGA transceiver IP core to sending the message by the receiving processing module. In an embodiment, the delay of sending the message by the medium access control layer can also be reduced. Continue to refer to Figure 1The low-latency transceiver further comprises a TX_MAC module 18 and a sending processing module 17. The sending processing module 17 is configured to send a sending message to the TX_MAC module 18. The TX_MAC module 18 is configured to perform pipeline processing on the sending message and add preset control codes (such as S code and T code required by 10GBASE-R) to the sending message during the pipeline processing, to obtain a coded sending message.

[0075] Referring to Figure 4 The preset control codes (such as S code and T code required by 10GBASE-R) can be added to the sending message after 2-3 clock cycles during the pipeline processing, to obtain a coded sending message.

[0076] Referring to Figure 5 In the related art, the sending message is stored in a buffer TX BUFFER during the process of receiving the sending message, and is sent out after the complete sending message is obtained.

[0077] In combination with the scheme shown in Figure 4 and Figure 5 The scheme of the embodiment can reduce the latency of MAC layer sending data, without setting a buffer and sending the coded sending message to a subsequent module after inserting the control codes for 2-3 clock cycles.

[0078] In an embodiment, on the basis of reducing the latency of the sending message at the PCS layer, referring to Figure 1 The low-latency transceiver further comprises a scrambling module 19 and a second conversion module 20. The scrambling module 19 is configured to perform scrambling processing on the coded sending message, to obtain a sending message of a second length.

[0079] The scrambling module 19 is configured to perform scrambling processing on the coded sending message, to obtain a sending message of a second length.

[0080] The second conversion module 20 is configured to perform length conversion on the sending message of the second length, to obtain a sending message of a first length, and send the sending message of the first length to the logic unit 11.

[0081] It should be noted that the scrambling processing of the scrambling module 19 on the message and the descrambling operation of the descrambling module 14 are two inverse operations. Therefore, the scrambling module 19 and the descrambling module 14 can use the same linear feedback shift register to generate a pseudo-random binary sequence, to ensure the randomness of the message in the transmission process and the correct recovery of the original data at the receiving end.

[0082] Thus, the low-latency transceiver provided by the embodiment can perform serial-parallel conversion on the original data by the logic unit 11, without using the buffer BUFFER and reducing the redundant pipeline, so as to reduce the latency at the PCS layer and the MAC layer, and can be transplanted to different network devices, and can also be applied to FPGA circuit devices and chip design.

[0083] Based on the low-latency transceiver, the embodiment of the disclosure further provides a data low-latency transceiving method, which is suitable for the low-latency transceiver, and refers to Figure 6 , the method comprises steps 61 and 62.

[0084] In step 61, the MAC layer of the low-latency transceiver adopts the Pipeline mode to parse the received message, to obtain a frame detection sequence of the received message.

[0085] In this step, the MAC layer of the low-latency transceiver is provided with an RX_MAC module 15. It is further referred to Figure 1 that the RX_MAC module 15 no longer adopts the scheme of receiving the entire message and buffering into the BUFFER, but adopts the Pipeline mode as shown in Figure 2 for processing. The RX_MAC module 15 can parse the frame detection sequence, i.e., the FCS sequence, from the received message in 2-3 time periods of the Pipeline mode processing.

[0086] In step 62, in response to the frame detection sequence being inconsistent with the check sequence, the frame detection sequence of the received message is updated to a target sequence, and the updated received message is forwarded; the target sequence is different from at least one bit of the check sequence.

[0087] In this step, the RX_MAC module 15 can also calculate the check sequence according to the message payload. Then, the RX_MAC module 15 can judge whether the FCS sequence is consistent with the check sequence. When the FCS sequence is consistent with the check sequence, it can be determined that the message payload is correct; when the FCS sequence is inconsistent with the check sequence, it can be determined that the message payload is incorrect. The RX_MAC module 15 can flip at least one bit in the check sequence to obtain a target sequence. Since at least one bit of the target sequence is flipped compared with the check sequence, it is an abnormal sequence. Then the RX_MAC module 15 can replace the FCS sequence with the target sequence.

[0088] It should be noted that in some possible examples, the RX_MAC module 15 can also replace the FCS sequence of the received message with a preset target sequence. For example, the target sequence is preset to be a set of illegal values, and the peer device cannot generate a check sequence when the illegal values are parsed, and directly discards the message, further reducing the latency.

[0089] In some possible examples, the data low-latency transceiving method provided by the present disclosure can further include: sending the updated receiving packet to a peer device after logical processing. Continuing to refer to Figure 1 The receiving processing module 16 of the low-latency transceiver can send the updated receiving packet to a peer device after logical processing. The peer device can determine that the receiving packet is incorrect and discard the updated receiving packet when detecting a target sequence in the receiving packet, and finally only keep the correct receiving packet.

[0090] In some possible examples, the data low-latency transceiving method provided by the present disclosure can further include: processing the sending packet in a Pipeline manner at the MAC layer of the low-latency transceiver, and adding a preset control code to the sending packet during the Pipeline manner processing to obtain a coded sending packet. Continuing to refer to Figure 1 The sending processing module 17 of the low-latency transceiver can receive the sending packet and send it to the RX_MAC module 15. The RX_MAC module 15 can process the sending packet in a Pipeline manner, and add a preset control code (such as an S code, a T code and the like required by 10GBASE-R) to the sending packet during the Pipeline manner processing to obtain a coded sending packet. In this way, the scheme of the present embodiment can reduce the latency of sending data at the MAC layer, and can send the coded sending packet to a subsequent module after inserting the control code in 2-3 clock cycles without setting a BUFFER.

[0091] In some possible examples, the data low-latency transceiving method provided by the present disclosure can further include: performing scrambling processing on the coded sending packet to obtain a second-length sending packet; performing length conversion on the second-length sending packet to obtain a first-length sending packet; and performing logical processing on the first-length sending packet to obtain a receiving packet to be forwarded. Continuing to refer to Figure 1 The scrambling module 19 of the low-latency transceiver can perform scrambling processing on the coded sending packet to obtain a second-length sending packet. The second conversion module 20 of the low-latency transceiver can perform length conversion on the second-length sending packet to obtain a first-length sending packet. The logic unit 11 of the low-latency transceiver can perform logical processing on the first-length sending packet to obtain a receiving packet to be forwarded.

[0092] In some possible examples, the data low-latency transceiving method provided by the present disclosure can further include: obtaining a first length of a received packet; aligning a packet header and the received packet according to position information in the packet header of the received packet to obtain a second length of the received packet; the second length is greater than the first length; performing descrambling processing on the second length of the received packet to obtain a data block type; and obtaining and forwarding a packet payload of the received packet according to the data block type. Figure 1 The synchronization module 12, the first conversion module 13 and the descrambling module 14 of the low-latency transceiver cooperate to complete the conversion and descrambling operation on the length of the received packet, and finally obtain the packet payload of the received packet. In this way, the PCS layer does not need to set the BUFFER in this example, and the latency can be reduced.

[0093] It should be noted that the data low-latency transceiving method provided by the present disclosure has been described as a description of the working process of the low-latency transceiver, and can be combined with the content of the low-latency transceiver embodiment.

[0094] Based on the above data low-latency transceiving method, the present disclosure further provides a data low-latency transceiving device suitable for a low-latency transceiver, which includes:

[0095] The detection sequence obtaining module is configured to parse a received packet in a Pipeline manner at a MAC layer of the low-latency transceiver to obtain a frame detection sequence of the received packet.

[0096] The updated packet obtaining module is configured to update the frame detection sequence of the received packet to a target sequence and forward the updated received packet in response to the frame detection sequence being inconsistent with a check sequence; the target sequence is different from at least one bit of the check sequence.

[0097] In some possible examples, the device further includes:

[0098] The updated packet forwarding module is configured to send the updated received packet to a peer device after logical processing; and the peer device discards the updated received packet when detecting the target sequence in the received packet.

[0099] In some possible examples, the device further includes:

[0100] The coded packet obtaining module is configured to process a sending packet in a Pipeline manner at a MAC layer of the low-latency transceiver, and add a preset control code to the sending packet during the Pipeline manner processing to obtain a coded sending packet.

[0101] In some possible examples, the device further includes:

[0102] The sending message obtaining module is configured to scramble the sending message after the adding of the code to obtain a second length of sending message.

[0103] The sending message conversion module is configured to convert the length of the second length of sending message to obtain a first length of sending message.

[0104] The sending message processing module is configured to perform logical processing on the first length of sending message to obtain the to-be-forwarded receiving message.

[0105] In some possible examples, the apparatus further includes:

[0106] The receiving message obtaining module is configured to obtain a first length of receiving message.

[0107] The receiving message alignment module is configured to align the message header and the receiving message according to the position information in the message header of the receiving message to obtain a second length of receiving message; the second length is greater than the first length.

[0108] The receiving message scrambling module is configured to perform descrambling processing on the second length of receiving message to obtain a data block type.

[0109] The message payload forwarding module is configured to obtain and forward the message payload of the receiving message according to the data block type.

[0110] It should be noted that the data low-latency transceiver apparatus provided in the embodiment is matched with the data low-latency transceiver method, and the specific implementation can be referred to the scheme content of the data low-latency transceiver method and the low-latency transceiver, which will not be described here.

[0111] In an example embodiment, a network device is also provided, including a processor and a memory;

[0112] The memory is configured to store a computer program executable by the processor;

[0113] The processor is configured to execute the computer program in the memory to implement the method as described above.

[0114] In an example embodiment, a non-transitory computer readable storage medium is also provided, which can implement the method as described above when the executable computer program in the storage medium is executed by a processor.

[0115] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. It is intended that the disclosure be construed as including any variations, uses, or adaptations of the specific embodiments following, including equivalents thereof, and including such as come within the general scope of the disclosure. The specification and examples are illustrative only, and not restrictive of the true scope of the disclosure, which is set forth in the following claims.

[0116] It should be understood that the present disclosure is not limited to the precise structures as herein described and illustrated in the drawings, and that various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. A data low-latency transceiving method, characterized by, The method is suitable for a low-latency transceiver, and the method comprises the following steps: A frame detection sequence of a received message is obtained by using a Pipeline mode to analyze the received message at a MAC layer of the low-latency transceiver; In response to the frame detection sequence being inconsistent with a check sequence, the frame detection sequence of the received message is updated to a target sequence, and the updated received message is forwarded; the target sequence is different from at least one bit in the check sequence; the check sequence is calculated according to a message payload.

2. The method of claim 1, wherein, The method further comprises the following steps: The updated received message is sent to a peer device after being logically processed; the peer device discards the updated received message when detecting the target sequence in the received message.

3. The method of claim 1, wherein, The method further comprises the following steps: A preset control code is added to a sending message during Pipeline mode processing of the sending message at the MAC layer of the low-latency transceiver, so that a coded sending message is obtained.

4. The method of claim 3, wherein, The method further comprises the following steps: The coded sending message is scrambled to obtain a sending message of a second length; The sending message of the second length is converted in length to obtain a sending message of a first length; The sending message of the first length is logically processed to obtain a received message to be forwarded.

5. The method of claim 1, wherein, The method further comprises the following steps: A received message of the first length is obtained; The received message of the second length is obtained by aligning a message header and the received message according to position information in the message header of the received message; the second length is greater than the first length; A data block type is obtained by descrambling the received message of the second length; A message payload of the received message is obtained and forwarded according to the data block type.

6. A data low latency transceiver apparatus, characterized by, The device comprises: A detection sequence obtaining module is configured to obtain a frame detection sequence of a received message by using a Pipeline mode to analyze the received message at a MAC layer of a low-latency transceiver. An updated message obtaining module is configured to update the frame detection sequence of the received message to a target sequence and forward the updated received message in response to the frame detection sequence being inconsistent with a check sequence; the target sequence is different from at least one bit in the check sequence; the check sequence is calculated according to a message payload.

7. The apparatus of claim 6, wherein, The device further comprises: An updated message forwarding module is configured to send an updated received message to a peer device after logically processing the updated received message; the peer device discards the updated received message when detecting a target sequence in the received message.

8. The apparatus of claim 6, wherein, The device further comprises: A coded message obtaining module is configured to add a preset control code to a sending message during Pipeline mode processing of the sending message at a MAC layer of a low-latency transceiver, so that a coded sending message is obtained.

9. The apparatus of claim 8, wherein, The device further comprises: A sending message obtaining module is configured to scramble the coded sending message to obtain a sending message of a second length. A sending message conversion module is configured to convert the sending message of the second length in length to obtain a sending message of a first length. A sending message processing module is configured to logically process the sending message of the first length to obtain a received message to be forwarded.

10. The apparatus of claim 6, wherein, The device further comprises: A receiving packet obtaining module is configured to obtain a receiving packet with a first length; A receiving packet aligning module is configured to align a packet header and the receiving packet according to position information in the packet header of the receiving packet, to obtain a receiving packet with a second length; the second length is greater than the first length; A receiving packet scrambling module is configured to perform descrambling processing on the receiving packet with the second length to obtain a data block type; A packet payload forwarding module is configured to obtain and forward a packet payload of the receiving packet according to the data block type.

11. A network device, comprising: Comprise: A processor and a memory; The memory is configured to store a computer program executable by the processor; The processor is configured to execute the computer program in the memory to implement the method in any one of claims 1-5.

12. A non-transitory computer-readable storage medium, comprising: When the executable computer program in the storage medium is executed by the processor, the method in any one of claims 1-5 can be implemented.

Images