Method for preparing semiconductor structure

Abstract

The disclosed embodiments relate to a method for preparing a semiconductor structure, comprising: providing a substrate on which a stacked structure is formed, the stacked structure comprising alternating sacrificial layers and supporting layers; forming a through hole in the stacked structure, the through hole penetrating the stacked structure, the sacrificial layer comprising a protrusion, the orthographic projection of the protrusion on the substrate partially overlapping the orthographic projection of the through hole opening on the substrate; injecting a doping element into the protrusion, the doping element being used to change the etching rate of the protrusion; and etching away the doped protrusion. After injecting the doping element that can change the etching rate of the protrusion into the protrusion, the doped protrusion can be removed, reducing the difference between the characteristic dimensions of the top and bottom of the through hole, thereby obtaining a through hole with vertical sidewalls, wherein the bottom of the through hole can expose the underlying structure below the through hole, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) includes multiple memory cells, each of which includes a transistor and a capacitor. As the size of DRAM devices gradually decreases, the aspect ratio of the through-holes formed during the manufacturing process of DRAM devices gradually increases. When etching a through-hole with a large aspect ratio on a substrate, the characteristic size of the top of the through-hole is larger than the characteristic size of the bottom. As a result, the depth of the capacitor hole in some areas may be less than the expected depth, and the bottom of the through-hole may not expose the underlying structure below the through-hole. Summary of the Invention

[0003] An embodiment of the present application provides a method for preparing a semiconductor structure, which can optimize the morphology of a through hole.

[0004] The present disclosure provides a method for preparing a semiconductor structure, comprising:

[0005] Providing a substrate, on which a stacked structure is formed, the stacked structure comprising sacrificial layers and supporting layers alternately stacked;

[0006] forming a through hole in the stacked structure, the through hole penetrating the stacked structure, the sacrificial layer including a protrusion, the orthographic projection of the protrusion on the substrate partially overlapping the orthographic projection of the opening of the through hole on the substrate;

[0007] injecting a doping element into the protrusion, wherein the doping element is used to change the etching rate of the protrusion;

[0008] The doped protrusions are removed by etching.

[0009] In one embodiment, an extending direction of the protrusion is perpendicular to an extending direction of the through hole.

[0010] In one embodiment, the doping element includes a first doping element and a second doping element, and the doping element is injected into the protrusion, comprising:

[0011] injecting a first doping element into the protrusion using a first injection process;

[0012] A second doping element is implanted into the protrusion using a second implantation process.

[0013] In one embodiment, the first doping element includes boron, the second doping element includes phosphorus, and the constituent material of the sacrificial layer includes silicon oxide.

[0014] In one embodiment, the injection directions of the first injection process and the second injection process are parallel to the extension direction of the through hole and perpendicular to the extension direction of the protrusion.

[0015] In one embodiment, the doping concentration of the first doping element is greater than the doping concentration of the second doping element.

[0016] In one embodiment, etching and removing the doped protrusions includes:

[0017] The doped protrusions are removed by wet etching.

[0018] In one embodiment, the wet etching reagent includes a mixed etching solution of dilute sulfuric acid and hydrogen peroxide.

[0019] In one embodiment, before the doping element is injected into the protrusion, the method further comprises:

[0020] A cleaning process is used to remove residues on the inner wall of the through hole.

[0021] In one embodiment, after etching away the doped protrusion, the method further comprises:

[0022] A capacitor structure is formed in the through hole.

[0023] The above-mentioned method for preparing a semiconductor structure forms a through hole that penetrates the stacked structure, and the orthographic projection of the protrusion on the substrate partially coincides with the orthographic projection of the opening of the through hole on the substrate. After injecting an impurity element that can change the etching rate of the protrusion into the protrusion, the doped protrusion can be removed, reducing the difference between the characteristic size of the top of the through hole and the characteristic size of other positions in the through hole, thereby obtaining a through hole with vertical sidewalls, and the bottom of the through hole can expose the bottom structure below the through hole, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0026] Figure 2 is a schematic cross-sectional view of a semiconductor structure after a through hole is formed through the stacked structure in one embodiment;

[0027] Figure 3 for Figure 2 A schematic cross-sectional view of a semiconductor structure after doping elements are implanted in a corresponding embodiment;

[0028] Figure 4 for Figure 2 A schematic cross-sectional view of the semiconductor structure after the protrusion is removed in a corresponding embodiment;

[0029] Figure 5 is a schematic flow chart of a method for preparing a semiconductor structure in another embodiment;

[0030] Figure 6 is a schematic diagram of a process for injecting doping elements into a protrusion in one embodiment;

[0031] Figure 7 FIG. 4 is a flow chart of a method for preparing a semiconductor structure in yet another embodiment.

[0032] Description of reference numerals:

[0033] 102, substrate; 104, laminated structure; 106, through hole; 107, first mask layer; 202, sacrificial layer; 204, supporting layer; 302, protrusion; 304, sacrificial structure. DETAILED DESCRIPTION

[0034] To facilitate understanding of the embodiments of the present application, a more comprehensive description of the embodiments of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings provide preferred embodiments of the embodiments of the present application. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the embodiments of the present application.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present application. The terms used herein in the description of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0036] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0037] It will be understood that the terms "first," "second," and the like used herein may be used herein to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish a first element from another element. For example, a first doping element may be referred to as a second doping element, and similarly, a second doping element may be referred to as a first doping element, without departing from the scope of this application. The first doping element and the second doping element are both doping elements, but they are not the same doping element.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of this application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0039] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0040] Figure 1 FIG. 1 is a flow chart of a method for preparing a semiconductor structure in one embodiment. Figure 1 As shown, in this embodiment, a method for preparing a semiconductor structure is provided, comprising:

[0041] S102, providing a substrate, on which a laminated structure is formed.

[0042] Figure 2 FIG. 1 is a schematic cross-sectional view of a semiconductor structure after forming a through hole in one embodiment. Figure 2As shown, a substrate 102 is provided, and a stacked structure 104 is formed on the substrate 102. The stacked structure includes alternately stacked sacrificial layers 202 and support layers 204, wherein the direction in which the sacrificial layers 202 and the support layers 204 are alternately stacked is from the surface of the substrate 102 forming the stacked structure 104 to the direction away from the substrate 102, Figure 2 The substrate 102 may be formed of materials including, but not limited to, undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In this embodiment, single crystal silicon is used as the material for the substrate 102. Among them, the bottom of the stacked structure 104 close to the substrate 102 can be either a sacrificial layer 202 or a supporting layer 204, and the top of the stacked structure 104 away from the substrate 102 can also be either a sacrificial layer 202 or a supporting layer 204. The present disclosure does not limit the top and bottom layers of the stacked structure 104. At the same time, the present disclosure does not limit the number of sacrificial layers 202 and the thickness of each sacrificial layer 202 in the stacked structure 104, and the number of supporting layers 204 and the thickness of each supporting layer 204. In the figure, the top layer of the stacked structure 104 is used as the supporting layer 204 and the bottom layer of the stacked structure 104 is used as the sacrificial layer 202, and the number of layers of the sacrificial layer 202 and the supporting layer 204 are both 2 for exemplary illustration.

[0043] S104 , forming a through hole in the stacked structure, wherein the through hole penetrates the stacked structure, the sacrificial layer includes a protrusion, and an orthographic projection of the protrusion on the substrate partially overlaps with an orthographic projection of an opening of the through hole on the substrate.

[0044] like Figure 2As shown, a through hole 106 is formed in the stacked structure 104 by photolithography and etching processes. The through hole 106 penetrates the stacked structure 104. The sacrificial layer 202 includes a protrusion 302. The orthographic projection of the protrusion 302 on the substrate 102 partially overlaps with the orthographic projection of the opening of the through hole 106 on the substrate 102. The bottom of the through hole 106 exposes the surface of the substrate 102. The orthographic projection of the opening of the through hole 106 on the sacrificial layer 202 overlaps with the part of the sacrificial layer 202. It can be understood that the opening size D1 of the through hole 106 is larger than the middle size D2 of the through hole 106 at the location of the sacrificial layer having the protrusion 302. The through hole 106 is larger than the middle size D2 of the through hole 106 at the location of the sacrificial layer having the protrusion 302. The opening size D1 of through hole 106 is also larger than the bottom size of through hole 106. The portion of the opening of through hole 106 where the orthographic projection of the sacrificial layer 202 does not overlap with the sacrificial layer 202 is a sacrificial structure 304. The protrusion 302 corresponds to the sacrificial layer 202. When the stacked structure 104 includes multiple sacrificial layers 304, the size of the protrusion 302 in the sacrificial layer 304 near the opening position of through hole 106 is smaller than the size of the protrusion 302 in the sacrificial layer 304 away from the opening position of through hole 106. The number of protrusions 302 is less than or equal to the number of layers of sacrificial layer 202, that is, there is no protrusion 302 in a sacrificial layer 304 with more than or equal to one layer. Figure 2 For example, each sacrificial layer 202 in the stacked structure 104 has a protrusion 302 .

[0045] S106 , injecting doping elements into the protrusions, where the doping elements are used to change the etching rate of the protrusions.

[0046] Figure 3 for Figure 2 A cross-sectional schematic diagram of a semiconductor structure after doping elements are implanted in an embodiment of the present invention is shown in FIG. Figure 3 As shown, the doping element 108 is injected into the protrusion 302, and the protrusion 302 after doping is as shown in FIG. Figure 3 As shown, the doping element 108 is used to change the etching rate V of the protrusion 302 in the extension direction X of the through hole 106. By injecting the doping element 108, each part of the protrusion 302 in the extension direction X of the through hole 106 has an expected etching rate V, so that the protrusion 302 can be completely removed later to obtain a through hole 106 with vertical side walls.

[0047] S108, etching to remove the doped protrusions.

[0048] Figure 4 for Figure 2 A cross-sectional view of the semiconductor structure after the protrusion is removed in a corresponding embodiment is shown in FIG. Figure 4As shown, the doped protrusion 302 is etched away by a suitable etching method and etching agent, such as a wet etching process, that is, the uneven protrusion portion of the side wall of the through hole 106 caused by the protrusion 302 is removed, so that the opening size D1 of the through hole 106 is equal to the middle size D2 of the through hole 106 at the location of the sacrificial layer 202 having the protrusion 302, and the opening size D1 of the through hole 106 is equal to the bottom size of the through hole 106, thereby obtaining a through hole 106 with vertical side walls.

[0049] In the above-mentioned method for preparing the semiconductor structure, a through hole 106 is formed that penetrates the stacked structure 104. The orthographic projection of the protrusion 302 in the sacrificial layer 202 on the substrate 102 partially overlaps with the orthographic projection of the opening of the through hole 106 on the substrate 102. After an impurity element that can change the etching rate of the protrusion 302 is injected into the protrusion 302, the doped protrusion 302 can be completely removed subsequently, reducing the difference between the characteristic size at the top of the through hole 106 and the characteristic size at other positions in the through hole 106, thereby obtaining a through hole 106 with vertical sidewalls. The bottom of the through hole 106 can completely expose the bottom structure below the through hole 106, thereby improving the performance of the semiconductor structure.

[0050] In one embodiment, the through hole 106 includes a capacitor hole, and the step of forming the through hole 106 in the stacked structure 104 includes: forming a patterned mask layer on the stacked structure 104, the patterned mask layer defining the shape and position of the through hole 106, patterning the stacked structure 104 using the patterned mask layer as a mask, removing the stacked structure 104 not covered by the patterned mask layer, and forming the through hole 106 in the stacked structure 104. Exemplarily, the material constituting the patterned mask layer includes, but is not limited to, photoresist.

[0051] like Figure 2 As shown, before forming a patterned mask layer on the stacked structure 104, the process further includes: forming a mask material layer on the stacked structure 104, the patterned mask layer being located on the mask material layer, patterning the mask material layer using the patterned mask layer as a mask to obtain a first mask layer 107, and then patterning the stacked structure 104 using the first mask layer 107 as a mask to form a through hole 106 located in the stacked structure 104. Exemplarily, the constituent material of the first mask layer 107 includes, but is not limited to, an anti-reflective layer, silicon oxynitride, or polysilicon.

[0052] In one embodiment, after obtaining the first mask layer 107 , the method further includes: removing the patterned mask layer.

[0053] In one embodiment, after etching away the doped protrusions, the process further includes: removing the first mask layer.

[0054] like Figure 2As shown, in one embodiment, the extension direction of the protrusion 302 is perpendicular to the extension direction of the through hole 106. The extension direction of the protrusion 302 is the direction of the protrusion 302 toward the central axis of the through hole 106, that is, the extension direction of the protrusion 302 is the aperture direction of the through hole 106. The extension direction of the protrusion 302 in the figure is indicated by Y. It can be clearly seen that the extension direction of the protrusion 302 can be any direction on the horizontal plane parallel to the surface of the substrate 102 where the Y direction is located. The extension direction of the through hole 106 is the direction from the bottom of the through hole 106 toward the opening of the through hole 106, that is, the direction perpendicular to the substrate 102, such as the X direction in the figure.

[0055] Figure 5 FIG. 1 is a flow chart of a method for preparing a semiconductor structure in another embodiment. Figure 2 、 Figure 5 As shown, the dopant element 108 is injected into the protrusion 302 by an injection process. After the through hole 106 is formed in the stacked structure 104 and before the dopant element 108 is injected into the protrusion 302, the process further includes:

[0056] S202, detecting the through hole and obtaining initial morphological parameters of the through hole.

[0057] S204, obtaining process parameters of the implantation process according to the initial morphology parameters.

[0058] Initial morphological parameters of the through hole 106 are obtained by detecting characteristic dimensions of the through hole 106. The initial morphological parameters include a first aperture and a second aperture. The first aperture is used to characterize the initial top dimension of the through hole 106, i.e., the opening dimension D1 of the through hole 106. The second aperture is used to characterize the intermediate aperture D0 of the through hole 106 corresponding to any point O in the region where each sacrificial layer 202 is located in the extension direction X of the through hole 106. The first aperture and the second aperture can be used to determine the morphology of the location where the sacrificial layer 202 is located, as well as the difference between the morphology of the location where the sacrificial layer 202 is located and the opening location of the through hole 106, i.e., the morphology of the protrusion 302. Based on the initial morphological parameters (the morphology of the protrusion 302), the expected etch rate corresponding to each location of the protrusion 302 in the extension direction X of the through hole 106 can be obtained, thereby obtaining process parameters of the implantation process, such as the implanted ion type, the number of implantations, the implantation energy, the implantation dose, the implantation angle, etc.

[0059] In one embodiment, before the dopant element 108 is implanted into the protrusion 302, a cleaning process is further performed to remove residues on the inner wall of the through hole 106. It is understood that before inspecting the through hole 106 and obtaining the initial morphology parameters of the through hole 106 in step S202, the cleaning process is performed to remove the residues on the inner wall of the through hole 106. In this case, the obtained initial morphology parameters are more accurate.

[0060] Exemplarily, the cleaning agent used in the cleaning process includes DSP (Dilute Sulfuric Peroxide Mixture), which is a mixture of sulfuric acid, hydrogen peroxide, hydrofluoric acid, and deionized water. Sulfuric acid and hydrogen peroxide can remove residual metal compounds and polymers generated during the initial formation of through-hole 106. Exemplarily, the metal compounds remaining on the sidewalls of through-hole 106 include, but are not limited to, Al2O3; polymers include soluble polymers soluble in hydrogen peroxide and / or sulfuric acid. Hydrofluoric acid can remove oxides. Exemplarily, the oxides include, but are not limited to, silicon dioxide.

[0061] Figure 6 FIG. 1 is a schematic diagram of a process for injecting doping elements into the protrusions in one embodiment. Figure 3 、 Figure 6 As shown, in one embodiment, the doping element 108 includes a first doping element and a second doping element, and implanting the doping element 108 into the protrusion 302 includes:

[0062] S302 , using a first implantation process to implant a first doping element into the protrusion.

[0063] S304 , injecting a second doping element into the protrusion using a second injection process.

[0064] The method for implanting the doping element 108 into the protrusion 302 is to ionize the doping element 108 into ions and focus them into an ion beam. The ion beam is accelerated in an electric field to obtain extremely high kinetic energy and then implanted into a predetermined position in the recess 302. The implantation depth, implantation dosage, and number of implantations of the first doping element and the second doping element are related to the length L of the protrusion 302 in the aperture direction (Y direction) of the through hole 106 and the thickness T of the protrusion 302 in the extension direction X of the through hole 106. The etching rate required to be adjusted at the thickness T1 position in the protrusion 302 is set by adjusting the length L1 and the thickness T1. The parameters of the first and second implantation processes, the order of the first and second implantation processes, the number of the first and second implantation processes, the types of the first and second doping elements, etc. are then adjusted to adjust the etching rate of the entire protrusion 302 after doping, thereby achieving the purpose of completely removing the protrusion 302.

[0065] In one embodiment, the injection directions of the first injection process and the second injection process are parallel to the extension direction of the through hole 106 and perpendicular to the extension direction (Y direction) of the protrusion 302, that is, the injection angles of the first injection process and the second injection process are 0, and the injection angle is the angle between the injection direction of the doping element and the X direction perpendicular to the substrate 102.

[0066] In one embodiment, both the first doping element and the second doping element are ions that increase the etching rate of the protrusion 302. The first doping element and the second doping element may be the same ion that increases the etching rate of the protrusion 302, or the first doping element and the second doping element may be different ions that increase the etching rate of the protrusion 302. In another embodiment, both the first doping element and the second doping element are ions that reduce the etching rate of the protrusion 302. The first doping element and the second doping element may be the same ion that reduces the etching rate of the protrusion 302, or the first doping element and the second doping element may be different ions that reduce the etching rate of the protrusion 302.

[0067] In one embodiment, the first doping element is an ion that increases the etching rate of the protrusion 302, and the second doping element is an ion that decreases the etching rate of the protrusion 302. Exemplarily, the first doping element that increases the etching rate of the protrusion 302 includes an N-type element, such as phosphorus, arsenic, or antimony, and the second doping element that decreases the etching rate of the protrusion 302 includes a P-type element, such as boron, gallium, or indium. Optionally, the doping concentration of the first doping element is less than the doping concentration of the second doping element.

[0068] It is understandable that the implantation dose of the first doping element and the second doping element must be controlled within a reasonable range, otherwise the etching rate of the protrusion 302 will be excessively affected, causing the first doping element and / or the second doping element in the local area of ​​the protrusion 302 to diffuse laterally (in the aperture direction (Y direction) of the through hole 106) into the sacrificial structure 304 (non-processed area), resulting in the side wall of the through hole 106 becoming an uneven surface morphology during the subsequent etching and removal of the protrusion 302, which not only distorts the measurement value of the subsequent characteristic size of the through hole 106, but also affects the uniformity of the through hole structure subsequently formed in the through hole 106, for example, affecting the uniformity of the lower electrode of the capacitor structure formed on the inner wall of the through hole 106.

[0069] In one embodiment, the first doping element includes phosphorus, the second doping element includes boron, and the constituent material of the sacrificial layer 202 includes but is not limited to undoped silicon oxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, or boron-phosphorus-doped silicon dioxide. The constituent material of the supporting layer 204 includes but is not limited to nitrides, such as silicon nitride, silicon oxynitride, and silicon carbide. Optionally, when the number of sacrificial layers 202 is greater than 1, the constituent material of each sacrificial layer 202 can be the same, the constituent material of each sacrificial layer 202 can be different, or the constituent material of each sacrificial layer 202 can be partially the same. Similarly, when the number of supporting layers 204 is greater than 1, the constituent material of each supporting layer 204 can be the same, the constituent material of each supporting layer 204 can be different, or the constituent material of each supporting layer 204 can be partially the same.

[0070] It is understood that by increasing the doping concentrations of boron and phosphorus in the B-P-doped silicon dioxide, the annealing temperature of the B-P-doped silicon dioxide can be reduced. Phosphorus can capture mobile metal cations, lowering the reflow temperature of the film, and boron can also lower the reflow temperature of the film. However, after the weight ratio of boron in the B-P-doped silicon dioxide reaches a certain amount, as the boron content increases, the water absorption of the B-P-doped silicon dioxide increases. Impurity elements in the B-P-doped silicon dioxide will continuously precipitate, forming bubble defects, causing serious process problems and affecting the performance of the semiconductor device. Therefore, the total weight percentage of the doping elements in the protrusion 302 is less than or equal to 10%. For example, when the protrusion 302 contains both a first doping element that reduces the etching rate of the protrusion 302 and a second doping element, the sum of the weight percentages of the first doping element and the second doping element in the protrusion is less than or equal to 5%. When the protrusion 302 contains both a first doping element that increases the etching rate of the protrusion 302 and a second doping element that reduces the etching rate of the protrusion 302, the sum of the weight percentages of the first doping element and the second doping element in the protrusion 302 is less than or equal to 4.4%. When the protrusion 302 contains both a first doping element that increases the etching rate of the protrusion 302 and a second doping element that reduces the etching rate of the protrusion 302, the weight percentage of the first doping element in the protrusion 302 is less than or equal to 4.4%, and the sum of the weight percentages of the second doping element in the protrusion 302 is less than or equal to 5%. It is understood that the doping elements in the protrusion 302 can also soften the protrusion 302, causing the constituent material of the protrusion 302 to flow, thereby facilitating the removal of the protrusion 302.

[0071] Table 1 shows the relationship between the implantation energy (energy), implantation dose (DOSE), and the ratio of the top feature size to the bottom feature size of the through hole (B / T). As can be seen from Table 1, when the implantation energy of the first doping element is smaller than the implantation energy of the second doping element, and the implantation dose of the first doping element is smaller than the implantation dose of the second doping element, the removal effect of the protrusion 302 is better.

[0072] Table 1 Relationship between doping process parameters and feature sizes

[0073]

[0074] In one embodiment, etching away the doped protrusion 302 includes: removing the doped protrusion 302 by wet etching.

[0075] In one embodiment, the wet etching reagent includes a mixture of dilute sulfuric acid and hydrogen peroxide. By controlling the ratio of the chemicals in the wet etching reagent and the wet etching time, the protrusion 302 can be completely removed.

[0076] Figure 7 FIG. 1 is a flow chart of a method for preparing a semiconductor structure in another embodiment. Figure 7 As shown, in one embodiment, after etching away the doped protrusion 302, the method further includes:

[0077] S402, detecting the through hole and obtaining actual morphological parameters of the through hole.

[0078] S404, adjusting the through-hole preparation parameters corresponding to the next product wafer according to the actual morphology parameters.

[0079] After etching away the doped protrusion 302, actual morphological parameters of the through hole 106 are obtained by detecting characteristic dimensions of the through hole 106. The actual morphological parameters include a third aperture and a fourth aperture. The third aperture is used to characterize the actual top dimension of the through hole 106, i.e., the actual opening dimension D11 of the through hole 106 after etching away the protrusion 302. The fourth aperture is used to characterize the actual middle aperture D01 of the through hole 106 corresponding to any point O in the region where the sacrificial layer 202 is located in the extension direction X of the through hole 106 after the protrusion 302 is removed. The actual morphology of the through hole 106 can be determined using the third and fourth apertures. The through hole preparation parameters corresponding to the next product wafer are then adjusted based on the actual morphological parameters of the through hole 106. The through hole preparation parameters are process parameters for forming the through hole 106 in the stacked structure 104. This achieves the purpose of adjusting the difference between the third and fourth apertures to reduce the difference between the top and bottom dimensions of the through hole 106 and make the sidewalls of the through hole 106 more vertical.

[0080] In one embodiment, the ratio of the actual bottom size of the through hole 106 to the actual opening size D11 of the through hole 106 is less than or equal to 1 and greater than or equal to 0.95, such as 0.96, 0.97, 0.98, 0.99, etc.

[0081] In one embodiment, the semiconductor structure includes a memory device, the through hole 106 includes a capacitor hole, and after etching to remove the doped protrusion 302, the step of forming a capacitor structure in the through hole 106 is also included. Optionally, a shallow trench isolation structure is formed in the substrate 102, and the shallow trench isolation structure isolates a plurality of spaced active areas in the substrate 102, each active area is formed with at least one transistor and at least one word line structure passing through the active area, and a bit line structure is formed on the surface of the active area. The gate of each transistor is electrically connected to the word line structure, the drain of each transistor is electrically connected to the bit line structure, the stacked structure 104 is located on the active area, the through hole 106 is located above the source of the transistor, and the source of each transistor is electrically connected to the capacitor structure in the corresponding through hole 106.

[0082] Exemplarily, a capacitor contact structure is formed in the through hole 106, and the source of the transistor is electrically connected to an electrode of the capacitor structure through the capacitor contact structure. Optionally, the constituent materials of the capacitor contact structure include but are not limited to polysilicon, metal, noble metal, metal nitride, conductive metal oxide, conductive noble metal oxide, metal carbide, metal silicide or a combination thereof. For example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al) tungsten nitride (WN), tungsten silicon (WSi) ruthenium (Ru), ruthenium oxide (RuO2), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack.

[0083] Exemplarily, the step of forming a capacitor structure in the through hole 106 includes: forming a first electrode layer on the inner wall of the through hole 106, the first electrode layer being electrically connected to the source of the transistor, the inner wall of the through hole 106 including the bottom of the through hole 106 and the sidewalls of the through hole 106; forming a capacitor dielectric layer on the surface of the first electrode layer; forming a second electrode layer on the surface of the capacitor dielectric layer, wherein the first electrode layer, the capacitor dielectric layer and the second electrode layer constitute a capacitor structure. Optionally, a capacitor contact structure is formed in the through hole 106, the first electrode layer covers the sidewalls of the through hole 106 and the surface of the capacitor contact structure facing away from the substrate, the first electrode layer contacts the capacitor contact structure, and is electrically connected to the first electrode layer through the capacitor contact structure. In some embodiments, before forming the capacitor dielectric layer on the surface of the first electrode layer, the step of removing the sacrificial layer 202 is also included; forming the capacitor dielectric layer on the surface of the first electrode layer includes: forming the capacitor dielectric layer on the inner and outer surfaces of the first electrode layer. In some embodiments, the material constituting the first electrode layer includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi). The material constituting the first electrode layer may be the same as or different from the material constituting the capacitor contact structure.

[0084] In some embodiments, the material constituting the second electrode layer includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi). The material constituting the second electrode layer may be the same as or different from the material constituting the first electrode layer and the material constituting the capacitor contact structure.

[0085] It should be understood that although Figure 1 、 Figure 5 、 Figure 6 and Figure 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 、 Figure 5 、 Figure 6 and Figure 7At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0086] An embodiment of the present disclosure further provides a semiconductor structure, which is manufactured using any of the above-mentioned methods for manufacturing a semiconductor structure.

[0087] In one embodiment, a semiconductor structure includes a memory device.

[0088] The present disclosure also provides an electronic device comprising any of the aforementioned semiconductor structures. The electronic device may include a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal. The present disclosure does not impose any particular restrictions on the specific form of the electronic device.

[0089] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above embodiments merely illustrate several implementation methods of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the scope of the present invention, and these modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, on which a stacked structure is formed, the stacked structure comprising sacrificial layers and supporting layers alternately stacked; forming a through hole in the stacked structure, the through hole penetrating the stacked structure, the sacrificial layer comprising a protrusion, the orthographic projection of the protrusion on the substrate partially overlapping the orthographic projection of the opening of the through hole on the substrate; injecting a doping element into the protrusion, wherein the doping element is used to change the etching rate of the protrusion; The doped protrusions are removed by etching.

2. The preparation method according to claim 1, characterized in that An extending direction of the protrusion is perpendicular to an extending direction of the through hole.

3. The preparation method according to claim 2, characterized in that The doping element includes a first doping element and a second doping element, and the step of injecting the doping element into the protrusion includes: injecting the first doping element into the protrusion using a first injection process; The second doping element is implanted into the protrusion by a second implantation process.

4. The preparation method according to claim 3, characterized in that The first doping element includes boron, the second doping element includes phosphorus, and the constituent material of the sacrificial layer includes silicon oxide.

5. The preparation method according to claim 4, characterized in that Injection directions of the first injection process and the second injection process are parallel to an extension direction of the through hole and perpendicular to an extension direction of the protrusion.

6. The preparation method according to any one of claims 3 to 5, characterized in that The doping concentration of the first doping element is greater than the doping concentration of the second doping element.

7. The preparation method according to claim 1, characterized in that Etching and removing the doped protrusion, comprising: The doped protrusions are removed by wet etching.

8. The preparation method according to claim 7, characterized in that The wet etching reagent includes a mixed etching solution of dilute sulfuric acid and hydrogen peroxide.

9. The preparation method according to claim 1, characterized in that Before injecting the doping element into the protrusion, the method further includes: A cleaning process is used to remove residues on the inner wall of the through hole.

10. The preparation method according to claim 1, characterized in that After etching away the doped protrusions, the method further comprises: A capacitor structure is formed in the through hole.

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