Semiconductor structure and method of fabricating the same
By forming a gate dielectric layer and a diffusion barrier layer that conformally covers the word line trench in the semiconductor structure and removing part of the diffusion barrier layer by oxidation and precursor reaction, the problem of high resistance of the word line structure is solved, and the resistance is reduced and the manufacturing steps are simplified.
Patent Information
- Application Number
- CN202310672000.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-06
- Publication Date
- 2025-10-21
- Estimated Expiration
- 2043-06-06
AI Technical Summary
The word line structure in the semiconductor structure has a relatively high resistance, mainly due to the relatively large thickness of the diffusion barrier layer, which results in a relatively high resistance value.
A word line trench is formed in the substrate, and a gate dielectric layer and a diffusion barrier layer are formed to conformally cover the word line trench. A first sub-portion of the diffusion barrier layer is exposed and partially oxidized, reacting with a precursor for forming a metal layer to be removed, thereby reducing the volume of the diffusion barrier layer and increasing the volume of the metal layer.
The resistance of the semiconductor structure is reduced, while the manufacturing steps are simplified, the volume of the diffusion barrier layer is reduced, the volume of the metal layer is increased, and the electrical performance is improved.
Smart Images
Figure CN119136535B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] With the continuous development of science and technology, the application of semiconductor structures is becoming more and more extensive. In the fields of computers, communications, etc., semiconductor structures with different functions are needed. Semiconductor structures include transistors and word line (WL) structures, among which the word line structure is often used for the gate of the transistor. The word line structure usually includes a metal layer and a barrier layer covering the side and bottom surfaces of the metal layer. The barrier layer can prevent the ions of the metal layer from diffusing outward. However, semiconductor structures often have the problem of high resistance of the word line structure. Summary of the Invention
[0003] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to reduce the resistance of the semiconductor structure.
[0004] According to some embodiments, a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:
[0005] forming a word line trench in the substrate;
[0006] forming a gate dielectric layer conformally covering the word line trench;
[0007] forming a diffusion barrier layer conformally covering the gate dielectric layer, wherein the diffusion barrier layer located in the word line trench includes a first sub-portion and remaining sub-portions except the first sub-portion;
[0008] covering the remaining sub-portion and exposing the first sub-portion, and oxidizing a portion of the first sub-portion;
[0009] A metal layer covering the diffusion barrier layer is formed in the word line trench, wherein during the formation of the metal layer, the oxidized first sub-portion reacts with a precursor for forming the metal layer and is removed.
[0010] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:
[0011] In a method for fabricating a semiconductor structure provided by embodiments of the present disclosure, a gate dielectric layer is formed conformally overlying a wordline trench, and a diffusion barrier layer is formed conformally overlying the gate dielectric layer. A first subsection of the diffusion barrier layer is exposed and partially oxidized. The oxidized first subsection reacts with a precursor used to form a metal layer and is removed, thereby thinning the first subsection, reducing the volume of the diffusion barrier layer within the wordline trench, increasing the volume of the metal layer in the wordline trench, and reducing resistance. Furthermore, the oxidized first subsection does not need to be removed separately; rather, the first subsection is thinned simultaneously during the metal layer formation process, simplifying the fabrication steps of the semiconductor structure.
[0012] According to some embodiments, a second aspect of the present disclosure provides a semiconductor structure comprising:
[0013] a substrate and a wordline trench located in the substrate;
[0014] a word line structure located in the word line trench, the word line structure comprising a gate dielectric layer, a diffusion barrier layer, a metal layer, and an isolation layer, the gate dielectric layer conformally covering the word line trench, the diffusion barrier layer covering the gate dielectric layer, the metal layer covering the diffusion barrier layer, the isolation layer covering top surfaces of the diffusion barrier layer and the metal layer, and completely filling the word line trench;
[0015] The diffusion barrier layer includes a first sub-portion and remaining sub-portions except the first sub-portion, and a thickness of the first sub-portion is smaller than a thickness of the remaining sub-portion.
[0016] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:
[0017] The semiconductor structure provided by the embodiment of the present disclosure includes a substrate and a word line structure arranged in the substrate. The diffusion barrier layer in the word line structure includes a first sub-portion and remaining sub-portions except the first sub-portion, and the thickness of the first sub-portion is less than the thickness of the remaining sub-portions, so as to reduce the volume of the diffusion barrier layer, increase the volume of the metal layer, and reduce the resistance of the word line structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure in one embodiment of the present disclosure;
[0019] Figure 2 Schematic diagram of a word line trench formed in one embodiment;
[0020] Figure 3 This is a schematic diagram after forming a gate dielectric layer in one embodiment of the present disclosure;
[0021] Figure 4 This is a schematic diagram of a diffusion barrier layer formed in one embodiment of the present disclosure;
[0022] Figure 5 Schematic diagram of a first structure of a diffusion barrier layer in an embodiment of the present disclosure;
[0023] Figure 6 This is a schematic diagram of a first metal layer formed in a first diffusion barrier layer in one embodiment of the present disclosure;
[0024] Figure 7 This is a schematic diagram of the first metal layer after etching back in the first diffusion barrier layer in one embodiment of the present disclosure;
[0025] Figure 8 A schematic diagram of a first sub-portion of a first diffusion barrier layer after partial oxidation in one embodiment of the present disclosure;
[0026] Figure 9 This is a schematic diagram of a second metal layer formed in the first diffusion barrier layer in one embodiment of the present disclosure;
[0027] Figure 10 This is a schematic diagram of an embodiment of the present disclosure after an isolation layer is formed in the first diffusion barrier layer;
[0028] Figure 11 This is a schematic diagram of a first sacrificial layer formed in the first diffusion barrier layer in one embodiment of the present disclosure;
[0029] Figure 12 This is a schematic diagram of the first sacrificial layer after etching back in the first diffusion barrier layer in one embodiment of the present disclosure;
[0030] Figure 13 Another schematic diagram of the first sub-portion of the first diffusion barrier layer after partial oxidation in one embodiment of the present disclosure;
[0031] Figure 14 This is a schematic diagram of the first sacrificial layer after removing the first diffusion barrier layer in one embodiment of the present disclosure;
[0032] Figure 15 This is a schematic diagram of a first diffusion barrier layer after a metal layer is formed in an embodiment of the present disclosure;
[0033] Figure 16 Another schematic diagram of an embodiment of the present disclosure after an isolation layer is formed in the first diffusion barrier layer;
[0034] Figure 17 Schematic diagram of a second structure of a diffusion barrier layer in an embodiment of the present disclosure;
[0035] Figure 18 This is a schematic diagram of a second type of diffusion barrier layer after forming a first sacrificial layer in an embodiment of the present disclosure;
[0036] Figure 19This is a schematic diagram of the second diffusion barrier layer after etching back the first sacrificial layer in one embodiment of the present disclosure;
[0037] Figure 20 This is a schematic diagram of a second sacrificial layer formed in the second diffusion barrier layer in one embodiment of the present disclosure;
[0038] Figure 21 This is a schematic diagram of the second sacrificial layer after etching back in the second diffusion barrier layer in one embodiment of the present disclosure;
[0039] Figure 22 This is a schematic diagram of the second diffusion barrier layer after removing the first sacrificial layer in one embodiment of the present disclosure;
[0040] Figure 23 A schematic diagram of a first sub-portion of the second diffusion barrier layer after partial oxidation in one embodiment of the present disclosure;
[0041] Figure 24 This is a schematic diagram of the second sacrificial layer after removing the second diffusion barrier layer in one embodiment of the present disclosure;
[0042] Figure 25 This is a schematic diagram of a second diffusion barrier layer after a metal layer is formed in an embodiment of the present disclosure;
[0043] Figure 26 Another schematic diagram of an embodiment of the present disclosure after an isolation layer is formed in the second diffusion barrier layer;
[0044] Figure 27 Schematic diagram of a third structure of a diffusion barrier layer in an embodiment of the present disclosure;
[0045] Figure 28 This is a schematic diagram of a third diffusion barrier layer after forming a first metal layer in an embodiment of the present disclosure;
[0046] Figure 29 This is a schematic diagram of the third diffusion barrier layer after etching back the first metal layer in one embodiment of the present disclosure;
[0047] Figure 30 This is a schematic diagram of a third type of diffusion barrier layer after forming a first sacrificial layer in an embodiment of the present disclosure;
[0048] Figure 31 This is a schematic diagram of the third diffusion barrier layer after etching back the first sacrificial layer in one embodiment of the present disclosure;
[0049] Figure 32 This is a schematic diagram of a third type of diffusion barrier layer after forming a second sacrificial layer in an embodiment of the present disclosure;
[0050] Figure 33This is a schematic diagram of the third diffusion barrier layer after etching back the second sacrificial layer in one embodiment of the present disclosure;
[0051] Figure 34 This is a schematic diagram of the third diffusion barrier layer after removing the first sacrificial layer in one embodiment of the present disclosure;
[0052] Figure 35 A schematic diagram of a third diffusion barrier layer after partial oxidation of the first sub-portion in an embodiment of the present disclosure;
[0053] Figure 36 This is a schematic diagram of the third diffusion barrier layer after removing the second sacrificial layer in one embodiment of the present disclosure;
[0054] Figure 37 This is a schematic diagram of a third diffusion barrier layer after a metal layer is formed in an embodiment of the present disclosure;
[0055] Figure 38 This is a schematic diagram of a third type of diffusion barrier layer after an isolation layer is formed in an embodiment of the present disclosure;
[0056] Figure 39 This is a schematic diagram of a third type of diffusion barrier layer after forming a first sacrificial layer in an embodiment of the present disclosure;
[0057] Figure 40 This is a schematic diagram of the third diffusion barrier layer after etching back the first sacrificial layer in one embodiment of the present disclosure;
[0058] Figure 41 This is a schematic diagram of a third type of diffusion barrier layer after forming a second sacrificial layer in an embodiment of the present disclosure;
[0059] Figure 42 This is a schematic diagram of the third diffusion barrier layer after etching back the second sacrificial layer in one embodiment of the present disclosure;
[0060] Figure 43 This is a schematic diagram of a third sacrificial layer formed in the third diffusion barrier layer in one embodiment of the present disclosure;
[0061] Figure 44 This is a schematic diagram of the third sacrificial layer after etching back in the third diffusion barrier layer in one embodiment of the present disclosure;
[0062] Figure 45 This is a schematic diagram of the third diffusion barrier layer after removing the first sacrificial layer in one embodiment of the present disclosure;
[0063] Figure 46 Another schematic diagram of the third diffusion barrier layer after partial oxidation of the first sub-portion in one embodiment of the present disclosure;
[0064] Figure 47This is a schematic diagram of the third sacrificial layer after removing the third diffusion barrier layer in one embodiment of the present disclosure;
[0065] Figure 48 This is a schematic diagram of a third diffusion barrier layer after a metal layer is formed in an embodiment of the present disclosure;
[0066] Figure 49 Another schematic diagram of the third diffusion barrier layer after forming an isolation layer in one embodiment of the present disclosure;
[0067] Figure 50 is a schematic structural diagram of a semiconductor structure in one embodiment of the present disclosure;
[0068] Figure 51 is another structural schematic diagram of a semiconductor structure in an embodiment of the present disclosure;
[0069] Figure 52 is another structural schematic diagram of a semiconductor structure in an embodiment of the present disclosure;
[0070] Figure 53 A process diagram of forming a gate dielectric layer of a semiconductor structure in one embodiment of the present disclosure;
[0071] Figure 54 FIG. 1 is a process diagram of forming a metal layer of a semiconductor structure in one embodiment of the present disclosure.
[0072] Description of reference numerals:
[0073] 10-substrate; 11-word line groove; 12-active pillar; 13-second isolation layer; 20-gate dielectric layer; 30-diffusion barrier layer; 31-first sub-section; 32-remaining sub-section; 33-second sub-section; 34-third sub-section; 40-metal layer; 41-first metal layer; 42-second metal layer; 51-first sacrificial layer; 52-second sacrificial layer; 53-third sacrificial layer; 60-first isolation layer. DETAILED DESCRIPTION
[0074] The prior art suffers from the problem of high resistance in wordline structures. The inventors have discovered that this is due to the fact that, to prevent ions in the metal layer from diffusing into other film layers, the diffusion barrier layer is often thicker. Because the resistance of the diffusion barrier layer is greater than that of the metal layer, the thicker diffusion barrier layer results in higher resistance in the wordline structure.
[0075] To this end, embodiments of the present disclosure provide a method for fabricating a semiconductor structure. A wordline trench is formed in a substrate, and a gate dielectric layer and a diffusion barrier layer conformally covering the wordline trench are formed. A first subsection of the diffusion barrier layer is exposed and partially oxidized. The oxidized first subsection reacts with a precursor used to form a metal layer and is removed. This reduces the volume of the diffusion barrier layer within the wordline trench, increases the volume of the metal layer within the wordline trench, and reduces the resistance of the semiconductor structure. Furthermore, the oxidized first subsection does not need to be removed separately; rather, the first subsection is simultaneously thinned during the metal layer formation process, simplifying the fabrication of the semiconductor structure.
[0076] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.
[0077] See Figure 1 The present disclosure provides a method for manufacturing a semiconductor structure, which may include the following steps:
[0078] Step S100: forming word line trenches in a substrate.
[0079] The substrate 10 includes a semiconductor substrate, which may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a silicon carbide substrate, or a gallium nitride substrate. Figure 2 , a word line trench 11 is formed in the substrate 10 , and there may be a plurality of word line trenches 11 , which are arranged at intervals.
[0080] In some examples, such as Figure 2 As shown, an active area and a shallow trench isolation structure defining the active area are formed in the semiconductor substrate. The active area includes a source region, a drain region, and a channel region. A wordline trench 11 passes through the active area and the shallow trench isolation structure. The active areas on either side of the wordline trench 11 are the source region and the drain region, respectively. The active area at the bottom of the wordline trench 11 forms a channel region, with the two ends of the channel region connecting the source region and the drain region, respectively. The wordline trench 11 is used to form a buried wordline structure, thereby forming the semiconductor structure into a recessed channel transistor.
[0081] For other examples, see Figure 53An active pillar 12 is formed in the semiconductor substrate. The active pillar 12 includes a source region, a channel region, and a drain region stacked in sequence. A word line trench 11 is formed on the side of the active pillar 12. The word line trench 11 exposes the channel region and is located on at least one side of the channel region or surrounds the channel region. The word line trench 11 is used to form a single-sided word line structure, a double-sided word line structure, or a fully surrounding word line structure, so that the semiconductor structure forms a vertical channel transistor. A second isolation layer 13 is provided between two adjacent columns of active pillars 12 to isolate different word line structures from each other.
[0082] Step S200: forming a gate dielectric layer conformally covering the word line trench.
[0083] See Figure 2 and Figure 3 A gate dielectric layer 20 is formed in the wordline trench 11, conformally covering the wordline trench 11. The gate dielectric layer 20 covers the inner wall of the wordline trench 11, and the outer wall of the gate dielectric layer 20 contacts the inner wall of the wordline trench 11. The shape of the gate dielectric layer 20 conforms to the shape of the inner wall of the wordline trench 11. The gate dielectric layer 20 does not completely fill the wordline trench 11; the gate dielectric layer 20 within the wordline trench 11 also forms a groove.
[0084] The gate dielectric layer 20 may be made of an insulating material, such as silicon oxide, and may have a thickness of 2 to 6 nm. The gate dielectric layer 20 may be formed by a thermal process or by in-situ steam generation (ISSG).
[0085] Step S300: forming a conformal diffusion barrier layer covering the gate dielectric layer, wherein the diffusion barrier layer located in the word line trench includes a first sub-portion and remaining sub-portions except the first sub-portion.
[0086] See Figure 4 A diffusion barrier layer 30 is formed on the gate dielectric layer 20, conformally covering the gate dielectric layer 20. The diffusion barrier layer 30 covers the inner wall of the gate dielectric layer 20, and the shape of the diffusion barrier layer 30 conforms to the shape of the gate dielectric layer 20. The diffusion barrier layer 30 does not completely fill the word line trench 11 covered by the gate dielectric layer 20, and the diffusion barrier layer 30 within the word line trench 11 also forms a groove.
[0087] The diffusion barrier layer 30 may be made of titanium nitride and may have a thickness of 2 nm to 5 nm. The diffusion barrier layer 30 may be formed at a process temperature of 400°C to 700°C by reactive plasma spraying, plasma enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), or metal organic chemical vapor deposition (MOVCD).
[0088] Among them, see Figure 5 The diffusion barrier layer 30 in the word line trench 11 includes a first sub-portion 31 and a remaining sub-portion 32. The remaining sub-portion 32 is the remaining portion of the diffusion barrier layer 30 in the word line trench 11 except the first sub-portion 31. The first sub-portion 31 and the remaining sub-portion 32 are connected to form a whole.
[0089] Step S400: covering the remaining sub-portions and exposing the first sub-portion, and oxidizing a portion of the first sub-portion.
[0090] A material is deposited on the exposed surface of the remaining sub-portion 32 to cover the remaining sub-portion 32 and expose the first sub-portion 31. A portion of the first sub-portion 31 is oxidized, that is, the exposed surface of the first sub-portion 31 is oxidized inward to a certain depth that is less than the thickness of the first sub-portion 31. The area of the first sub-portion 31 in contact with the gate dielectric layer 20 is not oxidized. In the example where the material of the diffusion barrier layer 30 includes titanium nitride, the material of the oxidized first sub-portion 31 includes titanium oxynitride.
[0091] Step S500 : forming a metal layer covering the diffusion barrier layer in the word line trench, wherein during the process of forming the metal layer, the oxidized first sub-portion reacts with a precursor for forming the metal layer and is removed.
[0092] See Figures 6 to 10 A metal layer 40 is formed within the wordline trench 11. The metal layer 40 covers the diffusion barrier layer 30. For example, the metal layer 40 completely fills the area enclosed by the diffusion barrier layer 30. During the formation of the metal layer 40, a precursor used to form the metal layer 40 reacts with the oxidized first sub-portion 31, removing the oxidized first sub-portion 31 and thinning the first sub-portion 31. This increases the volume of the metal layer 40 within the wordline trench 11, reduces the resistance of the metal layer 40, and improves the electrical performance of the semiconductor structure. Furthermore, the oxidized first sub-portion 31 does not need to be removed separately; that is, the first sub-portion 31 is thinned simultaneously during the formation of the metal layer 40, simplifying the fabrication steps of the semiconductor structure.
[0093] The metal layer 40 can be made of tungsten and have a thickness of 10 to 50 nm. It can be formed by chemical vapor deposition at a process temperature of 200 to 500°C. The material of the oxidized first sub-portion 31 includes titanium oxynitride, and the precursor material includes tungsten hexafluoride. Titanium oxynitride reacts with tungsten hexafluoride to form gaseous titanium tetrafluoride, which is then removed. By oxidizing a portion of the first sub-portion 31 and removing the oxidized first sub-portion 31, the volume of the remaining first sub-portion 31 is reduced. The precursor material may also include hydrogen, silane, and diborane. Hydrogen, silane, diborane, and tungsten hexafluoride react and deposit to form tungsten.
[0094] It is understood that in the example where the semiconductor structure is formed as a recessed channel transistor, the manufacturing process of the semiconductor structure can be referred to in Figures 6 to 10 In the example of forming a semiconductor structure as a vertical channel transistor, the manufacturing process of the semiconductor structure can be referred to Figure 53 and Figure 54 , but not limited thereto. It is understood that both the word line structure in the vertical channel transistor and the word line structure in the recessed channel transistor are buried word line structures. Therefore, the fabrication method of one (e.g., the word line structure in the recessed channel transistor) can be referenced to fabricate the other (e.g., the word line structure in the vertical channel transistor), and detailed description thereof will not be repeated here.
[0095] In some examples, after forming a metal layer covering the diffusion barrier layer in the word line trench (step S500 ), the method further includes:
[0096] Step S600: etching back the diffusion barrier layer and the metal layer, wherein the top surface of the retained diffusion barrier layer is lower than the top surface of the retained metal layer.
[0097] See Figure 10 The diffusion barrier layer 30 and the metal layer 40 are etched back to remove portions of the diffusion barrier layer 30 and the metal layer 40 away from the bottom of the word line trench 11, while retaining portions of the diffusion barrier layer 30 and the metal layer 40 near the bottom of the word line trench 11. The top surface of the retained diffusion barrier layer 30 is lower than the top surface of the retained metal layer 40. The top surface of the retained diffusion barrier layer 30 is 30 to 120 nm from the top surface of the substrate 10, and the top surface of the retained metal layer 40 is 30 to 90 nm from the top surface of the substrate 10.
[0098] Step S700: forming an isolation layer, where the isolation layer covers the retained diffusion barrier layer and the retained metal layer and fills the word line trench.
[0099] A first isolation layer 60 (also referred to as the "first isolation layer" to distinguish it from the second isolation layer 13) is formed on the retained diffusion barrier layer 30 and the retained metal layer 40. That is, the first isolation layer 60 covers the top surface of the retained diffusion barrier layer 30 and the top surface of the retained metal layer 40. The first isolation layer 60 also fills the wordline trench 11, that is, the top surface of the first isolation layer 60 is at least flush with the top surface of the substrate 10. For example, the first isolation layer 60 is formed by deposition and then etching back or planarization.
[0100] Because the top surface of the retained diffusion barrier layer 30 is lower than the top surface of the retained metal layer 40, a portion of the first isolation layer 60 is located on the diffusion barrier layer 30 and fills the gap between the diffusion barrier layer 30 and the gate dielectric layer 20 to reduce leakage. The material of the first isolation layer 60 can be an insulating material, such as silicon nitride.
[0101] In summary, the fabrication method in the disclosed embodiments forms a gate dielectric layer 20 conformally covering the wordline trench 11, and forms a diffusion barrier layer 30 conformally covering the gate dielectric layer 20. The first sub-portion 31 of the diffusion barrier layer 30 is exposed and partially oxidized. The oxidized first sub-portion 31 reacts with a precursor used to form the metal layer 40 and is removed, thereby thinning the first sub-portion 31, reducing the volume of the diffusion barrier layer 30 within the wordline trench 11, increasing the volume of the metal layer 40 within the wordline trench 11, and reducing the resistance of the semiconductor structure. Furthermore, the oxidized first sub-portion 31 does not need to be removed separately; rather, the first sub-portion 31 is thinned simultaneously during the formation of the metal layer 40, simplifying the fabrication of the semiconductor structure.
[0102] See Figure 5 The first sub-portion 31 is located on a side of the remaining sub-portion 32 away from the bottom of the wordline trench 11. That is, the remaining sub-portion 32 is close to the bottom of the wordline trench 11, and the first sub-portion 31 is close to the opening of the wordline trench 11. The top surface of the first sub-portion 31 can be flush with the top surface of the substrate 10. The thickness of the first sub-portion 31 is equal to the thickness of the remaining sub-portion 32, so as to facilitate the formation of the first sub-portion 31 and the remaining sub-portion 32.
[0103] For some possible examples, see Figure 6 and Figure 7 , covering the remaining sub-portion 32 and exposing the first sub-portion 31, including: forming a first metal layer 41 covering the diffusion barrier layer 30 and filling the word line trench 11; etching back the first metal layer 41, wherein the retained first metal layer 41 covers the remaining sub-portion 32.
[0104] like Figure 6As shown, a first metal layer 41 is deposited in the word line trench 11 where the gate dielectric layer 20 and the diffusion barrier layer 30 are formed. The first metal layer 41 fills the remaining word line trench 11 and may also cover the surface of the substrate 10. The first metal layer 41 is etched back, and the remaining first metal layer 41 covers the remaining sub-portion 32, so that at least a portion of the first sub-portion 31 is exposed. Figure 7 As shown, the retained first metal layer 41 may fill the bottom of the remaining word line trench 11. Alternatively, the retained first metal layer 41 conformally covers the surface of the remaining sub-portion 32, that is, the shape of the retained first metal layer 41 is adapted to the shape of the remaining sub-portion 32.
[0105] Accordingly, see Figures 8 to 10 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line trench 11, including: forming a second metal layer 42 covering the first sub-portion 31 and filling the word line trench 11; wherein the metal layer 40 includes the retained first metal layer 41 and the second metal layer 42.
[0106] like Figure 8 and Figure 9 As shown, a second metal layer 42 is deposited in the word line trench 11 where the gate dielectric layer 20, the diffusion barrier layer 30, and the first metal layer 41 are formed. The second metal layer 42 completely fills the word line trench 11. The second metal layer 42 covers the retained first metal layer 41 and the remaining first sub-portion 31 of the diffusion barrier layer 30. The second metal layer 42 and the retained first metal layer 41 form a metal layer 40. The material of the first metal layer 41 can be the same as that of the second metal layer 42, so that the first metal layer 41 and the second metal layer 42 form an integrated whole, thereby reducing the resistance of the metal layer 40. Figure 10 As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40. The first isolation layer 60 fills the word line trench.
[0107] For other possible examples, see Figure 11 and Figure 12 , covering the remaining sub-portion 32 and exposing the first sub-portion 31 , including: forming a first sacrificial layer 51 covering the diffusion barrier layer 30 and filling the word line trench 11 ; etching back the first sacrificial layer 51 , wherein the retained first sacrificial layer 51 covers the remaining sub-portion 32 .
[0108] like Figure 11 As shown, a first sacrificial layer 51 is deposited in the word line trench 11. The first sacrificial layer 51 covers the diffusion barrier layer 30 and at least fills the word line trench 11. That is, the gate dielectric layer 20, the diffusion barrier layer 30 and the first sacrificial layer 51 completely fill the word line trench 11. Figure 12As shown, the first sacrificial layer 51 is etched back, and the remaining first sacrificial layer 51 covers the remaining sub-portion 32, so that at least a portion of the first sub-portion 31 is exposed. The remaining first sacrificial layer 51 can completely fill the bottom of the remaining word line trench 11, or the remaining first sacrificial layer 51 can conformally cover the surface of the remaining sub-portion 32, that is, the shape of the retained first metal layer 41 is adapted to the shape of the remaining sub-portion 32.
[0109] Accordingly, see Figures 13 to 15 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line trench 11 , including: removing the first sacrificial layer 51 ; and forming a metal layer 40 covering the diffusion barrier layer 30 and filling the word line trench 11 .
[0110] like Figure 13 and Figure 14 As shown, after the exposed first sub-portion 31 is partially oxidized, the first sacrificial layer 51 is etched away to expose the remaining sub-portion 32. Figure 15 As shown, a metal layer 40 is deposited in the word line trench 11. The metal layer 40 covers the diffusion barrier layer 30 and fills the word line trench 11. The metal layer 40 is formed in one step, and the manufacturing process is simple. Figure 16 As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40 . The first isolation layer 60 fills the word line trench 11 .
[0111] See Figure 17 In some examples, the remaining sub-portion 32 is located on a side of the first sub-portion 31 away from the bottom of the wordline trench 11. That is, the first sub-portion 31 is close to the bottom of the wordline trench 11, and the remaining sub-portion 32 is close to the opening of the wordline trench 11. The top surface of the remaining sub-portion 32 can be flush with the top surface of the substrate 10. The thickness of the first sub-portion 31 is equal to the thickness of the remaining sub-portion 32, so as to facilitate the formation of the first sub-portion 31 and the remaining sub-portion 32.
[0112] See Figures 18 to 22 , covering the remaining sub-portion 32 and exposing the first sub-portion 31, including: forming a first sacrificial layer 51 covering the diffusion barrier layer 30 and filling the word line trench 11; etching back the first sacrificial layer 51, wherein the retained first sacrificial layer 51 covers the first sub-portion 31; forming a second sacrificial layer 52 conformally covering the remaining sub-portion 32 and the first sacrificial layer 51; etching back the second sacrificial layer 52, wherein the second sacrificial layer 52 retained in the word line trench 11 only covers the remaining sub-portion 32; and removing the retained first sacrificial layer 51.
[0113] like Figure 18 As shown, a first sacrificial layer 51 is deposited in the word line trench 11. The first sacrificial layer 51 covers the diffusion barrier layer 30 and at least fills the word line trench 11. Figure 19As shown, the first sacrificial layer 51 is etched back, and the remaining first sacrificial layer 51 covers the first sub-portion 31, so that the remaining sub-portion 32 is exposed. The remaining first sacrificial layer 51 can fill the bottom of the remaining word line trench 11, or the remaining first sacrificial layer 51 can conformally cover the surface of the first sub-portion 31, that is, the shape of the retained first metal layer 41 is adapted to the shape of the remaining sub-portion 32.
[0114] like Figure 20 As shown, a second sacrificial layer 52 is deposited on the remaining sub-portion 32 and the first sacrificial layer 51. The second sacrificial layer 52 conformally covers the remaining sub-portion 32 and the first sacrificial layer 51, that is, the second sacrificial layer 52 does not fill the word line trench 11. Figure 21 As shown, the second sacrificial layer 52 is etched back to remove at least a portion of the second sacrificial layer 52 on the first sacrificial layer 51 to expose the first sacrificial layer 51, and the second sacrificial layer 52 on the remaining sub-portion 32 is retained to cover the remaining sub-portion 32. Figure 22 As shown, the first sacrificial layer 51 is removed to expose the first sub-portion 31 .
[0115] Accordingly, see Figures 23 to 26 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line trench 11 , including: removing the retained second sacrificial layer 52 ; and forming a metal layer 40 covering the diffusion barrier layer 30 and filling the word line trench 11 .
[0116] like Figure 23 and Figure 24 As shown, after the exposed first sub-portion 31 is partially oxidized, the retained second sacrificial layer 52 is etched to expose the remaining sub-portion 32, thereby exposing the remaining diffusion barrier layer 30. Figure 25 As shown, a metal layer 40 is deposited in the word line trench 11, and the metal layer 40 covers the diffusion barrier layer 30 and fills the word line trench 11. Figure 26 As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40 . The first isolation layer 60 fills the word line trench 11 .
[0117] See Figure 27 In some examples, the remaining sub-portion 32 includes a second sub-portion 33 and a third sub-portion 34, and the second sub-portion 33 and the third sub-portion 34 are respectively located on both sides of the first sub-portion 31. The second sub-portion 33 is located on the side of the first sub-portion 31 close to the bottom of the wordline trench 11, and the third sub-portion 34 is located on the side of the first sub-portion 31 away from the bottom of the wordline trench 11. That is, in a direction away from the bottom of the wordline trench 11, the second sub-portion 33, the first sub-portion 31, and the third sub-portion 34 are arranged in sequence.
[0118] For some possible implementations, see Figures 28 to 34, covering the remaining sub-portion 32 and exposing the first sub-portion 31, including: forming a first metal layer 41 covering the diffusion barrier layer 30 and filling the full word line trench 11; etching back the first metal layer 41, wherein the retained first metal layer 41 covers the second sub-portion 33; forming a first sacrificial layer 51 covering the first sub-portion 31 and the third sub-portion 34 and filling the full word line trench 11; etching back the first sacrificial layer 51, wherein the retained first sacrificial layer 51 covers the first sub-portion 31; forming a second sacrificial layer 52 conformally covering the third sub-portion 34 and the first sacrificial layer 51; etching back the second sacrificial layer 52, wherein the second sacrificial layer 52 retained in the word line trench 11 only covers the third sub-portion 34; and removing the retained first sacrificial layer 51.
[0119] like Figure 28 As shown, a first metal layer 41 is deposited in the word line trench 11. The first metal layer 41 fills the word line trench 11 and covers the diffusion barrier layer 30. That is, the first metal layer 41, the diffusion barrier layer 30 and the gate dielectric layer 20 fully fill the word line trench 11. Figure 29 As shown, the first metal layer 41 is etched back to remove part of the first metal layer 41 , and the remaining first metal layer 41 covers the second sub-portion 33 , while the first sub-portion 31 and the third sub-portion 34 are exposed, that is, the remaining first metal layer 41 is close to the bottom of the word line trench 11 .
[0120] like Figure 30 As shown, a first sacrificial layer 51 is deposited in the word line trench 11, and the first sacrificial layer 51 fills the word line trench 11. The first sacrificial layer 51 is located on the first metal layer 41 and covers the first sub-portion 31 and the third sub-portion 34. That is, the first sacrificial layer 51, the first metal layer 41, the diffusion barrier layer 30 and the gate dielectric layer 20 completely fill the word line trench 11. Figure 31 As shown, the first sacrificial layer 51 is etched back to remove a portion of the first sacrificial layer 51. The remaining first sacrificial layer 51 covers the first sub-portion 31. That is, the remaining first sacrificial layer 51 covers the surface of the first sub-portion 31, and the third sub-portion 34 is exposed. For example, the remaining first sacrificial layer 51 is opposite to the first sub-portion 31 and fills the space between the first sub-portions 31.
[0121] like Figure 32 As shown, a second sacrificial layer 52 is formed on the first sacrificial layer 51 and the third sub-portion 34. The second sacrificial layer 52 conformally covers the surface of the first sacrificial layer 51 and the surface of the third sub-portion 34, that is, the second sacrificial layer 52 does not fill the word line trench 11. Figure 33 As shown, the second sacrificial layer 52 is etched back to remove the second sacrificial layer 52 on the first sacrificial layer 51. The remaining second sacrificial layer 52 only covers the third sub-portion 34, and the first sacrificial layer 51 is exposed. Figure 34As shown, the exposed first sacrificial layer 51 is then used to remove the remaining first sacrificial layer 51 , so as to remove the entire first sacrificial layer 51 and expose the first sub-portion 31 .
[0122] Accordingly, see Figures 35 to 37 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line trench 11, including: removing the retained second sacrificial layer 52; forming a second metal layer 42 covering the first sub-portion 31 and the third sub-portion 34 and filling the word line trench 11; wherein the metal layer 40 includes the retained first metal layer 41 and the second metal layer 42.
[0123] like Figure 35 and Figure 36 As shown, the second sacrificial layer 52 on the third sub-portion 34 is removed, that is, the retained second sacrificial layer 52 is removed to expose the third sub-portion 34. After removing the second sacrificial layer 52, both the first sub-portion 31 and the third sub-portion 34 are exposed. Figure 37 As shown, a second metal layer 42 is formed in the word line trench 11, and the second metal layer 42 fills the word line trench 11. The second metal layer 42 is located on the first metal layer 41 and covers the first sub-section 31 and the third sub-section 34. The second metal layer 42, the first metal layer 41, the diffusion barrier layer 30 and the gate dielectric layer 20 fill the word line trench 11. The metal layer 40 includes the retained first metal layer 41 and the second metal layer 42. Figure 38 As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40 . The first isolation layer 60 fills the word line trench 11 .
[0124] For other possible implementations, see Figures 39 to 45 , covering the remaining sub-portion 32 and exposing the first sub-portion 31, including: forming a first sacrificial layer 51 covering the diffusion barrier layer 30 and filling the full word line trench 11; etching back the first sacrificial layer 51, wherein the retained first sacrificial layer 51 covers the second sub-portion 33; forming a second sacrificial layer 52 covering the first sub-portion 31 and the third sub-portion 34 and filling the full word line trench 11; etching back the second sacrificial layer 52, wherein the retained second sacrificial layer 52 covers the first sub-portion 31; forming a third sacrificial layer 53 conformally covering the third sub-portion 34 and the second sacrificial layer 52; etching back the third sacrificial layer 53, wherein the third sacrificial layer 53 retained in the word line trench 11 only covers the third sub-portion 34; and removing the retained second sacrificial layer 52.
[0125] like Figure 39 As shown, a first sacrificial layer 51 is deposited in the word line trench 11. The first sacrificial layer 51 fills the word line trench 11 and covers the diffusion barrier layer 30. That is, the first sacrificial layer 51, the diffusion barrier layer 30 and the gate dielectric layer 20 fully fill the word line trench 11. Figure 40As shown, the first sacrificial layer 51 is etched back to remove part of the first sacrificial layer 51 , and the remaining first sacrificial layer 51 covers the second sub-portion 33 , while the first sub-portion 31 and the third sub-portion 34 are exposed, that is, the remaining first sacrificial layer 51 is close to the bottom of the word line trench 11 .
[0126] like Figure 41 As shown, a second sacrificial layer 52 is deposited in the word line trench 11, and the second sacrificial layer 52 fills the word line trench 11. The second sacrificial layer 52 is located on the first sacrificial layer 51 and covers the first sub-portion 31 and the third sub-portion 34. That is, the first sacrificial layer 51, the second sacrificial layer 52, the diffusion barrier layer 30 and the gate dielectric layer 20 fill the word line trench 11. Figure 42 As shown, the second sacrificial layer 52 is etched back to remove a portion of the second sacrificial layer 52. The remaining second sacrificial layer 52 covers the first sub-portion 31. That is, the remaining second sacrificial layer 52 covers the surface of the first sub-portion 31, and the third sub-portion 34 is exposed. For example, the remaining second sacrificial layer 52 is opposite to the first sub-portion 31 and fills the space between the first sub-portions 31.
[0127] like Figure 43 As shown, a third sacrificial layer 53 is formed on the second sacrificial layer 52 and the third sub-portion 34. The third sacrificial layer 53 conformally covers the surface of the second sacrificial layer 52 and the surface of the third sub-portion 34, that is, the third sacrificial layer 53 does not fill the word line trench 11. Figure 44 As shown, the third sacrificial layer 53 is etched back to remove the third sacrificial layer 53 on the second sacrificial layer 52. The remaining third sacrificial layer 53 only covers the third sub-portion 34, and the second sacrificial layer 52 is exposed. The exposed second sacrificial layer is then used to remove the remaining second sacrificial layer, thereby removing the entire second sacrificial layer and exposing the first sub-portion.
[0128] Accordingly, see Figures 46 to 49 , forming a metal layer 40 covering the diffusion barrier layer 30 in the word line trench 11, including: removing the retained third sacrificial layer 53 and the retained first sacrificial layer 51; forming a metal layer 40 covering the diffusion barrier layer 30 and filling the word line trench 11.
[0129] like Figure 46 and Figure 47 As shown, the third sacrificial layer 53 on the third sub-portion 34 and the first sacrificial layer 51 on the second sub-portion 33 are removed, and the first sub-portion 31, the second sub-portion 33 and the third sub-portion 34 are all exposed. At this time, only the gate dielectric layer 20 and the partially thinned diffusion barrier layer 30 are present in the word line trench 11. Figure 48 As shown, a metal layer 40 is formed in the word line trench 11. The metal layer 40 fills the word line trench 11, and the top surface of the metal layer 40 is flush with the top surface of the substrate 10. Figure 49As shown, the diffusion barrier layer 30 and the metal layer 40 are etched back, and then a first isolation layer 60 is formed on the remaining diffusion barrier layer 30 and the remaining metal layer 40 . The first isolation layer 60 fills the word line trench 11 .
[0130] See Figure 50 、 Figure 51 and Figure 52 The present disclosure also provides a semiconductor structure including a substrate 10 and a wordline structure. A wordline trench 11 is provided in the substrate 10, and the wordline structure is provided in the wordline trench 11. The substrate 10 includes a semiconductor substrate, which may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, a silicon carbide substrate, or a gallium nitride substrate.
[0131] In some examples, a semiconductor substrate includes an active region and a shallow trench isolation structure defining the active region, wherein the active region includes a source region, a drain region, and a channel region. A wordline structure passes through the active region and the shallow trench isolation structure, forming a buried wordline structure, i.e., a wordline structure that forms a recessed channel transistor, thereby forming the semiconductor structure into a recessed channel transistor.
[0132] In other examples, the semiconductor substrate includes an active pillar, the active pillar includes a source region, a channel region and a drain region arranged in a stacked manner, the word line structure exposes the channel region, which is located on at least one side of the channel region or surrounds the channel region, and the word line structure is formed as a single-sided word line structure, a double-sided word line structure or a fully surrounding word line structure, that is, the word line structure is a word line structure of a vertical channel transistor, so that the semiconductor structure forms a vertical channel transistor.
[0133] The word line structure includes a gate dielectric layer 20, a diffusion barrier layer 30, a metal layer 40 and a first isolation layer 60. The gate dielectric layer 20 conformally covers the word line trench 11, the diffusion barrier layer 30 covers the gate dielectric layer 20, the metal layer 40 covers the diffusion barrier layer 30, and the first isolation layer 60 covers the top surfaces of the diffusion barrier layer 30 and the metal layer 40 and fills the word line trench 11. The diffusion barrier layer 30 includes a first sub-portion 31 and a remaining sub-portion 32 other than the first sub-portion 31. The thickness of the first sub-portion 31 is less than the thickness of the remaining sub-portion 32.
[0134] The gate dielectric layer 20 conformally covers the wordline trench 11. The shape of the gate dielectric layer 20 matches the shape of the wordline trench 11, that is, the gate dielectric layer 20 is groove-shaped. The material of the gate dielectric layer 20 can be an insulating material, such as silicon oxide, and the thickness of the gate dielectric layer 20 can be 2 to 6 nm.
[0135] Diffusion barrier layer 30 covers the side of gate dielectric layer 20 near the bottom of wordline trench 11. The shape of diffusion barrier layer 30 matches the shape of gate dielectric layer 20 it covers, that is, diffusion barrier layer 30 also has a groove shape. Diffusion barrier layer 30 can be made of titanium nitride and can have a thickness of 2 nm to 5 nm.
[0136] The diffusion barrier layer 30 includes a first sub-portion 31 and a remaining sub-portion 32 excluding the first sub-portion 31. The thickness of the first sub-portion 31 is smaller than that of the remaining sub-portion 32, and the first sub-portion 31 and the remaining sub-portion 32 are connected to form a single body. By thinning the first sub-portion 31, the volume of the diffusion barrier layer 30 is reduced, providing more space for the wordline trench 11 in the metal layer 40, increasing the volume of the metal layer 40, and reducing the resistance of the wordline structure.
[0137] In some examples, such as Figure 50 As shown, the first sub-portion 31 is located on the side of the remaining sub-portion 32 away from the bottom of the word line trench 11; or Figure 51 As shown, the remaining sub-portion 32 is located on a side of the first sub-portion 31 away from the bottom of the word line trench 11. When the first sub-portion 31 is located on a side of the remaining sub-portion 32 away from the bottom of the word line trench 11, since the first sub-portion 31 is thicker than the remaining sub-portion 32, the diffusion barrier layer 30 near the bottom of the word line trench 11 is thicker, which can also reduce gate-induced drain leakage (GIDL).
[0138] For other examples, see Figure 52 The remaining subsections include a second subsection 33 and a third subsection 34. The second subsection 33 is located on the side of the first subsection 31 closer to the bottom of the wordline trench 11, and the third subsection 34 is located on the side of the first subsection 31 farther from the bottom of the wordline trench 11. This arrangement allows the diffusion barrier layer 30 to be thicker near the bottom of the wordline trench 11, thereby reducing gate-induced drain leakage. The thickness of the third subsection 34 and the second subsection 33 can be equal.
[0139] The metal layer 40 covers the diffusion barrier layer 30 and completely fills the bottom of the wordline trench 11. The material of the metal layer 40 can be tungsten, and the thickness of the metal layer 40 can be 10 to 50 nm. In some examples, the metal layer 40 can also extend beyond the area enclosed by the diffusion barrier layer 30, that is, the top surface of the metal layer 40 can be higher than the top surface of the diffusion barrier layer 30, and the metal layer 40 is separated from the gate dielectric layer 20. This configuration can, on the one hand, increase the volume of the metal layer 40 and reduce the resistance of the metal layer 40. On the other hand, the first isolation layer 60 is partially filled between the metal layer 40 and the gate dielectric layer 20, which can reduce leakage.
[0140] The first isolation layer 60 is located on the diffusion barrier layer 30 and the metal layer 40 to cover the top surfaces of the diffusion barrier layer 30 and the metal layer 40. The first isolation layer 60 is also located in the region opposite the gate dielectric layer 20 to fill the wordline trench 11. The material of the first isolation layer 60 can be a nitride, such as silicon nitride.
[0141] In summary, the semiconductor structure in the embodiment of the present disclosure includes a substrate 10 and a word line structure arranged in the substrate 10, and the diffusion barrier layer 30 in the word line structure includes a first sub-portion 31 and a remaining sub-portion 32 other than the first sub-portion 31, and the thickness of the first sub-portion 31 is less than the thickness of the remaining sub-portion 32, so as to reduce the volume of the diffusion barrier layer 30, increase the volume of the metal layer 40 covering the diffusion barrier layer 30, and reduce the resistance of the word line structure.
[0142] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a word line trench in the substrate; forming a gate dielectric layer conformally covering the word line trench; forming a diffusion barrier layer conformally covering the gate dielectric layer, wherein the diffusion barrier layer located in the word line trench includes a first sub-portion and remaining sub-portions except the first sub-portion; covering the remaining sub-portion and exposing the first sub-portion, and oxidizing a portion of the first sub-portion; A metal layer covering the diffusion barrier layer is formed in the word line trench, wherein during the formation of the metal layer, the oxidized first sub-portion reacts with a precursor for forming the metal layer and is removed.
2. The production method according to claim 1, characterized in that The first sub-portion is located on a side of the remaining sub-portion away from the bottom of the word line trench; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first metal layer covering the diffusion barrier layer and filling the word line trench; Etching back the first metal layer, wherein the remaining first metal layer covers the remaining sub-portion; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: A second metal layer is formed to cover the first sub-portion and completely fill the word line trench; wherein the metal layer includes the retained first metal layer and the second metal layer.
3. The production method according to claim 1, characterized in that The first sub-portion is located on a side of the remaining sub-portion away from the bottom of the word line trench; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first sacrificial layer covering the diffusion barrier layer and filling the word line trench; Etching back the first sacrificial layer, wherein the remaining first sacrificial layer covers the remaining sub-portion; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: removing the first sacrificial layer; The metal layer is formed to cover the diffusion barrier layer and fill the word line trench.
4. The production method according to claim 1, characterized in that The remaining sub-portion is located on a side of the first sub-portion away from the bottom of the word line trench; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first sacrificial layer covering the diffusion barrier layer and filling the word line trench; Etching back the first sacrificial layer, wherein the remaining first sacrificial layer covers the first sub-portion; forming a second sacrificial layer conformally covering the remaining sub-portion and the first sacrificial layer; Etching back the second sacrificial layer, wherein the second sacrificial layer remaining in the word line trench only covers the remaining sub-portion; removing the retained first sacrificial layer; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: removing the retained second sacrificial layer; The metal layer is formed to cover the diffusion barrier layer and fill the word line trench.
5. The production method according to claim 1, characterized in that: The remaining sub-portions include a second sub-portion and a third sub-portion, wherein the second sub-portion is located on a side of the first sub-portion close to the bottom of the word line trench, and the third sub-portion is located on a side of the first sub-portion away from the bottom of the word line trench; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first metal layer covering the diffusion barrier layer and filling the word line trench; Etching back the first metal layer, wherein the remaining first metal layer covers the second sub-portion; forming a first sacrificial layer covering the first sub-portion and the third sub-portion and filling the word line trench; Etching back the first sacrificial layer, wherein the remaining first sacrificial layer covers the first sub-portion; forming a second sacrificial layer conformally covering the third sub-portion and the first sacrificial layer; etching back the second sacrificial layer, wherein the second sacrificial layer remaining in the word line trench only covers the third sub-portion; removing the retained first sacrificial layer; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: removing the retained second sacrificial layer; A second metal layer is formed to cover the first sub-portion and the third sub-portion and to completely fill the word line trench; wherein the metal layer includes the retained first metal layer and the second metal layer.
6. The production method according to claim 1, characterized in that: The remaining sub-portions include a second sub-portion and a third sub-portion, wherein the second sub-portion is located on a side of the first sub-portion close to the bottom of the word line trench, and the third sub-portion is located on a side of the first sub-portion away from the bottom of the word line trench; Covering the remaining sub-portions and exposing the first sub-portion, comprising: forming a first sacrificial layer covering the diffusion barrier layer and filling the word line trench; Etching back the first sacrificial layer, wherein the remaining first sacrificial layer covers the second sub-portion; forming a second sacrificial layer covering the first sub-portion and the third sub-portion and filling the word line trench; Etching back the second sacrificial layer, wherein the remaining second sacrificial layer covers the first sub-portion; forming a third sacrificial layer conformally covering the third sub-portion and the second sacrificial layer; Etching back the third sacrificial layer, wherein the third sacrificial layer remaining in the word line trench only covers the third sub-portion; removing the retained second sacrificial layer; Forming the metal layer covering the diffusion barrier layer in the word line trench, comprising: removing the retained third sacrificial layer and the retained first sacrificial layer; The metal layer is formed to cover the diffusion barrier layer and fill the word line trench.
7. The production method according to any one of claims 1 to 6, characterized in that: After forming the metal layer covering the diffusion barrier layer in the word line trench, the method further includes: Etching back the diffusion barrier layer and the metal layer, wherein a top surface of the remaining diffusion barrier layer is lower than a top surface of the remaining metal layer; An isolation layer is formed, where the isolation layer covers the remaining diffusion barrier layer and the remaining metal layer and completely fills the word line trench.
8. The production method according to any one of claims 1 to 6, characterized in that: The diffusion barrier layer is made of titanium nitride, the oxidized first sub-portion is made of titanium oxynitride, the metal layer is made of tungsten, and the precursor is made of tungsten hexafluoride.
9. A semiconductor structure prepared according to any one of claims 1 to 8, characterized in that: include: a substrate and a wordline trench located in the substrate; a word line structure located in the word line trench, the word line structure comprising a gate dielectric layer, a diffusion barrier layer, a metal layer, and an isolation layer, the gate dielectric layer conformally covering the word line trench, the diffusion barrier layer covering the gate dielectric layer, the metal layer covering the diffusion barrier layer, the isolation layer covering top surfaces of the diffusion barrier layer and the metal layer, and completely filling the word line trench; The diffusion barrier layer includes a first sub-portion and remaining sub-portions except the first sub-portion, and a thickness of the first sub-portion is smaller than a thickness of the remaining sub-portion.
10. The semiconductor structure according to claim 9, wherein: The first sub-portion is located on a side of the remaining sub-portion away from the bottom of the word line trench; Alternatively, the remaining sub-portion is located on a side of the first sub-portion away from the bottom of the word line trench.
11. The semiconductor structure according to claim 9, wherein: The remaining sub-portions include a second sub-portion and a third sub-portion. The second sub-portion is located on a side of the first sub-portion close to the bottom of the word line trench. The third sub-portion is located on a side of the first sub-portion away from the bottom of the word line trench.
12. The semiconductor structure according to any one of claims 9 to 11, characterized in that: The word line structure serves as a word line structure of a recessed channel transistor or a vertical channel transistor.
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