Array substrate, driving method and display device

Abstract

The invention discloses an array substrate, a driving method thereof and a display device. In each row of sub-pixels of the array substrate, two adjacent grid lines in a plurality of grid lines are connected; at least one data line is connected with two adjacent columns of sub-pixels; the plurality of rows of sub-pixels comprise a plurality of groups of sub-pixels, each group of sub-pixels comprises partial rows of sub-pixels, each row of sub-pixels comprises sub-pixels connected with the same grid line, and the charging time of the partial rows of sub-pixels is overlapped; the partial row sub-pixels comprise a first part row sub-pixel and a second part row sub-pixel, the charging time of the second part row sub-pixel is longer than the charging time of the first part row sub-pixel, and the first part row sub-pixel and the second part row sub-pixel write the same data signal in a first time period overlapped by the charging time, and the first part row sub-pixel and the second part row sub-pixel write the same data signal in a second time period overlapped by the charging time. And in a second time period in which the charging time is not overlapped, the data signals written in the second part of row sub-pixels are at least partially the same as the data signals written in the first time period. The array substrate can realize an HST mode of a double-gate pixel driving structure.

Description

Array substrate, driving method and display device Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate, a driving method, and a display device. Background Art

[0002] In the field of display technology, for example, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines arranged to intersect with the gate lines. The driving of the gate lines can be achieved by a gate drive circuit. The driving of the data lines can be achieved by a source drive circuit. For example, the gate drive circuit provides a switching state voltage signal (gate signal) for the plurality of rows of gate lines of the pixel array, thereby, for example, controlling the plurality of rows of gate lines to be opened in sequence, and simultaneously providing a data signal by the data line to the pixel units of the corresponding rows in the pixel array, so as to form the grayscale voltage required for each grayscale of the display image in each pixel unit, thereby displaying a frame of image.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides an array substrate, comprising a pixel array formed by multiple rows and columns of sub-pixels, wherein multiple gate lines and multiple data lines intersect to define the multiple rows and columns of sub-pixels, wherein each row of sub-pixels is connected to two adjacent gate lines among the multiple gate lines; at least one data line among the multiple data lines is connected to two adjacent columns of sub-pixels among the multiple columns of sub-pixels; the multiple gate lines are used to turn on the multiple rows of sub-pixels, and the multiple data lines are used to charge the multiple columns of turned-on sub-pixels; the multiple rows of sub-pixels include multiple groups of sub-pixels, each group of sub-pixels includes some rows of sub-pixels among the multiple rows of sub-pixels, and each row of the some rows of sub-pixels includes multiple groups of sub-pixels. The sub-pixels include sub-pixels connected to the same gate line, and the charging times of the partial row sub-pixels overlap; the partial row sub-pixels include a first portion of row sub-pixels and a second portion of row sub-pixels, the charging time of the second portion of row sub-pixels is longer than the charging time of the first portion of row sub-pixels, and within a first time period where the charging times overlap, the first portion of row sub-pixels and the second portion of row sub-pixels are written with the same data signal, and within a second time period where the charging times do not overlap, the data signal written by the second portion of row sub-pixels is at least partially the same as the data signal written within the first time period.

[0005] For example, in the array substrate provided by an embodiment of the present disclosure, in some rows of sub-pixels, the same data line is connected to multiple sub-pixels corresponding to the same color.

[0006] For example, in the array substrate provided in one embodiment of the present disclosure, the charging time of the first part of the row sub-pixels is the charging time of one row of sub-pixels, the charging time of the second part of the row sub-pixels is the charging time of two rows of sub-pixels, and the first part of the row sub-pixels and the second part of the row sub-pixels start charging at the same time.

[0007] For example, in an array substrate provided in an embodiment of the present disclosure, the same data line connects multiple groups of sub-pixels, and multiple sub-pixels of the same color connected on the same data line are connected to gate lines of odd rows or to gate lines of even rows.

[0008] For example, in the array substrate provided in an embodiment of the present disclosure, sub-pixels in the same column correspond to the same color, multiple sub-pixels corresponding to red are connected to the gate lines of odd rows, multiple sub-pixels corresponding to green are connected to the gate lines of even rows, and multiple sub-pixels corresponding to blue connected to the same data line are connected to multiple gate lines of odd rows or are all connected to multiple gate lines of even rows; or multiple sub-pixels corresponding to green are connected to the gate lines of odd rows, multiple sub-pixels corresponding to blue are connected to the gate lines of even rows, and multiple sub-pixels corresponding to red connected to the same data line are connected to multiple gate lines of odd rows or are connected to multiple gate lines of even rows; or multiple sub-pixels corresponding to red are all connected to the gate lines of odd rows, multiple sub-pixels corresponding to blue are all connected to the gate lines of even rows, and multiple sub-pixels corresponding to green connected to the same data line are all connected to multiple gate lines of odd rows or are all connected to multiple gate lines of even rows.

[0009] For example, in the array substrate provided in one embodiment of the present disclosure, sub-pixels in the same column correspond to the same color, multiple sub-pixels corresponding to the red color connected to the same data line are all connected to the gate lines of multiple odd rows or are all connected to the gate lines of multiple even rows, multiple sub-pixels corresponding to the green color connected to the same data line are all connected to the gate lines of multiple odd rows or are all connected to the gate lines of multiple even rows, and multiple sub-pixels corresponding to the blue color connected to the same data line are all connected to the gate lines of multiple odd rows or are all connected to the gate lines of multiple even rows.

[0010] For example, in an array substrate provided in an embodiment of the present disclosure, an image frame includes a first display period and a second display period, two adjacent odd-numbered rows of gate lines are grouped as a group, two adjacent even-numbered rows of gate lines are grouped as a group, and two rows of sub-pixels connected to each group of gate lines are grouped as a group of sub-pixels. For the odd-numbered rows of gate lines, multiple groups of odd-numbered rows of gate lines are turned on in sequence during the first display period; for the even-numbered rows of gate lines, multiple groups of even-numbered rows of gate lines are turned on in sequence during the second display period, wherein, in each group of gate lines, the gate lines connected to the first part of the rows of sub-pixels are turned on earlier than the gate lines connected to the second part of the rows of sub-pixels.

[0011] For example, in an array substrate provided by an embodiment of the present disclosure, two gate lines serve as a gate line group, and two rows of sub-pixels respectively connected to the two gate lines in the gate line group form a sub-pixel group. The sub-pixel group has the same color as the sub-pixels connected to the same data line, and multiple groups of gate lines are turned on in sequence, wherein, for each group of gate lines, the gate lines connected to the first part of the rows of sub-pixels are turned on earlier than the gate lines connected to the second part of the rows of sub-pixels.

[0012] For example, in an array substrate provided by an embodiment of the present disclosure, the multiple gate lines include multiple first gate line groups, the multiple groups of sub-pixels include multiple first sub-pixel groups, each first gate line group includes two adjacent gate lines, and the two rows of sub-pixels connected to each first gate line group form the first sub-pixel group, and the colors corresponding to the two sub-pixels connected to the same data line in each first sub-pixel group are the same.

[0013] For example, in the array substrate provided in one embodiment of the present disclosure, the multiple groups of sub-pixels also include a second sub-pixel group, the second sub-pixel group includes multiple sub-pixels connected to the gate line that is first turned on among the multiple gate lines, and the multiple first sub-pixel groups include multiple rows of sub-pixels other than the sub-pixels included in the first two sub-pixel groups.

[0014] Another embodiment of the present disclosure provides a driving method, which is applied to the array substrate provided by any embodiment of the present disclosure, and the method includes: turning on multiple gate lines connected to each group of sub-pixels; and during the period when the multiple gate lines of each group of sub-pixels are turned on, multiple data lines charge each group of sub-pixels.

[0015] For example, in a driving method provided in an embodiment of the present disclosure, a plurality of groups of sub-pixels are connected to the same data line, and a plurality of sub-pixels with the same luminous color connected on the same data line are connected to gate lines of odd rows or to gate lines of even rows. An image frame includes a first display period and a second display period. The gate lines of two adjacent odd rows are grouped as a group, and the gate lines of two adjacent even rows are grouped as a group. The two rows of sub-pixels connected to each group of gate lines are grouped as a group of sub-pixels. Turning on the plurality of gate lines connected to each group of sub-pixels in sequence includes: in the first display period, turning on the gate lines of the odd rows in sequence; in the second display period, turning on the gate lines of the even rows in sequence, and in each group of gate lines, the gate lines connected to the sub-pixels of the first part of the rows are turned on earlier than the gate lines connected to the sub-pixels of the second part of the rows.

[0016] For example, in a driving method provided in an embodiment of the present disclosure, two gate lines are used as a gate line group, and two rows of sub-pixels respectively connected to the two gate lines in the gate line group form a sub-pixel group, and the sub-pixel group has the same luminous color corresponding to the sub-pixels connected to the same data line, and turning on the multiple gate lines connected to each group of sub-pixels in sequence includes: turning on the multiple groups of gate lines in sequence, wherein, for each group of gate lines, the gate lines connected to the first part of the rows of sub-pixels are turned on earlier than the gate lines connected to the second part of the rows of sub-pixels.

[0017] For example, in a driving method provided in an embodiment of the present disclosure, a plurality of gate lines include a plurality of first gate line groups, each group of sub-pixels is two adjacent rows of sub-pixels, each first gate line group includes two adjacent gate lines, and the two sub-pixels connected to the same data line in each first sub-pixel group have the same color corresponding to them, and turning on the plurality of gate lines connected to each group of sub-pixels in sequence includes: turning on each gate line in sequence, and in each group of sub-pixels, the gate line connected to the first part of the row of sub-pixels is turned on earlier than the gate line connected to the second part of the row of sub-pixels.

[0018] For example, in the driving method provided in one embodiment of the present disclosure, the charging time of the first part of the row sub-pixels is the charging time of 1 row of sub-pixels, the charging time of the second part of the row sub-pixels is the charging time of 2 rows of sub-pixels, and the first part of the row sub-pixels and the second part of the row sub-pixels start charging at the same time.

[0019] Another embodiment of the present disclosure provides a display device, including the array substrate provided by any embodiment of the present disclosure.

[0020] For example, in a display device provided in an embodiment of the present disclosure, it also includes: an opposing substrate, the opposing substrate includes a color filter layer, the color filter layer includes a plurality of color resists, the plurality of color resists include a plurality of blue color resists, a plurality of red color resists and a plurality of green color resists, and the plurality of color resists correspond one-to-one to the multiple rows and columns of sub-pixels.

[0021] For example, in a display device provided in an embodiment of the present disclosure, a circuit board is further included, the circuit board is provided with a timing controller, the array substrate also includes a source driver chip, the timing controller is coupled to the source driver chip, and is configured to provide display data to the source driver chip; the source driver chip is coupled to the multiple data lines, and is configured to provide the data signals to the multiple data lines according to the display data.

[0022] For example, in a display device provided in an embodiment of the present disclosure, the circuit board further includes a level conversion unit, the array substrate further includes a gate driving circuit, the level conversion unit is coupled to the timing controller, the gate driving circuit is connected to the level conversion unit and the plurality of gate lines, the level conversion unit is configured to receive a plurality of first clock signals provided by the timing controller, and convert the plurality of first clock signals into a plurality of second clock signals, and provide the plurality of second clock signals to the gate driving circuit, the gate driving circuit is configured to provide gate signals to the gate lines according to the plurality of second clock signals to control the gate lines to turn on. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0024] FIG1A shows a timing diagram of a conventional pixel driving mode;

[0025] FIG1B shows a timing diagram of the HSR pixel driving mode;

[0026] FIG2A shows a schematic diagram of an array substrate provided by at least one embodiment of the present disclosure;

[0027] FIG2B shows a timing diagram of the array substrate shown in FIG2A provided by at least one embodiment of the present disclosure;

[0028] FIG3A shows a schematic diagram of another array substrate provided in some embodiments of the present disclosure;

[0029] FIG3B shows a schematic diagram of another array substrate provided in some embodiments of the present disclosure;

[0030] FIG3C shows a schematic diagram of another array substrate provided in some embodiments of the present disclosure;

[0031] FIG4 shows a timing diagram of another driving method applied to FIG2A and FIG3A to FIG3C provided in some embodiments of the present disclosure;

[0032] FIG5A shows a schematic diagram of another array substrate provided by at least one embodiment of the present disclosure;

[0033] FIG5B shows a timing diagram of a driving method applied to the array substrate shown in FIG5A according to at least one embodiment of the present disclosure;

[0034] FIG6A shows a schematic diagram of a display device provided by at least one embodiment of the present disclosure;

[0035] FIG6B shows a schematic diagram of another display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0038] For example, a liquid crystal display is driven by row-by-row scanning, that is, rows are turned on in sequence, and each time a row is turned on, the data lines of all columns transmit data signals to the pixels in that row. Depending on the number of rows turned on at a certain moment and the input of the corresponding pixel signal, the pixel driving structure may include a single-gate pixel driving structure, a dual-gate pixel driving structure, and a triple-gate pixel driving structure. In a single-gate pixel driving structure, a row of sub-pixels is connected to a gate line and controlled by the gate line, and a column of sub-pixels is connected to a data line and controlled by the data line. For example, a 1G1D structure is a conventional single-gate pixel driving structure, that is, only one row is turned on at a certain moment, and the data lines of all columns transmit data signals to the pixels in that row. In a dual-gate pixel driving structure, the row scan lines are doubled, while the data lines are reduced by half, which can reduce the number of source driver chips and thus reduce costs.

[0039] Hardware Super Resolution (HSR) is a solution for achieving high refresh rates. HSR typically advances the charging start time for a row of subpixels by 1T, achieving a 2T charging time. This ensures that the odd (or even) rows are charged at the same time, while the even (or odd) rows achieve data compensation through pre-charging of the upper and lower odd (even) rows. This doubles the charging time while minimizing resolution loss, further facilitating a doubling of the refresh rate.

[0040] FIG. 1A shows a timing diagram of a conventional pixel driving mode; FIG. 1B shows a timing diagram of an HSR pixel driving mode.

[0041] As shown in Figure 1A, in a conventional pixel drive mode, multiple gate lines G1 to G12 are sequentially turned on. During the on-state period of each gate line, the data lines of all columns sequentially write data signals to each row of sub-pixels. For example, while gate line G1 is on, the data line writes data signal 1 to the row of sub-pixels controlled by gate line G1; after gate line G1 is turned off, the data line writes data signal 2 to the other row of sub-pixels controlled by gate line G2, and so on.

[0042] As shown in Figure 1B, when the HSR mode is turned on, the timing of the gate drive circuit remains unchanged, ensuring that even rows are charged. The data for odd rows is a combination of the data from two adjacent rows, doubling the charging time for even row data. For example, while gate lines G1 and G2 are both on, the data line writes data signal 1 to a row of sub-pixels controlled by gate line G1, and writes data signal 1 to another row of sub-pixels controlled by gate line G2. After gate line G2 is turned off, the data line writes data signal 2 to two rows of sub-pixels controlled by gate lines G3 and G4, respectively, and so on. The HSR pixel drive mode shown in this example ensures that even row charging is the same as in the normal mode, thereby doubling the frequency.

[0043] Currently, HSR has been widely used in products with a single-gate pixel driving structure, but is difficult to implement in a dual-gate pixel driving structure.

[0044] An embodiment of the present disclosure provides an array substrate capable of implementing super-division frequency multiplication technology in a dual-gate system. The array substrate includes a pixel array formed by multiple rows and columns of sub-pixels. Multiple gate lines and multiple data lines intersect to define the multiple rows and columns of sub-pixels. Each row of sub-pixels includes two adjacent sub-pixels, each connected to two adjacent gate lines among the multiple gate lines. At least one data line among the multiple data lines is connected to two adjacent columns of sub-pixels among the multiple columns of sub-pixels. The multiple gate lines are used to turn on the multiple rows of sub-pixels, and the multiple data lines are used to charge the turned-on sub-pixels in the multiple columns. The multiple rows of sub-pixels include multiple groups of sub-pixels, each group of sub-pixels includes a portion of the multiple rows of sub-pixels, and the charging time of the portion of the rows of sub-pixels overlaps. The portion of the rows of sub-pixels includes a first portion of the rows of sub-pixels and a second portion of the rows of sub-pixels, and the charging time of the second portion of the rows of sub-pixels is longer than the charging time of the first portion of the rows of sub-pixels. During a first time period of overlapping charging time, the first portion of the rows of sub-pixels and the second portion of the rows of sub-pixels are written with the same data signal. During a second time period of non-overlapping charging time, the data signal written to the second portion of the rows of sub-pixels is at least partially identical to the data signal written during the first time period. This embodiment implements dual-gate super-frequency multiplication technology. In other embodiments of the present disclosure, not only can the super-resolution frequency doubling technology of the dual gate be realized, but also the technical problem of cross-color caused by the application of the super-resolution frequency doubling technology in the dual gate can be alleviated. Since in the dual-gate pixel driving structure, each data line controls two columns of sub-pixels, directly using HSR is prone to cross-color problems. For example, a data line controls a column of sub-pixels located on the left side of the data line and a column of sub-pixels located on the right side of the data line. The first sub-pixel (for example, a red sub-pixel) located on the left side of the data line in the first row of sub-pixels and the second sub-pixel (for example, a green sub-pixel) located on the right side of the data line in the first row of sub-pixels are respectively connected to the first gate line and the second gate line. When the first gate line and the second gate line are in the on state at the same time, the data line is connected to the first sub-pixel and the second sub-pixel, resulting in a cross-color problem in which green is displayed simultaneously when red is displayed.

[0045] FIG2A is a schematic diagram of an array substrate provided by at least one embodiment of the present disclosure; FIG2B is a timing diagram of the array substrate shown in FIG2A provided by at least one embodiment of the present disclosure.

[0046] As shown in FIG2A , the array substrate 100 includes a pixel array formed by multiple rows and columns of sub-pixels. Multiple gate lines and multiple data lines intersect to define the multiple rows and columns of sub-pixels. The multiple gate lines may include, for example, gate lines G1 to G8. The multiple data lines may include, for example, data lines D1 to D7.

[0047] It should be noted that although FIG2A shows only 8 gate lines and 7 data lines, this is merely an example. The number of gate lines and data lines included in the array substrate may be less than or greater than the example shown in FIG2A . The number of sub-pixels included in the array substrate may be more or less than the example shown in FIG2A .

[0048] Each sub-pixel requires polarity inversion driving. In the example of Figure 2A , the pixel polarity inversion driving mode is column inversion driving, meaning that the polarities of adjacent data lines are opposite. For example, the data signal on the first data line is positive, the data signal on the second data line is negative, the data signal on the third data line is positive, and so on.

[0049] As shown in FIG. 2A , each row of sub-pixels in the array substrate 100 is connected to two adjacent gate lines among a plurality of gate lines.

[0050] For example, the i-th row of sub-pixels is connected to the N-th gate line and the N+1-th gate line (N is a positive integer), the i+1-th row of sub-pixels is connected to the N+2-th gate line and the N+3-th gate line, and so on, and each row of sub-pixels is connected to two gate scanning signal lines. Taking the 1st row of sub-pixels as an example, for example, from left to right are the first sub-pixel (located in the first column), the second sub-pixel (located in the second column), the third sub-pixel (located in the third column), the fourth sub-pixel (located in the fourth column), and so on. Gate line G1 is connected to the first sub-pixel, the third sub-pixel, the fourth sub-pixel, the seventh sub-pixel, the ninth sub-pixel, and the tenth sub-pixel in the row. Gate line G2 is connected to the second sub-pixel, the fifth sub-pixel, the sixth sub-pixel, the eighth sub-pixel, the eleventh sub-pixel, and the twelfth sub-pixel in the row. The connection relationship between the sub-pixels in other rows and other gate lines is similar.

[0051] In other embodiments of the present disclosure, for example, the two gate lines connected to the same row of sub-pixels include a gate line connected to one of the even-numbered column sub-pixels and the odd-numbered column sub-pixels in the corresponding row, and a gate line connected to the other of the even-numbered column sub-pixels and the odd-numbered column sub-pixels in the corresponding row. The embodiments of the present disclosure do not limit the connection relationship between each row of sub-pixels and the two adjacent gate lines.

[0052] As shown in FIG. 2A , at least one data line among the plurality of data lines in the array substrate 100 is connected to two adjacent columns of sub-pixels among the plurality of columns of sub-pixels.

[0053] For example, the jth data line is connected to the Mth column of sub-pixels and the M+1th column of sub-pixels (M is a positive integer), the j+1th data line is connected to the M+2th and M+3th columns of sub-pixels, and so on. For example, as shown in FIG2 , the second data line D2 is connected to the 2nd column of sub-pixels and the 3rd column of sub-pixels; the third data line D3 is connected to the 4th column of sub-pixels and the 5th column of sub-pixels, and the connection relationship between other data lines and other columns of sub-pixels is similar. In this embodiment, in addition to including data lines connected to two adjacent columns of sub-pixels in a plurality of columns of sub-pixels, the array substrate 100 may also include data lines connected to only one column of sub-pixels. For example, the first data line is connected to the first column of sub-pixels, and the last data line is connected to the last column of sub-pixels.

[0054] The plurality of gate lines G1 - G8 in the array substrate 100 are used to turn on multiple rows of sub-pixels, and the plurality of data lines D1 - D7 are used to charge multiple columns of turned-on sub-pixels, ie, write data signals to the multiple columns of turned-on sub-pixels.

[0055] As shown in FIG2A , in an embodiment of the present disclosure, Rx represents the red sub-pixel in the x-th row, where x is an integer greater than or equal to 1, for example, x=1, and R1 represents the red sub-pixel in the first row. Similarly, Gx represents the green sub-pixel in the x-th row, and Bx represents the blue sub-pixel in the x-th row.

[0056] In the array substrate 100 , multiple rows of sub-pixels include multiple groups of sub-pixels. Each group of sub-pixels includes some rows of sub-pixels in the multiple rows of sub-pixels. Each row of sub-pixels in the some rows of sub-pixels includes sub-pixels connected to the same gate line, and charging times of some rows of sub-pixels overlap.

[0057] In an embodiment of the present disclosure, a plurality of sub-pixels with overlapping charging times are used as a group of sub-pixels. Charging time overlap refers to that in a certain time period, the data line writes data signals to two rows of sub-pixels at the same time. The charging time overlap is illustrated with the example of Figure 2B. For example, the gate lines G1 and G3 shown in Figure 2B, in time period t1, the data line simultaneously writes data signals to the sub-pixels in the first row of sub-pixels that are turned on by the control of the gate line G1 and the sub-pixels in the third row of sub-pixels that are turned on by the control of the gate line G3. The time period t1 is the time period when the charging time overlaps (i.e., the high levels of G1 and G3 overlap). In time period t2, the gate line G1 is closed, and the data line no longer writes data signals to the sub-pixels in the first row of sub-pixels that are controlled by the gate line G1. The data line still writes data signals to the sub-pixels in the third row of sub-pixels that are controlled by the gate line G3. Time period t2 is the time period when the charging time does not overlap (i.e., the time period when the high level of G1 and the high level of G3 do not overlap, and the high level corresponding to G3 is charged into the data signal). Time period t1 is an example of the first time period. The time period t2 is an example of the second time period.

[0058] For example, as shown in Figure 2B, the charging time of the multiple sub-pixels connected to the gate line G1 and the multiple sub-pixels connected to the gate line G3 overlap, so the multiple sub-pixels connected to the gate line G1 and the multiple sub-pixels connected to the gate line G3 are regarded as a group of sub-pixels. In this example, the charging time of the multiple sub-pixels connected to the gate line G1 and the multiple sub-pixels connected to the gate line G3 overlap, so the multiple sub-pixels connected to the gate line G1 and the multiple sub-pixels connected to the gate line G3 are regarded as a group of sub-pixels. In this example, the gate line G1 and the gate line G3 are regarded as a group, and the multiple sub-pixels connected to these two gate lines are regarded as a group of sub-pixels, in which the partial row sub-pixels are the partial sub-pixels in the first row of sub-pixels connected to the gate line G1 (the first sub-pixel, the third sub-pixel, the fourth sub-pixel, the seventh sub-pixel, the ninth sub-pixel and the tenth sub-pixel in the first row) and the partial sub-pixels in the third row of sub-pixels connected to the gate line G3 (the first sub-pixel, the third sub-pixel, the fourth sub-pixel, the seventh sub-pixel, the ninth sub-pixel and the tenth sub-pixel in the third row).

[0059] The partial row sub-pixels include a first portion of row sub-pixels and a second portion of row sub-pixels, and the charging time of the second portion of row sub-pixels is longer than the charging time of the first portion of row sub-pixels. For example, in an example where gate line G1 and gate line G3 are taken as a group, and a plurality of sub-pixels respectively connected to the two gate lines are taken as a group of sub-pixels, the first sub-pixel, the third sub-pixel, the fourth sub-pixel, the seventh sub-pixel, the ninth sub-pixel, and the tenth sub-pixel in the first row are the first portion of row sub-pixels, and the first sub-pixel, the third sub-pixel, the fourth sub-pixel, the seventh sub-pixel, the ninth sub-pixel, and the tenth sub-pixel in the third row are the second portion of row sub-pixels.

[0060] In some embodiments of the present disclosure, each group of subpixels includes two rows of subpixels, a first portion of the rows of subpixels are at least a portion of the subpixels in one of the two rows of subpixels, and a second portion of the rows of subpixels are at least a portion of the subpixels in the other of the two rows of subpixels.

[0061] In other embodiments of the present disclosure, each group of sub-pixels may include more than two rows of sub-pixels or one row of sub-pixels. The present disclosure does not limit the number of sub-pixels in each group of sub-pixels.

[0062] In the array substrate 100, during a first time period in which the charging times overlap, the same data signals are written into the first portion of row sub-pixels and the second portion of row sub-pixels; during a second time period in which the charging times do not overlap, the data signals written into the second portion of row sub-pixels are at least partially identical to the data signals written into the first time period.

[0063] As shown in Figure 2B, during the time period t1 where the charging times overlap, the data signal DA is written into the multiple sub-pixels in the first row of sub-pixels connected to the gate line G1 (hereinafter referred to as "G1 sub-pixels") and the multiple sub-pixels in the third row of sub-pixels connected to the gate line G3 (hereinafter referred to as "G3 sub-pixels"); during the time period t2 where the charging times do not overlap, the data signal written into the G3 sub-pixels is also the data signal DA.

[0064] In other embodiments of the present disclosure, during time period t2, where the charging times do not overlap, the data signals written into the G3 sub-pixels may include data signal 1 and other data signals. That is, during time period t2, where the charging times do not overlap, the data signals written into the second portion of the row sub-pixels may be completely identical to the data signals written into the first time period, or may be identical for part of the time period and different for another part of the time period. FIG2B illustrates a case where the data signals written into the second portion of the row sub-pixels may be completely identical to the data signals written into the first time period.

[0065] In the above example, the first row of sub-pixels and the third row of sub-pixels are used as an example to illustrate a pixel group. The charging time and charging method of other pixel groups in the array substrate 100 are similar to this pixel group and are not described in detail.

[0066] In other embodiments of the present disclosure, two rows of sub-pixels corresponding to two adjacent gate lines may be considered as a pixel group, for example, the first row of sub-pixels and the second row of sub-pixels may be considered as a pixel group. Except for the overlapping charging time, the present disclosure does not limit the division rules of the pixel groups.

[0067] In some embodiments of the present disclosure, the charging time of the second part of the row sub-pixels is twice the charging time of the first part of the row sub-pixels. For example, the charging time of the first part of the row sub-pixels is the charging time of 1 row of sub-pixels, and the charging time of the second part of the row sub-pixels is the charging time of 2 rows of sub-pixels. The first part of the row sub-pixels and the second part of the row sub-pixels start charging at the same time. For example, the charging time of the first row sub-pixels is 1H, the charging time of the third row sub-pixels is 2H, and the charging time of the third row sub-pixels is 1H, for example, with reference to Figure 2B, the charging time corresponding to t1 is 1H, and the charging time corresponding to t2 is 1H, so for G3, the time to charge the B2 data signal is 2H. For high-resolution products, the charging rate of the display panel can be improved.

[0068] In some embodiments of the present disclosure, in some rows of sub-pixels, the same data line connects to sub-pixels corresponding to the same color. For example, in some rows of sub-pixels, the same data line connects to all red sub-pixels, all green sub-pixels, or all blue sub-pixels. This can alleviate the aforementioned cross-color problem while achieving the HSR function.

[0069] It should be noted that in the embodiments of the present disclosure, the same color or the same color refers to the same color corresponding to the color resist. Here, the color resist can be set on the opposing substrate or on the array substrate (COA technology, the color filter layer is set on one side of the array substrate).

[0070] For example, in the timing diagram shown in FIG2B , two gate lines serve as a gate line group, and two rows of sub-pixels respectively connected to the two gate lines in the gate line group form a sub-pixel group. The sub-pixels in the sub-pixel group connected to the same data line correspond to the same color to alleviate the cross-color problem.

[0071] For example, as shown in Figures 2A and 2B, gate lines G1 and G3 form a gate line group, and subpixels G1 and G3 form a subpixel group. In this subpixel group, two subpixels connected to the same data line correspond to the same color. For example, in this subpixel group, subpixels 201 and 203 connected to data line D1 are both red subpixels; subpixels 202 and 204 connected to data line D2 are both blue subpixels. Other data lines are similar to data lines D1 and D2.

[0072] In the example of Fig. 2 A and 2B, multiple groups of gate lines are turned on in sequence, and the gate lines connected to the first part of the row sub-pixels for each group of gate lines are turned on earlier than the gate lines connected to the second part of the row sub-pixels. For example, in the example of Fig. 2 B, every two adjacent odd-numbered row gate lines serve as an odd-numbered gate line group, and every two adjacent even-numbered row gate lines serve as an even-numbered gate line group, and the odd-numbered gate line group and the even-numbered gate line group alternate with each other. The first gate line group (gate line G1 and gate line G3), the second gate line group (gate line G2 and gate line G4), ..., the sixth gate line group (gate line G10 and gate line G12) are turned on in sequence. For each group of gate lines, for example, gate line G1 and gate line G3, the gate line G1 connected to the second part of the row sub-pixels (that is, G1 sub-pixel) is turned on earlier than the gate line G3 connected to the second part of the row sub-pixels (that is, G3 sub-pixel).

[0073] The array substrate shown in FIG. 2A adopts the timing shown in FIG. 2B to alleviate the cross-color problem when the double-gate pixel driving structure applies the HSR mode.

[0074] The main reason why the dual-gate pixel drive structure uses the HSR mode to display cross-color is that the colors corresponding to the sub-pixels controlled by two adjacent rows of gate lines on the same data line are different. Therefore, by changing the scanning order of the gate lines, the colors corresponding to the sub-pixels controlled by two adjacent rows of gate lines on the same data line can be made the same, and the HSR display mode can be achieved. As shown in Figure 2A, in the array substrate 100, for example, the same column contains sub-pixels of the same color, such as the first column contains red sub-pixels, the second column contains green sub-pixels, and the third column contains blue sub-pixels. The red sub-pixels, green sub-pixels, and blue sub-pixels are then cycled in the order of red sub-pixels, green sub-pixels, and blue sub-pixels. The normal gate line activation sequence is G1 → G2 → G3 → G4 → G5 → G6 → G7 → G8. For example, for data line D2, the corresponding sub-pixel activation sequence is B1 → G1 → B2 → G2 → B3 → G3 → B4 → G4... At this time, since the colors corresponding to the two adjacent activated sub-pixels are different, directly activating the HSR display mode will cause cross-color problems. As shown in Figure 2B, in the embodiment of the present disclosure, the gate line opening order is G1→G3→G2→G4→G5→G7→G6→G8..., for example, for the data line D2, the corresponding sub-pixel opening order is B1 (blue sub-pixel) →B2 (blue sub-pixel) →G1 (green sub-pixel) →G2 (green sub-pixel) →B3 (blue sub-pixel) →B4 (blue sub-pixel) →G3 (green sub-pixel) →G4 (green sub-pixel)..., at this time, the colors corresponding to the two adjacent sub-pixels turned on are the same, and it is only necessary to ensure that the charging and turning on HSR mode of B2, G2, B4, G4... will not cause cross-color problems, thereby realizing the application of HSR display mode in the dual-gate pixel driving structure.

[0075] In other embodiments of the present disclosure, the same data line is connected to multiple groups of sub-pixels, and the multiple sub-pixels corresponding to the same color connected on the same data line are connected to the gate lines of odd rows or to the gate lines of even rows. It should be noted that the odd and even rows here are not absolute and can refer to two adjacent rows of gate lines, one being an odd row and the other being an even row.

[0076] For example, a plurality of green sub-pixels connected to the same data line D2 are all connected to the gate lines of even rows, and a plurality of blue sub-pixels connected to the same data line D2 are all connected to the gate lines of odd rows.

[0077] In some embodiments of the present disclosure, a plurality of sub-pixels corresponding to the red color are connected to the grid lines of the odd rows, a plurality of sub-pixels corresponding to the green color are connected to the grid lines of the even rows, and a plurality of sub-pixels corresponding to the blue color connected to the same data line are connected to the grid lines of the odd rows or are all connected to the grid lines of the even rows. As shown in Figure 2A, all red sub-pixels are connected to the grid lines of the odd rows and are controlled by the grid lines of the odd rows, all green sub-pixels are connected to the grid lines of the even rows and are controlled by the grid lines of the even rows, and the blue sub-pixels on the same data line are only connected to the grid lines of the odd rows or the even rows and are controlled by the grid lines of the odd or even rows. For example, the third column sub-pixel is a blue sub-pixel, and the blue sub-pixel positioned at the third column is only connected to the grid lines of the odd rows; the sixth column sub-pixel is a blue sub-pixel, and the blue sub-pixel positioned at the sixth column is only connected to the grid lines of the even rows.

[0078] FIG3A shows a schematic diagram of another array substrate provided in some embodiments of the present disclosure.

[0079] As shown in FIG3A , in this embodiment, multiple sub-pixels corresponding to green are connected to gate lines in odd-numbered rows, multiple sub-pixels corresponding to blue are connected to gate lines in even-numbered rows, and multiple sub-pixels corresponding to red connected to the same data line are connected to multiple gate lines in odd-numbered rows or multiple gate lines in even-numbered rows. For example, if the sub-pixels in the fourth column are red sub-pixels, the red sub-pixels in the fourth column are connected only to gate lines in even-numbered rows; if the sub-pixels in the first column are red sub-pixels, the red sub-pixels in the first column are connected only to gate lines in odd-numbered rows.

[0080] FIG3B shows a schematic diagram of another array substrate provided in some embodiments of the present disclosure.

[0081] As shown in FIG3B , in this embodiment, multiple sub-pixels corresponding to red are all connected to the gate lines of odd-numbered rows, multiple sub-pixels corresponding to blue are all connected to the gate lines of even-numbered rows, and multiple sub-pixels corresponding to green connected to the same data line are all connected to multiple gate lines of odd-numbered rows or multiple gate lines of even-numbered rows. For example, if the sub-pixels in the second column are green sub-pixels, the green sub-pixels in the second column are only connected to the gate lines of odd-numbered rows; if the sub-pixels in the fifth column are green sub-pixels, the green sub-pixels in the fifth column are only connected to the gate lines of even-numbered rows.

[0082] FIG3C shows a schematic diagram of another array substrate provided in some embodiments of the present disclosure.

[0083] As shown in Figure 3C, in this embodiment, the sub-pixels in the same column correspond to the same color, and the multiple sub-pixels corresponding to the red color connected to the same data line are all connected to the gate lines of multiple odd rows or are all connected to the gate lines of multiple even rows, the multiple sub-pixels corresponding to the green color connected to the same data line are all connected to the gate lines of multiple odd rows or are all connected to the gate lines of multiple even rows, and the multiple sub-pixels corresponding to the blue color connected to the same data line are all connected to the gate lines of multiple odd rows or are all connected to the gate lines of multiple even rows. For example, the sub-pixels in the fourth column are red sub-pixels, and the red sub-pixels in the fourth column are only connected to the gate lines of even rows; the sub-pixels in the first column are red sub-pixels, and the red sub-pixels in the first column are only connected to the gate lines of odd rows. For example, the sub-pixels in the second column are green sub-pixels, and the green sub-pixels in the second column are only connected to the gate lines of odd rows; the sub-pixels in the fifth column are green sub-pixels, and the green sub-pixels in the fifth column are only connected to the gate lines of even rows. For example, the sub-pixels in the third column are blue sub-pixels, and the blue sub-pixels in the third column are only connected to the odd-numbered gate lines; the sub-pixels in the sixth column are blue sub-pixels, and the blue sub-pixels in the sixth column are only connected to the even-numbered gate lines.

[0084] The array substrates shown in FIG. 3A to FIG. 3C can all be driven using the timing diagram shown in FIG. 2B .

[0085] FIG. 4 shows a timing diagram of another driving method applied to FIG. 2A and FIG. 3A to FIG. 3C provided by some embodiments of the present disclosure.

[0086] In this example, an image frame is divided into a first display period and a second display period. Two adjacent odd-numbered rows of gate lines are grouped as a group, and two adjacent even-numbered rows of gate lines are grouped as a group. The two rows of sub-pixels connected by each group of gate lines are grouped as a group of sub-pixels. For the odd-numbered rows of gate lines, multiple groups of odd-numbered rows of gate lines are turned on in sequence during the first display period; for the even-numbered rows of gate lines, multiple groups of even-numbered rows of gate lines are turned on in sequence during the second display period. In each group of gate lines, the gate lines connected to the first part of the rows of sub-pixels are turned on earlier than the gate lines connected to the second part of the rows of sub-pixels.

[0087] In some embodiments of the present disclosure, the first display period and the second display period have the same length. For example, an image frame is evenly divided into a first half-frame and a second half-frame, the display period of the first half-frame is the first display period, and the display period of the second half-frame is the second display period. Optionally, a display frame may include the first display period, the second display period, and a blanking period, which is not limited here. In other embodiments of the present disclosure, the first display period and the second display period have different lengths.

[0088] For example, as shown in Figures 2A and 3A to 3C, the odd-numbered rows of gate lines include gate lines G1, G3, G5, G7, G9, and G11, and every two adjacent odd-numbered rows of gate lines are grouped together, for example, gate lines G1 and G3 are grouped together, gate lines G5 and G7 are grouped together, and gate lines G9 and G11 are grouped together. Multiple groups of odd-numbered rows of gate lines are sequentially turned on in the first half frame. For example, the even-numbered rows of gate lines include gate lines G2, G4, G6, G8, G10, and G12, and every two adjacent even-numbered rows of gate lines are grouped together, for example, gate lines G2 and G4 are grouped together, gate lines G6 and G8 are grouped together, and gate lines G10 and G12 are grouped together, and multiple groups of even-numbered rows of gate lines are sequentially turned on in the second half frame.

[0089] As shown in Figure 4, during the display period of the first half frame, gate lines G1, G3, G5, G7, G9, and G11 are sequentially turned on, and gate lines G2, G4, G6, G8, G10, and G12 remain in a closed state. During the display period of the second half frame, gate lines G1, G3, G5, G7, G9, and G11 remain in a closed state, and gate lines G2, G4, G6, G8, G10, and G12 are sequentially turned on. In the first half frame, the STV1A initial trigger signal is turned on, and in the second half frame, the STV1B initial trigger signal is turned on. The initial trigger signal is used to input the first row or the first few rows of gate drive circuits to turn on the first row or the first few rows of gate drive circuits. For example, STV1A can turn on the G1 row, or turn on the G1 and G3 rows at the same time; for example, STV1B can turn on the G2 row, or turn on the G21 and G4 rows at the same time, etc., which is not limited here.

[0090] For each group of gate lines, the first portion of row sub-pixels are the sub-pixels with the preceding sequence number, and the second portion of row sub-pixels are the sub-pixels with the following sequence number. For example, in the gate line group consisting of gate lines G5 and G7, gate line G5 is the first portion of row sub-pixels, and gate line G7 is the second portion of row sub-pixels; in the gate line group consisting of gate lines G2 and G4, gate line G2 is the first portion of row sub-pixels, and gate line G4 is the second portion of row sub-pixels. The same applies to the remaining gate line groups.

[0091] In the example of FIG4 , odd rows are turned on in the first half frame, and even rows are turned on in the second half frame. In other embodiments of the present disclosure, even rows may be turned on in the first half frame, and odd rows may be turned on in the second half frame.

[0092] For the pixel architectures of Figures 2A and 3A-3C, when only the odd-numbered or even-numbered gate lines are turned on, the sub-pixels connected on the same data line correspond to the same color. When the odd-numbered gate lines and even-numbered gate lines are respectively turned on in HSR mode, there is no cross-color problem. Therefore, for example, if a frame time is split into the first half frame and the second half frame, the odd-numbered gate lines are turned on in the first half frame, and the even-numbered gate lines are turned on in the second half frame, and then the HSR display mode is turned on for the odd and even lines respectively (see Figure 4 for the timing), the HSR display mode can be applied to the dual-gate pixel drive structure.

[0093] In the example of Fig. 4, the gate line that will be connected with odd number row and the gate line that will be connected with even number row are controlled respectively, make for odd number row can be driven according to HSR mode in the first half frame, even number row can be driven according to HSR model in the second half frame, and because each data line is connected the sub-pixel of same color all is subject to the control of odd number row gate line or even number row gate line, therefore can alleviate the cross color problem.Refer to Figure 4, G1 and G3 high level overlap time, the data signal 1 that charges, G1 and G3 high level do not overlap time, the data signal that charges is also 1, namely charges identical data signal, optional, G1 and G3 high level overlap time is 1H (one row charging time), G1 and G3 high level do not overlap time, charging time is also 1H, namely 3 charges into the time that data signal 1 can charge 2H altogether, improves display charging time, improves the problem of insufficient charging rate.Other odd number row or even number row are similar, do not repeat them here.

[0094] It should be noted that, except for the different ways in which the red sub-pixels, blue sub-pixels, and green sub-pixels are connected to the gate lines, the array substrates shown in FIG. 3A to FIG. 3C have similar structures to the array substrate shown in FIG. 2A .

[0095] Figure 5A shows a schematic diagram of another array substrate 500 provided by at least one embodiment of the present disclosure. Figure 5B shows a timing diagram of a driving method applied to the array substrate 500 shown in Figure 5A provided by at least one embodiment of the present disclosure.

[0096] As shown in Figure 5A, the array substrate 500 includes a plurality of gate lines G1-G8. The plurality of gate lines G1-G8 include a plurality of first gate line groups, each of which includes two adjacent gate lines. Two rows of sub-pixels connected to each first gate line form a first sub-pixel group.

[0097] In the example of FIG5A , in the same row, the sub-pixels in odd-numbered columns are connected to the same gate line, and the sub-pixels in even-numbered columns are connected to the same gate line. For example, in the first row, the sub-pixels in odd-numbered columns are connected to gate line G1, and the sub-pixels in even-numbered columns are connected to gate line G2; in the second row, the sub-pixels in odd-numbered columns are connected to gate line G4, and the sub-pixels in even-numbered columns are connected to gate line G3. For example, gate line G2 and gate line G3 form a first gate line group, and multiple sub-pixels in the first row of sub-pixels connected by gate line G2 (multiple sub-pixels located in even columns) and multiple sub-pixels in the second row of sub-pixels connected by gate line G3 (multiple sub-pixels located in even columns) form a first sub-pixel group; gate line G4 and gate line G5 form a first gate line group, and multiple sub-pixels in the second row of sub-pixels connected by gate line G4 (multiple sub-pixels located in odd columns) and multiple sub-pixels in the third row of sub-pixels connected by gate line G5 (multiple sub-pixels located in odd columns) form a first sub-pixel group. Other first gate line groups and first sub-pixel groups are similar to the above.

[0098] It should be noted that in the embodiment of the present disclosure, odd columns and even columns are relative, one of two adjacent columns is an odd column and the other is an even column, and odd columns and even columns alternate in the pixel array.

[0099] In the example of Figure 5A, the colors corresponding to the two sub-pixels connected to the same data line in each first sub-pixel group are the same. For example, for the first gate line group formed by gate line G2 and gate line G3, the sub-pixel 501 in the second column in the first row connected to gate line G2 and the sub-pixel 502 in the second column in the second row connected to gate line G3 are connected to the same data line, and sub-pixel 501 and sub-pixel 502 are both green sub-pixels. That is, in an embodiment of the present disclosure, for example, the DN-th data line connects the Pn and P(n+1)-th column sub-pixels, and the gate line Gi, gate line Gi+1 (where i is greater than or equal to 2), gate line Gi+3, and gate line Gi+4 are connected to the DN-th data line. Gate line Gi and gate line Gi+1 correspond to the P(n+1)th column sub-pixels of the same color, gate line Gi+3 and gate line Gi+4 correspond to the Pnth column sub-pixels of the same color, and so on; or, gate line Gi and gate line Gi+1 correspond to the Pnth column sub-pixels of the same color, gate line Gi+3 and gate line Gi+4 correspond to the P(n+1)th column sub-pixels of the same color, and so on.

[0100] In the example of Figure 5A, the plurality of groups of sub-pixels may further include a second sub-pixel group, the second sub-pixel including a plurality of sub-pixels connected to the gate line that is first turned on among the plurality of gate lines, and the plurality of first sub-pixel groups including a plurality of rows of sub-pixels other than the sub-pixels included in the second sub-pixel group. For example, as shown in Figure 5B, the gate line that is first turned on among the plurality of gate lines is gate line G1, and the plurality of sub-pixels connected to gate line G1 (a plurality of sub-pixels located in odd-numbered columns) are the second sub-pixel group. In addition to the plurality of sub-pixels connected to gate line G1, the plurality of rows of sub-pixels are divided into a plurality of first sub-pixel groups.

[0101] As shown in FIG5B , the HSR display mode can be applied starting from gate line G2, that is, after gate line G1 is turned on and data signal 1 is written to the second sub-pixel group, the HSR display mode is applied. In the HSR display mode, multiple gate lines are turned on sequentially, and in each group of sub-pixels, the gate lines connected to the first portion of the rows of sub-pixels are turned on earlier than the gate lines connected to the second portion of the rows of sub-pixels. For example, gate line G2 is turned on earlier than gate line G3, gate line G4 is turned on earlier than gate line G5, and so on. For example, referring to Figure 5B, when G1 is turned on, the data signal is charged into the first row of pixels, and the data signal 1 is charged. The time for charging the data signal can be 2H, that is, the charging time of the 2H pixel (it should be noted that the data signal written to the first row of pixels can also be 1H, which is not limited here). The HSR mode is turned on from the second row of gate lines and subsequent gate lines, that is, G2 is turned on to charge the data signal 2, and the time for charging the data signal 2 is 1H. After G3 is turned on, the part of G3 that does not overlap with G2 timing is charged with data signal 2, and the time is also 1H, that is, G3 is charged with data signal 2H in total. The other G4 and G5, G6 and G7 refer to the signal input method of G2 and G3, and the details are not repeated here.

[0102] As shown in FIG5B , for each group of sub-pixels, the data line simultaneously starts writing the same data signal to the multiple sub-pixels included in each group of sub-pixels. For example, the pixel groups corresponding to gate lines G2 and G3 write the same data signal 2. For example, the charging time of the multiple sub-pixels connected to gate line G2 is 1 hour, and the charging time of the multiple sub-pixels connected to gate line G3 is 2 hours, and there is an overlap of 1 hour in the charging time.

[0103] In the examples of Figures 5A and 5B, the order in which the gate lines are turned on is G1→G2→G3→G4→G5→G6→G7→8... For example, for the data line D2, the order in which multiple sub-pixels are turned on is B1→R1→R2→B2→B3→R3→R4. At this time, the colors corresponding to the two adjacent sub-pixels that are turned on are the same. It is only necessary to ensure that the R2, B3, and R4 sub-pixels are charged and turned on in the HSR mode to avoid cross-color problems, thereby realizing the application of the HSR display mode in the dual-gate pixel driving structure.

[0104] Another aspect of the present disclosure provides a driving method. This driving method is applicable to the array substrate provided in any embodiment of the present disclosure. The driving method includes turning on multiple gate lines connected to each group of sub-pixels and, while the multiple gate lines of each group of sub-pixels are turned on, charging each group of sub-pixels with multiple data lines. In this embodiment, dual-gate super-resolution frequency multiplication technology is implemented. In other embodiments of the present disclosure, not only can dual-gate super-resolution frequency multiplication technology be implemented, but the technical problem of color crosstalk caused by applying super-resolution frequency multiplication technology to dual-gates can also be alleviated.

[0105] Some embodiments of the present disclosure provide a driving method applicable to, for example, Figures 2A and 3A to 3C above. As shown in Figures 2A and 3A to 3C, multiple groups of sub-pixels are connected to the same data line, and multiple sub-pixels with the same luminous color connected to the same data line are connected to gate lines in odd rows or to gate lines in even rows.

[0106] In this example, an image frame is divided into a first display period and a second display period. Two adjacent odd-numbered rows of gate lines are grouped together, and two adjacent even-numbered rows of gate lines are grouped together. The two rows of sub-pixels connected by each group of gate lines are grouped together. In the first display period, the odd-numbered rows of gate lines are sequentially turned on. In the second display period, the even-numbered rows of gate lines are sequentially turned on. In each group of gate lines, the gate lines connected to the first portion of the rows of sub-pixels are turned on earlier than the gate lines connected to the second portion of the rows of sub-pixels.

[0107] In some embodiments of the present disclosure, the first display period and the second display period have the same duration. For example, an image frame is evenly divided into a first half-frame and a second half-frame, with the display period of the first half-frame being the first display period and the display period of the second half-frame being the second display period. In other embodiments of the present disclosure, the first display period and the second display period have different durations.

[0108] The driving method is driven, for example, according to the timing shown in FIG4 . For example, in the display period of the first half frame, gate lines G1, G3, G5, G7, G9, and G11 are sequentially turned on, and gate lines G2, G4, G6, G8, G10, and G12 remain in an off state. In the display period of the second half frame, gate lines G1, G3, G5, G7, G9, and G11 remain in an off state, and gate lines G2, G4, G6, G8, G10, and G12 are sequentially turned on.

[0109] For each group of gate lines, the first portion of row sub-pixels are the sub-pixels with the preceding sequence number, and the second portion of row sub-pixels are the sub-pixels with the following sequence number. For example, in the gate line group consisting of gate lines G5 and G7, gate line G5 is the first portion of row sub-pixels, and gate line G7 is the second portion of row sub-pixels; in the gate line group consisting of gate lines G2 and G4, gate line G2 is the first portion of row sub-pixels, and gate line G4 is the second portion of row sub-pixels. The same applies to the remaining gate line groups.

[0110] In the example of FIG4 , odd rows are turned on in the first half frame, and even rows are turned on in the second half frame. In other embodiments of the present disclosure, even rows may be turned on in the first half frame, and odd rows may be turned on in the second half frame.

[0111] For the pixel architectures of Figures 2A and 3A-3C, when only the odd-numbered or even-numbered gate lines are turned on, the sub-pixels connected on the same data line correspond to the same color. When the odd-numbered gate lines and even-numbered gate lines are respectively turned on in HSR mode, there is no cross-color problem. Therefore, for example, if a frame time is split into the first half frame and the second half frame, the odd-numbered gate lines are turned on in the first half frame, and the even-numbered gate lines are turned on in the second half frame, and then the HSR display mode is turned on for the odd and even lines respectively (see Figure 4 for the timing), the HSR display mode can be applied to the dual-gate pixel drive structure.

[0112] In some embodiments of the present disclosure, the charging time of the first part of the row of sub-pixels is the charging time of 1 row of sub-pixels, the charging time of the second part of the row of sub-pixels is the charging time of 2 rows of sub-pixels, and the first part of the row of sub-pixels and the second part of the row of sub-pixels start charging at the same time.

[0113] Some embodiments of the present disclosure provide another driving method applicable to, for example, Figures 2A and 3A to 3C above. As shown in Figures 2A and 3A to 3C, two gate lines form a gate line group, and two rows of sub-pixels connected to the two gate lines in the gate line group form a sub-pixel group. The sub-pixel group and the sub-pixels connected to the same data line emit the same color.

[0114] The driving timing of the driving method is, for example, the timing shown in Figure 2B. Multiple groups of gate lines are turned on in sequence, and for each group of gate lines, the gate lines connected to the first part of the rows of sub-pixels are turned on earlier than the gate lines connected to the second part of the rows of sub-pixels.

[0115] Some embodiments of the present disclosure provide a driving method applied to an array substrate such as that shown in FIG. 5A above.

[0116] For the array substrate shown in FIG5A , the plurality of gate lines include a plurality of first gate line groups, each group of sub-pixels comprises two adjacent rows of sub-pixels, each first gate line group comprises two adjacent gate lines, and the two sub-pixels connected to the same data line in each first sub-pixel group have the same color. The driving timing sequence of this driving method is, for example, the timing sequence shown in FIG2B . Each gate line is turned on sequentially, and in each group of sub-pixels, the gate line connected to the first portion of the rows of sub-pixels is turned on earlier than the gate line connected to the second portion of the rows of sub-pixels.

[0117] Regarding the above-mentioned driving method provided by the embodiment of the present disclosure and the various features described in the aforementioned array substrate, please refer to the relevant description of the array substrate for the driving method and will not be repeated here.

[0118] Other embodiments of the present disclosure further provide a display device, which includes the array substrate provided by any embodiment of the present disclosure.

[0119] FIG6A shows a schematic diagram of a display device 600 provided by at least one embodiment of the present disclosure.

[0120] As shown in FIG6A , the display device 600 includes an array substrate 610 . The array substrate 610 may be the array substrate provided by any of the above embodiments.

[0121] In addition to the array substrate 610, the display device 600 also includes an opposing substrate 620. The opposing substrate 620 is disposed opposite the array substrate 610. For example, when the display device is a liquid crystal display device, the display device also includes a liquid crystal layer disposed between the opposing substrate and the array substrate. The opposing substrate includes a color filter layer, which includes multiple color resists. The multiple color resists include multiple columns of blue color resists, multiple columns of red color resists, and multiple columns of green color resists. The multiple columns of color resists are disposed corresponding to the multiple columns of sub-pixels.

[0122] FIG6B shows a schematic diagram of another display device 700 provided by at least one embodiment of the present disclosure.

[0123] In addition to the array substrate 610, the display device 700 may also include a circuit board 710, which is electrically connected to the array substrate (it should be noted that the electrical connection in this case can be a direct electrical connection or an indirect electrical connection, that is, other components or devices are provided between them, which is not limited here). The circuit board 710 includes a timing controller 711. The optional circuit board can be a printed circuit board (PCB). The array substrate 610 also includes a source driver chip 611. The optional source driver chip is bonded to the non-display area of ​​the array substrate (COG technology) to provide data signals to the data lines in the display area. Alternatively, the source driver chip is provided on a flexible circuit board, and the flexible circuit board is bonded to the bonding area of ​​the non-display area of ​​the array substrate to achieve electrical connection (COF process). The timing controller 711 is coupled to the source driver chip 611 and is configured to provide display data to the source driver chip 611. The source driver chip 611 is coupled to multiple data lines DA (for example, data lines D1 to D6 in Figure 2A) and is configured to provide data signals to the multiple data lines DA based on the display data.

[0124] The source driver chip 611 can be provided in a plurality, with different source driver chips coupled to different data lines. For example, as shown in FIG1 , the source driver chip 611 can be provided in two, with one source driver chip 611 coupled to half the number of data lines, and the other source driver chip 611 coupled to the other half of the number of data lines. Of course, the source driver chip 611 can also be provided in three, four, or more, which can be designed and determined according to the needs of the actual application and is not limited here.

[0125] The timing controller 711 sends the display data to the source driver chip 611, so that the source driver chip 611 loads the data signal (i.e., data voltage) to the data line in the array substrate according to the received display data, thereby charging the sub-pixels and charging each sub-pixel with the corresponding target data voltage to realize the screen display function.

[0126] In addition to the timing controller 711 , the circuit board 710 may further include a level conversion unit 712 , and the array substrate 610 may further include a gate driving circuit 612 .

[0127] The level conversion unit 712 is coupled to the timing controller 711, and the gate drive circuit 623 is connected to the level conversion unit 712 and a plurality of gate lines GA (for example, gate lines G1 to G8 in FIG2A ). The level conversion unit 712 is configured to receive a plurality of first clock signals provided by the timing controller 711, and convert the plurality of first clock signals into a plurality of second clock signals, and provide a plurality of second clock signals to the gate drive circuit 623. The gate drive circuit 623 is configured to provide a plurality of gate signals to the gate lines GA according to the plurality of second clock signals to control the gate lines to be turned on. Referring to FIG6B , a scheme is shown in which gate drive circuits are provided on both sides of the non-display area around the display panel. The gate drive circuits on both sides can drive the same gate lines in the display area, or the gate drive circuit on one side drives the gate lines of odd rows and the gate drive circuit on the other side drives the gate lines of even rows; or the present scheme can also provide a gate drive circuit only in the non-display area on one side of the display panel, which is not limited here.

[0128] The optional display device also includes a system chip SOC, which is electrically connected to the timing controller. Exemplarily, in this case, the HSR function is turned on to increase the charging rate of the display row, so that the data signals of at least some display rows are charged for 2 hours. Here, in order to achieve that at least some row data signals are charged for 2 hours, it can be achieved in the following ways, but not limited to the following ways, such as the system control chip deletes part of the data, or the timing controller deletes part of the data, or the source driver chip deletes part of the data, wherein the deleted data can be, for example, deleting half of the data of each frame, and the deleted data can be interlaced deletion, for example, only retaining the data of odd rows and deleting the data of even rows in each frame; or; only retaining the data of even rows in each frame, Delete the data of odd rows; or; in two adjacent frames, the first frame retains the odd row data and deletes the even row data, and the second frame retains the even row data and deletes the odd row data, for example, the first frame only retains the grid line row data such as 1, 3, 5, 7, 9, and the second frame only retains the data corresponding to the even-numbered grid line rows such as 2, 4, 6, 8, 10; or, in two adjacent frames, the first frame retains the even row data and deletes the odd row data, and the second frame retains the odd row data and deletes the even row data, for example, the first frame only retains the grid line row data such as 2, 4, 6, 8, 10, and the second frame only retains the data corresponding to the grid lines such as 1, 3, 5, 7, 9; the "row" here refers to the pixels connected to each grid line corresponding to a row, and the pixels connected to different grid lines correspond to different rows. No limitation is made here.

[0129] The level conversion unit 712 can be implemented as a level conversion circuit or a chip for level conversion. The level conversion unit 712 can, for example, change the period or amplitude of each of the multiple first clock signals to obtain multiple second clock signals. For example, the level conversion unit 712 increases the voltage amplitude and period of the multiple first clock signals. The level conversion unit 712 can convert the p first clock signals provided by the timing controller 711 into q second clock signals, where p is an integer greater than or equal to 1, q is an integer greater than or equal to 2, and q is greater than or equal to p. For example, if the array substrate includes 8 gate lines as a cycle group, then q can be equal to 8.

[0130] Regarding this disclosure, the following points need to be explained:

[0131] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0132] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0133] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An array substrate, comprising a pixel array formed by a plurality of rows and columns of sub-pixels, wherein a plurality of gate lines and a plurality of data lines cross and define the plurality of rows and columns of sub-pixels, Each row of sub-pixels is connected to two adjacent gate lines among the plurality of gate lines; At least one data line among the plurality of data lines is connected to two adjacent columns of sub-pixels among the plurality of columns of sub-pixels; The plurality of gate lines are used to turn on a plurality of rows of sub-pixels, and the plurality of data lines are used to charge a plurality of columns of turned-on sub-pixels; The multiple rows of sub-pixels include multiple groups of sub-pixels, each group of sub-pixels includes some rows of sub-pixels in the multiple rows of sub-pixels, each row of sub-pixels in the some rows of sub-pixels includes sub-pixels connected to the same gate line, and charging times of the some rows of sub-pixels overlap; The part of row sub-pixels includes a first part of row sub-pixels and a second part of row sub-pixels, the charging time of the second part of row sub-pixels is longer than the charging time of the first part of row sub-pixels, In a first time period when the charging time overlaps, the first part of the row sub-pixels and the second part of the row sub-pixels are written with the same data signal, In a second time period where the charging times do not overlap, the data signals written into the sub-pixels in the second part of the rows are at least partially identical to the data signals written into the first time period.

2. The array substrate according to claim 1, in, In the partial rows of sub-pixels, the same data line is connected to a plurality of sub-pixels corresponding to the same color.

3. The array substrate according to claim 1 or 2, in, The charging time of the first part of the row of sub-pixels is the charging time of one row of sub-pixels, the charging time of the second part of the row of sub-pixels is the charging time of two rows of sub-pixels, and the first part of the row of sub-pixels and the second part of the row of sub-pixels start charging at the same time.

4. The array substrate according to any one of claims 1 to 3, in, The same data line is connected to multiple groups of sub-pixels, and the multiple sub-pixels corresponding to the same color connected to the same data line are connected to the gate lines of odd-numbered rows or to the gate lines of even-numbered rows.

5. The array substrate according to claim 4, in, Sub-pixels in the same column correspond to the same color. The multiple sub-pixels corresponding to red are connected to the gate lines of odd-numbered rows, the multiple sub-pixels corresponding to green are connected to the gate lines of even-numbered rows, and the multiple sub-pixels corresponding to blue connected to the same data line are connected to multiple gate lines of odd-numbered rows or are all connected to multiple gate lines of even-numbered rows; or A plurality of sub-pixels corresponding to green are connected to the gate lines of odd-numbered rows, a plurality of sub-pixels corresponding to blue are connected to the gate lines of even-numbered rows, and a plurality of sub-pixels corresponding to red connected to the same data line are connected to a plurality of gate lines of odd-numbered rows or to a plurality of gate lines of even-numbered rows; or The multiple sub-pixels corresponding to red are all connected to the gate lines of odd rows, the multiple sub-pixels corresponding to blue are all connected to the gate lines of even rows, and the multiple sub-pixels corresponding to green connected to the same data line are all connected to the gate lines of odd rows or to the gate lines of even rows.

6. The array substrate according to claim 4, in, The sub-pixels in the same column correspond to the same color, the multiple sub-pixels corresponding to the red color connected to the same data line are all connected to the gate lines of multiple odd rows or are all connected to the gate lines of multiple even rows, the multiple sub-pixels corresponding to the green color connected to the same data line are all connected to the gate lines of multiple odd rows or are all connected to the gate lines of multiple even rows, and the multiple sub-pixels corresponding to the blue color connected to the same data line are all connected to the gate lines of multiple odd rows or are all connected to the gate lines of multiple even rows.

7. The array substrate according to any one of claims 4 to 6, in, An image frame includes a first display period and a second display period, two adjacent odd-numbered rows of gate lines are grouped as a group, two adjacent even-numbered rows of gate lines are grouped as a group of sub-pixels, and two rows of sub-pixels connected by each group of gate lines are grouped as a group of sub-pixels. For the odd-numbered rows of gate lines, multiple groups of the odd-numbered rows of gate lines are turned on in sequence during the first display period; For the gate lines of even-numbered rows, multiple groups of gate lines of even-numbered rows are turned on in sequence during the second display period. Among them, in each group of gate lines, the gate lines connected to the first part of the row sub-pixels are turned on earlier than the gate lines connected to the second part of the row sub-pixels.

8. The array substrate according to any one of claims 4 to 6, in, Two gate lines are used as a gate line group, and two rows of sub-pixels respectively connected to the two gate lines in the gate line group form a sub-pixel group, and the sub-pixels corresponding to the sub-pixels connected to the same data line in the sub-pixel group have the same color. A plurality of groups of gate lines are turned on in sequence, wherein, for each group of gate lines, the gate lines connected to the first part of the rows of sub-pixels are turned on earlier than the gate lines connected to the second part of the rows of sub-pixels.

9. The array substrate according to any one of claims 1 to 3, in, The multiple gate lines include multiple first gate line groups, the multiple groups of sub-pixels include multiple first sub-pixel groups, each first gate line group includes two adjacent gate lines, and two rows of sub-pixels connected to each first gate line group form the first sub-pixel group, and the colors corresponding to the two sub-pixels connected to the same data line in each first sub-pixel group are the same.

10. The array substrate according to claim 9, in, The multiple groups of sub-pixels also include a second sub-pixel group, which includes multiple sub-pixels connected to the gate line that is first turned on among the multiple gate lines, and the multiple first sub-pixel groups include multiple rows of sub-pixels except the sub-pixels included in the first two sub-pixel groups.

11. The array substrate according to claim 9 or 10, in, The plurality of gate lines are turned on in sequence, and in each group of sub-pixels, the gate lines connected to the first part of the rows of sub-pixels are turned on earlier than the gate lines connected to the second part of the rows of sub-pixels.

12. A driving method, applied to the array substrate according to claim 1, wherein the method include: Turning on a plurality of gate lines connected to each group of sub-pixels; as well as During the period when the gate lines of each group of sub-pixels are turned on, the data lines charge each group of sub-pixels.

13. The method according to claim 12, in, The same data line is connected to multiple groups of sub-pixels, and the multiple sub-pixels with the same luminous color connected to the same data line are connected to the gate lines of odd rows or to the gate lines of even rows. An image frame includes a first display period and a second display period. Two adjacent gate lines of odd rows are grouped as a group, and two adjacent gate lines of even rows are grouped as a group. Two rows of sub-pixels connected to each group of gate lines are grouped as a group of sub-pixels. The multiple gate lines that sequentially open each group of sub-pixels connected include: In the first display period, the gate lines of the odd-numbered rows are turned on in sequence; In the second display period, the gate lines of the even-numbered rows are turned on in sequence. Among them, in each group of gate lines, the gate lines connected to the first part of the row sub-pixels are turned on earlier than the gate lines connected to the second part of the row sub-pixels.

14. The method according to claim 12, in, Two gate lines are used as a gate line group, and two rows of sub-pixels respectively connected to the two gate lines in the gate line group form a sub-pixel group, and the sub-pixels corresponding to the sub-pixels connected to the same data line in the sub-pixel group have the same luminous color. The multiple gate lines that sequentially open each group of sub-pixels connected include: A plurality of groups of gate lines are turned on in sequence, wherein, for each group of gate lines, the gate lines connected to the first part of the rows of sub-pixels are turned on earlier than the gate lines connected to the second part of the rows of sub-pixels.

15. The method according to claim 12, in, The plurality of gate lines include a plurality of first gate line groups, each group of sub-pixels is two adjacent rows of sub-pixels, each first gate line group includes two adjacent gate lines, and the colors corresponding to the two sub-pixels connected to the same data line in each first sub-pixel group are the same. The multiple gate lines that sequentially open each group of sub-pixels connected include: Each gate line is turned on in sequence, and in each group of sub-pixels, the gate line connected to the first part of the rows of sub-pixels is turned on earlier than the gate line connected to the second part of the rows of sub-pixels.

16. The method according to any one of claims 12 to 15, in, The charging time of the first part of the row of sub-pixels is the charging time of one row of sub-pixels, the charging time of the second part of the row of sub-pixels is the charging time of two rows of sub-pixels, and the first part of the row of sub-pixels and the second part of the row of sub-pixels start charging at the same time.

17. A display device comprising the array substrate according to any one of claims 1 to 11.

18. The display device according to claim 17, further comprising: include: The opposing substrate comprises a color filter layer, the color filter layer comprises a plurality of color resists, the plurality of color resists comprises a plurality of blue color resists, a plurality of red color resists and a plurality of green color resists, and the plurality of color resists correspond one-to-one to the plurality of rows and columns of sub-pixels.

19. The display device according to claim 17 or 18, further comprising a circuit board, wherein the circuit board is provided with a timing controller, and the array substrate further comprises a source driver chip. The timing controller is coupled to the source driver chip and is configured to provide display data to the source driver chip; The source driving chip is coupled to the plurality of data lines and is configured to provide the data signals to the plurality of data lines according to the display data.

20. The display device according to claim 19, in, The circuit board further includes a level conversion unit, and the array substrate further includes a gate driving circuit. The level conversion unit is coupled to the timing controller, and the gate driving circuit is connected to the level conversion unit and the plurality of gate lines. The level conversion unit is configured to receive a plurality of first clock signals provided by the timing controller, convert the plurality of first clock signals into a plurality of second clock signals, and provide the plurality of second clock signals to the gate driving circuit. The gate driving circuit is configured to provide a gate signal to the gate line according to the plurality of second clock signals to control the gate line to be turned on.

Images