Pixel driving circuit, display device and method for driving display device

Abstract

A pixel driving circuit is provided. The pixel driving circuit comprises a first circuit, a second circuit and one or more third circuits. The first circuit is configured to compensate for a change in a threshold voltage of the driving transistor in the one or more third circuits. The first circuit is coupled to the first control signal line, the second control signal line, the first light emission control signal line, and the second light emission control signal line. The second circuit is coupled to the first light emission control signal line and the second light emission control signal line. The first light emission control signal line and the second light emission control signal line are configured to transmit inverted light emission control signals.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to a pixel driving circuit, a display device and a method for driving the display device. Background Art

[0002] Organic light emitting diode display technology has been developed in many applications. Organic light emitting diode displays have the problem of uneven light emission of individual diodes, which requires certain compensation to ensure display quality. Many internal and external compensation methods have been developed to improve the display quality of organic light emitting diode display panels. Summary of the invention

[0003] On the one hand, the present disclosure provides a pixel driving circuit, comprising a first circuit, a second circuit and one or more third circuits; wherein the first circuit is configured to compensate for changes in the threshold voltage of a driving transistor in the one or more third circuits; wherein the first circuit is coupled to a first control signal line, a second control signal line, a first light-emitting control signal line and a second light-emitting control signal line; the second circuit is coupled to the first light-emitting control signal line and the second light-emitting control signal line; and the first light-emitting control signal line and the second light-emitting control signal line are configured to transmit inverted light-emitting control signals.

[0004] Optionally, the one or more third circuits are capable of operating in a compensation mode or a non-compensation mode; in the compensation mode, the one or more third circuits are configured to drive the light-emitting element to emit light and compensate for the change in the threshold voltage of the driving transistor in the one or more third circuits; in the non-compensation mode, the one or more third circuits are configured to drive the light-emitting element to emit light without compensating for the change in the threshold voltage of the driving transistor in the one or more third circuits.

[0005] Optionally, the one or more third circuits are capable of operating in a compensation mode or a non-compensation mode; in the compensation mode, the second control signal line and the second light-emitting control signal line are configured to transmit an inverted light-emitting control signal; and in the non-compensation mode, the second control signal line and the second light-emitting control signal line are configured to transmit an in-phase light-emitting control signal.

[0006] Optionally, the first circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; wherein the first transistor includes a gate coupled to the second light-emitting control signal line, a first electrode coupled to the reference signal line, and a second electrode coupled to the second electrode of the third transistor; the second transistor includes a gate coupled to the second electrode of the fourth transistor and the first electrode of the fifth transistor, a first electrode configured to receive a second voltage signal from a second voltage supply line, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the fifth transistor; the third transistor includes a gate coupled to the first light-emitting control signal line, a first electrode coupled to the second electrode of the second transistor and the second electrode of the fifth transistor, and a second electrode coupled to the second electrode of the first transistor; the fourth transistor includes a gate coupled to the first control signal line, a first electrode coupled to the reset signal line, a second electrode coupled to the gate and the second electrode of the second transistor and the first electrode of the fifth transistor; and the fifth transistor includes a gate coupled to the second control signal line, a first electrode coupled to the gate of the second transistor and the second electrode of the fourth transistor, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the second transistor.

[0007] Optionally, the first circuit further includes a sixth transistor having a gate coupled to the first light emission control signal line, a first electrode coupled to the second voltage supply line, and a second electrode coupled to the first electrode of the second transistor.

[0008] Optionally, the first circuit also includes a seventh transistor having a gate coupled to a reset control signal line, a first electrode coupled to a second reset signal line, and a second electrode coupled to the first electrode of the second transistor and the second electrode of the sixth transistor.

[0009] Optionally, the first circuit further includes an eighth transistor having a gate coupled to a third control signal line, a first electrode coupled to the second electrode of the first transistor and the second electrode of the third transistor, and a second electrode coupled to a sensing line.

[0010] Optionally, the first circuit also includes a ninth transistor and a tenth transistor; the gate of the ninth transistor is coupled to a third control signal line, the first electrode of the ninth transistor is coupled to the reference signal line, and the second electrode of the ninth transistor is coupled to the first electrode of the first transistor and the first electrode of the tenth transistor; the gate of the tenth transistor is coupled to a fourth control signal line, the first electrode of the tenth transistor is coupled to the first electrode of the first transistor and the second electrode of the ninth transistor, and the second electrode of the tenth transistor is coupled to a sensing line; and the sensing line is coupled to an external compensation circuit, which is configured to further compensate for the change in the threshold voltage in the driving transistor in the one or more third circuits.

[0011] Optionally, the first circuit further comprises a first capacitor having a first capacitor electrode coupled to the second voltage supply line, and a second capacitor electrode coupled to the second electrode of the first transistor and the second electrode of the third transistor.

[0012] Optionally, the first circuit also includes a first capacitor having a first capacitor electrode coupled to the second electrode of the sixth transistor and the first electrode of the second transistor, and a second capacitor electrode coupled to the second electrode of the first transistor and the second electrode of the third transistor.

[0013] Optionally, the second control signal line is the same as the first light emitting control signal line; and the gate of the fifth transistor is configured to receive a first light emitting control signal from the first light emitting control signal line.

[0014] Optionally, the first control signal line is the same as a first gate line configured to provide a gate scan signal to a row of third circuits; and the gate of the fourth transistor is configured to receive the gate scan signal from the first gate line.

[0015] Optionally, the second voltage supply line is the same as the first voltage supply line; and the first voltage supply line is configured to provide a first voltage supply signal to the second circuit and the first electrode of the second transistor.

[0016] Optionally, the second circuit includes a first light-emitting control transistor and a second light-emitting control transistor; wherein the first light-emitting control transistor includes a gate coupled to the first light-emitting control signal line, a first electrode coupled to a first voltage supply line, and a second electrode coupled to the second electrode of the second light-emitting control transistor; and the second light-emitting control transistor includes a gate coupled to the second light-emitting control signal line, a first electrode coupled to a reset signal line, and a second electrode coupled to the second electrode of the first light-emitting control transistor.

[0017] Optionally, each third circuit in the one or more third circuits includes a driving transistor, a data writing transistor and a second capacitor; wherein the driving transistor includes a gate coupled to the second capacitor electrode of the second capacitor and the second electrode of the data writing transistor, a first electrode coupled to the second electrode of the first light-emitting control transistor and the second electrode of the second light-emitting control transistor in the second circuit, and a second electrode coupled to the anode of the light-emitting element; the data writing transistor includes a gate coupled to a corresponding gate line among a plurality of gate lines, a first electrode coupled to a corresponding data line among a plurality of data lines, and a second electrode coupled to the gate of the driving transistor and the second capacitor electrode of the second capacitor; and the second capacitor includes a first capacitor electrode coupled to the second electrode of the first transistor in the first circuit and the second electrode of the third transistor.

[0018] Optionally, the one or more third circuits are arranged in an array having multiple rows and columns; the third circuits in the same column are coupled to the same data line; the third circuits in the same row are coupled to the same gate line; the second capacitors in the third circuits in different rows have different capacitances; and the capacitance of the second capacitors in the third circuits gradually decreases row by row.

[0019] Optionally, the pixel driving circuit is configured to drive a plurality of sub-pixels to emit light, the plurality of sub-pixels including a first sub-pixel configured to emit light of a first color, a second sub-pixel configured to emit light of a second color, and a third sub-pixel configured to emit light of a third color; a driving transistor in a third circuit in the pixel driving circuit configured to drive the first sub-pixel, the second sub-pixel, and the third sub-pixel to emit light has the same ratio of channel length to channel width; and Wherein, W2 represents the channel width of the second transistor, L2 represents the channel length of the second transistor, Wd1 represents the channel width of the driving transistor in each of the third circuits, and Ld1 represents the channel length of the driving transistor in each of the third circuits.

[0020] Optionally, the pixel driving circuit is configured to drive first sub-pixels of the same color to emit light; the driving transistors in the third circuit in the pixel driving circuit configured to drive the first sub-pixels of the same color to emit light have the same ratio of channel length to channel width; and Among them, W12 represents the channel width of the second transistor in the pixel driving circuit, L12 represents the channel length of the second transistor in the pixel driving circuit, Wd11 represents the channel width of the driving transistor in each third circuit in the pixel driving circuit, and Ld11 represents the channel length of the driving transistor in each third circuit in the pixel driving circuit.

[0021] On the other hand, the present disclosure provides a display device, including the pixel driving circuit described herein, and a plurality of light emitting elements coupled to the pixel driving circuit.

[0022] On the other hand, the present disclosure provides a method for driving a display device, wherein the display device includes a pixel driving circuit and a plurality of light-emitting elements coupled to the pixel driving circuit; wherein the pixel driving circuit includes a first circuit, a second circuit and one or more third circuits; wherein the first circuit is coupled to a first control signal line, a second control signal line, a first light-emitting control signal line and a second light-emitting control signal line; and the second circuit is coupled to the first light-emitting control signal line and the second light-emitting control signal line; wherein the method includes: providing a first light-emitting control signal to the first circuit and the second circuit through the first light-emitting control signal line; and providing a second light-emitting control signal to the first circuit and the second circuit through the second light-emitting control signal line; wherein the first light-emitting control signal line and the second light-emitting control signal line are configured to transmit inverted light-emitting control signals.

[0023] Optionally, the method also includes: operating the one or more third circuits in one of a compensation mode or a non-compensation mode; in the compensation mode, driving the light-emitting element to emit light through the one or more third circuits and compensating for changes in the threshold voltage of the driving transistor in the one or more third circuits; and in the non-compensation mode, driving the light-emitting element to emit light through the one or more third circuits without compensating for the changes in the threshold voltage of the driving transistor in the one or more third circuits.

[0024] Optionally, the method also includes: operating the one or more third circuits in one of a compensation mode or a non-compensation mode; in the compensation mode, providing an inverted light-emitting control signal to the second control signal line and the second light-emitting control signal line, respectively; and in the non-compensation mode, providing a same-phase light-emitting control signal to the second control signal line and the second light-emitting control signal line.

[0025] Optionally, the first circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; wherein the first transistor includes a gate coupled to the second light-emitting control signal line, a first electrode coupled to a reference signal line, and a second electrode coupled to the second electrode of the third transistor; the second transistor includes a gate coupled to the second electrode of the fourth transistor and the first electrode of the fifth transistor, a first electrode configured to receive a second voltage signal from a second voltage supply line, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the fifth transistor; the third transistor includes a gate coupled to the first light-emitting control signal line, a first electrode coupled to the second electrode of the second transistor and the second electrode of the fifth transistor, and a second electrode coupled to the second electrode of the first transistor; the fourth transistor includes a gate coupled to the first control signal line, a first electrode coupled to a reset signal line, and a second electrode coupled to the gate and the second electrode of the second transistor and the first electrode of the fifth transistor; and the fifth transistor includes a gate coupled to the second control signal line, a first electrode coupled to the second transistor a first electrode of the gate and the second electrode of the fourth transistor, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the second transistor; wherein, in the compensation mode, the method comprises: in a first stage, providing a turn-on control signal to the gate of the fourth transistor through the first control signal line, providing a turn-off control signal to the gate of the fifth transistor through the second control signal line, providing a turn-off control signal to the gate of the third transistor through the first light-emitting control signal line, and providing a turn-on control signal to the gate of the first transistor through the second light-emitting control signal line; in a second stage, providing a turn-off control signal to the gate of the fourth transistor through the first control signal line, and providing a turn-on control signal to the gate of the first transistor through the second light-emitting control signal line; and in a light-emitting stage, providing a turn-off control signal to the gate of the first transistor through the second light-emitting control signal line, providing a turn-on control signal to the gate of the fifth transistor through the second control signal line, and providing a turn-on control signal to the gate of the third transistor through the first light-emitting control signal line.

[0026] Optionally, in non-compensation mode, the method includes: providing a turn-on control signal through the first light-emitting control signal line throughout the image frame; providing a turn-off control signal through the second light-emitting control signal line throughout the image frame; and providing a turn-off control signal through the second control signal line throughout the image frame.

[0027] Optionally, the second control signal line is the same as the first light emitting control signal line; and the method comprises: providing a first light emitting control signal to the gate of the fifth transistor through the first light emitting control signal line.

[0028] Optionally, the first control signal line is the same as a first gate line configured to provide a gate scan signal to a row of third circuits; and the method includes: providing a gate scan signal to the gate of the fourth transistor through the first gate line.

[0029] Optionally, the second voltage supply line is the same as the first voltage supply line; and the method comprises: providing a first voltage supply signal to the second circuit and the first electrode of the second transistor through the first voltage supply line. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0031] Figure 1 is a schematic diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure.

[0032] Figure 2 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0033] Figure 3 is a schematic diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure.

[0034] Figure 4 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0035] Figure 5 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0036] Figure 6 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0037] Fig. 7A is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0038] Figure 7B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0039] Figure 8 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0040] Fig. 9 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0041] Fig.10 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0042] Fig.11 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0043] Fig.12 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0044] Fig.13 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0045] Fig.14 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0046] Fig.15 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0047] Fig.16 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0048] Fig.17 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0049] Fig.18 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0050] Fig.19 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0051] Fig. 20 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0052] Fig.21 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0053] Fig. 22 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0054] Fig.23 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0055] Fig.24 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0056] Fig.25 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0057] Fig.26 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0058] Fig. 27 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0059] Fig.28 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0060] Fig.29 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure.

[0061] Fig.30 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0062] Fig.31 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0063] Fig.32 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Specific embodiments

[0064] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0065] Therefore, the present disclosure particularly provides a pixel driving circuit, a display device and a method for driving a display device, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. On the one hand, the present disclosure provides a pixel driving circuit. In some embodiments, the pixel driving circuit includes a first circuit, a second circuit and one or more third circuits. Optionally, the first circuit is configured to compensate for changes in the threshold voltage of the driving transistor in the one or more third circuits. Optionally, the first circuit is coupled to a first control signal line, a second control signal line, a first light-emitting control signal line and a second light-emitting control signal line. Optionally, the second circuit is coupled to a first light-emitting control signal line and a second light-emitting control signal line. Optionally, the first light-emitting control signal line and the second light-emitting control signal line are configured to transmit an inverted light-emitting control signal.

[0066] Figure 1 is a schematic diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 1 In some embodiments, the pixel driving circuit includes a first circuit Cir1, a second circuit Cir2, and one or more third circuits Cir3. The first circuit Cir1 is configured to compensate for the change in the threshold voltage of the driving transistor in the one or more third circuits Cir3. The second circuit Cir2 is configured to provide a voltage supply signal to the driving transistor. Each of the one or more third circuits Cir3 is configured to generate a driving current for driving the light-emitting element to emit light.

[0067] In some embodiments, the first circuit Cir1 is coupled to a first voltage supply line Vdd1, a first light-emitting control signal line em1, a second light-emitting control signal line em2, a corresponding gate line Gln in a plurality of gate lines, a reset signal line Vint, and a reference signal line Vref. Optionally, the first light-emitting control signal line em1 and the second light-emitting control signal line em2 are configured to transmit an inverted light-emitting control signal. For example, at the same time point, the first light-emitting control signal line em1 is configured to transmit a valid voltage signal, and the second light-emitting control signal line em2 is configured to transmit an invalid voltage signal. In another example, at the same time point, the first light-emitting control signal line em1 is configured to transmit an invalid voltage signal, and the second light-emitting control signal line em2 is configured to transmit a valid voltage signal. Optionally, the corresponding gate line Gln is one of N gate lines configured to provide a gate scan signal to the N-row third circuit, and N is a positive integer.

[0068] In some embodiments, the second circuit Cir2 is coupled to the reset signal line Vint, the first light emitting control signal line em1, the second light emitting control signal line em2, and the first voltage supply line Vdd1.

[0069] In some embodiments, each of the one or more third circuits Cir3 is coupled to a corresponding gate line (eg, Figure 1 ), an anode of a corresponding light emitting element LE, and a corresponding data line among a plurality of data lines (eg, Figure 1 The cathode of each light emitting element LE is coupled to the low voltage signal line Vss. Each third circuit is coupled to the first circuit Cir1 and to the second circuit Cir2.

[0070] In some embodiments, the one or more third circuits Cir3 include a plurality of third circuits configured to drive a plurality of light-emitting elements to emit light. In some embodiments, the plurality of third circuits are arranged in an array. For example, Figure 1 An array of third circuits arranged in two rows and two columns is depicted. In some embodiments, the third circuits in the same column are coupled to the same data line. For example, the third circuit in the first column is coupled to the first data line DL1, and the third circuit in the second column is coupled to the second data line DL2. In some embodiments, the third circuits in the same row are coupled to the same gate line. For example, the third circuit in the first row is coupled to the first gate line GL1, and the third circuit in the second row is coupled to the second gate line GL2.

[0071] Figure 2 is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. Figure 1 and Figure 2 In some embodiments, the first circuit Cir1 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a first capacitor C1.

[0072] In some embodiments, the gate of the first transistor M1 is coupled to the second light emitting control signal line em2, the first electrode of the first transistor M1 is coupled to the reference signal line Vref, and the second electrode of the first transistor M1 is coupled to the second electrode of the third transistor M3 and the second capacitor electrode of the first capacitor C1.

[0073] In some embodiments, a gate and a second electrode of the second transistor M2 are coupled to the second electrode of the fourth transistor M4 and the first electrode of the third transistor M3 , and a first electrode of the second transistor M2 is coupled to the first voltage supply line Vdd1 .

[0074] In some embodiments, the gate of the third transistor M3 is coupled to the first light emitting control signal line em1; the first electrode of the third transistor M3 is coupled to the gate and the second electrode of the second transistor M2 and the second electrode of the fourth transistor M4; the second electrode of the third transistor M3 is coupled to the second electrode of the first transistor M1 and the second capacitor electrode of the first capacitor C1.

[0075] In some embodiments, the gate of the fourth transistor M4 is coupled to a corresponding gate line Gln among multiple gate lines; the first electrode of the fourth transistor M4 is coupled to the reset signal line Vint; the second electrode of the fourth transistor M4 is coupled to the gate and second electrode of the second transistor M2 and the first electrode of the third transistor M3.

[0076] In some embodiments, a first capacitor electrode of the first capacitor C1 is coupled to a first electrode of the second transistor M2 and a first voltage supply line Vdd1 , and a second capacitor electrode of the first capacitor C1 is coupled to a second electrode of the first transistor M1 and a second electrode of the third transistor M3 .

[0077] In some embodiments, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to each third circuit. Optionally, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to the first capacitor electrode of the second capacitor C2 of each third circuit.

[0078] In some embodiments, the second circuit Cir2 includes a first light emission control transistor Ms1 and a second light emission control transistor Ms2.

[0079] In some embodiments, the gate of the first light emission control transistor Ms1 is coupled to the first light emission control signal line em1, the first electrode of the first light emission control transistor Ms1 is coupled to the first voltage supply line Vdd1, and the second electrode of the first light emission control transistor Ms1 is coupled to the second electrode of the second light emission control transistor Ms2.

[0080] In some embodiments, the gate of the second light emitting control transistor Ms2 is coupled to the second light emitting control signal line em2, the first electrode of the second light emitting control transistor Ms2 is coupled to the reset signal line Vint, and the second electrode of the second light emitting control transistor Ms2 is coupled to the second electrode of the first light emitting control transistor Ms1.

[0081] In some embodiments, the second electrodes of the first emission control transistor Ms1 and the second emission control transistor Ms2 are coupled to respective third circuits. Optionally, the second electrodes of the first emission control transistor Ms1 and the second emission control transistor Ms2 are coupled to the first electrodes of the driving transistors Md1 of respective third circuits.

[0082] In some embodiments, each third circuit includes a driving transistor Md1 , a data writing transistor Mp1 , and a second capacitor C2 .

[0083] In some embodiments, the gate of the driving transistor Md1 is coupled to the second capacitor electrode of the second capacitor C2 and the second electrode of the data writing transistor Mp1, the first electrode of the driving transistor Md1 is coupled to the second electrode of the first light emitting control transistor Ms1 and the second electrode of the second light emitting control transistor Ms2, and the second electrode of the driving transistor Md1 is coupled to the anode of the corresponding light emitting element LE.

[0084] In some embodiments, the gate of the data write transistor Mp1 is coupled to a corresponding gate line among a plurality of gate lines (for example, the third circuit in the first row is coupled to the first gate line GL1, and the third circuit in the second row is coupled to the second gate line GL2), the first electrode of the data write transistor Mp1 is coupled to a corresponding data line among a plurality of data lines (for example, the third circuit in the first column is coupled to the first data line DL1, and the third circuit in the second column is coupled to the second data line DL2), and the second electrode of the data write transistor Mp1 is coupled to the gate of the driving transistor Md1 and the second capacitor electrode of the second capacitor C2.

[0085] In some embodiments, a first capacitor electrode of the second capacitor C2 is coupled to the first circuit Cir1. Optionally, a first capacitor electrode of the second capacitor C2 is coupled to a second capacitor electrode of the first capacitor C1, a second electrode of the first transistor M1, and a second electrode of the third transistor M3.

[0086] In some embodiments, a second capacitor electrode of the second capacitor C2 is coupled to the second electrode of the data write transistor Mp1 and the gate of the drive transistor Md1 .

[0087] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, wherein the first terminal and the second terminal are connected to an active layer of the transistor. The direction in which current flows through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction in which current flows through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0088] The present disclosure can be implemented in a pixel driving circuit having various types of transistors, including a pixel driving circuit having a p-type transistor, a pixel driving circuit having an n-type transistor, and a pixel driving circuit having one or more p-type transistors and one or more n-type transistors. For a p-type transistor, a valid control signal (e.g., a turn-on control signal) is a low voltage signal, while an invalid control signal (e.g., a turn-off control signal) is a high voltage signal. For an n-type transistor, a valid control signal (e.g., a turn-on control signal) is a high voltage signal, while an invalid control signal (e.g., a turn-off control signal) is a low voltage signal. Reference Figure 2 In some embodiments, the transistor is a p-type transistor such as a polysilicon transistor. In an alternative example, one or more transistors of the pixel driving circuit may be an n-type transistor.

[0089] Figure 3 is a schematic diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 3 In some embodiments, the pixel driving circuit includes a first circuit Cir1, a second circuit Cir2, and one or more third circuits Cir3. The first circuit Cir1 is coupled to a second voltage supply line Vdd2, a first light emitting control signal line em1, a second light emitting control signal line em2, a first control signal line CS1, a second control signal line CS2, a reset signal line Vint, and a reference signal line Vref.

[0090] In some embodiments, the first light-emitting control signal line em1 and the second light-emitting control signal line em2 are configured to transmit inverted light-emitting control signals. For example, at the same time point, the first light-emitting control signal line em1 is configured to transmit a valid voltage signal, and the second light-emitting control signal line em2 is configured to transmit an invalid voltage signal. In another example, at the same time point, the first light-emitting control signal line em1 is configured to transmit an invalid voltage signal, and the second light-emitting control signal line em2 is configured to transmit a valid voltage signal.

[0091] In some embodiments, the second control signal line CS2 and the second light-emitting control signal line em2 are configured to transmit inverted control signals. For example, at the same time point, the second control signal line CS2 is configured to transmit a valid voltage signal, while the second light-emitting control signal line em2 is configured to transmit an invalid voltage signal. In another example, at the same time point, the second control signal line CS2 is configured to transmit an invalid voltage signal, while the second light-emitting control signal line em2 is configured to transmit a valid voltage signal.

[0092] In an alternative embodiment, the second control signal line CS2 and the second light emitting control signal line em2 are configured to transmit control signals of the same phase. For example, at the same time point, the second control signal line CS2 is configured to transmit a valid voltage signal, and the second light emitting control signal line em2 is also configured to transmit a valid voltage signal. In another example, at the same time point, the second control signal line CS2 is configured to transmit an invalid voltage signal, and the second light emitting control signal line em2 is also configured to transmit an invalid voltage signal.

[0093] In some embodiments, when the first gate line GL1 is configured to provide a gate scan signal, the first control signal line CS1 and the first gate line GL1 are configured to provide a signal in phase. For example, at the same time point, the first gate line GL1 is configured to transmit a valid voltage signal, and the first control signal line CS1 is also configured to transmit a valid voltage signal. In another example, at the same time point, the first gate line GL1 is configured to transmit an invalid voltage signal, and the first control signal line CS1 is also configured to transmit an invalid voltage signal.

[0094] In some embodiments, the second circuit Cir2 is coupled to the reset signal line Vint, the first light emitting control signal line em1, the second light emitting control signal line em2, and the first voltage supply line Vdd1.

[0095] In some embodiments, each of the one or more third circuits Cir3 is coupled to a corresponding gate line (eg, Figure 3 ), an anode of a corresponding light emitting element LE, and a corresponding data line among a plurality of data lines (eg, Figure 3 The cathode of each light emitting element LE is coupled to the low voltage signal line Vss. Each third circuit is coupled to the first circuit Cir1 and to the second circuit Cir2.

[0096] In some embodiments, the one or more third circuits Cir3 include a plurality of third circuits configured to drive a plurality of light-emitting elements to emit light. In some embodiments, the plurality of third circuits are arranged in an array. For example, Figure 3 An array of third circuits arranged in two rows and two columns is depicted. In some embodiments, the third circuits in the same column are coupled to the same data line. For example, the third circuit in the first column is coupled to the first data line DL1, and the third circuit in the second column is coupled to the second data line DL2. In some embodiments, the third circuits in the same row are coupled to the same gate line. For example, the third circuit in the first row is coupled to the first gate line GL1, and the third circuit in the second column is coupled to the second gate line GL2.

[0097] Figure 4is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. Figure 3 and Figure 4 In some embodiments, the first circuit Cir1 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a first capacitor C1.

[0098] In some embodiments, the gate of the first transistor M1 is coupled to the second light emitting control signal line em2, the first electrode of the first transistor M1 is coupled to the reference signal line Vref, and the second electrode of the first transistor M1 is coupled to the second electrode of the third transistor M3 and the second capacitor electrode of the first capacitor C1.

[0099] In some embodiments, the gate of the second transistor M2 is coupled to the second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5, the first electrode of the second transistor M2 is coupled to the second electrode of the sixth transistor M6, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3 and the second electrode of the fifth transistor M5.

[0100] In some embodiments, the gate of the third transistor M3 is coupled to the first light emitting control signal line em1; the first electrode of the third transistor M3 is coupled to the second electrode of the second transistor M2 and the second electrode of the fifth transistor M5; the second electrode of the third transistor M3 is coupled to the second electrode of the first transistor M1 and the second capacitor electrode of the first capacitor C1.

[0101] In some embodiments, a gate of the fourth transistor M4 is coupled to the first control signal line CS1; a first electrode of the fourth transistor M4 is coupled to the reset signal line Vint; a second electrode of the fourth transistor M4 is coupled to the gate of the second transistor M2 and a first electrode of the fifth transistor M5.

[0102] In some embodiments, the gate of the fifth transistor M5 is coupled to the second control signal line CS2, the first electrode of the fifth transistor M5 is coupled to the gate of the second transistor M2 and the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is coupled to the first electrode of the third transistor M3 and the second electrode of the second transistor M2.

[0103] In some embodiments, a gate of the sixth transistor M6 is coupled to the first light emission control signal line em1, a first electrode of the sixth transistor M6 is coupled to the second voltage supply line Vdd2, and a second electrode of the sixth transistor M6 is coupled to the first electrode of the second transistor M2.

[0104] In some embodiments, a first capacitor electrode of the first capacitor C1 is coupled to a first electrode of the sixth transistor M6 and a second voltage supply line Vdd2 , and a second capacitor electrode of the first capacitor C1 is coupled to second electrodes of the first transistor M1 and the third transistor M3 .

[0105] In some embodiments, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to each third circuit. Optionally, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to the first capacitor electrode of the second capacitor C2 of each third circuit.

[0106] In some embodiments, the second circuit Cir2 includes a first light emission control transistor Ms1 and a second light emission control transistor Ms2.

[0107] In some embodiments, the gate of the first light emission control transistor Ms1 is coupled to the first light emission control signal line em1, the first electrode of the first light emission control transistor Ms1 is coupled to the first voltage supply line Vdd1, and the second electrode of the first light emission control transistor Ms1 is coupled to the second electrode of the second light emission control transistor Ms2.

[0108] In some embodiments, the gate of the second light emitting control transistor Ms2 is coupled to the second light emitting control signal line em2, the first electrode of the second light emitting control transistor Ms2 is coupled to the reset signal line Vint, and the second electrode of the second light emitting control transistor Ms2 is coupled to the second electrode of the first light emitting control transistor Ms1.

[0109] In some embodiments, the second electrodes of the first emission control transistor Ms1 and the second emission control transistor Ms2 are coupled to respective third circuits. Optionally, the second electrodes of the first emission control transistor Ms1 and the second emission control transistor Ms2 are coupled to the first electrodes of the driving transistors Md1 of respective third circuits.

[0110] In some embodiments, each third circuit includes a driving transistor Md1 , a data writing transistor Mp1 , and a second capacitor C2 .

[0111] In some embodiments, the gate of the driving transistor Md1 is coupled to the second capacitor electrode of the second capacitor C2 and the second electrode of the data writing transistor Mp1, the first electrode of the driving transistor Md1 is coupled to the second electrode of the first light emitting control transistor Ms1 and the second electrode of the second light emitting control transistor Ms2, and the second electrode of the driving transistor Md1 is coupled to the anode of the corresponding light emitting element LE.

[0112] In some embodiments, the gate of the data write transistor Mp1 is coupled to a corresponding gate line among a plurality of gate lines (for example, the third circuit in the first row is coupled to the first gate line GL1, and the third circuit in the second row is coupled to the second gate line GL2), the first electrode of the data write transistor Mp1 is coupled to a corresponding data line among a plurality of data lines (for example, the third circuit in the first column is coupled to the first data line DL1, and the third circuit in the second column is coupled to the second data line DL2), and the second electrode of the data write transistor Mp1 is coupled to the gate of the driving transistor Md1 and the second capacitor electrode of the second capacitor C2.

[0113] In some embodiments, a first capacitor electrode of the second capacitor C2 is coupled to the first circuit Cir1. Optionally, a first capacitor electrode of the second capacitor C2 is coupled to a second capacitor electrode of the first capacitor C1, a second electrode of the first transistor M1, and a second electrode of the third transistor M3.

[0114] In some embodiments, a second capacitor electrode of the second capacitor C2 is coupled to the second electrode of the data write transistor Mp1 and the gate of the drive transistor Md1 .

[0115] The inventors of the present disclosure have discovered that Figure 3 and Figure 4 The pixel drive circuit depicted in the embodiment is superior to Figure 1 and Figure 2 For example, in operation Figure 1 and Figure 2 In the initial stage of the pixel driving circuit depicted in , the inventors of the present disclosure observed a leakage current flowing from the first voltage supply line Vdd1 through the second transistor M2 and the fourth transistor M4 to the corresponding reset signal line. Figure 3 and Figure 4 In the pixel driving circuit depicted in FIG. 1 , by providing the sixth transistor M6 , leakage current in the initial stage can be prevented, thereby significantly reducing the power consumption of the pixel driving circuit.

[0116] In addition, the inventors of the present disclosure have found that by providing a second control signal line CS2 in addition to the first light-emission control signal line em1 and the second light-emission control signal line em2, it is possible to operate each third circuit in a compensation mode (first mode) or a non-compensation mode (second mode) by respectively providing different control signals and light-emission control signals for different operation modes. On the other hand, Figure 1 and Figure 2 The pixel driving circuit depicted in cannot be operated in two different modes.

[0117] Furthermore, the inventors of the present disclosure have discovered that by making the second voltage supply line Vdd2 independent of the first voltage supply line Vdd1 , the flexibility and selectivity of operating the pixel driving circuit can be enhanced.

[0118] Figure 5 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Figure 5 FIG. 2 shows the operation of the pixel driving circuit in the compensation mode. Figures 3 to 5 During one image frame, the operation of the pixel driving circuit includes a first phase t1, a second phase t2 and a light emitting phase te.

[0119] In some embodiments, in the first stage t1, a turn-on control signal is provided to the gate of the fourth transistor M4 through the first control signal line CS1 to turn on the fourth transistor M4, so that the initialization voltage signal from the reset signal line Vint is transferred from the first electrode of the fourth transistor M4 to the second electrode of the fourth transistor M4; and then to the gate of the second transistor M2. The gate of the second transistor M2 is initialized. A turn-off control signal is provided to the gate of the fifth transistor M5 through the second control signal line CS2 to turn off the fifth transistor M5.

[0120] A turn-off control signal is provided to gates of the third transistor M3 , the sixth transistor M6 , and the first light emission control transistor Ms1 through the first light emission control signal line em1 to turn off the third transistor M3 , the sixth transistor M6 , and the first light emission control transistor Ms1 .

[0121] The conduction control signal is provided to the gate of the first transistor M1 through the second light emitting control signal line em2, so that the reference signal from the reference signal line Vref is transferred from the first electrode of the first transistor M1 to the second electrode of the first transistor M1; and then transferred to the first capacitor electrode of the second capacitor C2 in the corresponding third circuit. The reference signal from the reference signal line Vref is written to the first capacitor electrode of the second capacitor C2 in the corresponding third circuit, thereby stabilizing the voltage level of the first capacitor electrode of the second capacitor C2 in the corresponding third circuit, and preventing the voltage level at the gate of the driving transistor Md1 from fluctuating when the data signal is written to the third circuit in a row other than the row with the corresponding third circuit.

[0122] A turn-on control signal is provided to the gate of the data write transistor Mp1 in the corresponding third circuit through the corresponding gate line (e.g., the first gate line GL1 for the first row third circuit), so that the data signal from the corresponding data line (e.g., the first data line DL1 for the first column third circuit) is transferred from the first electrode of the data write transistor Mp1 to the second electrode of the data write transistor Mp1. The data signal is written to the gate of the drive transistor Md1 in the corresponding third circuit.

[0123] A conduction control signal is provided to the gate of the second light-emitting control transistor Ms2 through the second light-emitting control signal line em2, so that the initialization voltage signal from the reset signal line Vint is transmitted from the first electrode of the second light-emitting control transistor Ms2 to the second electrode of the second light-emitting control transistor Ms2, and then transmitted to the first electrode of the driving transistor Md1 in the corresponding third circuit, thereby preventing the driving transistor from being abnormally turned on when the data signal is written to the gate of the driving transistor Md1 in the corresponding third circuit.

[0124] In some embodiments, in the second phase t2, a turn-off control signal is provided to the gate of the fourth transistor M4 through the first control signal line CS1 to turn off the fourth transistor M4, thereby completing the initialization of the gate of the second transistor M2.

[0125] The turn-off control signal is provided to the gate of the data writing transistor Mp1 in the corresponding third circuit through the first gate line GL1 to turn off the data writing transistor Mp1 in the corresponding third circuit, thereby completing the writing of the data signal to the gate of the driving transistor Md1 in the corresponding third circuit.

[0126] The conduction control signal is provided to the gate of the data write transistor Mp1 in the third circuit in the next row (for example, the second row when the corresponding third circuit is in the first row) through the second gate line GL2, so that the data signal from the second gate line GL2 is transferred from the first electrode of the data write transistor Mp1 in the third circuit in the next row to the second electrode of the data write transistor Mp1 in the third circuit in the next row. The data signal is written to the gate of the drive transistor Md1 in the third circuit in the next row.

[0127] The conduction control signal is provided to the gate of the first transistor M1 through the second light emitting control signal line em2, so that the reference signal from the reference signal line Vref is transferred from the first electrode of the first transistor M1 to the second electrode of the first transistor M1; and then transferred to the first capacitor electrode of the second capacitor C2 in the third circuit in the next row. The reference signal from the reference signal line Vref is written to the first capacitor electrode of the second capacitor C2 in the third circuit in the next row, thereby stabilizing the voltage level of the first capacitor electrode of the second capacitor C2 in the third circuit in the next row, and preventing the voltage level at the gate of the driving transistor Md1 from fluctuating when the data signal is written to the third circuit in a row other than the next row.

[0128] A turn-on control signal is provided to the gate of the second light-emitting control transistor Ms2 through the second light-emitting control signal line em2, so that the initialization voltage signal from the reset signal line Vint is transmitted from the first electrode of the second light-emitting control transistor Ms2 to the second electrode of the second light-emitting control transistor Ms2, and then transmitted to the first electrode of the driving transistor Md1 in the third circuit in the next row, thereby preventing the driving transistor from being abnormally turned on when the data signal is written to the gate of the driving transistor Md1 in the third circuit in the next row.

[0129] For illustration purposes only, Figure 4 and Figure 5 An example is depicted in which the third circuit is arranged in an array of two rows and two columns. However, the pixel driving circuit may include more than two rows and two columns, or only one row and one column.

[0130] Figure 6 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Figure 6 The operation of the pixel driving circuit is depicted, wherein the third circuit is arranged in an array having n rows. Figure 6 , repeatable data writing steps ( Figure 5 During one image frame, the operation of the pixel driving circuit includes at least (n+1) phases, including the first phase t1, the second phase t2, the (n-1)th phase t(n-1), the nth phase tn, and the light emitting phase te.

[0131] In some embodiments, in the light emitting phase te, a turn-off control signal is provided to the gate of the data writing transistor Mp1 in the corresponding third circuit through the first gate line GL1 to turn off the data writing transistor Mp1 in the corresponding third circuit.

[0132] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the next row through the second gate line GL2 to turn off the data write transistor Mp1 in the third circuit in the next row.

[0133] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the (n-1)th row through the (n-1)th gate line GL(n-1) to turn off the data write transistor Mp1 in the third circuit in the (n-1)th row.

[0134] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the n-th row through the n-th gate line GLn to turn off the data write transistor Mp1 in the third circuit in the n-th row.

[0135] A turn-off control signal is supplied to the gate of the second light emission control transistor Ms2 through the second light emission control signal line em2 to turn off the second light emission control transistor Ms2.

[0136] A turn-off control signal is supplied to the gate of the first transistor M1 through the second light emitting control signal line em2 to turn off the first transistor M1.

[0137] A turn-on control signal is provided to the gate of the fifth transistor M5 through the second control signal line CS2 to turn on the fifth transistor M5.

[0138] A turn-on control signal is supplied to the gate of the sixth transistor M6 through the first light emitting control signal line em1 to turn on the sixth transistor M6.

[0139] When the fifth transistor M5 and the sixth transistor M6 are turned on, the voltage levels at the gate and the second electrode (eg, the drain) of the second transistor M2 are: (the voltage level of the second voltage supply line Vdd2 + the voltage level of the threshold voltage Vth).

[0140] A turn-on control signal is provided to the gate of the third transistor M3 through the first light emitting control signal line em1 to turn on the third transistor M3. Because the fifth transistor M5 and the third transistor M3 are turned on, the voltage level at the gate and the second electrode of the second transistor M2 is written to the first capacitor electrode of the second capacitor C2. The voltage level at the first capacitor electrode of the second capacitor C2 is then coupled to the gate of the driving transistor Md1. As a result, the voltage difference Vgs between the gate and the first electrode of the driving transistor Md1 is expressed as: (voltage level of the data signal written to the gate of the driving transistor Md1 + voltage level of the second voltage supply line Vdd2 + voltage level of the threshold voltage Vth - voltage level of the reference signal line Vref - voltage level of the first voltage supply line Vdd1). The driving current I flowing through the driving transistor is expressed as K×(Vgs-voltage level of the threshold voltage Vth) 2 , which is equal to K×(the voltage level of the data signal written to the gate of the driving transistor Md1+the voltage level of the second voltage supply line Vdd2−the voltage level of the reference signal line Vref−the voltage level of the first voltage supply line Vdd1) 2 .

[0141] Fig. 7A is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Fig. 7A FIG. 2 shows the operation of the pixel driving circuit in the non-compensation mode. Figure 3 , Figure 4 and Fig. 7AIn the non-compensation mode, a turn-on control signal is provided through the first light-emitting control signal line em1 throughout the image frame, a turn-off control signal is provided through the second light-emitting control signal line em2 throughout the image frame, and a turn-off control signal is provided through the second control signal line CS2 throughout the image frame. Therefore, in the non-compensation mode, the second transistor M2, the third transistor M3, the sixth transistor M6, and the first light-emitting control transistor Ms1 are turned on throughout the image frame. The second voltage supply signal is transmitted through the sixth transistor M6, the second transistor M2, and the third transistor M3, and then transmitted to the first capacitor electrode of the second capacitor C2. The data signal is written to the second capacitor electrode of the second capacitor C2. The operation of the pixel driving circuit does not involve coupling the voltage level at the first capacitor electrode of the second capacitor C2 to the gate of the driving transistor Md1, and does not include the extraction of the threshold voltage Vth.

[0142] For illustration purposes only, Figure 4 and Fig. 7A An example is depicted in which the third circuit is arranged in an array of two rows and two columns. However, the pixel driving circuit may include more than two rows and two columns, or only one row and one column.

[0143] Figure 8 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Figure 8 The operation of the pixel driving circuit is depicted, wherein the third circuit is arranged in an array having n rows. Figure 8 , repeatable data writing steps ( Fig. 7A t1 and t2 in ), until the process is completed for all n rows of the third circuit.

[0144] Figure 7B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Figure 7B The operation of the pixel driving circuit in the non-compensation mode in an alternative embodiment is shown. Figure 3 , Figure 4 and Figure 7BIn the non-compensation mode, a turn-on control signal is provided through the first light-emitting control signal line em1 throughout the image frame, a turn-off control signal is provided through the second light-emitting control signal line em2 throughout the image frame, a turn-off control signal is provided through the first control signal line CS1 throughout the image frame, and a turn-on control signal is provided through the second control signal line CS2 throughout the image frame. Therefore, in the non-compensation mode, the third transistor M3, the sixth transistor M6, the fifth transistor M5, and the first light-emitting control transistor Ms1 are turned on throughout the image frame. The first transistor M1, the second transistor M2, and the fourth transistor M4 are turned off throughout the image frame. The operation of the pixel driving circuit does not involve coupling the voltage level at the first capacitor electrode of the second capacitor C2 to the gate of the driving transistor Md1, and does not include extraction of the threshold voltage Vth.

[0145] Fig. 9 is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. Figure 3 and Fig. 9 In some embodiments, the first circuit Cir1 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a first capacitor C1. Fig. 9 The pixel drive circuit depicted in Figure 4 The difference between the pixel drive circuit depicted in is that Fig. 9 The pixel driving circuit depicted in does not include the sixth transistor M6.

[0146] In some embodiments, the gate of the first transistor M1 is coupled to the second light emitting control signal line em2, the first electrode of the first transistor M1 is coupled to the reference signal line Vref, and the second electrode of the first transistor M1 is coupled to the second electrode of the third transistor M3 and the second capacitor electrode of the first capacitor C1.

[0147] In some embodiments, the gate of the second transistor M2 is coupled to the second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5, the first electrode of the second transistor M2 is coupled to the second voltage supply line Vdd2, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3 and the second electrode of the fifth transistor M5.

[0148] In some embodiments, the gate of the third transistor M3 is coupled to the first light emitting control signal line em1; the first electrode of the third transistor M3 is coupled to the second electrode of the second transistor M2 and the second electrode of the fifth transistor M5; the second electrode of the third transistor M3 is coupled to the second electrode of the first transistor M1 and the second capacitor electrode of the first capacitor C1.

[0149] In some embodiments, a gate of the fourth transistor M4 is coupled to the first control signal line CS1; a first electrode of the fourth transistor M4 is coupled to the reset signal line Vint; a second electrode of the fourth transistor M4 is coupled to the gate of the second transistor M2 and a first electrode of the fifth transistor M5.

[0150] In some embodiments, the gate of the fifth transistor M5 is coupled to the second control signal line CS2, the first electrode of the fifth transistor M5 is coupled to the gate of the second transistor M2 and the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is coupled to the first electrode of the third transistor M3 and the second electrode of the second transistor M2.

[0151] In some embodiments, a first capacitor electrode of the first capacitor C1 is coupled to a first electrode of the second transistor M2 and a second voltage supply line Vdd2 , and a second capacitor electrode of the first capacitor C1 is coupled to second electrodes of the first transistor M1 and the third transistor M3 .

[0152] In some embodiments, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to each third circuit. Optionally, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to the first capacitor electrode of the second capacitor C2 of each third circuit.

[0153] In some embodiments, the second circuit Cir2 includes a first light emission control transistor Ms1 and a second light emission control transistor Ms2.

[0154] In some embodiments, the gate of the first light emission control transistor Ms1 is coupled to the first light emission control signal line em1, the first electrode of the first light emission control transistor Ms1 is coupled to the first voltage supply line Vdd1, and the second electrode of the first light emission control transistor Ms1 is coupled to the second electrode of the second light emission control transistor Ms2.

[0155] In some embodiments, the gate of the second light emitting control transistor Ms2 is coupled to the second light emitting control signal line em2, the first electrode of the second light emitting control transistor Ms2 is coupled to the reset signal line Vint, and the second electrode of the second light emitting control transistor Ms2 is coupled to the second electrode of the first light emitting control transistor Ms1.

[0156] In some embodiments, the second electrodes of the first emission control transistor Ms1 and the second emission control transistor Ms2 are coupled to respective third circuits. Optionally, the second electrodes of the first emission control transistor Ms1 and the second emission control transistor Ms2 are coupled to the first electrodes of the driving transistors Md1 of respective third circuits.

[0157] In some embodiments, each third circuit includes a driving transistor Md1 , a data writing transistor Mp1 , and a second capacitor C2 .

[0158] In some embodiments, the gate of the driving transistor Md1 is coupled to the second capacitor electrode of the second capacitor C2 and the second electrode of the data writing transistor Mp1, the first electrode of the driving transistor Md1 is coupled to the second electrode of the first light emitting control transistor Ms1 and the second electrode of the second light emitting control transistor Ms2, and the second electrode of the driving transistor Md1 is coupled to the anode of the corresponding light emitting element LE.

[0159] In some embodiments, the gate of the data write transistor Mp1 is coupled to a corresponding gate line among a plurality of gate lines (for example, the third circuit in the first row is coupled to the first gate line GL1, and the third circuit in the second row is coupled to the second gate line GL2), the first electrode of the data write transistor Mp1 is coupled to a corresponding data line among a plurality of data lines (for example, the third circuit in the first column is coupled to the first data line DL1, and the third circuit in the second column is coupled to the second data line DL2), and the second electrode of the data write transistor Mp1 is coupled to the gate of the driving transistor Md1 and the second capacitor electrode of the second capacitor C2.

[0160] In some embodiments, a first capacitor electrode of the second capacitor C2 is coupled to the first circuit Cir1. Optionally, a first capacitor electrode of the second capacitor C2 is coupled to a second capacitor electrode of the first capacitor C1, a second electrode of the first transistor M1, and a second electrode of the third transistor M3.

[0161] In some embodiments, a second capacitor electrode of the second capacitor C2 is coupled to the second electrode of the data write transistor Mp1 and the gate of the drive transistor Md1 .

[0162] The inventors of the present disclosure have found that by providing a second control signal line CS2 in addition to the first light-emission control signal line em1 and the second light-emission control signal line em2, it is possible to operate each third circuit in a compensation mode (first mode) or a non-compensation mode (second mode) by respectively providing different control signals and light-emission control signals for different operation modes. On the other hand, Figure 1 and Figure 2 The pixel driving circuit depicted in cannot be operated in two different modes.

[0163] Furthermore, the inventors of the present disclosure have discovered that by making the second voltage supply line Vdd2 independent of the first voltage supply line Vdd1 , the flexibility and selectivity of operating the pixel driving circuit can be enhanced.

[0164] Fig. 9The operation of the pixel drive circuit in compensation mode is similar to Figure 5 and Figure 6 The operation is basically the same as described in . Figures 3 to 5 In the compensation mode, during one image frame, the operation of the pixel driving circuit includes a first phase t1, a second phase t2 and a light emitting phase te.

[0165] In some embodiments, in the first stage t1, a turn-on control signal is provided to the gate of the fourth transistor M4 through the first control signal line CS1 to turn on the fourth transistor M4, so that the initialization voltage signal from the reset signal line Vint is transferred from the first electrode of the fourth transistor M4 to the second electrode of the fourth transistor M4; and then to the gate of the second transistor M2. The gate of the second transistor M2 is initialized. A turn-off control signal is provided to the gate of the fifth transistor M5 through the second control signal line CS2 to turn off the fifth transistor M5.

[0166] A turn-off control signal is supplied to gates of the third transistor M3 and the first light emission control transistor Ms1 through the first light emission control signal line em1 to turn off the third transistor M3 and the first light emission control transistor Ms1.

[0167] The conduction control signal is provided to the gate of the first transistor M1 through the second light emitting control signal line em2, so that the reference signal from the reference signal line Vref is transferred from the first electrode of the first transistor M1 to the second electrode of the first transistor M1; and then transferred to the first capacitor electrode of the second capacitor C2 in the corresponding third circuit. The reference signal from the reference signal line Vref is written to the first capacitor electrode of the second capacitor C2 in the corresponding third circuit, thereby stabilizing the voltage level of the first capacitor electrode of the second capacitor C2 in the corresponding third circuit, and preventing the voltage level at the gate of the driving transistor Md1 from fluctuating when the data signal is written to the third circuit in a row other than the row with the corresponding third circuit.

[0168] A turn-on control signal is provided to the gate of the data write transistor Mp1 in the corresponding third circuit through the corresponding gate line (e.g., the first gate line GL1 for the first row third circuit), so that the data signal from the corresponding data line (e.g., the first data line DL1 for the first column third circuit) is transferred from the first electrode of the data write transistor Mp1 to the second electrode of the data write transistor Mp1. The data signal is written to the gate of the drive transistor Md1 in the corresponding third circuit.

[0169] A conduction control signal is provided to the gate of the second light-emitting control transistor Ms2 through the second light-emitting control signal line em2, so that the initialization voltage signal from the reset signal line Vint is transmitted from the first electrode of the second light-emitting control transistor Ms2 to the second electrode of the second light-emitting control transistor Ms2, and then transmitted to the first electrode of the driving transistor Md1 in the corresponding third circuit, thereby preventing the driving transistor from being abnormally turned on when the data signal is written to the gate of the driving transistor Md1 in the corresponding third circuit.

[0170] In some embodiments, in the second phase t2, a turn-off control signal is provided to the gate of the fourth transistor M4 through the first control signal line CS1 to turn off the fourth transistor M4, thereby completing the initialization of the gate of the second transistor M2.

[0171] The turn-off control signal is provided to the gate of the data writing transistor Mp1 in the corresponding third circuit through the first gate line GL1 to turn off the data writing transistor Mp1 in the corresponding third circuit, thereby completing the writing of the data signal to the gate of the driving transistor Md1 in the corresponding third circuit.

[0172] The conduction control signal is provided to the gate of the data write transistor Mp1 in the third circuit in the next row (for example, the second row when the corresponding third circuit is in the first row) through the second gate line GL2, so that the data signal from the second gate line GL2 is transferred from the first electrode of the data write transistor Mp1 in the third circuit in the next row to the second electrode of the data write transistor Mp1 in the third circuit in the next row. The data signal is written to the gate of the drive transistor Md1 in the third circuit in the next row.

[0173] The conduction control signal is provided to the gate of the first transistor M1 through the second light emitting control signal line em2, so that the reference signal from the reference signal line Vref is transferred from the first electrode of the first transistor M1 to the second electrode of the first transistor M1; and then transferred to the first capacitor electrode of the second capacitor C2 in the third circuit in the next row. The reference signal from the reference signal line Vref is written to the first capacitor electrode of the second capacitor C2 in the third circuit in the next row, thereby stabilizing the voltage level of the first capacitor electrode of the second capacitor C2 in the third circuit in the next row, and preventing the voltage level at the gate of the driving transistor Md1 from fluctuating when the data signal is written to the third circuit in a row other than the next row.

[0174] A turn-on control signal is provided to the gate of the second light-emitting control transistor Ms2 through the second light-emitting control signal line em2, so that the initialization voltage signal from the reset signal line Vint is transmitted from the first electrode of the second light-emitting control transistor Ms2 to the second electrode of the second light-emitting control transistor Ms2, and then transmitted to the first electrode of the driving transistor Md1 in the third circuit in the next row, thereby preventing the driving transistor from being abnormally turned on when the data signal is written to the gate of the driving transistor Md1 in the third circuit in the next row.

[0175] For illustration purposes only, Fig. 9 and Figure 5 An example is depicted in which the third circuit is arranged in an array of two rows and two columns. However, the pixel driving circuit may include more than two rows and two columns, or only one row and one column. Figure 6 The operation of the pixel driving circuit is depicted, wherein the third circuit is arranged in an array having n rows. Figure 6 , repeatable data writing steps ( Figure 5 During one image frame, the operation of the pixel driving circuit includes at least (n+1) phases, including the first phase t1, the second phase t2, the (n-1)th phase t(n-1), the nth phase tn, and the light emitting phase te.

[0176] In some embodiments, in the light emitting phase te, a turn-off control signal is provided to the gate of the data writing transistor Mp1 in the corresponding third circuit through the first gate line GL1 to turn off the data writing transistor Mp1 in the corresponding third circuit.

[0177] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the next row through the second gate line GL2 to turn off the data write transistor Mp1 in the third circuit in the next row.

[0178] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the (n-1)th row through the (n-1)th gate line GL(n-1) to turn off the data write transistor Mp1 in the third circuit in the (n-1)th row.

[0179] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the n-th row through the n-th gate line GLn to turn off the data write transistor Mp1 in the third circuit in the n-th row.

[0180] A turn-off control signal is supplied to the gate of the second light emission control transistor Ms2 through the second light emission control signal line em2 to turn off the second light emission control transistor Ms2.

[0181] A turn-off control signal is supplied to the gate of the first transistor M1 through the second light emitting control signal line em2 to turn off the first transistor M1.

[0182] A turn-on control signal is provided to the gate of the fifth transistor M5 through the second control signal line CS2 to turn on the fifth transistor M5.

[0183] When the fifth transistor M5 is turned on, the voltage levels at the gate and the second electrode (eg, the drain) of the second transistor M2 are: (the voltage level of the second voltage supply line Vdd2 + the voltage level of the threshold voltage Vth).

[0184] A turn-on control signal is provided to the gate of the third transistor M3 through the first light emitting control signal line em1 to turn on the third transistor M3. Because the fifth transistor M5 and the third transistor M3 are turned on, the voltage level at the gate and the second electrode of the second transistor M2 is written to the first capacitor electrode of the second capacitor C2. The voltage level at the first capacitor electrode of the second capacitor C2 is then coupled to the gate of the driving transistor Md1. As a result, the voltage difference Vgs between the gate and the first electrode of the driving transistor Md1 is expressed as: (voltage level of the data signal written to the gate of the driving transistor Md1 + voltage level of the second voltage supply line Vdd2 + voltage level of the threshold voltage Vth - voltage level of the reference signal line Vref - voltage level of the first voltage supply line Vdd1). The driving current I flowing through the driving transistor is expressed as K×(Vgs-voltage level of the threshold voltage Vth) 2 , which is equal to K×(the voltage level of the data signal written to the gate of the driving transistor Md1+the voltage level of the second voltage supply line Vdd2−the voltage level of the reference signal line Vref−the voltage level of the first voltage supply line Vdd1) 2 .

[0185] Reference Figure 3 , Fig. 9 and Fig. 7AIn the non-compensation mode, a turn-on control signal is provided through the first light-emitting control signal line em1 throughout the image frame, a turn-off control signal is provided through the second light-emitting control signal line em2 throughout the image frame, and a turn-off control signal is provided through the second control signal line CS2 throughout the image frame. Therefore, in the non-compensation mode, the second transistor M2, the third transistor M3, and the first light-emitting control transistor Ms1 are turned on throughout the image frame. The second voltage supply signal is transmitted through the sixth transistor M6, the second transistor M2, and the third transistor M3, and then transmitted to the first capacitor electrode of the second capacitor C2. The data signal is written to the second capacitor electrode of the second capacitor C2. The operation of the pixel driving circuit does not involve coupling the voltage level at the first capacitor electrode of the second capacitor C2 to the gate of the driving transistor Md1, and does not include the extraction of the threshold voltage Vth.

[0186] Reference Figure 3 , Fig. 9 and Figure 7B In the non-compensation mode, a turn-on control signal is provided through the first light-emitting control signal line em1 throughout the image frame, a turn-off control signal is provided through the second light-emitting control signal line em2 throughout the image frame, a turn-off control signal is provided through the first control signal line CS1 throughout the image frame, and a turn-on control signal is provided through the second control signal line CS2 throughout the image frame. Therefore, in the non-compensation mode, the third transistor M3, the fifth transistor M5, and the first light-emitting control transistor Ms1 are turned on throughout the image frame. The first transistor M1, the second transistor M2, and the fourth transistor M4 are turned off throughout the image frame. The operation of the pixel driving circuit does not involve coupling the voltage level at the first capacitor electrode of the second capacitor C2 to the gate of the driving transistor Md1, and does not include extraction of the threshold voltage Vth.

[0187] For illustration purposes only, Fig. 9 and Fig. 7A An example is depicted in which the third circuit is arranged in an array of two rows and two columns. However, the pixel driving circuit may include more than two rows and two columns, or only one row and one column. Figure 8 The operation of the pixel driving circuit is depicted, wherein the third circuit is arranged in an array having n rows. Figure 8 , repeatable data writing steps ( Fig. 7A t1 and t2 in ), until the process is completed for all n rows of the third circuit.

[0188] Fig.10 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure. Fig.10 The pixel drive circuit depicted in Figure 4 The difference between the pixel driving circuits depicted in FIG. 1 and FIG. 2 is that the first circuit does not include the first capacitor C1.

[0189] Fig.11 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure. Fig.11 The pixel drive circuit depicted in Fig. 9 The difference between the pixel driving circuits depicted in FIG. 1 and FIG. 2 is that the first circuit does not include the first capacitor C1.

[0190] Fig.12 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure. Fig.12 The pixel drive circuit depicted in Figure 4 The difference between the pixel driving circuit depicted in the figure is that the gate of the fourth transistor M4 is coupled to the first gate line GL1 (instead of the first control signal line CS1), the gate of the fifth transistor M5 is coupled to the first light emitting control signal line em1 (instead of the second control signal line CS2), and the first electrode of the sixth transistor M6 is coupled to the first voltage supply line Vdd1 (instead of the second voltage supply line Vdd2).

[0191] Fig.13 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure. Fig.13 The pixel drive circuit depicted in Fig. 9 The difference between the pixel driving circuit depicted in the figure is that the gate of the fourth transistor M4 is coupled to the first gate line GL1 (instead of the first control signal line CS1), the gate of the fifth transistor M5 is coupled to the first light emitting control signal line em1 (instead of the second control signal line CS2), and the first electrode of the second transistor M2 is coupled to the first voltage supply line Vdd1 (instead of the second voltage supply line Vdd2).

[0192] Fig.14 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure. Fig.14 The pixel drive circuit depicted in Fig.10 The difference between the pixel driving circuit depicted in the figure is that the gate of the fourth transistor M4 is coupled to the first gate line GL1 (instead of the first control signal line CS1), the gate of the fifth transistor M5 is coupled to the first light emitting control signal line em1 (instead of the second control signal line CS2), and the first electrode of the sixth transistor M6 is coupled to the first voltage supply line Vdd1 (instead of the second voltage supply line Vdd2).

[0193] Fig.15 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure. Fig.15 The pixel drive circuit depicted in Fig.11The difference between the pixel driving circuit depicted in the figure is that the gate of the fourth transistor M4 is coupled to the first gate line GL1 (instead of the first control signal line CS1), the gate of the fifth transistor M5 is coupled to the first light emitting control signal line em1 (instead of the second control signal line CS2), and the first electrode of the second transistor M2 is coupled to the first voltage supply line Vdd1 (instead of the second voltage supply line Vdd2).

[0194] Fig.16 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Fig.17 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Fig.16 and Fig.17 Depicted Figures 12 to 15 The pixel driving circuit depicted in FIG. 1 operates in compensation mode.

[0195] Fig.18 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Fig.19 is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Fig.18 and Fig.19 Depicted Figures 12 to 15 The pixel driving circuit depicted in FIG. 1 operates in a non-compensated mode.

[0196] Reference Fig.12 , Fig.14 , Fig.16 and Fig.17 During one image frame, the operation of the pixel driving circuit includes a first stage t1, a second stage t2, and a light emitting stage te. In some embodiments, in the first stage t1, a turn-on control signal is provided to the gate of the fourth transistor M4 through the first gate line GL1 to turn on the fourth transistor M4, so that the initialization voltage signal from the reset signal line Vint is transferred from the first electrode of the fourth transistor M4 to the second electrode of the fourth transistor M4; and then to the gate of the second transistor M2. The gate of the second transistor M2 is initialized. A turn-off control signal is provided to the gate of the fifth transistor M5 through the first light emitting control signal line em1 to turn off the fifth transistor M5.

[0197] A turn-off control signal is provided to gates of the third transistor M3 , the sixth transistor M6 , and the first light emission control transistor Ms1 through the first light emission control signal line em1 to turn off the third transistor M3 , the sixth transistor M6 , and the first light emission control transistor Ms1 .

[0198] The conduction control signal is provided to the gate of the first transistor M1 through the second light emitting control signal line em2, so that the reference signal from the reference signal line Vref is transferred from the first electrode of the first transistor M1 to the second electrode of the first transistor M1; and then transferred to the first capacitor electrode of the second capacitor C2 in the corresponding third circuit. The reference signal from the reference signal line Vref is written to the first capacitor electrode of the second capacitor C2 in the corresponding third circuit, thereby stabilizing the voltage level of the first capacitor electrode of the second capacitor C2 in the corresponding third circuit, and preventing the voltage level at the gate of the driving transistor Md1 from fluctuating when the data signal is written to the third circuit in a row other than the row with the corresponding third circuit.

[0199] A turn-on control signal is provided to the gate of the data write transistor Mp1 in the corresponding third circuit through the corresponding gate line (e.g., the first gate line GL1 for the first row third circuit), so that the data signal from the corresponding data line (e.g., the first data line DL1 for the first column third circuit) is transferred from the first electrode of the data write transistor Mp1 to the second electrode of the data write transistor Mp1. The data signal is written to the gate of the drive transistor Md1 in the corresponding third circuit.

[0200] A conduction control signal is provided to the gate of the second light-emitting control transistor Ms2 through the second light-emitting control signal line em2, so that the initialization voltage signal from the reset signal line Vint is transmitted from the first electrode of the second light-emitting control transistor Ms2 to the second electrode of the second light-emitting control transistor Ms2, and then transmitted to the first electrode of the driving transistor Md1 in the corresponding third circuit, thereby preventing the driving transistor from being abnormally turned on when the data signal is written to the gate of the driving transistor Md1 in the corresponding third circuit.

[0201] In some embodiments, in the second phase t2, a turn-off control signal is provided to the gate of the fourth transistor M4 through the first gate line GL1 to turn off the fourth transistor M4. The initialization of the gate of the second transistor M2 is completed.

[0202] The turn-off control signal is provided to the gate of the data writing transistor Mp1 in the corresponding third circuit through the first gate line GL1 to turn off the data writing transistor Mp1 in the corresponding third circuit, thereby completing the writing of the data signal to the gate of the driving transistor Md1 in the corresponding third circuit.

[0203] The conduction control signal is provided to the gate of the data write transistor Mp1 in the third circuit in the next row (for example, the second row when the corresponding third circuit is in the first row) through the second gate line GL2, so that the data signal from the second gate line GL2 is transferred from the first electrode of the data write transistor Mp1 in the third circuit in the next row to the second electrode of the data write transistor Mp1 in the third circuit in the next row. The data signal is written to the gate of the drive transistor Md1 in the third circuit in the next row.

[0204] The conduction control signal is provided to the gate of the first transistor M1 through the second light emitting control signal line em2, so that the reference signal from the reference signal line Vref is transferred from the first electrode of the first transistor M1 to the second electrode of the first transistor M1; and then transferred to the first capacitor electrode of the second capacitor C2 in the third circuit in the next row. The reference signal from the reference signal line Vref is written to the first capacitor electrode of the second capacitor C2 in the third circuit in the next row, thereby stabilizing the voltage level of the first capacitor electrode of the second capacitor C2 in the third circuit in the next row, and preventing the voltage level at the gate of the driving transistor Md1 from fluctuating when the data signal is written to the third circuit in a row other than the next row.

[0205] A turn-on control signal is provided to the gate of the second light-emitting control transistor Ms2 through the second light-emitting control signal line em2, so that the initialization voltage signal from the reset signal line Vint is transmitted from the first electrode of the second light-emitting control transistor Ms2 to the second electrode of the second light-emitting control transistor Ms2, and then transmitted to the first electrode of the driving transistor Md1 in the third circuit in the next row, thereby preventing the driving transistor from being abnormally turned on when the data signal is written to the gate of the driving transistor Md1 in the third circuit in the next row.

[0206] For illustration purposes only, Fig.12 , Fig.14 and Fig.16 An example is depicted in which the third circuit is arranged in an array of two rows and two columns. However, the pixel driving circuit may include more than two rows and two columns, or only one row and one column.

[0207] Fig.17 The operation of the pixel driving circuit is depicted, wherein the third circuit is arranged in an array having n rows. Fig.17 , repeatable data writing steps ( Fig.16 During one image frame, the operation of the pixel driving circuit includes at least (n+1) phases, including the first phase t1, the second phase t2, the (n-1)th phase t(n-1), the nth phase tn, and the light emitting phase te.

[0208] In some embodiments, in the light emitting phase te, a turn-off control signal is provided to the gate of the data writing transistor Mp1 in the corresponding third circuit through the first gate line GL1 to turn off the data writing transistor Mp1 in the corresponding third circuit.

[0209] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the next row through the second gate line GL2 to turn off the data write transistor Mp1 in the third circuit in the next row.

[0210] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the (n-1)th row through the (n-1)th gate line GL(n-1) to turn off the data write transistor Mp1 in the third circuit in the (n-1)th row.

[0211] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the n-th row through the n-th gate line GLn to turn off the data write transistor Mp1 in the third circuit in the n-th row.

[0212] A turn-off control signal is supplied to the gate of the second light emission control transistor Ms2 through the second light emission control signal line em2 to turn off the second light emission control transistor Ms2.

[0213] A turn-off control signal is supplied to the gate of the first transistor M1 through the second light emitting control signal line em2 to turn off the first transistor M1.

[0214] A turn-on control signal is supplied to the gate of the fifth transistor M5 through the first light emitting control signal line em1 to turn on the fifth transistor M5.

[0215] A turn-on control signal is supplied to the gate of the sixth transistor M6 through the first light emitting control signal line em1 to turn on the sixth transistor M6.

[0216] When the fifth transistor M5 and the sixth transistor M6 are turned on, the voltage levels at the gate and the second electrode (eg, the drain) of the second transistor M2 are: (the voltage level of the first voltage supply line Vdd1 + the voltage level of the threshold voltage Vth).

[0217] A turn-on control signal is provided to the gate of the third transistor M3 through the first light emitting control signal line em1 to turn on the third transistor M3. Because the fifth transistor M5 and the third transistor M3 are turned on, the voltage level at the gate and the second electrode of the second transistor M2 is written to the first capacitor electrode of the second capacitor C2. The voltage level at the first capacitor electrode of the second capacitor C2 is then coupled to the gate of the driving transistor Md1. As a result, the voltage difference Vgs between the gate and the first electrode of the driving transistor Md1 is expressed as: (the voltage level of the data signal written to the gate of the driving transistor Md1 + the voltage level of the first voltage supply line Vdd1 + the voltage level of the threshold voltage Vth - the voltage level of the reference signal line Vref - the voltage level of the first voltage supply line Vdd1) = (the voltage level of the data signal written to the gate of the driving transistor Md1 + the voltage level of the threshold voltage Vth - the voltage level of the reference signal line Vref). The driving current I flowing through the driving transistor is expressed as K×(Vgs-the voltage level of the threshold voltage Vth) 2 , which is equal to K×(the voltage level of the data signal written to the gate of the driving transistor Md1 - the voltage level of the reference signal line Vref) 2 .

[0218] Fig.18 FIG. 2 shows the operation of the pixel driving circuit in the non-compensation mode. Fig.12 , Fig.14 and Fig.18 In the non-compensation mode, a turn-on control signal is provided through the first light-emitting control signal line em1 throughout the image frame, and a turn-off control signal is provided through the second light-emitting control signal line em2 throughout the image frame. Therefore, in the non-compensation mode, the second transistor M2, the third transistor M3, the sixth transistor M6, and the first light-emitting control transistor Ms1 are turned on throughout the image frame. The first voltage supply signal from the first voltage supply line Vdd1 is transmitted through the sixth transistor M6, the second transistor M2, and the third transistor M3, and then transmitted to the first capacitor electrode of the second capacitor C2. The data signal is written to the second capacitor electrode of the second capacitor C2. The operation of the pixel driving circuit does not involve coupling the voltage level at the first capacitor electrode of the second capacitor C2 to the gate of the driving transistor Md1, and does not include the extraction of the threshold voltage Vth.

[0219] For illustration purposes only, Fig.12 , Fig.14 and Fig.18 An example is depicted in which the third circuit is arranged in an array of two rows and two columns. However, the pixel driving circuit may include more than two rows and two columns, or only one row and one column.

[0220] Fig.19The operation of the pixel driving circuit is depicted, wherein the third circuit is arranged in an array having n rows. Fig.19 , repeatable data writing steps ( Fig.18 t1 and t2 in ), until the process is completed for all n rows of the third circuit.

[0221] Reference Fig.13 , Fig.15 , Fig.16 and Fig.17 In the compensation mode, during one image frame, the operation of the pixel driving circuit includes a first stage t1, a second stage t2, and a light emitting stage te. In some embodiments, in the first stage t1, a turn-on control signal is provided to the gate of the fourth transistor M4 through the first gate line GL1 to turn on the fourth transistor M4, so that the initialization voltage signal from the reset signal line Vint is transferred from the first electrode of the fourth transistor M4 to the second electrode of the fourth transistor M4; and then to the gate of the second transistor M2. The gate of the second transistor M2 is initialized. A turn-off control signal is provided to the gate of the fifth transistor M5 through the first light emitting control signal line em1 to turn off the fifth transistor M5.

[0222] A turn-off control signal is supplied to gates of the third transistor M3 and the first light emission control transistor Ms1 through the first light emission control signal line em1 to turn off the third transistor M3 and the first light emission control transistor Ms1.

[0223] The conduction control signal is provided to the gate of the first transistor M1 through the second light emitting control signal line em2, so that the reference signal from the reference signal line Vref is transferred from the first electrode of the first transistor M1 to the second electrode of the first transistor M1; and then transferred to the first capacitor electrode of the second capacitor C2 in the corresponding third circuit. The reference signal from the reference signal line Vref is written to the first capacitor electrode of the second capacitor C2 in the corresponding third circuit, thereby stabilizing the voltage level of the first capacitor electrode of the second capacitor C2 in the corresponding third circuit, and preventing the voltage level at the gate of the driving transistor Md1 from fluctuating when the data signal is written to the third circuit in a row other than the row with the corresponding third circuit.

[0224] A turn-on control signal is provided to the gate of the data write transistor Mp1 in the corresponding third circuit through the corresponding gate line (e.g., the first gate line GL1 for the first row third circuit), so that the data signal from the corresponding data line (e.g., the first data line DL1 for the first column third circuit) is transferred from the first electrode of the data write transistor Mp1 to the second electrode of the data write transistor Mp1. The data signal is written to the gate of the drive transistor Md1 in the corresponding third circuit.

[0225] A conduction control signal is provided to the gate of the second light-emitting control transistor Ms2 through the second light-emitting control signal line em2, so that the initialization voltage signal from the reset signal line Vint is transmitted from the first electrode of the second light-emitting control transistor Ms2 to the second electrode of the second light-emitting control transistor Ms2, and then transmitted to the first electrode of the driving transistor Md1 in the corresponding third circuit, thereby preventing the driving transistor from being abnormally turned on when the data signal is written to the gate of the driving transistor Md1 in the corresponding third circuit.

[0226] In some embodiments, in the second phase t2, a turn-off control signal is provided to the gate of the fourth transistor M4 through the first gate line GL1 to turn off the fourth transistor M4. The initialization of the gate of the second transistor M2 is completed.

[0227] The turn-off control signal is provided to the gate of the data writing transistor Mp1 in the corresponding third circuit through the first gate line GL1 to turn off the data writing transistor Mp1 in the corresponding third circuit, thereby completing the writing of the data signal to the gate of the driving transistor Md1 in the corresponding third circuit.

[0228] The conduction control signal is provided to the gate of the data write transistor Mp1 in the third circuit in the next row (for example, the second row when the corresponding third circuit is in the first row) through the second gate line GL2, so that the data signal from the second gate line GL2 is transferred from the first electrode of the data write transistor Mp1 in the third circuit in the next row to the second electrode of the data write transistor Mp1 in the third circuit in the next row. The data signal is written to the gate of the drive transistor Md1 in the third circuit in the next row.

[0229] The conduction control signal is provided to the gate of the first transistor M1 through the second light emitting control signal line em2, so that the reference signal from the reference signal line Vref is transferred from the first electrode of the first transistor M1 to the second electrode of the first transistor M1; and then transferred to the first capacitor electrode of the second capacitor C2 in the third circuit in the next row. The reference signal from the reference signal line Vref is written to the first capacitor electrode of the second capacitor C2 in the third circuit in the next row, thereby stabilizing the voltage level of the first capacitor electrode of the second capacitor C2 in the third circuit in the next row, and preventing the voltage level at the gate of the driving transistor Md1 from fluctuating when the data signal is written to the third circuit in a row other than the next row.

[0230] A turn-on control signal is provided to the gate of the second light-emitting control transistor Ms2 through the second light-emitting control signal line em2, so that the initialization voltage signal from the reset signal line Vint is transmitted from the first electrode of the second light-emitting control transistor Ms2 to the second electrode of the second light-emitting control transistor Ms2, and then transmitted to the first electrode of the driving transistor Md1 in the third circuit in the next row, thereby preventing the driving transistor from being abnormally turned on when the data signal is written to the gate of the driving transistor Md1 in the third circuit in the next row.

[0231] For illustration purposes only, Fig.13 , Fig.15 and Fig.16 An example is depicted in which the third circuit is arranged in an array of two rows and two columns. However, the pixel driving circuit may include more than two rows and two columns, or only one row and one column. Fig.17 The operation of the pixel driving circuit is depicted, wherein the third circuit is arranged in an array having n rows. Fig.17 , repeatable data writing steps ( Fig.16 During one image frame, the operation of the pixel driving circuit includes at least (n+1) phases, including the first phase t1, the second phase t2, the (n-1)th phase t(n-1), the nth phase tn, and the light emitting phase te.

[0232] In some embodiments, in the light emitting phase te, a turn-off control signal is provided to the gate of the data writing transistor Mp1 in the corresponding third circuit through the first gate line GL1 to turn off the data writing transistor Mp1 in the corresponding third circuit.

[0233] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the next row through the second gate line GL2 to turn off the data write transistor Mp1 in the third circuit in the next row.

[0234] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the (n-1)th row through the (n-1)th gate line GL(n-1) to turn off the data write transistor Mp1 in the third circuit in the (n-1)th row.

[0235] A turn-off control signal is supplied to the gate of the data write transistor Mp1 in the third circuit in the n-th row through the n-th gate line GLn to turn off the data write transistor Mp1 in the third circuit in the n-th row.

[0236] A turn-off control signal is supplied to the gate of the second light emission control transistor Ms2 through the second light emission control signal line em2 to turn off the second light emission control transistor Ms2.

[0237] A turn-off control signal is supplied to the gate of the first transistor M1 through the second light emitting control signal line em2 to turn off the first transistor M1.

[0238] A turn-on control signal is supplied to the gate of the fifth transistor M5 through the first light emitting control signal line em1 to turn on the fifth transistor M5.

[0239] When the fifth transistor M5 is turned on, the voltage levels at the gate and the second electrode (eg, the drain) of the second transistor M2 are: (the voltage level of the first voltage supply line Vdd1 + the voltage level of the threshold voltage Vth).

[0240] A turn-on control signal is provided to the gate of the third transistor M3 through the first light emitting control signal line em1 to turn on the third transistor M3. Because the fifth transistor M5 and the third transistor M3 are turned on, the voltage level at the gate and the second electrode of the second transistor M2 is written to the first capacitor electrode of the second capacitor C2. The voltage level at the first capacitor electrode of the second capacitor C2 is then coupled to the gate of the driving transistor Md1. As a result, the voltage difference Vgs between the gate and the first electrode of the driving transistor Md1 is expressed as: (the voltage level of the data signal written to the gate of the driving transistor Md1 + the voltage level of the first voltage supply line Vdd1 + the voltage level of the threshold voltage Vth - the voltage level of the reference signal line Vref - the voltage level of the first voltage supply line Vdd1) = (the voltage level of the data signal written to the gate of the driving transistor Md1 + the voltage level of the threshold voltage Vth - the voltage level of the reference signal line Vref). The driving current I flowing through the driving transistor is expressed as K×(Vgs-the voltage level of the threshold voltage Vth) 2 , which is equal to K×(the voltage level of the data signal written to the gate of the driving transistor Md1 - the voltage level of the reference signal line Vref) 2 .

[0241] Reference Figure 3 , Fig.13 , Fig.15 and Fig.18In the non-compensation mode, a turn-on control signal is provided through the first light-emitting control signal line em1 throughout the image frame, and a turn-off control signal is provided through the second light-emitting control signal line em2 throughout the image frame. Therefore, in the non-compensation mode, the second transistor M2, the third transistor M3, and the first light-emitting control transistor Ms1 are turned on throughout the image frame. The first voltage supply signal from the first voltage supply line Vdd1 is transmitted through the sixth transistor M6, the second transistor M2, and the third transistor M3, and then transmitted to the first capacitor electrode of the second capacitor C2. The data signal is written to the second capacitor electrode of the second capacitor C2. The operation of the pixel driving circuit does not involve coupling the voltage level at the first capacitor electrode of the second capacitor C2 to the gate of the driving transistor Md1, and does not include the extraction of the threshold voltage Vth.

[0242] For illustration purposes only, Fig.13 , Fig.15 and Fig.18 An example is depicted in which the third circuit is arranged in an array of two rows and two columns. However, the pixel driving circuit may include more than two rows and two columns, or only one row and one column. Fig.19 The operation of the pixel driving circuit is depicted, wherein the third circuit is arranged in an array having n rows. Fig.19 , repeatable data writing steps ( Fig.18 t1 and t2 in ), until the process is completed for all n rows of the third circuit.

[0243] Fig. 20 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure. Fig. 20 The pixel drive circuit depicted in Figure 4 The difference between the pixel drive circuit depicted in is that Fig. 20 The transistors in the pixel drive circuit depicted in FIG. 1 are n-type transistors, while Figure 4 The transistors in the pixel driving circuit depicted in are p-type transistors.

[0244] Fig.21 is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. Figure 3 and Fig.21 In some embodiments, the first circuit Cir1 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a first capacitor C1.

[0245] In some embodiments, the gate of the first transistor M1 is coupled to the second light emitting control signal line em2, the first electrode of the first transistor M1 is coupled to the reference signal line Vref, and the second electrode of the first transistor M1 is coupled to the second electrode of the third transistor M3 and the second capacitor electrode of the first capacitor C1.

[0246] In some embodiments, the gate of the second transistor M2 is coupled to the second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5, the first electrode of the second transistor M2 is coupled to the second electrode of the sixth transistor M6 and the second electrode of the seventh transistor M7, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3 and the second electrode of the fifth transistor M5.

[0247] In some embodiments, the gate of the third transistor M3 is coupled to the first light emitting control signal line em1; the first electrode of the third transistor M3 is coupled to the second electrode of the second transistor M2 and the second electrode of the fifth transistor M5; the second electrode of the third transistor M3 is coupled to the second electrode of the first transistor M1 and the second capacitor electrode of the first capacitor C1.

[0248] In some embodiments, a gate of the fourth transistor M4 is coupled to the first control signal line CS1; a first electrode of the fourth transistor M4 is coupled to the reset signal line Vint; a second electrode of the fourth transistor M4 is coupled to the gate of the second transistor M2 and a first electrode of the fifth transistor M5.

[0249] In some embodiments, the gate of the fifth transistor M5 is coupled to the second control signal line CS2, the first electrode of the fifth transistor M5 is coupled to the gate of the second transistor M2 and the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is coupled to the first electrode of the third transistor M3 and the second electrode of the second transistor M2.

[0250] In some embodiments, a gate of the sixth transistor M6 is coupled to the first light emission control signal line em1, a first electrode of the sixth transistor M6 is coupled to the second voltage supply line Vdd2, and a second electrode of the sixth transistor M6 is coupled to the first electrode of the second transistor M2.

[0251] In some embodiments, the gate of the seventh transistor M7 is coupled to the reset control signal line rst, the first electrode of the seventh transistor M7 is coupled to the second reset signal line Vint2, and the second electrode of the seventh transistor M7 is coupled to the first electrode of the second transistor M2 and the second electrode of the sixth transistor M6. In one example, the reset control signal line rst is an independent signal line. In another example, the reset control signal line rst is the same as the first control signal line CS1. In another example, the reset control signal line rst is the same as the first gate line GL1. In one example, the second reset signal line Vint2 is an independent signal line. In another example, the second reset signal line Vint2 is the same as the reset signal line Vint.

[0252] In some embodiments, a first capacitor electrode of the first capacitor C1 is coupled to a first electrode of the sixth transistor M6 and a second voltage supply line Vdd2 , and a second capacitor electrode of the first capacitor C1 is coupled to second electrodes of the first transistor M1 and the third transistor M3 .

[0253] In some embodiments, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to each third circuit. Optionally, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to the first capacitor electrode of the second capacitor C2 of each third circuit.

[0254] Fig.21 The structure of the second circuit Cir2 and one or more third circuits Cir3 of the pixel driving circuit depicted in Figure 4 The structure depicted in is very similar.

[0255] Fig. 22 is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. Fig. 22 , Fig. 22 The operation of the pixel drive circuit depicted in Figure 5 and Figure 6 The operation of the pixel driving circuit depicted in is similar. Fig. 22The operation of the pixel driving circuit depicted in also includes the participation of the reset control signal line rst. In some embodiments, in the first stage t1, the turn-on control signal is provided to the gate of the seventh transistor M7 through the reset control signal line rst to turn on the seventh transistor M7, so that the initialization voltage signal from the second reset signal line Vint2 is transferred from the first electrode of the seventh transistor M7 to the second electrode of the seventh transistor M7; and then to the first electrode of the second transistor M2. Initialize the first electrode of the second transistor M2. The inventors of the present disclosure have found that by setting the seventh transistor M7, the change of the threshold voltage of the driving transistor in one or more third circuits can be better compensated.

[0256] Fig. 22 The operation of the pixel driving circuit in the second phase t2 and the light emitting phase te depicted in FIG. Figure 5 and Figure 6 The operation depicted in is very similar.

[0257] Fig.23 is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. Figure 3 and Fig.23 In some embodiments, the first circuit Cir1 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, an eighth transistor M8 and a first capacitor C1.

[0258] In some embodiments, the gate of the first transistor M1 is coupled to the second light emitting control signal line em2, the first electrode of the first transistor M1 is coupled to the reference signal line Vref, and the second electrode of the first transistor M1 is coupled to the second electrode of the third transistor M3 and the second capacitor electrode of the first capacitor C1.

[0259] In some embodiments, the gate of the second transistor M2 is coupled to the second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5, the first electrode of the second transistor M2 is coupled to the second electrode of the sixth transistor M6, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3 and the second electrode of the fifth transistor M5.

[0260] In some embodiments, the gate of the third transistor M3 is coupled to the first light emitting control signal line em1; the first electrode of the third transistor M3 is coupled to the second electrode of the second transistor M2 and the second electrode of the fifth transistor M5; the second electrode of the third transistor M3 is coupled to the second electrode of the first transistor M1 and the second capacitor electrode of the first capacitor C1.

[0261] In some embodiments, a gate of the fourth transistor M4 is coupled to the first control signal line CS1; a first electrode of the fourth transistor M4 is coupled to the reset signal line Vint; a second electrode of the fourth transistor M4 is coupled to the gate of the second transistor M2 and a first electrode of the fifth transistor M5.

[0262] In some embodiments, the gate of the fifth transistor M5 is coupled to the second control signal line CS2, the first electrode of the fifth transistor M5 is coupled to the gate of the second transistor M2 and the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is coupled to the first electrode of the third transistor M3 and the second electrode of the second transistor M2.

[0263] In some embodiments, a gate of the sixth transistor M6 is coupled to the first light emission control signal line em1, a first electrode of the sixth transistor M6 is coupled to the second voltage supply line Vdd2, and a second electrode of the sixth transistor M6 is coupled to the first electrode of the second transistor M2.

[0264] In some embodiments, a first capacitor electrode of the first capacitor C1 is coupled to a first electrode of the sixth transistor M6 and a second voltage supply line Vdd2 , and a second capacitor electrode of the first capacitor C1 is coupled to second electrodes of the first transistor M1 and the third transistor M3 .

[0265] In some embodiments, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to each third circuit. Optionally, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to the first capacitor electrode of the second capacitor C2 of each third circuit.

[0266] In some embodiments, the gate of the eighth transistor M8 is coupled to the third control signal line CS3; the first electrode of the eighth transistor M8 is coupled to the first capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3; the second electrode of the eighth transistor M8 is coupled to the sensing line SL. The sensing line SL is coupled to an external compensation circuit, which is configured to further compensate for changes in the threshold voltage of the driving transistor in one or more third circuits. The inventors of the present disclosure have found that by coupling the eighth transistor M8 to the external compensation circuit, changes in the threshold voltage of the driving transistor in one or more third circuits can be better compensated. In one example, the third control signal line CS3 is an independent signal line. In another example, the third control signal line CS3 is the same as the second light emitting control signal line em2.

[0267] Fig.23The structure of the second circuit Cir2 and one or more third circuits Cir3 of the pixel driving circuit depicted in Figure 4 The structure depicted in is very similar.

[0268] Fig.24 is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. Fig.24 , the operation of the pixel driving circuit includes an internal compensation period ICS and an external compensation period ECS. Fig.24 The internal compensation period depicted in the ICS is the operation of the pixel drive circuit with Figure 5 and Figure 6 The operation depicted in is very similar, Fig.24 The operation of the pixel driving circuit depicted in FIG. 1 also includes the participation of the third control signal line CS3. Fig.24 In some embodiments, during the external compensation period, a turn-on control signal is provided to the gate of the eighth transistor M8 through the third control signal line CS3 to turn on the eighth transistor M8, so that the voltage signals at the first capacitor electrode of the first capacitor C1 and the second electrodes of the first transistor M1 and the third transistor M3 are transferred from the first electrode of the eighth transistor M8 to the second electrode of the eighth transistor M8; and then transferred to the external compensation circuit. The inventors of the present disclosure have found that by setting the eighth transistor M8, the change of the threshold voltage of the driving transistor in one or more third circuits can be better compensated.

[0269] Fig.25 is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. Figure 3 and Fig.25 In some embodiments, the first circuit Cir1 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a ninth transistor M9, a tenth transistor M10 and a first capacitor C1.

[0270] In some embodiments, the gate of the first transistor M1 is coupled to the second light emitting control signal line em2, the first electrode of the first transistor M1 is coupled to the reference signal line Vref, and the second electrode of the first transistor M1 is coupled to the second electrode of the third transistor M3 and the second capacitor electrode of the first capacitor C1.

[0271] In some embodiments, the gate of the second transistor M2 is coupled to the second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5, the first electrode of the second transistor M2 is coupled to the second electrode of the sixth transistor M6, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3 and the second electrode of the fifth transistor M5.

[0272] In some embodiments, the gate of the third transistor M3 is coupled to the first light emitting control signal line em1; the first electrode of the third transistor M3 is coupled to the second electrode of the second transistor M2 and the second electrode of the fifth transistor M5; the second electrode of the third transistor M3 is coupled to the second electrode of the first transistor M1 and the second capacitor electrode of the first capacitor C1.

[0273] In some embodiments, a gate of the fourth transistor M4 is coupled to the first control signal line CS1; a first electrode of the fourth transistor M4 is coupled to the reset signal line Vint; a second electrode of the fourth transistor M4 is coupled to the gate of the second transistor M2 and a first electrode of the fifth transistor M5.

[0274] In some embodiments, the gate of the fifth transistor M5 is coupled to the second control signal line CS2, the first electrode of the fifth transistor M5 is coupled to the gate of the second transistor M2 and the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is coupled to the first electrode of the third transistor M3 and the second electrode of the second transistor M2.

[0275] In some embodiments, a gate of the sixth transistor M6 is coupled to the first light emission control signal line em1, a first electrode of the sixth transistor M6 is coupled to the second voltage supply line Vdd2, and a second electrode of the sixth transistor M6 is coupled to the first electrode of the second transistor M2.

[0276] In some embodiments, a first capacitor electrode of the first capacitor C1 is coupled to a first electrode of the sixth transistor M6 and a second voltage supply line Vdd2 , and a second capacitor electrode of the first capacitor C1 is coupled to second electrodes of the first transistor M1 and the third transistor M3 .

[0277] In some embodiments, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to each third circuit. Optionally, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to the first capacitor electrode of the second capacitor C2 of each third circuit.

[0278] In some embodiments, the gate of the ninth transistor M9 is coupled to the third control signal line CS3, the first electrode of the ninth transistor M9 is coupled to the reference signal line Vref, and the second electrode of the ninth transistor M9 is coupled to the first electrode of the first transistor M1 and the first electrode of the tenth transistor M10. In one example, the third control signal line CS3 is an independent signal line. In another example, the third control signal line CS3 is the same as the fourth control signal line CS4. In another example, the third control signal line CS3 is the same as the second light emitting control signal line em2.

[0279] In some embodiments, the gate of the tenth transistor M10 is coupled to the fourth control signal line CS4, the first electrode of the tenth transistor M10 is coupled to the first electrode of the first transistor M1 and the second electrode of the ninth transistor M9, and the second electrode of the tenth transistor M10 is coupled to the sensing line SL. The sensing line SL is coupled to an external compensation circuit, which is configured to further compensate for the change in the threshold voltage of the driving transistor in one or more third circuits. In one example, the fourth control signal line CS4 is an independent signal line. In another example, the fourth control signal line CS4 is the same as the third control signal line CS3. In another example, the fourth control signal line CS4 is the same as the second light emitting control signal line em2. In another example, the third control signal line CS3, the fourth control signal line CS4 and the second light emitting control signal line em2 are the same signal line.

[0280] The inventors of the present disclosure have discovered that by providing the ninth transistor M9 and the tenth transistor M10 coupled to an external compensation circuit, the variation of the threshold voltage of the driving transistor in one or more third circuits can be better compensated.

[0281] Fig.25 The structure of the second circuit Cir2 and one or more third circuits Cir3 of the pixel driving circuit depicted in Figure 4 The structure depicted in is very similar.

[0282] Fig.26 is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. Fig.24 , the operation of the pixel driving circuit includes an internal compensation period ICS and an external compensation period ECS. Fig.26 The internal compensation period of the ICS pixel drive circuit is depicted in the operation with Figure 5 and Figure 6 The operation depicted in is very similar. Fig.26 The operation of the pixel driving circuit depicted in FIG. 1 also includes the participation of the third control signal line CS3 and the fourth control signal line CS4. Fig.26 In some embodiments, in the first stage t1 or the second stage t2 of the internal compensation period ICS, a turn-on control signal is provided to the gate of the ninth transistor M9 through the third control signal line CS3 to turn on the ninth transistor M9, so that the reference signal is transmitted from the first electrode of the ninth transistor M9 to the second electrode of the ninth transistor M9; and then to the first electrode of the first transistor M1.

[0283] In the first stage t1 or the second stage t2 of the internal compensation period ICS, a turn-on control signal is provided to the gate of the first transistor M1 through the second light-emitting control signal em2 to turn on the first transistor M1, so that the reference signal is transmitted from the first electrode of the first transistor M1 to the second electrode of the first transistor M1; and then transmitted to the first capacitor electrode of the second capacitor C2 in the third circuit (for example, the third circuit in the current row relative to the first stage t1, or the third circuit in the next row relative to the second stage t2).

[0284] During the external compensation period ECS, a turn-on control signal is provided to the gate of the tenth transistor M10 through the fourth control signal line CS4 to turn on the tenth transistor M10, so that the voltage signal at the first electrode of the first transistor M1 (which is maintained as the voltage level of the first capacitor electrode of the first capacitor C1 and the second electrodes of the first transistor M1 and the third transistor M3 during the internal compensation period ICS) is transferred from the first electrode of the tenth transistor M10 to the second electrode of the tenth transistor M10; and then to the external compensation circuit. The inventors of the present disclosure have found that by setting the tenth transistor M10, the change in the threshold voltage of the driving transistor in one or more third circuits can be better compensated.

[0285] Fig. 27 is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. Figure 3 and Fig. 27 In some embodiments, the first circuit Cir1 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a first capacitor C1.

[0286] In some embodiments, the gate of the first transistor M1 is coupled to the second light emitting control signal line em2, the first electrode of the first transistor M1 is coupled to the reference signal line Vref, and the second electrode of the first transistor M1 is coupled to the second electrode of the third transistor M3 and the second capacitor electrode of the first capacitor C1.

[0287] In some embodiments, the gate of the second transistor M2 is coupled to the second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5, the first electrode of the second transistor M2 is coupled to the second electrode of the sixth transistor M6, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3 and the second electrode of the fifth transistor M5.

[0288] In some embodiments, the gate of the third transistor M3 is coupled to the first light emitting control signal line em1; the first electrode of the third transistor M3 is coupled to the second electrode of the second transistor M2 and the second electrode of the fifth transistor M5; the second electrode of the third transistor M3 is coupled to the second electrode of the first transistor M1 and the second capacitor electrode of the first capacitor C1.

[0289] In some embodiments, a gate of the fourth transistor M4 is coupled to the first control signal line CS1; a first electrode of the fourth transistor M4 is coupled to the reset signal line Vint; a second electrode of the fourth transistor M4 is coupled to the gate of the second transistor M2 and a first electrode of the fifth transistor M5.

[0290] In some embodiments, the gate of the fifth transistor M5 is coupled to the second control signal line CS2, the first electrode of the fifth transistor M5 is coupled to the gate of the second transistor M2 and the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is coupled to the first electrode of the third transistor M3 and the second electrode of the second transistor M2.

[0291] In some embodiments, a gate of the sixth transistor M6 is coupled to the first light emission control signal line em1, a first electrode of the sixth transistor M6 is coupled to the second voltage supply line Vdd2, and a second electrode of the sixth transistor M6 is coupled to the first electrode of the second transistor M2.

[0292] In some embodiments, a first capacitor electrode of the first capacitor C1 is coupled to the second electrode of the sixth transistor M6 and the first electrode of the second transistor M2 , and a second capacitor electrode of the first capacitor C1 is coupled to the second electrode of the first transistor M1 and the second electrode of the third transistor M3 .

[0293] In some embodiments, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to each third circuit. Optionally, the second capacitor electrode of the first capacitor C1, the second electrode of the first transistor M1, and the second electrode of the third transistor M3 are coupled to the first capacitor electrode of the second capacitor C2 of each third circuit.

[0294] Fig. 27 The structure of the second circuit Cir2 and one or more third circuits Cir3 of the pixel driving circuit depicted in Figure 4 is very similar to the structure depicted in Fig. 27 The operation of the pixel drive circuit depicted in Figure 5 and Figure 6 The operation depicted in is very similar.

[0295] Fig.28is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. Fig.28 In some embodiments, at least one (eg, both) of the first transistor M1 and the fourth transistor M4 is a dual-gate transistor. The inventors of the present disclosure have found that by making at least one of the first transistor M1 and the fourth transistor M4 a dual-gate transistor, the leakage current in the first circuit can be further reduced.

[0296] Fig.29 is a circuit diagram of a pixel driving circuit in some embodiments of the present disclosure. Fig.29 The pixel drive circuit depicted in Figure 4 The difference between the pixel drive circuit depicted in is that Fig.29 The first transistor M1 and the fourth transistor M4 in the pixel driving circuit depicted in FIG. 1 are n-type transistors, and Figure 4 The first transistor M1 and the fourth transistor M4 in the pixel driving circuit depicted in the figure are p-type transistors. The inventors of the present disclosure have found that by making at least one of the first transistor M1 and the fourth transistor M4 an n-type transistor, the leakage current in the first circuit can be further reduced. N-type transistors such as metal oxide transistors have relatively small leakage currents. P-type transistors such as low temperature polysilicon transistors have relatively high mobility and enhanced driving capabilities.

[0297] Reference Figure 3 , Figure 4 , Figures 9 to 15 , Fig.17 , Fig. 20 , Fig.21 , Fig.23 , Fig.25 and Figure 27 to Figure 29 In some embodiments, one or more third circuits are arranged in an array having multiple rows and multiple columns. In some embodiments, the third circuits in the same column are coupled to the same data line, and the third circuits in the same row are coupled to the same gate line. In some embodiments, the second capacitors in the third circuits in different rows have different capacitances. In some embodiments, the capacitance of the second capacitors in the third circuits decreases row by row (e.g., from the first row to the second row).

[0298] In some embodiments, the pixel driving circuit is configured to drive a plurality of sub-pixels to emit light, the plurality of sub-pixels including a first sub-pixel configured to emit light of a first color, a second sub-pixel configured to emit light of a second color, and a third sub-pixel configured to emit light of a third color. In one example, the first color is red, the second color is green, and the third color is blue. In some embodiments, a driving transistor in a third circuit in the pixel driving circuit configured to drive the first sub-pixel, the second sub-pixel, and the third sub-pixel to emit light has the same ratio of channel length to channel width; and

[0299] For example, or

[0300] Wherein, W2 represents the channel width of the second transistor M2 , L2 represents the channel length of the second transistor M2 , Wd1 represents the channel width of the driving transistor Md1 in each third circuit, and Ld1 represents the channel length of the driving transistor Md1 in each third circuit.

[0301] In some embodiments, the array substrate with the pixel driving circuit is a silicon-based array substrate. The silicon-based semiconductor process can ensure the uniformity of transistors (eg, driving transistors in one or more third circuits and second transistors in the first circuit).

[0302] Fig.30 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Fig.30 In some embodiments, the display panel includes a plurality of sub-pixels, the plurality of sub-pixels including a first sub-pixel Sp1 configured to emit light of a first color, a second sub-pixel Sp2 configured to emit light of a second color, and a third sub-pixel Sp3 configured to emit light of a third color. In one example, the first color is red, the second color is green, and the third color is blue.

[0303] In some embodiments, the same pixel driving circuit is configured to drive sub-pixels of the same color to emit light. In one example, the first pixel driving circuit is configured to drive a first sub-pixel of a first color to emit light. In another example, the second pixel driving circuit is configured to drive a second sub-pixel of a second color to emit light. In another example, the third pixel driving circuit is configured to drive a third sub-pixel of a third color to emit light. Fig.30 A first pixel driving circuit PDC1 is shown, which is configured to drive a first sub-pixel (eg Sp1 ) of a first color to emit light.

[0304] In some embodiments, the driving transistors in the third circuit in the first pixel driving circuit configured to drive the first sub-pixel of the first color (eg, the red sub-pixel) to emit light have the same ratio of channel length to channel width; and

[0305] For example, or

[0306] Among them, W12 represents the channel width of the second transistor M2 in the first pixel driving circuit, L12 represents the channel length of the second transistor M2 in the first pixel driving circuit, Wd11 represents the channel width of the driving transistor Md1 in each third circuit in the first pixel driving circuit, and Ld11 represents the channel length of the driving transistor Md1 in each third circuit in the first pixel driving circuit.

[0307] In some embodiments, the driving transistors in the third circuit in the second pixel driving circuit configured to drive the second sub-pixel of the second color (eg, the green sub-pixel) to emit light have the same ratio of channel length to channel width; and

[0308] For example, or

[0309] Among them, W22 represents the channel width of the second transistor M2 in the second pixel driving circuit, L22 represents the channel length of the second transistor M2 in the second pixel driving circuit, Wd21 represents the channel width of the driving transistor Md1 in each third circuit in the second pixel driving circuit, and Ld21 represents the channel length of the driving transistor Md1 in each third circuit in the second pixel driving circuit.

[0310] In some embodiments, the driving transistors in the third circuit in the third pixel driving circuit configured to drive the third sub-pixel of the third color (eg, the blue sub-pixel) to emit light have the same ratio of channel length to channel width; and

[0311] For example, or

[0312] Among them, W32 represents the channel width of the second transistor M2 in the third pixel driving circuit, L32 represents the channel length of the second transistor M2 in the third pixel driving circuit, Wd31 represents the channel width of the driving transistor Md1 in each third circuit in the third pixel driving circuit, and Ld31 represents the channel length of the driving transistor Md1 in each third circuit in the third pixel driving circuit.

[0313] Fig.31 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Fig.32 Display panels with different pixel configurations are shown. In some embodiments, the same pixel driving circuit is configured to drive sub-pixels of the same color to emit light. In one example, a first pixel driving circuit is configured to drive a first sub-pixel of a first color to emit light. In another example, a second pixel driving circuit is configured to drive a second sub-pixel of a second color to emit light. In another example, a third pixel driving circuit is configured to drive a third sub-pixel of a third color to emit light. Fig.31 A second pixel driving circuit PDC2 is shown, which is configured to drive a second sub-pixel (eg Sp2 ) of a second color to emit light.

[0314] Fig.32 1 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. In some embodiments, the same pixel driving circuit is configured to drive sub-pixels of the same color to emit light. In one example, the first pixel driving circuit is configured to drive a first sub-pixel of a first color to emit light. In another example, the second pixel driving circuit is configured to drive a second sub-pixel of a second color to emit light. In another example, the third pixel driving circuit is configured to drive a third sub-pixel of a third color to emit light. Fig.32 A third pixel driving circuit PDC3 is shown, which is configured to drive a third sub-pixel (eg Sp3 ) of a third color to emit light.

[0315] In another aspect, the present invention provides a display device, comprising a pixel driving circuit as described herein or manufactured by the method described herein, and a plurality of light emitting elements connected to the pixel driving circuit. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0316] On the other hand, the present disclosure provides a method for driving a display device. In some embodiments, the display device includes a pixel driving circuit and a plurality of light-emitting elements coupled to the pixel driving circuit. The pixel driving circuit includes a first circuit, a second circuit, and one or more third circuits. The first circuit is coupled to a first control signal line, a second control signal line, a first light-emitting control signal line, and a second light-emitting control signal line. The second circuit is coupled to the first light-emitting control signal line and the second light-emitting control signal line. In some embodiments, the method includes: providing a first light-emitting control signal to the first circuit and the second circuit via the first light-emitting control signal line; and providing a second light-emitting control signal to the first circuit and the second circuit via the second light-emitting control signal line. Optionally, the first light-emitting control signal line and the second light-emitting control signal line are configured to transmit inverted light-emitting control signals.

[0317] In some embodiments, the method also includes: operating one or more third circuits in one of a compensation mode or a non-compensation mode; in the compensation mode, driving the light-emitting element to emit light through the one or more third circuits and compensating for changes in the threshold voltage of the driving transistor in the one or more third circuits; and in the non-compensation mode, driving the light-emitting element to emit light through the one or more third circuits without compensating for changes in the threshold voltage of the driving transistor in the one or more third circuits.

[0318] In some embodiments, the method also includes: operating one or more third circuits in one of a compensation mode or a non-compensation mode; in the compensation mode, providing an inverted light-emitting control signal to the second control signal line and the second light-emitting control signal line, respectively; in the non-compensation mode, providing the same-phase light-emitting control signal to the second control signal line and the second light-emitting control signal line.

[0319] In some embodiments, the first circuit includes: a first transistor having a gate coupled to a second light-emitting control signal line, a first electrode coupled to a reference signal line, and a second electrode coupled to a second electrode of a third transistor; a second transistor having a gate coupled to the second electrode of a fourth transistor and a first electrode of a fifth transistor, a first electrode configured to receive a second voltage signal from a second voltage supply line, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the fifth transistor; a third transistor having a gate coupled to the first light-emitting control signal line, a first electrode coupled to the second electrode of the second transistor and the second electrode of the fifth transistor, and a second electrode coupled to the second electrode of the first transistor; a fourth transistor having a gate coupled to the first control signal line, a first electrode coupled to a reset signal line, and a second electrode coupled to the gate and second electrodes of the second transistor M2 and the first electrode of the fifth transistor; and a fifth transistor having a gate coupled to the second control signal line, a first electrode coupled to the gate of the second transistor and the second electrode of the fourth transistor, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the second transistor.

[0320] In some embodiments, in the compensation mode, the method includes: in a first stage, providing a turn-on control signal to the gate of the fourth transistor through the first control signal line, providing a turn-off control signal to the gate of the fifth transistor through the second control signal line, providing a turn-off control signal to the gate of the third transistor through the first light-emitting control signal line, and providing a turn-on control signal to the gate of the first transistor through the second light-emitting control signal line; in a second stage, providing a turn-off control signal to the gate of the fourth transistor through the first control signal line, and providing a turn-on control signal to the gate of the first transistor through the second light-emitting control signal line; in the light-emitting stage, providing a turn-off control signal to the gate of the first transistor through the second light-emitting control signal line, providing a turn-on control signal to the gate of the fifth transistor through the second control signal line, and providing a turn-on control signal to the gate of the third transistor through the first light-emitting control signal line.

[0321] In some embodiments, in a non-compensation mode, the method includes: providing a turn-on control signal through a first light-emitting control signal line throughout an image frame; providing a turn-off control signal through a second light-emitting control signal line throughout an image frame; and providing a turn-off control signal through a second control signal line throughout an image frame.

[0322] In some embodiments, the second control signal line is the same as the first light emitting control signal line. Optionally, the method includes: providing the first light emitting control signal to the gate of the fifth transistor through the first light emitting control signal line.

[0323] In some embodiments, the first control signal line is the same as a first gate line configured to provide a gate scan signal to a row of the third circuit. Optionally, the method includes: providing a gate scan signal to a gate of the fourth transistor through the first gate line.

[0324] In some embodiments, the second voltage supply line is the same as the first voltage supply line. Optionally, the method includes: providing a first voltage supply signal to the second circuit and the first electrode of the second transistor through the first voltage supply line.

[0325] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that, without departing from the scope of the present invention defined by the appended claims, those skilled in the art may make changes to the described embodiments. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly stated in the appended claims.

Claims

1. A pixel driving circuit, comprising a first circuit, a second circuit and one or more third circuits; in, The first circuit is configured to compensate for variations in threshold voltages of drive transistors in the one or more third circuits; Wherein, the first circuit is coupled to a first control signal line, a second control signal line, a first light-emitting control signal line, and a second light-emitting control signal line; the second circuit is coupled to the first light emission control signal line and the second light emission control signal line; and The first light emission control signal line and the second light emission control signal line are configured to transmit light emission control signals of inverted phases.

2. The pixel driving circuit according to claim 1, in, capable of operating the one or more third circuits in a compensation mode or a non-compensation mode; In the compensation mode, the one or more third circuits are configured to drive the light emitting element to emit light and compensate for the change in the threshold voltage of the driving transistor in the one or more third circuits; In the non-compensation mode, the one or more third circuits are configured to drive the light emitting element to emit light without compensating for the variation of the threshold voltage of the driving transistor in the one or more third circuits.

3. The pixel driving circuit according to claim 1, in, capable of operating the one or more third circuits in a compensation mode or a non-compensation mode; In the compensation mode, the second control signal line and the second light emitting control signal line are configured to transmit an inverted light emitting control signal; as well as In the non-compensation mode, the second control signal line and the second light emission control signal line are configured to transmit light emission control signals in phase.

4. The pixel driving circuit according to any one of claims 1 to 3, in, The first circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; The first transistor includes a gate coupled to the second light emitting control signal line, a first electrode coupled to the reference signal line, and a second electrode coupled to the second electrode of the third transistor; the second transistor including a gate coupled to the second electrode of the fourth transistor and the first electrode of the fifth transistor, a first electrode configured to receive a second voltage signal from a second voltage supply line, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the fifth transistor; the third transistor includes a gate coupled to the first light emission control signal line, a first electrode coupled to the second electrode of the second transistor and the second electrode of the fifth transistor, and a second electrode coupled to the second electrode of the first transistor; the fourth transistor includes a gate coupled to a first control signal line, a first electrode coupled to a reset signal line, a second electrode coupled to the gate and the second electrode of the second transistor and the first electrode of the fifth transistor; and The fifth transistor includes a gate coupled to the second control signal line, a first electrode coupled to the gate of the second transistor and the second electrode of the fourth transistor, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the second transistor.

5. The pixel driving circuit according to claim 4, in, The first circuit also includes a sixth transistor having a gate coupled to the first light emission control signal line, a first electrode coupled to the second voltage supply line, and a second electrode coupled to the first electrode of the second transistor.

6. The pixel driving circuit according to claim 5, in, The first circuit also includes a seventh transistor having a gate coupled to a reset control signal line, a first electrode coupled to a second reset signal line, and a second electrode coupled to the first electrode of the second transistor and the second electrode of the sixth transistor.

7. The pixel driving circuit according to claim 4, in, The first circuit also includes an eighth transistor having a gate coupled to a third control signal line, a first electrode coupled to the second electrode of the first transistor and the second electrode of the third transistor, and a second electrode coupled to a sensing line.

8. The pixel driving circuit according to claim 4, in, The first circuit also includes a ninth transistor and a tenth transistor; The gate of the ninth transistor is coupled to the third control signal line, the first electrode of the ninth transistor is coupled to the reference signal line, and the second electrode of the ninth transistor is coupled to the first electrode of the first transistor and the first electrode of the tenth transistor; A gate of the tenth transistor is coupled to a fourth control signal line, a first electrode of the tenth transistor is coupled to the first electrode of the first transistor and the second electrode of the ninth transistor, and a second electrode of the tenth transistor is coupled to a sensing line; as well as The sense line is coupled to an external compensation circuit configured to further compensate for the variation in the threshold voltage in the drive transistors in the one or more third circuits.

9. The pixel driving circuit according to claim 4, in, The first circuit also includes a first capacitor having a first capacitor electrode coupled to the second voltage supply line and a second capacitor electrode coupled to the second electrode of the first transistor and the second electrode of the third transistor.

10. The pixel driving circuit according to claim 5, in, The first circuit also includes a first capacitor having a first capacitor electrode coupled to the second electrode of the sixth transistor and the first electrode of the second transistor, and a second capacitor electrode coupled to the second electrode of the first transistor and the second electrode of the third transistor.

11. The pixel driving circuit according to claim 4, in, The second control signal line is the same as the first light emission control signal line; and The gate of the fifth transistor is configured to receive a first light emission control signal from the first light emission control signal line.

12. The pixel driving circuit according to claim 4, in, The first control signal line is the same as a first gate line configured to provide a gate scanning signal to a row of third circuits; and The gate of the fourth transistor is configured to receive a gate scan signal from the first gate line.

13. The pixel driving circuit according to claim 4, in, The second voltage supply line is the same as the first voltage supply line; and The first voltage supply line is configured to provide a first voltage supply signal to the second circuit and the first electrode of the second transistor.

14. The pixel driving circuit according to any one of claims 1 to 13, in, The second circuit includes a first light emission control transistor and a second light emission control transistor; wherein the first light emission control transistor comprises a gate coupled to the first light emission control signal line, a first electrode coupled to a first voltage supply line, and a second electrode coupled to a second electrode of the second light emission control transistor; and The second light emission control transistor includes a gate coupled to the second light emission control signal line, a first electrode coupled to a reset signal line, and a second electrode coupled to the second electrode of the first light emission control transistor.

15. The pixel driving circuit according to any one of claims 1 to 14, in, Each of the one or more third circuits includes a drive transistor, a data write transistor, and a second capacitor; wherein the driving transistor includes a gate coupled to a second capacitor electrode of the second capacitor and a second electrode of the data writing transistor, a first electrode coupled to a second electrode of a first light emission control transistor and a second electrode of a second light emission control transistor in the second circuit, and a second electrode coupled to an anode of a light emitting element; The data write transistor includes a gate coupled to a corresponding gate line among a plurality of gate lines, a first electrode coupled to a corresponding data line among a plurality of data lines, and a second electrode coupled to the gate of the drive transistor and the second capacitor electrode of the second capacitor; and The second capacitor includes a first capacitor electrode coupled to a second electrode of a first transistor and a second electrode of a third transistor in the first circuit.

16. The pixel driving circuit according to any one of claims 1 to 15, in, The one or more third circuits are arranged in an array having a plurality of rows and a plurality of columns; The third circuits in the same column are coupled to the same data line; The third circuits in the same row are coupled to the same gate line; The second capacitors in the third circuits in different rows have different capacitances; as well as The capacitance of the second capacitor in the third circuit gradually decreases row by row.

17. The pixel driving circuit according to any one of claims 1 to 16, in, The pixel driving circuit is configured to drive a plurality of sub-pixels to emit light, the plurality of sub-pixels including a first sub-pixel configured to emit light of a first color, a second sub-pixel configured to emit light of a second color, and a third sub-pixel configured to emit light of a third color; The driving transistors in a third circuit in the pixel driving circuit configured to drive the first sub-pixel, the second sub-pixel, and the third sub-pixel to emit light have the same ratio of channel length to channel width; and Wherein, W2 represents the channel width of the second transistor, L2 represents the channel length of the second transistor, Wd1 represents the channel width of the driving transistor in each of the third circuits, and Ld1 represents the channel length of the driving transistor in each of the third circuits.

18. The pixel driving circuit according to any one of claims 1 to 16, in, The pixel driving circuit is configured to drive first sub-pixels of the same color to emit light; The driving transistors in the third circuit in the pixel driving circuit configured to drive the first sub-pixels of the same color to emit light have the same ratio of channel length to channel width; and Among them, W12 represents the channel width of the second transistor in the pixel driving circuit, L12 represents the channel length of the second transistor in the pixel driving circuit, Wd11 represents the channel width of the driving transistor in each third circuit in the pixel driving circuit, and Ld11 represents the channel length of the driving transistor in each third circuit in the pixel driving circuit. 19 . A display device comprising the pixel driving circuit according to claim 1 , and a plurality of light emitting elements coupled to the pixel driving circuit.

20. A method of driving a display device, in, The display device includes a pixel driving circuit and a plurality of light emitting elements coupled to the pixel driving circuit; Wherein, the pixel driving circuit includes a first circuit, a second circuit and one or more third circuits; Wherein, the first circuit is coupled to a first control signal line, a second control signal line, a first light-emitting control signal line, and a second light-emitting control signal line; and the second circuit is coupled to the first light emission control signal line and the second light emission control signal line; and Wherein, the method comprises: providing a first light emission control signal to the first circuit and the second circuit through the first light emission control signal line; and providing a second light emission control signal to the first circuit and the second circuit through the second light emission control signal line; The first light-emitting control signal line and the second light-emitting control signal line are configured to transmit inverted light-emitting control signals.

21. The method according to claim 20, further comprising: include: operating the one or more third circuits in one of a compensation mode or a non-compensation mode; In the compensation mode, the light emitting element is driven to emit light by the one or more third circuits, and a change in the threshold voltage of the driving transistor in the one or more third circuits is compensated; as well as In the non-compensation mode, the light emitting element is driven to emit light by the one or more third circuits without compensating for the change in the threshold voltage of the driving transistor in the one or more third circuits.

22. The method according to claim 20, further comprising: include: operating the one or more third circuits in one of a compensation mode or a non-compensation mode; In the compensation mode, providing an inverted light emitting control signal to the second control signal line and the second light emitting control signal line respectively; as well as In the non-compensation mode, the second control signal line and the second light emission control signal line are provided with light emission control signals of the same phase.

23. The method according to any one of claims 20 to 22, in, The first circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; The first transistor includes a gate coupled to the second light emitting control signal line, a first electrode coupled to the reference signal line, and a second electrode coupled to the second electrode of the third transistor; the second transistor including a gate coupled to the second electrode of the fourth transistor and the first electrode of the fifth transistor, a first electrode configured to receive a second voltage signal from a second voltage supply line, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the fifth transistor; the third transistor includes a gate coupled to the first light emission control signal line, a first electrode coupled to the second electrode of the second transistor and the second electrode of the fifth transistor, and a second electrode coupled to the second electrode of the first transistor; the fourth transistor includes a gate coupled to a first control signal line, a first electrode coupled to a reset signal line, and a second electrode coupled to the gate and the second electrode of the second transistor and the first electrode of the fifth transistor; and the fifth transistor including a gate coupled to the second control signal line, a first electrode coupled to the gate of the second transistor and the second electrode of the fourth transistor, and a second electrode coupled to the first electrode of the third transistor and the second electrode of the second transistor; Wherein, in the compensation mode, the method comprises: In the first stage, a turn-on control signal is provided to the gate of the fourth transistor through the first control signal line, a turn-off control signal is provided to the gate of the fifth transistor through the second control signal line, a turn-off control signal is provided to the gate of the third transistor through the first light-emitting control signal line, and a turn-on control signal is provided to the gate of the first transistor through the second light-emitting control signal line; In the second phase, a turn-off control signal is provided to the gate of the fourth transistor through the first control signal line, and a turn-on control signal is provided to the gate of the first transistor through the second light emission control signal line; and In the light-emitting stage, a cut-off control signal is provided to the gate of the first transistor through the second light-emitting control signal line, a turn-on control signal is provided to the gate of the fifth transistor through the second control signal line, and a turn-on control signal is provided to the gate of the third transistor through the first light-emitting control signal line.

24. The method according to claim 23, in, In the non-compensation mode, the method comprises: providing a conduction control signal through the first light emitting control signal line in the entire image frame; providing a cutoff control signal through the second light emission control signal line throughout the image frame; and A cutoff control signal is provided through the second control signal line throughout the image frame.

25. The method according to claim 23, in, The second control signal line is the same as the first light emission control signal line; and The method includes providing a first light emission control signal to the gate of the fifth transistor through the first light emission control signal line.

26. The method according to claim 23, in, The first control signal line is the same as a first gate line configured to provide a gate scanning signal to a row of third circuits; and The method includes providing a gate scan signal to the gate of the fourth transistor through the first gate line.

27. The method according to claim 23, in, The second voltage supply line is the same as the first voltage supply line; and The method includes providing a first voltage supply signal to the second circuit and the first electrode of the second transistor through the first voltage supply line.

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