Pixel driving circuit and driving method, display substrate and display device

Abstract

The invention discloses a pixel driving circuit and a driving method thereof, a display substrate and a display device. The pixel driving circuit (1) comprises a driving transistor (T3), a first reset sub-circuit (51), a second reset sub-circuit (52), a light-emitting control sub-circuit (30), a data write-in circuit (10), a first energy storage element (41) and a second energy storage element (42). The first reset sub-circuit (51) is configured to write an initialization voltage signal to the third node (N3) in response to a first reset signal; a second reset sub-circuit (52) configured to switch on a gate (T3) of the driving transistor and a fourth node (N4) in response to a second reset signal, and to reset the gate of the driving transistor (T3) and the fourth node (N4); the data writing sub-circuit (10) is configured to write a data voltage signal to the second energy storage element (42) in response to a scanning signal; the light-emitting control sub-circuit (30) is configured to respond to a first light-emitting control signal and conduct a first pole of the driving transistor (T3) and a power supply end; and transmitting the data voltage signal to the gate of the driving transistor (T3) in response to the second light emission control signal.

Description

Pixel driving circuit and driving method, display substrate, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and driving method, a display substrate, and a display device. Background Art

[0002] Active Matrix Organic Light Emitting Diode (AMOLED) panels are becoming increasingly popular. The pixel display device of AMOLED is an organic light-emitting diode (OLED). AMOLED emits light by driving a thin-film transistor in a saturated state to generate a driving current, which drives the light-emitting device to emit light.

[0003] Summary of the Invention

[0004] The present disclosure provides a pixel driving circuit and driving method, a display substrate, and a display device.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit, comprising: a driving transistor, a first reset sub-circuit, a second reset sub-circuit, a light emitting control sub-circuit, a data writing circuit, a first energy storage element, and a second energy storage element; wherein,

[0006] The first reset subcircuit is configured to, in response to a first reset signal, write an initialization voltage signal to a third node; the third node is a connection node between the second electrode of the driving transistor and the first end of the first energy storage element;

[0007] The second reset sub-circuit is configured to, in response to a second reset signal, connect the gate of the driving transistor to a fourth node and reset the gate of the driving transistor and the fourth node; the fourth node is a connection node between the first energy storage element, the second energy storage element, and the second reset sub-circuit;

[0008] The data writing sub-circuit is configured to write a data voltage signal into the second energy storage element in response to a scan signal;

[0009] The light emitting control subcircuit is configured to, in response to a first light emitting control signal, conduct the first electrode of the driving transistor to the power supply terminal; and in response to a second light emitting control signal, transmit the data voltage signal to the gate of the driving transistor.

[0010] In some embodiments, the first reset sub-circuit includes: a first reset transistor, wherein a gate of the first reset transistor is connected to a first reset signal line, a first electrode is connected to an initialization signal line, and a second electrode is connected to the third node.

[0011] In some embodiments, the initialization signal line extends along a first direction, the orthographic projection of the initialization signal line on the substrate is located on one side of the orthographic projection of the first reset signal line on the substrate along a second direction, and the first direction intersects the second direction; the initialization signal line is connected to the first electrode of the first reset transistor through a first via.

[0012] In some embodiments, the second reset subcircuit includes: a second reset transistor and a third reset transistor, wherein:

[0013] The gate of the second reset transistor is connected to the second reset signal line, the first electrode is connected to the reference voltage line, and the second electrode is connected to the fourth node;

[0014] The gate of the third reset transistor is connected to the second reset signal line, the first electrode is connected to the gate of the driving transistor, and the second electrode is connected to the fourth node.

[0015] In some embodiments, the second reset transistor and the third reset transistor are both dual-gate transistors, the first gate of the second reset transistor and the third gate of the third reset transistor are an integrated structure, and the second gate of the second reset transistor and the second gate of the third reset transistor are an integrated structure;

[0016] The second reset signal line connects the first gate of the second reset transistor and the first gate of the third reset transistor through a second via, and connects the second gate of the second reset transistor and the second gate of the third reset transistor through a third via.

[0017] In some embodiments, the second reset subcircuit includes: a second reset transistor and a third reset transistor, wherein:

[0018] The gate of the second reset transistor is connected to the second reset signal line, the first electrode is connected to the reference voltage line, and the second electrode is connected to the gate of the driving transistor;

[0019] The gate of the third reset transistor is connected to the second reset signal line, the first electrode is connected to the gate of the driving transistor, and the second electrode is connected to the fourth node.

[0020] In some embodiments, the light emitting control subcircuit includes: a first light emitting control transistor and a second light emitting control transistor, wherein:

[0021] The gate of the first light emitting control transistor is connected to the first light emitting control line, the first electrode is connected to the first power line, and the second electrode is connected to the first electrode of the driving transistor;

[0022] The gate of the second light emitting control transistor is connected to the second light emitting control line, the first electrode is connected to the first electrode of the driving transistor, and the second electrode is connected to the second energy storage element.

[0023] In some embodiments, the first power line includes: a first sub-power line and a second sub-power line, the first sub-power line extends along a first direction, the second sub-power line extends along a second direction, and the first direction intersects the second direction;

[0024] The first sub power line is connected to the first electrode of the first light emission control transistor through a fourth via hole, and the second sub power line is connected to the first sub power line through a fifth via hole.

[0025] In some embodiments, the second light-emitting control transistor is a dual-gate transistor, the second light-emitting control line is connected to the first gate of the second light-emitting control transistor through a sixth via hole, and is connected to the second gate of the second light-emitting control transistor through a seventh via hole, and the second light-emitting control line extends along the first direction.

[0026] In some embodiments, the pixel driving circuit further includes: a first switching electrode, the first switching electrode being connected to the first electrode of the second light emitting control transistor through an eighth via hole, and being connected to the gate electrode of the driving transistor through a ninth via hole.

[0027] In some embodiments, the data writing subcircuit includes: a data writing transistor, the gate of the data writing transistor is connected to the scan signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the second energy storage element and the light emitting control subcircuit.

[0028] In some embodiments, the data signal line extends along the second direction, and the scan signal line includes: a scan line body, a first connecting portion, and a second connecting portion formed into an integrated structure, the scan line body extends along the first direction, the first connecting portion and the second connecting portion are respectively located on opposite sides of the scan line body and arranged along the second direction; the first direction intersects the second direction;

[0029] The data writing transistor is a dual-gate transistor, the first connecting portion is connected to the first gate of the data writing transistor through a tenth via hole, and the second connecting portion is connected to the second gate of the data writing transistor through an eleventh via hole.

[0030] In some embodiments, the pixel driving circuit further includes: a second switching electrode, the second switching electrode is connected to the first electrode of the data writing transistor through a twelfth via hole, and the data signal line is connected to the second switching electrode through a thirteenth via hole.

[0031] In some embodiments, the first energy storage element includes: a first capacitor, the first capacitor includes a first plate and a second plate, the first plate is connected to the second electrode of the driving transistor, and the second plate is connected to the second energy storage element.

[0032] In some embodiments, the first electrode plate is located on a side of the second electrode plate away from the substrate, the driving transistor is a dual-gate transistor, the second gate of the driving transistor is located on a side of the first gate of the driving transistor away from the substrate, and the first gate of the driving transistor is shared with the first electrode plate.

[0033] In some embodiments, the pixel driving circuit further includes: a third switching electrode, one end of the third switching electrode is connected to the first gate of the driving transistor through a fourteenth via hole, and the other end is connected to the second electrode of the driving transistor through a fifteenth via hole.

[0034] In some embodiments, the second reset subcircuit includes: a second reset transistor and a third reset transistor;

[0035] The first electrode is located on a side of the second electrode away from the substrate. The pixel driving circuit also includes a fourth switching electrode, one end of which is connected to the second electrode through a sixteenth via hole, and the other end of which is connected to the second electrode of the third reset transistor through a seventeenth via hole.

[0036] In some embodiments, the second energy storage element includes: a second capacitor, the second capacitor includes a third plate and a fourth plate, the third plate is connected to the first energy storage element, and the fourth plate is connected to the data writing sub-circuit.

[0037] In some embodiments, the data writing sub-circuit includes: a data writing transistor;

[0038] The pixel driving circuit further includes: a fifth switching electrode, one end of which is connected to the second electrode of the data writing transistor through an eighteenth via hole, and the other end of which is connected to the fourth electrode plate through a nineteenth via hole.

[0039] In some embodiments, the first energy storage element includes a first capacitor, the first capacitor includes a first electrode plate and a second electrode plate, and the third electrode plate of the second capacitor is connected to the second electrode plate to form an integrated structure.

[0040] In some embodiments, the pixel driving circuit includes: a first gate metal layer, a semiconductor layer, and a second gate metal layer, which are sequentially arranged in a direction away from the substrate;

[0041] In which, each transistor in the pixel driving circuit is a dual-gate transistor, the semiconductor layer includes the active layer, the first electrode and the second electrode of each transistor in the pixel driving circuit; the first gate metal layer includes the first gate of each transistor in the pixel driving circuit, and the second gate metal layer includes the second gate of each transistor in the pixel driving circuit.

[0042] In some embodiments, the light emission control subcircuit includes a first light emission control transistor and a second light emission control transistor;

[0043] The pixel driving circuit also includes: a first source-drain metal layer, located on the side of the second gate metal layer away from the base substrate; the first source-drain metal layer includes: a first transfer electrode, the first transfer electrode is connected to the first electrode of the second light-emitting control transistor through an eighth via hole, and is connected to the gate of the driving transistor through a ninth via hole.

[0044] In some embodiments, the first electrode of the first light-emitting control transistor is connected to a first power line, the first power line includes: a first sub-power line and a second sub-power line, the first sub-power line is located in the first source-drain metal layer, the second sub-power line is located in the second source-drain metal layer, and the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate;

[0045] The first sub power line is connected to the first electrode of the first light emission control transistor through a fourth via hole, and the second sub power line is connected to the first sub power line through a fifth via hole.

[0046] In some embodiments, the first reset sub-circuit includes: a first reset transistor; the second reset sub-circuit includes: a second reset transistor and a third reset transistor; the data writing sub-circuit includes: a data writing transistor;

[0047] The orthographic projections of the active layer of the second reset transistor, the active layer of the third reset transistor, the active layer of the second light emission control transistor, and the active layer of the data writing transistor on the base substrate all overlap with the orthographic projection of the second sub-power line on the base substrate;

[0048] The orthographic projections of the active layer of the first reset transistor, the active layer of the first light emission control transistor, and the active layer of the driving transistor on the base substrate all overlap with the orthographic projection of the second power line on the base substrate.

[0049] In some embodiments, the second reset subcircuit includes: a second reset transistor and a third reset transistor;

[0050] The pixel driving circuit further includes: a first source-drain metal layer located on a side of the second gate metal layer away from the substrate; the first source-drain metal layer includes a reference voltage line, and the reference voltage line is connected to the first electrode of the second reset transistor through a twentieth via hole.

[0051] In some embodiments, the data writing sub-circuit includes: a data writing transistor;

[0052] The pixel driving circuit further includes: a first source-drain metal layer and a second source-drain metal layer, wherein the first source-drain metal layer is located on a side of the second gate metal layer away from the base substrate, and the second source-drain metal layer is located on a side of the first source-drain metal layer away from the base substrate;

[0053] The first source-drain metal layer includes: a scan signal line and a second transfer electrode; the second source-drain metal layer includes: a data signal line; the scan signal line is connected to the first gate of the data writing transistor through a tenth via hole, and is connected to the second gate of the data writing transistor through an eleventh via hole;

[0054] The second switching electrode is connected to the first electrode of the data writing transistor through a twelfth via hole, and the data signal line is connected to the second switching electrode through a thirteenth via hole.

[0055] In some embodiments, the pixel driving circuit further includes a light-shielding metal layer, and the light-shielding metal layer is located between the first gate metal layer and the base substrate;

[0056] The first energy storage element includes a first capacitor, which includes a first plate and a second plate; the second energy storage element includes a second capacitor, which includes a third plate and a fourth plate; the light-shielding metal layer includes the second plate and the third plate; and the first gate metal layer also includes the first plate and the fourth plate.

[0057] In some embodiments, the pixel driving circuit further includes: a first source / drain metal layer located on a side of the second gate metal layer away from the substrate;

[0058] The first source-drain metal layer includes a third switching electrode, one end of which is connected to the first gate electrode of the driving transistor through a fourteenth via hole, and the other end of which is connected to the second electrode of the driving transistor through a fifteenth via hole.

[0059] In some embodiments, the second reset subcircuit includes: a second reset transistor and a third reset transistor;

[0060] The first source-drain metal layer further includes: a fourth transfer electrode, one end of which is connected to the second electrode plate through a sixteenth via hole, and the other end of which is connected to the second electrode of the third reset transistor through a seventeenth via hole.

[0061] In some embodiments, the pixel driving circuit further includes: a first source / drain metal layer located on a side of the second gate metal layer away from the substrate;

[0062] The data writing sub-circuit includes: a data writing transistor; the first source-drain metal layer includes: a fifth transfer electrode, one end of the fifth transfer electrode is connected to the second electrode of the data writing transistor through the eighteenth via hole, and the other end is connected to the fourth electrode plate through the nineteenth via hole.

[0063] In a second aspect, the present disclosure further provides a driving method for the above-mentioned pixel driving circuit, comprising:

[0064] In the reset phase, the first reset signal and the second reset signal are in a working level state, and the first reset sub-circuit writes an initialization voltage signal to the third node; the second reset sub-circuit connects the gate of the driving transistor to the fourth node and resets the gate of the driving transistor and the fourth node;

[0065] In the threshold compensation stage, the first light-emitting control signal and the second reset signal are in a working level state, and the second reset sub-circuit connects the gate of the driving transistor to the fourth node to write the threshold voltage of the driving transistor into the first energy storage element;

[0066] In the data writing phase, the second reset signal and the scan signal are in a working level state, the data writing sub-circuit writes the data voltage signal into the second energy storage element, and the second reset sub-circuit resets the fourth node;

[0067] In the light-emitting stage, the first light-emitting control signal and the second light-emitting control signal are both in the working level state, the light-emitting control subcircuit connects the first electrode of the driving transistor to the power supply end, and transmits the data voltage signal to the gate of the driving transistor, so that the driving transistor provides a driving current for the light-emitting device.

[0068] In a third aspect, the present disclosure further provides a display substrate, comprising a display area, wherein the display area comprises a plurality of pixel areas, wherein the pixel areas are provided with: the above-mentioned pixel driving circuit, and a light-emitting device electrically connected to the pixel driving circuit.

[0069] In a fourth aspect, the present disclosure further provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0071] FIG1 is a schematic diagram of a pixel driving circuit and a light-emitting device provided in some embodiments.

[0072] FIG2 is a timing diagram of the pixel driving circuit in FIG1 .

[0073] FIG3 is a schematic diagram of a pixel driving circuit and a light-emitting device provided in some embodiments of the present disclosure.

[0074] FIG4 is a schematic diagram of a pixel driving circuit and a light-emitting device provided in some other embodiments of the present disclosure.

[0075] FIG5 is a schematic diagram of a pixel driving circuit and a light-emitting device provided in some other embodiments of the present disclosure.

[0076] FIG6A is a timing diagram of a pixel driving circuit provided in some embodiments of the present disclosure.

[0077] FIG6B is a signal simulation diagram of a pixel driving circuit provided in some embodiments of the present disclosure.

[0078] FIG. 7 is a schematic diagram of a driving method of a pixel driving circuit provided in some embodiments of the present disclosure.

[0079] FIG8 is a planar schematic diagram of a light-shielding metal layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0080] FIG9 is a plan view of a first gate metal layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0081] FIG10 is a schematic diagram illustrating the superposition of a light-shielding metal layer and a first gate metal layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0082] FIG11 is a planar schematic diagram of a semiconductor layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0083] FIG12 is a schematic diagram showing the superposition of a light-shielding metal layer, a first gate metal layer, and a semiconductor layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0084] FIG13 is a plan view of a second gate metal layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0085] FIG14 is a schematic diagram illustrating the superposition of a light-shielding metal layer, a first gate metal layer, a semiconductor layer, and a second gate metal layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0086] FIG15 is a planar schematic diagram of a first source-drain metal layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0087] 16 is a schematic diagram illustrating the superposition of a light-shielding metal layer, a first gate metal layer, a semiconductor layer, a second gate metal layer, and a first source-drain metal layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0088] FIG17 is a plan view of a second source-drain metal layer of a pixel driving circuit provided in some embodiments of the present disclosure.

[0089] FIG18 is an overall plan view of a pixel driving circuit provided in some embodiments of the present disclosure.

[0090] FIG19 is a cross-sectional view taken along line AA' in FIG16.

[0091] FIG20 is a cross-sectional view taken along line BB' in FIG16.

[0092] FIG21 is a cross-sectional view taken along line CC' in FIG18. DETAILED DESCRIPTION

[0093] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0094] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0095] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0096] It should be noted that the film layers in the embodiments of the present disclosure are schematically illustrated and do not represent the actual thickness of the film layers.

[0097] In addition, each transistor involved in the embodiments of the present disclosure can be independently selected from one of a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor. The "first electrode" involved in the present disclosure specifically refers to the source electrode of the transistor, and the corresponding "second electrode" specifically refers to the drain electrode of the transistor. Of course, those skilled in the art should know that the "first electrode" and the "second electrode" can be interchanged.

[0098] In addition, the working level state refers to a level state that can turn on the first and second poles of the transistor, and the non-working level state refers to a level state that can turn off the first and second poles of the transistor. Transistors can be divided into N-type transistors and P-type transistors. Each transistor in the present disclosure can be independently selected from an N-type transistor or a P-type transistor; for an N-type transistor, the working level state is a high level state, and the non-working level state is a low level state; for a P-type transistor, the working level state is a low level state, and the non-working level state is a high level state. In the following embodiments, all transistors in the pixel unit will be described as N-type transistors as an example. In this case, the transistors in the pixel driving circuit can be prepared simultaneously using the same preparation process.

[0099] The display substrate includes a display area and a peripheral area located around the display area. The display area includes a plurality of pixel areas. Each pixel area is provided with a light emitting device and a pixel driving circuit for providing a driving signal to the light emitting device.

[0100] Figure 1 is a schematic diagram of a pixel driving circuit and a light-emitting device provided in some embodiments. As shown in Figure 1, the pixel driving circuit 1 includes: a driving transistor T2', a threshold compensation sub-circuit 20, a data writing sub-circuit 10, a reset sub-circuit 50, a light-emitting control sub-circuit 30 and an energy storage element 40.

[0101] The data writing subcircuit 10, the threshold compensation subcircuit 20, the gate of the driving transistor T2', and the energy storage element 40 are connected to the N1' node. The second electrode of the driving transistor T2', the reset subcircuit 50, and the energy storage element 40 are connected to the N3' node. The reset subcircuit 50 is configured to write the initialization voltage signal to the N3' node in response to the reset signal. The data writing subcircuit 10 is configured to write the data voltage signal to the first node in response to the first scan signal. The threshold compensation subcircuit 20 is configured to write the reference voltage signal to the first node in response to the second scan signal. The light emission control subcircuit 30 is configured to connect the first power line VDD to the first electrode of the driving transistor T2' in response to the light emission control signal.

[0102] In one example, the data write subcircuit 10 includes a data write transistor T4', having its gate connected to the first scan signal line GL1, its first electrode connected to the data signal line DL, and its second electrode connected to the N1' node. The reset subcircuit 50 includes a reset transistor T1', having its gate connected to the reset signal line RstL, its first electrode connected to the initialization signal line Init, and its second electrode connected to the N3' node. The threshold compensation subcircuit 20 includes a threshold compensation transistor T3', having its gate connected to the second scan line GL2, its first electrode connected to the reference signal line Ref, and its second electrode connected to the N1' node. The light emission control subcircuit 30 includes a light emission control transistor T5', having its gate connected to the light emission control line EM, its first electrode connected to the first power line VDD, and its second electrode connected to the first electrode of the drive transistor T2'. The second electrode of the drive transistor T2' is connected to the first electrode of the light emitting device 2, and the second electrode of the light emitting device 2 is connected to the second power line VSS. The energy storage element 40 includes a capacitor C, and two ends of the capacitor C are connected to the N1 ′ node and the N3 ′ node respectively.

[0103] Figure 2 is a timing diagram of the pixel driving circuit in Figure 1. As shown in Figure 2, during reset phase t1', the reset signal provided by the reset signal line is at an operating level. At this time, reset transistor T1' is turned on, transmitting the initialization voltage signal provided by the initialization signal line Init to node N3'. Thereafter, the scan signal provided by the second scan signal line GL2 is at an operating level, thereby controlling threshold compensation transistor T3' to turn on, transmitting the reference voltage signal provided by the reference signal line Ref to node N1'. During reset phase t1', nodes N1' and N3' are reset.

[0104] During the threshold compensation phase t2', the light control signal provided by the light control line Em is at an operating level. At this point, the light control transistor T5' connects the first power line to the first electrode of the driving transistor T2'. Furthermore, the second scan signal provided by the second scan signal line GL2 is at an operating level, turning on the reset transistor T3'. The reset signal provided by the reset signal line Ref is transmitted to the N1' node. Because the gate-source voltage of the driving transistor T2' is greater than the threshold voltage, the driving transistor T2' is turned on. When the N3' node continues to charge to Vref-Vth, the driving transistor T2' is turned off. At this point, the potential of the N3' node is Vref-Vth. Vref is the voltage of the reference voltage signal, and Vth is the threshold voltage of the driving transistor T2'.

[0105] In the data writing phase t3', the first scanning signal provided by the first scanning signal line GL1 is at a working level, the data writing transistor T4' is turned on, and the data signal on the data signal line DL is transmitted to the N1' node. The potential of the N1' node is recorded as Vdata.

[0106] During light-emitting phase t4', the light-emitting control signal provided by the light-emitting control line EM is at an operating level. At this point, the light-emitting control transistor T5' is turned on, and the potential at node N3' suddenly rises to Vdd. Under the bootstrap effect of capacitor C, the potential at node N1' changes to Vdata + Vdd - Vref + Vth. The light-emitting device emits light under the drive transistor T2'. At this point, the drive transistor T2' operates in the saturation region, and the gate-source voltage Vgs of the drive transistor T2' is: (Vdata + Vdd - Vref + Vth) - Vdd = Vdata - Vref + Vth.

[0107] The driving current expression of the driving transistor T2' is as follows: IOLED = β (Vgs - Vth) 2 =(Vdata-Vref+Vth-Vth) 2 =(Vdata-Vref) 2

[0108] in, μ n is the electron mobility of TFT, C ox is the insulation capacitance per unit area, is the width-to-length ratio of the driving transistor T2'.

[0109] However, for the above-mentioned pixel driving circuit, during the data writing phase, since the N3' node is floating, when the data voltage signal is written to the N1' node, the bootstrap effect of the capacitor C causes the potential of the N3' node to change. The amount of change in the N3' node varies for different data voltages, resulting in a poor display effect for the overall picture.

[0110] Figure 3 is a schematic diagram of a pixel driving circuit and a light-emitting device provided in some embodiments of the present disclosure. As shown in Figure 3, the pixel driving circuit 1 includes: a driving transistor T3, a first reset sub-circuit 51, a second reset sub-circuit 52, a light-emitting control sub-circuit 30, a data writing sub-circuit 10, a first energy storage element 41 and a second energy storage element 42.

[0111] The gate of the driving transistor T3, the second reset sub-circuit 52, and the light-emission control sub-circuit 30 are connected to a first node N1; the light-emission control sub-circuit 30 and the first electrode of the driving transistor T3 are connected to a second node N2. The first reset sub-circuit 51, the second electrode of the driving transistor T3, and the first energy storage element 41 are connected to a third node N3. The second reset sub-circuit 52, the first energy storage element 41, and the second energy storage element 42 are connected to a fourth node N4. The data writing sub-circuit 10, the light-emission control sub-circuit 30, and the second energy storage element 42 are connected to a fifth node N5. The second electrode of the driving transistor T3 is connected to the first electrode of the light-emitting device 2, wherein the light-emitting device 2 may be an organic electroluminescent diode, the first electrode of the light-emitting device 2 may be an anode, and the second electrode of the light-emitting device 2 may be a cathode.

[0112] The first reset subcircuit 51 is configured to write an initialization voltage signal to the third node N3 in response to a first reset signal. The second reset subcircuit 52 is configured to connect the gate of the driving transistor T3 to the fourth node N4 in response to a second reset signal, and reset the gate of the driving transistor T3 and the fourth node N4. The data write subcircuit 10 is configured to write a data voltage signal to the second energy storage element 42, that is, to the fifth node N5, in response to a scan signal. The light emission control subcircuit 30 is configured to connect the first electrode of the driving transistor T3 to the power supply terminal in response to a first light emission control signal; and to connect the fifth node N5 to the gate of the driving transistor T3 in response to a second light emission control signal, thereby transmitting the data voltage signal to the gate of the driving transistor T3.

[0113] In the embodiment of the present disclosure, in the reset stage, the first reset sub-circuit 51 can be used to write an initialization voltage signal to the third node N3, and the second reset sub-circuit 52 can be used to write a reset voltage signal to the fourth node N4; in the threshold compensation stage, the light-emitting control sub-circuit 30 can be used to connect the first power line VDD and the first electrode of the driving transistor T3; and the second reset sub-circuit 52 can be used to connect the gate of the driving transistor T3 and the fourth node N4, so that the threshold voltage of the driving transistor T3 is written into the first energy storage element 41; in the data writing stage, the data writing sub-circuit 10 can be used to write a data voltage signal to the second energy storage element 42; in the light-emitting stage, the light-emitting control sub-circuit 30 can be used to write a data voltage signal to the gate of the driving transistor T3, and the power supply terminal and the source of the driving transistor T3 are connected. At this time, the driving transistor T3 provides a driving current for the light-emitting device, and the magnitude of the driving current is independent of the threshold voltage.

[0114] Furthermore, since the pixel driving circuit in the present disclosure includes two energy storage elements, the second reset sub-circuit 52 can reset the fourth node N4 in response to the second reset signal. Therefore, in the data writing stage, the second reset signal can be controlled to be in a working level state, and the second light-emitting control signal can be controlled to be in a non-working level state. At this time, the fourth node N4 maintains a fixed potential, and the fifth node N5 is disconnected from the first node N1, and the voltages of the two will not affect each other. Therefore, when the data voltage signal is written to the second energy storage element 42, the third node N3 will not be affected, thereby improving the display quality.

[0115] FIG4 is a schematic diagram of a pixel driving circuit and a light-emitting device provided in some other embodiments of the present disclosure. The pixel driving circuit shown in FIG4 is a specific implementation of FIG3 . As shown in FIG4 , the first reset sub-circuit 51 includes a first reset transistor T7, a gate of the first reset transistor T7 connected to a first reset signal line Rst1, a first electrode of the first reset transistor T7 connected to an initialization signal line Init, and a second electrode of the first reset transistor T7 connected to a third node N3. The first reset signal line Rst1 is used to provide a first reset signal, and the initialization signal line Init is used to provide an initialization voltage signal.

[0116] When the first reset signal reaches the working level state, the first electrode and the second electrode of the first reset transistor T7 are turned on, thereby transmitting the initialization voltage signal on the initialization signal line Init to the third node N3.

[0117] The second reset sub-circuit 52 includes a second reset transistor T2 and a third reset transistor T1. The gate of the second reset transistor T2 is connected to the second reset signal line Rst2, the first electrode of the second reset transistor T2 is connected to the reference voltage line, and the second electrode of the second reset transistor T2 is connected to the gate of the driving transistor T3. The gate of the third reset transistor T1 is connected to the second reset signal line Rst2, the first electrode of the third reset transistor T1 is connected to the gate of the driving transistor T3, and the second electrode is connected to the fourth node N4.

[0118] When the second reset signal reaches the working level state, the first and second electrodes of the second reset transistor T2 are turned on, and the first and second electrodes of the third reset transistor T1 are turned on, so that the reference voltage signal on the reference voltage line is transmitted to the gate of the driving transistor T3 and the fourth node N4.

[0119] The light control subcircuit 30 includes a first light control transistor T5 and a second light control transistor T6. The gate of the first light control transistor T5 is connected to a first light control line EM1, a first electrode of the first light control transistor T5 is connected to a power supply terminal, and a second electrode of the first light control transistor T5 is connected to a first electrode of a driving transistor T3. The gate of the second light control transistor T6 is connected to a second light control line EM2, a first electrode of the second light control transistor T6 is connected to a first electrode of the driving transistor T3, and a second electrode of the second light control transistor T6 is connected to a second energy storage element 42. The first light control line EM1 is used to provide a first light control signal, and the second light control line EM2 is used to provide a second light control signal.

[0120] When the first light-emitting control signal reaches the working level state, the first and second electrodes of the first light-emitting control transistor T5 are turned on, thereby turning on the first power line VDD and the first electrode of the driving transistor T3; when the second light-emitting control signal reaches the working level state, the first and second electrodes of the second light-emitting control transistor T6 are turned on, thereby turning on the fifth node N5 and the gate of the driving transistor T3.

[0121] As shown in FIG4 , the data writing sub-circuit 10 includes a data writing transistor T4, wherein the gate of the data writing transistor T4 is connected to the scanning signal line GL, the first electrode of the data writing transistor T4 is connected to the data signal line, and the second electrode of the data writing transistor T4 is connected to the second energy storage element 42 and the light emitting control sub-circuit 30. The scanning signal line GL is used to provide a scanning signal, and the data signal line is used to provide a data signal.

[0122] When the scan signal reaches the working level potential, the data writing transistor T4 is turned on, thereby transmitting the data signal on the data signal line to the fifth node N5.

[0123] As shown in FIG4 , the first energy storage element 41 includes a first capacitor C1, which includes a first plate C11 and a second plate C12. The first plate C11 connects the second electrode of the driving transistor T3 to the first reset sub-circuit 51, and the second plate C12 connects the second energy storage element 42 to the second reset sub-circuit 52. The second energy storage element 42 includes a second capacitor C2, which includes a third plate C23 and a fourth plate C24. The third plate C23 connects the first energy storage element 41 and the second reset sub-circuit 52, and the fourth plate C24 connects the data writing sub-circuit 10 and the light emission control sub-circuit 30.

[0124] FIG5 is a schematic diagram of a pixel driving circuit and a light-emitting device provided in some other embodiments of the present disclosure. As shown in FIG5 , the pixel driving circuit shown in FIG5 is similar to that shown in FIG4 , except that the transistors in the second reset sub-circuit 52 are connected differently. In FIG5 , the second reset sub-circuit 52 includes a second reset transistor T2 and a third reset transistor T1. The gate of the second reset transistor T2 is connected to the second reset signal line Rst2, the first electrode of the second reset transistor T2 is connected to the reference voltage line Ref, and the second electrode of the second reset transistor T2 is connected to the fourth node N4. The gate of the third reset transistor T1 is connected to the second reset signal line Rst2, the first electrode of the third reset transistor T1 is connected to the gate of the driving transistor T3, and the second electrode of the third reset transistor T1 is connected to the fourth node N4.

[0125] In FIG. 5 , when the second reset signal provided by the second reset signal line Rst2 is at the working level, the reference voltage signal on the reference voltage line Ref can also be transmitted to the gate of the driving transistor T3 and the fourth node N4 .

[0126] In FIG5 , the specific structures of other sub-circuits may be the same as those in FIG4 , and will not be described again here.

[0127] In an embodiment of the present disclosure, at least one transistor in the pixel driving circuit 1 may be a dual-gate transistor, wherein the two gates of the dual-gate transistor are arranged in a direction away from the substrate, thereby reducing the leakage current generated by the active layer of the transistor due to light exposure, thereby improving the characteristics of the transistor. In one example, each transistor in the pixel driving circuit 1 may be set as a dual-gate transistor, or a portion of the transistors in the pixel driving circuit 1 may be set as a dual-gate transistor, and the remaining transistors may be set as single-gate transistors, for example, the driving transistor may be set as a dual-gate transistor, and the remaining transistors may be single-gate transistors.

[0128] FIG6A is a timing diagram of a pixel driving circuit provided in some embodiments of the present disclosure, and FIG6B is a signal simulation diagram of a pixel driving circuit provided in some embodiments of the present disclosure. The pixel driving circuit is described using the structure of FIG4 as an example, wherein the second electrode of the first light-emitting control transistor T5 and the first electrode of the driving transistor T3 are connected to the second node N2, and the gate of the driving transistor T3 and the first electrode of the second light-emitting control transistor T6 are connected to the first node N1. As shown in FIG6A and FIG6B , the operation process of the pixel driving circuit includes:

[0129] During reset phase t1, the first emission control signal provided by the first emission control line EM1, the second emission control signal provided by the second emission control line EM2, and the scan signal provided by the scan signal line GL are all in a non-operating state, thereby turning off the first emission control transistor T5, the second emission control transistor T6, and the data write transistor T4. The second reset signal provided by the second reset signal line Rst2 reaches an operating state, thereby turning on the second reset transistor T2 and the third reset transistor T1. The reference voltage signal provided by the reference voltage line Ref is transmitted to the first node N1 and the fourth node N4, and the potentials of the first node N1 and the fourth node N4 both reach Vref. Subsequently, the first reset signal provided by the first reset signal line Rst1 reaches an operating state, thereby turning on the first reset transistor T7 and transmitting the initialization voltage signal on the initialization signal line Init to the third node N3.

[0130] During the threshold compensation phase t2, the second emission control signal provided by the second emission control line EM2, the first reset signal provided by the first reset signal line Rst1, and the scan signal provided by the scan signal line GL are all in a non-operating state. At this point, the second emission control transistor T6, the first reset transistor T7, and the data write transistor T4 are all turned off. Furthermore, the first emission control signal provided by the first emission control line EM1 and the second reset signal provided by the second reset signal line Rst2 turn on the first emission control transistor T5, the second reset transistor T2, and the third reset transistor T1. The reference voltage signal provided by the reference voltage line Ref is transmitted to the first node. Because the gate-source voltage of the drive transistor T3 is greater than the threshold voltage, the drive transistor T3 is turned on. When the third node N3 continues to charge to Vref-Vth, the drive transistor T3 is turned off. At this point, the potential of the third node N3 is Vref-Vth. Vref is the voltage of the reference voltage signal, and Vth is the threshold voltage of the drive transistor T3.

[0131] During the data write phase t3, the scan signal provided by the scan signal line GL reaches an active level, turning on the data write transistor T4. The data signal on the data signal line DL is transmitted to the fifth node N5, and the potential of the fifth node N5 is denoted as Vdata. Furthermore, the first light control signal provided by the first light control line EM1 and the second reset signal provided by the second reset signal line Rst2 are at an active level, turning on the first light control transistor T5, the second reset transistor T2, and the third reset transistor T1. The potential of the fourth node N4 remains at Vref. Since the fourth node N4 receives a fixed potential signal, the second capacitor does not bootstrap, thereby ensuring that the fourth node N4 and the third node N3 are not affected by the data signal. Simultaneously, the second light control signal provided by the second light control line EM2 is at an inactive level, turning off the second light control transistor, preventing the voltage at the fifth node N5 from affecting the first node N1 and the fourth node N4.

[0132] During light-emitting phase t4, the first reset signal provided by the first reset signal line Rst1, the second reset signal provided by the second reset signal line Rst2, and the scan signal provided by the scan signal line GL are all in a non-operating state. The first reset transistor T7, the second reset transistor T2, the third reset transistor T1, and the data write transistor T4 are all turned off. The first light-emitting control signal provided by the first light-emitting control line EM1 and the second light-emitting control signal provided by the second light-emitting control line EM2 are both in an operating state. At this time, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both turned on, and the potential of the third node N3 changes to Vdd. Under the bootstrap effect of the first capacitor C1 and the second capacitor C2, the potentials of the fourth node N4 and the fifth node N5 change accordingly. The potential of the fifth node N5 changes to Vdata + Vdd - Vref + Vth, thereby causing the potential of the first node N1 to reach Vdata + Vdd - Vref + Vth. The light emitting device 2 emits light under the driving of the driving transistor T3. At this time, the driving transistor T3 operates in the saturation region, and the gate-source voltage Vgs of the driving transistor T3 is: (Vdata+Vdd-Vref+Vth)-Vdd=Vdata-Vref+Vth.

[0133] The driving current expression of the driving transistor T3 is as follows: IOLED=β(Vgs-Vth) 2 =(Vdata-Vref+Vth-Vth) 2 =(Vdata-Vref) 2

[0134] in, μ n is the electron mobility of TFT, C oxis the insulation capacitance per unit area, is the width-to-length ratio of the driver transistor.

[0135] For the circuit in Figure 5, although its structure is different from the circuit in Figure 4, its working process is the same as the circuit in Figure 4. The signal timing and the changes in the potential of each node can refer to the above description of Figure 4 and will not be repeated here.

[0136] FIG7 is a schematic diagram of a driving method of a pixel driving circuit provided in some embodiments of the present disclosure, wherein the pixel driving circuit is the pixel driving circuit in any of the above embodiments. As shown in FIG7 , the driving method of the pixel driving circuit includes:

[0137] S1. In the reset phase, the first reset signal and the second reset signal are in the working level state, and the first reset sub-circuit writes the initialization voltage signal to the third node; the second reset sub-circuit connects the gate of the driving transistor to the fourth node and resets the gate of the driving transistor and the fourth node.

[0138] S2. In the threshold compensation stage, the first light-emitting control signal and the second reset signal are in a working level state, and the second reset sub-circuit connects the gate of the driving transistor to the fourth node to write the threshold voltage of the driving transistor into the first energy storage element.

[0139] S3. In the data writing phase, the second reset signal and the scan signal are in a working level state, the data writing sub-circuit writes the data voltage signal into the second energy storage element, and the second reset sub-circuit resets the fourth node.

[0140] S4. In the light-emitting stage, the first light-emitting control signal and the second light-emitting control signal are both in the working level state, the light-emitting control subcircuit connects the first electrode of the driving transistor to the power supply end, and transmits the data voltage signal to the gate of the driving transistor, so that the driving transistor provides a driving current for the light-emitting device.

[0141] The specific driving process of the pixel driving circuit is described above and will not be repeated here.

[0142] The following describes the layout of the pixel driving circuit using the pixel driving circuit in Figure 5 as an example. Figure 8 is a planar schematic diagram of the light-shielding metal layer of the pixel driving circuit provided in some embodiments of the present disclosure, Figure 9 is a planar schematic diagram of the first gate metal layer of the pixel driving circuit provided in some embodiments of the present disclosure, Figure 10 is a schematic diagram of the superposition of the light-shielding metal layer and the first gate metal layer of the pixel driving circuit provided in some embodiments of the present disclosure, Figure 11 is a planar schematic diagram of the semiconductor layer of the pixel driving circuit provided in some embodiments of the present disclosure, Figure 12 is a schematic diagram of the superposition of the light-shielding metal layer, the first gate metal layer, and the semiconductor layer of the pixel driving circuit provided in some embodiments of the present disclosure, Figure 13 is a planar schematic diagram of the second gate metal layer of the pixel driving circuit provided in some embodiments of the present disclosure, and Figure 14 is a schematic diagram of the pixel driving circuit provided in some embodiments of the present disclosure. FIG15 is a schematic diagram of the superposition of the light-shielding metal layer, the first gate metal layer, the semiconductor layer and the second gate metal layer of the pixel driving circuit provided in some embodiments of the present disclosure, FIG16 is a schematic diagram of the superposition of the light-shielding metal layer, the first gate metal layer, the semiconductor layer, the second gate metal layer and the first source-drain metal layer of the pixel driving circuit provided in some embodiments of the present disclosure, FIG17 is a schematic diagram of the superposition of the second source-drain metal layer of the pixel driving circuit provided in some embodiments of the present disclosure, FIG18 is an overall plan view of the pixel driving circuit provided in some embodiments of the present disclosure, FIG19 is a cross-sectional view along line A-A' in FIG16, FIG20 is a cross-sectional view along line B-B' in FIG16, and FIG21 is a cross-sectional view along line C-C' in FIG18.

[0143] As shown in Figures 8 to 21, the pixel driving circuit includes: a light-shielding metal layer BSM, a first gate metal layer G1, a semiconductor layer Poly, a second gate metal layer G2, a first source and drain metal layer SD1, and a second source and drain metal layer SD2, which are arranged in a direction away from the base substrate 101.

[0144] As shown in Figure 8, the light-shielding metal layer BSM is arranged on the base substrate 101, and the light-shielding metal layer BSM may include: the second plate C12 of the first capacitor C1 and the third plate C23 of the second capacitor C2 in Figure 8. Among them, the second plate C12 and the third plate C23 are electrically connected. In one example, the second plate C12 and the third plate C23 are connected as an integrated structure. It should be noted that in other examples, the second plate C12 and the third plate C23 can also be arranged separately and connected by other conductive structures. The light-shielding metal layer BSM may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the light-shielding metal layer BSM may include gold (Au), a gold alloy, silver (Ag), a silver alloy, aluminum (Al), an aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), a copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), a molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The light-shielding metal layer BSM may have a single layer or multiple layers.

[0145] As shown in Figures 19 to 21, the first gate insulating layer GI1 is disposed between the light-shielding metal layer BSM and the first gate metal layer G1. The first gate insulating layer GI1 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The first gate insulating layer GI1 may be formed as a single layer or multiple layers.

[0146] As shown in Figures 9, 10, and 19 to 21, the first gate metal layer G1 is disposed on a side of the first gate insulation layer GI1 away from the substrate 101. The first gate metal layer G1 includes: the first gates of each transistor in the pixel driving circuit, the fourth plate C24 of the second capacitor C2, and the first plate C11 of the first capacitor C1. The first plate C11 of the first capacitor C1 and the first gate T3_g1 of the driving transistor T3 are integrally formed, and the first gate T2_g1 of the second reset transistor T2 and the first gate T1_g1 of the third reset transistor T1 are integrally formed. Furthermore, the first light-emitting control line EM1 may include a first sub-control line EM11 and a second sub-control line EM12, and the first reset signal line Rst1 may include a first sub-reset line Rst11 and a second sub-reset line Rst12. The first sub-control line EM11 and the first sub-reset line Rst11 are located in the first gate metal layer G1. The first gate T5_g1 of the first emission control transistor T5 and the first sub-control line EM11 form an integrated structure. The first gate T7_g1 of the first reset transistor T7 and the first sub-reset line Rst11 form an integrated structure.

[0147] The first sub-control line EM11 , the second sub-control line EM12 , the first sub-reset line Rst11 , and the second sub-reset line Rst12 may all extend along the first direction.

[0148] It should be noted that the signal line involved in the embodiments of the present disclosure "extending along the first direction" (or "extending along the second direction") does not necessarily mean that the signal line must be a straight line, and it may also have certain bends, as long as the signal line as a whole tends to extend along the first direction (or second direction).

[0149] The first gate metal layer G1 may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first gate metal layer G1 may include gold (Au), a gold alloy, silver (Ag), a silver alloy, aluminum (Al), an aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), a copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), a molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first gate metal layer G1 may have a single layer or multiple layers.

[0150] As shown in Figures 19 to 21, the second gate insulating layer GI2 is provided on a side of the first gate metal layer G1 away from the base substrate 101. The second gate insulating layer GI2 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The first gate insulating layer GI1 may be formed as a single layer or multiple layers.

[0151] As shown in Figures 11, 12, and 19 to 21, the semiconductor layer Poly is disposed on a side of the second gate insulating layer GI2 away from the base substrate 101. The semiconductor layer Poly may include active layers T1_a to T7_a and doping region patterns of each transistor in the pixel driving circuit (i.e., the third reset transistor T1, the second reset transistor T2, the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the first reset transistor T7). The active layer and doping region pattern of each transistor in the same first pixel circuit are integrally arranged. For the same transistor, doping region patterns are provided on both sides of the active layer of the transistor. The doping region patterns on both sides of the active layer can serve as the first and second poles of the transistor, respectively. The active layers T1_a to T7_a of each transistor are identified in Figure 11. It should be noted that in the embodiments of the present disclosure, the position of the active layer of each transistor represents the position of the corresponding transistor.

[0152] Among them, the second electrode of the first light-emitting control transistor T5 and the first electrode of the driving transistor T3 form an integrated structure, the second electrode of the driving transistor T3 and the first electrode of the first reset transistor T7 form an integrated structure, the second electrode of the data writing transistor T4 and the second electrode of the second light-emitting control transistor T6 form an integrated structure, the first electrode of the second light-emitting control transistor T6 and the first electrode of the third reset transistor T1 form an integrated structure, and the second electrode of the third reset transistor T1 and the first electrode of the second reset transistor T2 form an integrated structure.

[0153] In an example, the active layer T4_a of the data writing transistor T4, the active layer T6_a of the second light-emitting control transistor T6, and the active layer T1_a of the third reset transistor T1 are roughly arranged along the second direction; the active layer T5_a of the first light-emitting control transistor T5, the active layer T3_a of the driving transistor T3, and the active layer T7_a of the first reset transistor T7 are roughly arranged along the second direction; the active layer T1_a of the third reset transistor T1 and the active layer T2_a of the second reset transistor T2 are roughly arranged along the first direction.

[0154] The semiconductor layer Poly may be formed by patterning a semiconductor material, and the semiconductor material may be an oxide semiconductor material, such as IGZO.

[0155] As shown in Figures 19 to 21, the interlayer dielectric layer ILD is arranged on the side of the semiconductor layer Poly away from the base substrate 101. The material of the interlayer dielectric layer ILD can be selected from the materials of the first gate insulation layer GI1 and the second gate insulation layer GI2 listed above. The interlayer dielectric layer ILD can be one layer or multiple layers.

[0156] As shown in Figures 13, 14, and 19 to 21, the second gate metal layer G2 is disposed on a side of the interlayer dielectric layer ILD away from the substrate 101. The second gate metal layer G2 includes the second gates of each transistor in the pixel driving circuit, as well as a second sub-control line EM12 and a second sub-reset line Rst12. The second gate T5_g2 of the first emission control transistor T5 is integrally formed with the second sub-control line EM12, and the second gate T7_g2 of the first reset transistor T7 is integrally formed with the second sub-reset line Rst12.

[0157] In some examples, the first sub-control line EM11, the second sub-control line EM12, the first sub-reset line Rst11 and the second sub-reset line Rst12 can all extend to the peripheral area of ​​the display substrate, in which the first sub-control line EM11 and the second sub-control line EM12 are connected by vias, and the first sub-reset line Rst11 and the second sub-reset line Rst12 are connected by vias.

[0158] In one example, the orthographic projection of the second sub-control line EM12 on the substrate 101 at least partially overlaps with the orthographic projection of the first sub-control line EM11 on the substrate 101. For example, the orthographic projection of the second sub-control line EM12 on the substrate 101 substantially coincides with the orthographic projection of the first sub-control line EM11 on the substrate 101. In one example, the orthographic projection of the second sub-reset line Rst12 on the substrate 101 at least partially overlaps with the orthographic projection of the first sub-reset line Rst11 on the substrate 101. For example, the orthographic projection of the second sub-reset line Rst12 on the substrate 101 substantially coincides with the orthographic projection of the first sub-reset line Rst11 on the substrate 101.

[0159] It should be noted that, in the embodiments of the present disclosure, Figures 8 to 21 are illustrated using the example of each transistor in the pixel driving circuit being a dual-gate transistor, but the present disclosure is not limited to this. Individual transistors in the pixel driving circuit may also be set as dual-gate transistors, and the remaining transistors may be set as single-gate transistors. In this case, the first gate and the second gate of the dual-gate transistor are respectively located in the first gate metal layer G1 and the second gate metal layer G2, and the gate of the single-gate transistor may be located in the first gate metal layer G1 or in the second gate metal layer G2.

[0160] As shown in Figures 19 to 21, the first passivation layer PVX1 is arranged on the side of the second gate metal layer G2 away from the base substrate 101. The material of the first passivation layer PVX1 can be selected from the materials of the first gate insulation layer GI1 and the second gate insulation layer GI2 listed above. The first passivation layer PVX1 can be one layer or more layers.

[0161] As shown in Figures 15, 16, and 19 to 21, the first source-drain metal layer SD1 is located on a side of the first passivation layer PVX1 away from the base substrate 101. The material of the first source-drain metal layer SD1 can be selected from the materials of the first gate metal layer G1 listed above. Of course, in addition to the materials of the first gate metal layer G1 listed above, the first source-drain metal layer SD1 can also be made of a molybdenum / titanium alloy or a stacked layer, such as a titanium / aluminum / titanium stacked layer. The first source-drain metal layer SD1 includes: a scan signal line GL, a second light-emitting control line EM2, a reference voltage line Ref, a second reset signal line Rst2, an initialization signal line Init, a first transfer electrode E1, a second transfer electrode E2, a third transfer electrode E3, a fourth transfer electrode E4, and a fifth transfer electrode E5.

[0162] The first power line VDD includes a first sub-power line VDD1 and a second sub-power line VDD2. The first sub-power line VDD1 is located in the first source-drain metal layer SD1 and extends along the first direction. As shown in Figures 15 and 16, the first sub-power line VDD1 is connected to the first electrode T5_1 of the first emission control transistor T5 through a fourth via V4.

[0163] The second switching electrode E2 is located at one side of the first sub-power line VDD1 along the second direction, and the second switching electrode E2 is connected to the first electrode T4_1 of the data writing transistor T4 through the twelfth via hole V12 .

[0164] As shown in Figures 15 and 16, the scan signal line GL is located on a side of the second transfer electrode E2 away from the first sub-power line VDD1. The scan signal line GL includes an integral structure: a scan line body GL0, a first connecting portion GLa, and a second connecting portion GLb. The scan line body GL0 extends along a first direction, and the first connecting portion GLa and the second connecting portion GLb are located on opposite sides of the scan line body GL0 and arranged along a second direction, with the first direction intersecting the second direction. For example, the first direction is perpendicular to the second direction. The first connecting portion GLa is connected to the first gate T4_g1 of the data write transistor T4 through the tenth via V10, and the second connecting portion GLb is connected to the second gate T4_g2 of the data write transistor T4 through the eleventh via V11.

[0165] As shown in Figures 15, 16, and 19, the fifth transfer electrode E5 is located between the scan signal line GL and the second light-emitting control line EM2. One end of the fifth transfer electrode E5 is connected to the second electrode T4_2 of the data writing transistor T4 through the eighteenth via V18, and the other end is connected to the fourth plate C24 of the second capacitor C2 through the nineteenth via V19.

[0166] As shown in Figures 10 to 16, the second emission control line EM2 is located on a side of the scan signal line GL away from the first sub-power line VDD1 and extends along the first direction. The second emission control line EM2 is connected to the first gate T6_g1 of the second emission control transistor T6 through a sixth via V6, and is connected to the second gate T6_g2 of the second emission control transistor T6 through a seventh via V7. The sixth and seventh vias V6 and V7 are arranged along the first direction.

[0167] As shown in Figures 10 to 16, the first transfer electrode E1 is located between the second light-emitting control line EM2 and the reference voltage line Ref. The first transfer electrode E1 is connected to the first electrode T6_1 of the second light-emitting control transistor T6 through the eighth via V8, and is connected to the second gate T3_g2 of the driving transistor T3 through the ninth via V9.

[0168] 10 to 16 , the reference voltage line Ref is located on a side of the second light emitting control line EM2 away from the scanning signal line GL and extends along the first direction. The reference voltage line Ref is connected to the first electrode of the second reset transistor T2 through the twentieth via hole V20.

[0169] As shown in Figures 10 to 16, the second reset signal line Rst2 is located on a side of the reference voltage line Ref away from the second light-emitting control line EM2, and includes a reset line body Rst20 and a third connection portion Rst21 formed as an integrated structure. The reset line body Rst20 extends along the first direction, and the third connection portion Rst21 is located on a side of the reset line body Rst20 close to the reference voltage line Ref or away from the reference voltage line Ref.

[0170] As shown in Figures 10 to 16, the third connection portion Rst21 of the second reset signal line Rst2 is connected to the first gate T2_g1 of the second reset transistor T2 and the first gate T1_g1 of the third reset transistor T1 through the second via V2, and the reset line body Rst20 is connected to the second gate T2_g2 of the second reset transistor T2 and the second gate T1_g2 of the third reset transistor T1 through the third via V3.

[0171] As shown in Figures 10 to 16, the third transfer electrode E3 and the fourth transfer electrode E4 are both located between the second reset signal line Rst2 and the initialization signal line Init. One end of the third transfer electrode E3 is connected to the second gate electrode T3_g2 of the driving transistor T3 via a fourteenth via V14, and the other end is connected to the second electrode T3_2 of the driving transistor T3 via a fifteenth via V15. Connecting the first gate electrode T3_g1 and the second electrode T3_2 of the driving transistor T3 helps improve the driving stability of the driving transistor T3.

[0172] As shown in FIG. 8 to FIG. 16 , one end of the fourth transfer electrode E4 is connected to the second electrode plate C12 through the sixteenth via hole V16 , and the other end is connected to the second electrode of the third reset transistor T1 through the seventeenth via hole V17 .

[0173] As shown in Figures 8 to 16, the initialization signal line Init is located on a side of the second reset signal line Rst2 away from the reference voltage line Ref and extends along the first direction. Furthermore, the orthogonal projection of the initialization signal line Init on the base substrate 101 is located on a side of the orthogonal projection of the first reset signal line Rst1 on the base substrate 101 along the second direction. The initialization signal line Init is connected to the first electrode T7_1 of the first reset transistor T7 through a first via V1.

[0174] As shown in Figures 19 to 21, the insulating spacer layer 80 is located on the side of the first source-drain metal layer SD1 away from the base substrate 101. The insulating spacer layer 80 may include at least one of a second passivation layer and a planarization layer. For example, the insulating spacer layer 80 may include only the second passivation layer; or only the planarization layer; or the second passivation layer and the planarization layer, and the planarization layer is located on the side of the second passivation layer away from the base substrate 101. The material of the second passivation layer can be selected from the materials of the first gate insulating layer GI1 listed above, which will not be repeated here. The material of the planarization layer may include an organic insulating material, such as a resin material such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, etc. The second passivation layer PVX2 may be a single layer or multiple layers.

[0175] As shown in Figures 19 to 21, the second source / drain metal layer SD2 is located on the side of the second passivation layer PVX2 away from the base substrate 101. The material of the second source / drain metal layer SD2 can be selected from the materials for the first gate metal layer G1 listed above. Of course, in addition to the materials for the first gate metal layer G1 listed above, the second source / drain metal layer SD2 can also be made of a molybdenum / titanium alloy or a stacked layer, such as a titanium / aluminum / titanium stacked layer. As shown in Figure 17, the second source / drain metal layer SD2 may include: a data signal line DL, a second sub-power line VDD2, and a second power line VSS.

[0176] As shown in Figures 11, 17, and 18, the data signal line DL extends along the second direction and is connected to the first electrode T4_1 of the data write transistor T4 via a thirteenth via V13. The second sub-power line VDD2 extends along the second direction and is connected to the first sub-power line VDD1 via a fifth via V5. The first sub-power line VDD1 extends generally along the first direction, and the second sub-power line VDD2 extends generally along the second direction, thereby forming a grid structure for the first power line VDD. This reduces the voltage drop across the first power line VDD, facilitating display uniformity. The orthographic projections of the active layer T2_a of the second reset transistor T2, the active layer T1_a of the third reset transistor T1, the active layer T6_a of the second emission control transistor T6, and the active layer T4_a of the data write transistor on the substrate 101 all overlap with the orthographic projection of the second sub-power line VDD2 on the substrate 101. This further reduces leakage current in the transistors due to light exposure and improves the electrical characteristics of the transistors. For example, the orthographic projections of the active layer T2_a, the active layer T1_a, the active layer T6_a, and the active layer T4_a on the base substrate 101 are all located within the orthographic projection range of the second sub power line VDD2 on the base substrate 101 .

[0177] The second power line VSS extends along the second direction and is located on a side of the second sub-power line VDD2 away from the data signal line DL. The second power line VSS is used to provide a voltage signal to the second electrode of the light-emitting device 2. For example, the second electrode of the light-emitting device 2 extends to the peripheral area, where it is connected to the second power line VSS through a via. The orthographic projections of the active layer T7_a of the first reset transistor T7, the active layer T5_a of the first light-emission control transistor T5, and the active layer T3_a of the drive transistor T3 on the substrate 101 all overlap with the orthographic projection of the second power line VSS on the substrate 101. This further reduces leakage current in the transistors due to light exposure and improves the electrical characteristics of the transistors. For example, the orthographic projections of the active layers T7_a, T5_a, and T3_a on the substrate 101 all lie within the orthographic projection of the second power line VSS on the substrate 101.

[0178] An embodiment of the present disclosure further provides a display substrate, comprising the pixel driving circuit in the above embodiment.

[0179] The display substrate includes a display area and a peripheral area located around the display area. The display area includes multiple pixel areas, and the multiple pixel areas can be arranged in an array. A pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit can be provided in each pixel area. In the same row of pixel areas, the data writing transistors of the multiple pixel driving circuits are connected to the same scanning signal line; the first reset transistors of the multiple pixel driving circuits are connected to the same first reset signal line; the second reset transistors and third reset transistors of the multiple pixel driving circuits are connected to the same second reset signal line; the first light-emitting control transistors of the multiple pixel driving circuits are connected to the same first light-emitting control line and to the same first power line; the second light-emitting control transistors of the multiple pixel driving circuits are connected to the same second light-emitting control line, and the data writing transistors of the multiple pixel driving circuits are connected to the same scanning signal line. In the same column of pixel areas, the data writing transistors of the multiple pixel driving circuits are connected to the same data signal line.

[0180] The present disclosure also provides a display device. The display device may include the display substrate as described above. The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0181] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A pixel driving circuit, include: A driving transistor, a first reset sub-circuit, a second reset sub-circuit, a light emitting control sub-circuit, a data writing circuit, a first energy storage element and a second energy storage element; wherein, The first reset subcircuit is configured to, in response to a first reset signal, write an initialization voltage signal to a third node; the third node is a connection node between the second electrode of the driving transistor and the first end of the first energy storage element; The second reset subcircuit is configured to, in response to a second reset signal, conduct the gate of the driving transistor to a fourth node and reset the gate of the driving transistor and the fourth node; the fourth node is a connection node between the first energy storage element, the second energy storage element and the second reset subcircuit; The data writing sub-circuit is configured to write a data voltage signal into the second energy storage element in response to a scan signal; The light emitting control subcircuit is configured to, in response to a first light emitting control signal, conduct the first electrode of the driving transistor with the power supply terminal; and in response to a second light emitting control signal, transmit the data voltage signal to the gate of the driving transistor.

2. The pixel driving circuit according to claim 1, in, The first reset subcircuit includes: a first reset transistor, wherein a gate of the first reset transistor is connected to a first reset signal line, a first electrode is connected to an initialization signal line, and a second electrode is connected to the third node.

3. The pixel driving circuit according to claim 2, in, The initialization signal line extends along a first direction, an orthographic projection of the initialization signal line on the base substrate is located on one side of an orthographic projection of the first reset signal line on the base substrate along a second direction, and the first direction intersects the second direction; The initialization signal line is connected to the first electrode of the first reset transistor through a first via hole.

4. The pixel driving circuit according to claim 1, in, The second reset subcircuit comprises: a second reset transistor and a third reset transistor, wherein: The gate of the second reset transistor is connected to the second reset signal line, the first electrode is connected to the reference voltage line, and the second electrode is connected to the fourth node; The gate of the third reset transistor is connected to the second reset signal line, the first electrode is connected to the gate of the driving transistor, and the second electrode is connected to the fourth node.

5. The pixel driving circuit according to claim 4, in, The second reset transistor and the third reset transistor are both dual-gate transistors, the first gate of the second reset transistor and the third gate of the third reset transistor are an integrated structure, and the second gate of the second reset transistor and the second gate of the third reset transistor are an integrated structure; The second reset signal line connects the first gate of the second reset transistor and the first gate of the third reset transistor through a second via, and connects the second gate of the second reset transistor and the second gate of the third reset transistor through a third via.

6. The pixel driving circuit according to claim 1, in, The second reset subcircuit comprises: a second reset transistor and a third reset transistor, wherein: The gate of the second reset transistor is connected to the second reset signal line, the first electrode is connected to the reference voltage line, and the second electrode is connected to the gate of the driving transistor; The gate of the third reset transistor is connected to the second reset signal line, the first electrode is connected to the gate of the driving transistor, and the second electrode is connected to the fourth node.

7. The pixel driving circuit according to claim 1, in, The light emitting control subcircuit comprises: a first light emitting control transistor and a second light emitting control transistor, wherein: The gate of the first light emitting control transistor is connected to the first light emitting control line, and the first electrode is connected to The second electrode of the first power line is connected to the first electrode of the driving transistor; The gate of the second light emitting control transistor is connected to the second light emitting control line, the first electrode is connected to the first electrode of the driving transistor, and the second electrode is connected to the second energy storage element.

8. The pixel driving circuit according to claim 7, in, The first power line includes: a first sub-power line and a second sub-power line, the first sub-power line extends along a first direction, the second sub-power line extends along a second direction, and the first direction intersects with the second direction; The first sub power line is connected to the first electrode of the first light emission control transistor through a fourth via hole, and the second sub power line is connected to the first sub power line through a fifth via hole.

9. The pixel driving circuit according to claim 8, in, The second light emitting control transistor is a dual-gate transistor, the second light emitting control line is connected to the first gate of the second light emitting control transistor through a sixth via hole, and is connected to the second gate of the second light emitting control transistor through a seventh via hole, and the second light emitting control line extends along the first direction.

10. The pixel driving circuit according to claim 7, in, The pixel driving circuit further includes: a first switching electrode, wherein the first switching electrode is connected to the first electrode of the second light emitting control transistor through an eighth via hole, and is connected to the gate electrode of the driving transistor through a ninth via hole.

11. The pixel driving circuit according to claim 1, in, The data writing subcircuit comprises: a data writing transistor, a gate of the data writing transistor is connected to a scanning signal line, a first electrode is connected to a data signal line, and a second electrode is connected to the second energy storage element and the light emitting control subcircuit.

12. The pixel driving circuit according to claim 11, in, The data signal line extends along the second direction, and the scan signal line includes: a scan line body, a first connecting portion, and a second connecting portion formed in an integrated structure, the scan line body extends along the first direction, the first connecting portion and the second connecting portion are respectively located at two opposite sides of the scan line body and arranged along the second direction; the first direction intersects the second direction; The data writing transistor is a dual-gate transistor, the first connecting portion is connected to the first gate of the data writing transistor through a tenth via hole, and the second connecting portion is connected to the second gate of the data writing transistor through an eleventh via hole.

13. The pixel driving circuit according to claim 11, in, The pixel driving circuit further includes: a second switching electrode, wherein the second switching electrode is connected to the first electrode of the data writing transistor through a twelfth via hole, and the data signal line is connected to the second switching electrode through a thirteenth via hole.

14. The pixel driving circuit according to any one of claims 1 to 13, in, The first energy storage element includes: a first capacitor, the first capacitor includes a first plate and a second plate, the first plate is connected to the second electrode of the driving transistor, and the second plate is connected to the second energy storage element.

15. The pixel driving circuit according to claim 14, in, The first electrode plate is located on a side of the second electrode plate away from the substrate, the driving transistor is a dual-gate transistor, the second gate of the driving transistor is located on a side of the first gate of the driving transistor away from the substrate, and the first gate of the driving transistor is shared with the first electrode plate.

16. The pixel driving circuit according to claim 15, in, The pixel driving circuit further includes: a third switching electrode, one end of which is connected to the first gate electrode of the driving transistor through a fourteenth via hole, and the other end of which is connected to the second electrode of the driving transistor through a fifteenth via hole.

17. The pixel driving circuit according to claim 14, in, The second reset subcircuit comprises: a second reset transistor and a third reset transistor; The first electrode is located on a side of the second electrode away from the substrate. The pixel driving circuit also includes a fourth switching electrode, one end of which is connected to the second electrode through a sixteenth via hole, and the other end of which is connected to the second electrode of the third reset transistor through a seventeenth via hole.

18. The pixel driving circuit according to any one of claims 1 to 17, in, The second energy storage element includes: a second capacitor, the second capacitor includes a third plate and a fourth plate, the third plate is connected to the first energy storage element, and the fourth plate is connected to the data writing sub-circuit.

19. The pixel driving circuit according to claim 18, in, The data writing sub-circuit comprises: a data writing transistor; The pixel driving circuit further includes: a fifth switching electrode, one end of which is connected to the second electrode of the data writing transistor through an eighteenth via hole, and the other end of which is connected to the fourth electrode plate through a nineteenth via hole.

20. The pixel driving circuit according to claim 17, in, The first energy storage element includes a first capacitor, the first capacitor includes a first electrode plate and a second electrode plate, and the third electrode plate of the second capacitor is connected to the second electrode plate as an integrated structure.

21. The pixel driving circuit according to any one of claims 1 to 20, in, The pixel driving circuit comprises: a first gate metal layer, a semiconductor layer, and a second gate metal layer which are sequentially arranged in a direction away from the substrate; Among them, each transistor in the pixel driving circuit is a dual-gate transistor, the semiconductor layer includes an active layer, a first electrode and a second electrode of each transistor in the pixel driving circuit; the first gate metal layer includes a first gate of each transistor in the pixel driving circuit, and the second gate metal layer includes a second gate of each transistor in the pixel driving circuit.

22. The pixel driving circuit according to claim 21, in, The light emission control subcircuit includes a first light emission control transistor and a second light emission control transistor; The pixel driving circuit also includes: a first source-drain metal layer, located on a side of the second gate metal layer away from the base substrate; the first source-drain metal layer includes: a first transfer electrode, the first transfer electrode is connected to the first electrode of the second light-emitting control transistor through an eighth via hole, and is connected to the gate of the driving transistor through a ninth via hole.

23. The pixel driving circuit according to claim 22, in, The first electrode of the first light emitting control transistor is connected to a first power line, the first power line includes: a first sub-power line and a second sub-power line, the first sub-power line is located in the first source-drain metal layer, the second sub-power line is located in the second source-drain metal layer, and the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate; The first sub power line is connected to the first electrode of the first light emission control transistor through a fourth via hole, and the second sub power line is connected to the first sub power line through a fifth via hole.

24. The pixel driving circuit according to claim 23, in, The first reset subcircuit includes: a first reset transistor; the second reset subcircuit includes: a second reset transistor and a third reset transistor; the data writing subcircuit includes: a data writing transistor; The active layer of the second reset transistor, the active layer of the third reset transistor, the active layer of the second light emission control transistor, and the active layer of the data write transistor are arranged on the The orthographic projections on the base substrate overlap with the orthographic projections of the second sub-power lines on the base substrate; The orthographic projections of the active layer of the first reset transistor, the active layer of the first light emission control transistor, and the active layer of the driving transistor on the base substrate all overlap with the orthographic projection of the second power line on the base substrate.

25. The pixel driving circuit according to claim 21, in, The second reset subcircuit comprises: a second reset transistor and a third reset transistor; The pixel driving circuit further includes: a first source-drain metal layer located on a side of the second gate metal layer away from the substrate; the first source-drain metal layer includes a reference voltage line, and the reference voltage line is connected to the first electrode of the second reset transistor through a twentieth via hole.

26. The pixel driving circuit according to claim 21, in, The data writing sub-circuit comprises: a data writing transistor; The pixel driving circuit further comprises: a first source-drain metal layer and a second source-drain metal layer, wherein the first source-drain metal layer is located on a side of the second gate metal layer away from the substrate, and the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate; The first source-drain metal layer includes: a scan signal line and a second transfer electrode; the second source-drain metal layer includes: a data signal line; the scan signal line is connected to the first gate of the data writing transistor through the tenth via hole, and is connected to the second gate of the data writing transistor through the eleventh via hole; The second switching electrode is connected to the first electrode of the data writing transistor through a twelfth via hole, and the data signal line is connected to the second switching electrode through a thirteenth via hole.

27. The pixel driving circuit according to claim 21, in, The pixel driving circuit further includes a light-shielding metal layer, and the light-shielding metal layer is located between the first gate metal layer and the base substrate; The first energy storage element includes a first capacitor, which includes a first plate and a second plate; the second energy storage element includes a second capacitor, which includes a third plate and a fourth plate; the shading metal layer includes the second plate and the third plate; and the first gate metal layer also includes the first plate and the fourth plate.

28. The pixel driving circuit according to claim 27, in, The pixel driving circuit further comprises: a first source-drain metal layer, located on a side of the second gate metal layer away from the substrate; The first source-drain metal layer includes: a third switching electrode, one end of which is connected to the first gate electrode of the driving transistor through a fourteenth via hole, and the other end of which is connected to the second electrode of the driving transistor through a fifteenth via hole.

29. The pixel driving circuit according to claim 28, in, The second reset subcircuit comprises: a second reset transistor and a third reset transistor; The first source-drain metal layer further includes: a fourth switching electrode, one end of which is connected to the second electrode plate through a sixteenth via hole, and the other end of which is connected to the second electrode of the third reset transistor through a seventeenth via hole.

30. The pixel driving circuit according to claim 27, in, The pixel driving circuit further comprises: a first source-drain metal layer, located on a side of the second gate metal layer away from the substrate; The data writing sub-circuit includes: a data writing transistor; the first source-drain metal layer includes: a fifth switching electrode, one end of the fifth switching electrode is connected to the second electrode of the data writing transistor through an eighteenth via hole, and the other end is connected to the fourth electrode plate through a nineteenth via hole.

31. A driving method of a pixel driving circuit as claimed in any one of claims 1 to 30, include: In the reset stage, the first reset signal and the second reset signal are in a working level state, and the first reset subcircuit writes an initialization voltage signal to the third node; The second reset subcircuit conducts the gate of the driving transistor to the fourth node, and resets the gate of the driving transistor and the fourth node; In the threshold compensation stage, the first light emitting control signal and the second reset signal are in a working level state, and the second reset subcircuit conducts the gate of the driving transistor with the fourth node to write the threshold voltage of the driving transistor into the first energy storage element; In the data writing stage, the second reset signal and the scanning signal are in a working level state, the data writing subcircuit writes the data voltage signal into the second energy storage element, and the second reset subcircuit resets the fourth node; In the light-emitting stage, the first light-emitting control signal and the second light-emitting control signal are both in the working level state, the light-emitting control subcircuit connects the first electrode of the driving transistor to the power supply terminal, and transmits the data voltage signal to the gate of the driving transistor, so that the driving transistor provides a driving current for the light-emitting device.

32. A display substrate comprising a display area, in, The display area includes a plurality of pixel areas, in which are disposed: a pixel driving circuit according to any one of claims 1 to 30, and a light-emitting device electrically connected to the pixel driving circuit.

33. A display device comprising the display substrate according to claim 32.

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