Power saving method and device and computer readable storage medium

Abstract

A method of conserving power is provided. The method is used for the slave device. The method includes receiving a first switching request indicating that a clock source is switched from a first clock to a second clock when the slave device enters a sleep mode. The method includes transmitting a first clock source signal indicative of switching a clock source from a first clock to a second clock to a register. The method includes switching a clock source of a register from a first clock to a second clock according to a first clock source signal.

Description

Technical Field

[0001] The present disclosure generally relates to a method and apparatus for saving power. More specifically, aspects of the present disclosure relate to a method and apparatus for saving power in a system power management interface (SPMI) slave device. Background Art

[0002] Computing devices are ubiquitous in modern society. The proliferation of computing devices is at least partially due to the rise of mobile computing devices such as smartphones. Computing devices often rely on different application-specific integrated circuits (ICs) that perform specific functions for the computing device. When there are multiple ICs, there must be an accepted protocol or standard by which the ICs can communicate with each other. Just as ICs may be specialized in the tasks they are able to perform, specialized protocols are also created. One such protocol is the system power management interface (SPMI) proposed by the MIPI Alliance.

[0003] In the SPMI protocol, a simple SPMI slave device can only operate when the master device provides the SPMI clock (SCLK) signal. When the SPMI slave device has only a single clock domain (such as the system clock), once the SPMI access is stopped and the system clock in the SPMI slave device is turned off, the SPMI slave device cannot perform any function.

[0004] In order to save power consumption of the system-on-chip (SOC) of the SPMI slave device, the high-speed system clock will be adaptively turned off when the SPMI slave device is idle. However, the function-related registers in the SPMI slave device that use the system clock are only updated when the system clock is valid. Once the system clock is turned off, these registers may not be updated through SPMI access, and when the system clock is turned off, other devices on the SPMI bus cannot communicate with the SPMI slave device.

[0005] Therefore, a power saving method and device are needed to solve this problem. Summary of the invention

[0006] The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce the concepts, highlights, benefits, and advantages of the novel and non-obvious technologies described herein. Selected, but not all, implementations are further described in the detailed description below. Therefore, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

[0007] Therefore, the main purpose of the present invention is to provide a power saving method and device, so that the system clock can be adaptively turned off when the device is idle, and external devices can still communicate with the device during the period when the system clock is turned off.

[0008] In an exemplary embodiment, a method for saving power in a slave device is provided. The method is used in the slave device. The method includes receiving a first switching request indicating that a clock source is switched from a first clock to a second clock when the slave device enters a sleep mode. The method includes transmitting a first clock source signal indicating that the clock source is switched from the first clock to the second clock to a register. The method includes switching a clock source of the register from the first clock to the second clock according to the first clock source signal.

[0009] In some embodiments, the method also includes detecting whether the SPMI bus is idle; in response to the SPMI bus being idle, transmitting the first clock source signal to the register.

[0010] In some embodiments, the method further includes delaying sending the first clock source signal to the register in response to the SPMI bus not being idle until the SPMI bus is idle.

[0011] In some embodiments, the method further includes receiving a second switching request indicating switching the clock source from the second clock to the first clock when the slave device enters the wake-up mode. The method further includes transmitting a second clock source signal indicating switching the clock source from the second clock to the first clock to the register.

[0012] In some embodiments, the method further includes the register switching the clock source from the second clock to the first clock according to the second clock source signal.

[0013] In some embodiments, when the slave device is in sleep mode, the slave device is clocked by the second clock.

[0014] In some embodiments, the slave device is a SPMI slave device.

[0015] In some embodiments, the method further includes allowing the external device to access the register via the SPMI bus, wherein the register is clocked by the second clock when the slave device is in the sleep mode.

[0016] In some embodiments, the external device is a SPMI master device.

[0017] In some embodiments, the first clock is a system clock and the second clock is a system power management interface (SPMI) clock (SCLK).

[0018] In an exemplary embodiment, a device for power saving is provided. The device includes a processor, a register, and a dynamic clock source controller. The dynamic clock source controller is coupled to the processor and the register, and is configured to receive a first switching request, the first switching request indicating that the clock source is switched from a first clock to a second clock when the device enters a sleep mode. The dynamic clock source controller is also configured to send a first clock source signal to the register indicating that the clock source is switched from the first clock to the second clock. The dynamic clock source controller is also used to switch the clock source from the first clock to the second clock to the register according to the first clock source signal.

[0019] In an exemplary embodiment, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions, which, when executed by a subsystem in a slave device, cause the slave device to perform a method for saving power, the method comprising: receiving a first switching request indicating switching a clock source from a system clock to a system power management interface (SPMI) clock (SCLK) when the slave device enters a sleep mode; detecting whether an SPMI bus is idle; in response to the SPMI bus being idle, transmitting a first clock source signal indicating switching the clock source from the system clock to the SCLK to an SPMI register; and the SPMI register switches the clock source from the system clock to the SCLK according to the first clock source signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of the present disclosure. The accompanying drawings illustrate embodiments of the present disclosure and together with the description are used to explain the principles of the present disclosure. It should be understood that the drawings are not necessarily drawn to scale, as some components may be shown out of proportion to the dimensions in actual implementation in order to clearly illustrate the concepts of the present disclosure.

[0021] Figure 1 is a block diagram of an SPMI system having multiple master devices and multiple slave devices attached to a two-wire SPMI bus.

[0022] Figure 2 is a schematic diagram of an exemplary slave device for saving power according to an embodiment of the present invention.

[0023] Figure 3 FIG. 4 is a flow chart of a power saving method for a slave device according to an embodiment of the present invention.

[0024] Figure 4 FIG. 4 is a flow chart of a power saving method for a slave device according to an embodiment of the present invention.

[0025] Figure 5A A set of timing waveforms depicting switching operations during idle periods are shown according to an embodiment of the present disclosure.

[0026] Figure 5B A set of timing waveforms depicting switching operations during a busy period are shown according to an embodiment of the present disclosure.

[0027] Figure 5C A set of timing waveforms depicting switching operations during a busy period of back-to-back transactions according to an embodiment of the present disclosure are shown.

[0028] Figure 6 An exemplary operating environment for implementing embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0029] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to any particular structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those with ordinary knowledge in the art. Based on the teachings herein, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether implemented independently or in combination with any other aspect of the present disclosure. For example, a plurality of aspects set forth herein may be used to implement a device or a practical method. In addition, the scope of the present disclosure is intended to cover a device or method that is practiced using another structure, function, or structure and function other than or in addition to the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied through one or more elements of the claims.

[0030] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Furthermore, unless otherwise indicated in the specification, like numerals refer to like elements throughout the several views, and the articles "a," "an," and "the" include plural references.

[0031] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements. Other words used to describe the relationship between elements should be interpreted in a similar manner. (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0032] In order to better describe the embodiments of the present invention, the specific terms used in the present invention are first defined as follows.

[0033] Master device: A device on the SPMI bus that can drive the SCLK line.

[0034] Slave device: A device on the SPMI bus that cannot drive the SCLK line, that is, it is not a master device.

[0035] Bus arbitration: Bus arbitration is the process of assigning the bus to a device to transmit a sequence.

[0036] Sequence: A bus transaction on the SPMI bus that begins with bus arbitration, contains a sequence start condition (SSC), a command frame, potential data and address frames, and ends with a bus park cycle. A sequence can be transmitted by a master device or a slave device with request capability.

[0037] Bus idle: The SPMI bus is idle when both SCLK and SDATA are at logic level 0 between the end of the sequence and the start of bus arbitration.

[0038] The System Power Management Interface (SPMI) is a two-wire serial interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor system to one or more Power Management Integrated Circuits (PMIC) voltage regulation systems. SPMI enables the system to dynamically adjust the power and substrate bias of the internal voltage domains of the SoC using a single SPMI bus.

[0039] In a PC, SPMI-related functions are called "master" devices. In a PMIC, SPMI-related functions are called "slave" devices. A single SPMI bus can have up to 4 masters and 16 slaves. Multiple SPMI masters and slaves can reside on a single IC, on separate ICs, or any combination of the two.

[0040] Figure 1 1 is a block diagram of an SPMI system 100 having a plurality of master devices and a plurality of slave devices attached to a two-wire SPMI bus 102. In this regard, the SPMI system 100 includes a plurality of master devices 104(1)-104(N) and a plurality of slave devices 106(1)-106(M). As shown, N=3 and M=2, but it should be understood that the SPM standard allows for up to four master devices 104 and up to sixteen slave devices 106. The SPMI bus 102 may include a clock line 108 and a data line 110 (in Figure 11 and 11. The SPMI interfaces 112(1)-112(2) are also referred to as SCLK and SDATA, respectively, in the master device 104(1). A given master device 104(1) may have multiple (in this case two) SPMI interfaces 112(1)-112(2) coupled to the SPMI bus 102. More commonly, a master device such as master device 104(N) may have a single SPMI interface 114 coupled to the SPMI bus 102. Similarly, a slave device such as slave device 106(1) may have a single SPMI interface 116, and a slave device such as slave device 106(M) may have multiple (in this case two) SPMI interfaces 118(1)-118(2).

[0041] Figure 2 2 is a schematic diagram of an exemplary slave device 200 for power saving according to an embodiment of the present invention. The slave device 200 may include a central processing unit (CPU) 210 and an SPMI slave subsystem 240. The SPMI slave subsystem 240 includes an SPMI receiver 242 (sometimes referred to as SPMI RX in the drawings), an SPMI register 244, a request capable slave (RCS) function 246 and a transmission (TX) function 2462, and a dynamic clock source controller 248.

[0042] In one embodiment, the CPU 210 is a component with non-always-on functionality, and the SPMI receiver 242, the SPMI register 244, the RCS function 246, the TX function 2462, and the dynamic clock source controller 248 support the always-on functionality.

[0043] like Figure 2 As shown, the CPU 210 is coupled to the TX function 2462 and the dynamic clock source controller 248 , the SPMI register 244 is coupled to the SPMI receiver 242 , the TX function 2462 and the dynamic clock source controller 248 , and the RCS function 246 is coupled to the TX function 2462 .

[0044] In the slave device 200, the SPMI receiver 242 and the RCS function 246 belong to the SCLK domain, while the CPU 210, the TX function 2462, and the dynamic clock source controller 248 belong to the system clock domain. The SPMI register 244 can be accessed in both the SCLK domain and the system clock domain. Specifically, the SPMI receiver 242, the SPMI register 244, and the RCS function 246 can operate when the SCLK is operating or the system clock is turned on, and the SCLK only operates when data is transmitted on the SPMI bus 250. The CPU 210, the TX function 2462, the SPMI register 244, and the dynamic clock source controller 248 operate when the system clock is turned on.

[0045] In one embodiment, it should be noted that the SPMI register 244 can operate on two clock sources. That is, the SPMI register can be clocked by the SPMI clock (SCLK) and the system clock. According to the clock source signal from the dynamic clock source controller 248, the clock source of the SPMI register 244 will be determined. When SCLK is selected according to the clock source signal from the dynamic clock source controller 248, the clock source of the SPMI register 244 will be switched to SCLK, and the SPMI register 244 will work in the SCLK domain accordingly. On the contrary, when the system clock is selected according to the clock source signal from the dynamic clock source controller 248, the clock source of the SPMI register 244 will be switched to the system clock, and the SPMI register 244 can operate in the system clock domain accordingly. In an embodiment of the present invention, the clock source of the SPMI register 244 can be dynamically switched between SCLK and the system clock according to the clock source signal. For example, the SPMI register 244 can include ten registers. All 10 registers can be accessed by both the SCLK domain and the system clock domain.

[0046] External devices ( Figure 2 ) can communicate with the slave device 200 via the SPMI bus 250, where the external device is a SPMI master device.

[0047] When the CPU 210 wants to sleep, the CPU 210 may send a first switching request to the dynamic clock source controller 248 and enter the sleep mode, wherein the first switching request indicates switching the clock source from the system clock to the power management interface (SPMI) clock (SCLK).

[0048] When the slave device enters the sleep mode, the dynamic clock source controller 248 receives a first switch request instructing to switch the clock source from the system clock to SCLK (step 1).

[0049] Then, the dynamic clock source controller 248 detects whether the SPMI bus 250 is idle (step 2).

[0050] Next, the dynamic clock source controller 248 transmits a clock source signal indicating switching of the clock source from the system clock to the SCLK to the SPMI register 244 in response to the SPMI bus being idle (step 3).

[0051] The SPMI register 244 switches the clock source from the system clock to SCLK according to the first clock source signal (step 4).

[0052] In other words, in sleep mode, the system clock is turned off and the slave device is clocked by the SPMI clock (SCLK). Since the SPMI receiver 242, SPMI register 244, and RCS function 246 belong to the SCLK domain, when the system clock is turned off, the SPMI receiver 242, SPMI register 244, and RCS function 246 still operate. When the slave device 200 is in sleep mode, the slave device 200 can allow external devices to access the SPMI register 244 via the SPMI bus 250.

[0053] Once the CPU 210 wants to wake up, the CPU 210 may send a second switching request to the dynamic clock source controller 248 and enter the wake-up mode, wherein the second switching request indicates to switch the clock source from the SCLK to the system clock.

[0054] Then, when the slave device enters the wake-up mode, the dynamic clock source controller 248 receives a second switching request instructing to switch the clock source from the SCLK to the system clock.

[0055] Next, the dynamic clock source controller 248 transmits a clock source signal instructing to switch the clock source from SCLK to the system clock to the SPMI register 244 .

[0056] The SPMI register 244 switches the clock source from SCLK to the system clock according to the second clock source signal.

[0057] Figure 3 FIG. 3 is a flow chart showing a method for saving power in a slave device according to an embodiment of the present disclosure. In this embodiment, the method is applied to Figure 2 The slave device 200 in .

[0058] In step S305, when the slave device enters sleep mode, the dynamic clock source controller of the slave device receives a first switching request indicating to switch the clock source from a first clock to a second clock, wherein the slave device is an SPMI slave device. In some embodiments, the first clock is a system clock and the second clock is a system power management interface (SPMI) clock (SCLK).

[0059] In step S310 , the dynamic clock source controller transmits a first clock source signal instructing to switch the clock source from the first clock to the second clock to a register, wherein the register is an SPMI register.

[0060] In step S315 , the SPMI register of the slave device switches the clock source from the first clock to the second clock according to the first clock source signal.

[0061] Before the dynamic clock source controller sends the first clock source signal, the dynamic clock source controller may also detect whether the SPMI bus is idle. In response to the SPMI bus being idle, the dynamic clock source controller transmits the first clock source signal to the register

[0062] After the SPMI register switches the clock source from the first clock to the second clock, registers belonging to the SCLK domain can be accessed by external devices, wherein these registers are clocked by the second clock when the slave device is in sleep mode.

[0063] In some embodiments, the dynamic clock source controller may delay transmitting the first clock source signal to the register in response to the SPMI bus not being idle until the SPMI bus is idle.

[0064] In another embodiment, when the slave device enters the wake-up mode after step S320, the dynamic clock source controller may also receive a second switching request indicating that the clock source is switched from the second clock to the first clock. Then, the dynamic clock source controller sends a second clock source signal indicating that the clock source is switched from the second clock to the first clock to the register. The register switches the clock source from the second clock to the first clock according to the second clock source signal.

[0065] Figure 4 FIG. 4 is a flow chart showing a method for saving power in a slave device according to an embodiment of the present disclosure. In this embodiment, the method is applied to Figure 2 The slave device 200 in .

[0066] In step S405 , when the slave device enters the sleep mode, the dynamic clock source controller of the slave device receives a first switching request instructing to switch the clock source from the system clock to the system power management interface (SPMI) clock (SCLK), wherein the slave device is a SPMI slave device.

[0067] Then, in step S410 , the dynamic clock source controller of the slave device detects whether the SPMI bus is idle.

[0068] In step S415 , the dynamic clock source controller transmits a first clock source signal instructing to switch the clock source from the system clock to the SCLK to the SPMI register in response to the SPMI bus being idle.

[0069] In step S420, the SPMI register of the slave device switches the clock source from the system clock to SCLK according to the first clock source signal.

[0070] Figure 5A to Figure 5C Three sets of timing waveforms related to the switching operation of the slave device according to an embodiment of the present disclosure are shown. The timing waveforms illustrate waveforms related to the SPMI clock signal SCLK, the command state CMD_STA, and the switching operation of the slave device, wherein the command state CMD_STA describes the state of the command sent by the external device.

[0071] Figure 5A A set of timing waveforms according to an embodiment of the present disclosure are shown, depicting a switching operation during an idle period. When the dynamic clock source controller receives a first switching request from the CPU at 501, the switching operation begins. During the idle period, the clock source immediately switches from the system clock to SCLK, and the switching operation is completed at 502. The time between 501 and 502 is called transient time. At 503, the external device writes an instruction to the SPMI register. Figure 5A As shown, as long as the dynamic clock source controller receives the first switching request during any idle period, the switching operation can be completed before the external device writes the instruction into the SPMI register.

[0072] Figure 5B A set of timing waveforms depicting a switching operation during a busy period according to an embodiment of the present disclosure is shown. The dynamic clock source controller receives a first switching request from the CPU at 504. Since the first switching request is received during the busy period when the command is written to the SPMI register at 505, the dynamic clock source controller delays sending the first clock at 506, transferring the source signal to the SPMI register until the SPMI bus is idle, and completes the switching operation at 507. Figure 5B As shown, when the switching operation occurs during any busy cycle, the clock source will switch from the system clock to SCLK during the next idle cycle.

[0073] Figure 5C A set of timing waveforms depicting switching operations during a busy period of back-to-back transactions according to an embodiment of the present disclosure are shown.

[0074] When the dynamic clock source controller receives the first switching request from the CPU and the last instruction has been written to the SPMI register, the switching operation starts at 508. Another instruction CMD starts at 509, and the switching operation can still be performed at 510. Obviously, the transient time of the clock switching between 508 and 510 is much smaller than the interval between two consecutive instructions written to the SPMI register. It can be understood by those skilled in the art that the instruction is written to the SPMI register at the time point between BP and A / N (BP→A / N). In other words, although the instruction transmission is relatively intensive, there is still enough time to switch between the system clock and SCLK, and the situation of "the clock source cannot be switched when the instruction transmission is the most intensive" will not occur.

[0075] As described above, the power saving method and device of the present invention can still allow external devices to access SPMI registers when the system clock is turned off. In other words, without waking up the entire slave device, SPMI-related functional registers can still be accessed and updated, which can more effectively achieve the purpose of saving power. In addition, the external device can send SPMI instructions to the updated register at any time to achieve the effect of zero recovery delay.

[0076] It should be noted that Figure 2 The CPU 210, the system clock circuit 230, the SPMI receiver 242, the system clock control circuit 244, the RCS function 246, the TX function 2462, and the always-on function 248 in the embodiment can be implemented in hardware, software, firmware, or any combination thereof. For example, the CPU 210, the system clock circuit 230, the SPMI receiver 242, the system clock control circuit 244, the RCS function 246, the TX function 2462, and the always-on function 248 can be implemented as computer program codes set to execute in one or more processors. Alternatively, the CPU 210, the system clock circuit 230, the SPMI receiver 242, the system clock control circuit 244, the RCS function 246, the TX function 2462, and the always-on function 248 can be implemented as hardware logic / circuitry.

[0077] The embodiments described herein, including systems, methods / processes and / or devices, may use well-known servers / computers (such as Figure 6 For example, the slave device 200 may be implemented using one or more electronic devices 600. For illustrative purposes, the electronic device 600 is described as follows.

[0078] Reference now Figure 6, an exemplary operating environment for implementing embodiments of the present disclosure is shown, and is generally referred to as electronic device 600. Electronic device 600 is merely an example of a suitable computing environment and is not intended to limit the scope of its use or functionality. Electronic device 600 should also not be interpreted as having any dependency or requirement relating to any one or combination of elements illustrated.

[0079] The present disclosure may be implemented through computer program code or machine-usable commands, including computer executable commands, such as program modules, executed by a computer or other handheld device (e.g., a personal digital assistant (PDA) or other machine). In general, a program module may include routines, programs, objects, components, data structures, etc., and refers to program code that performs a specific task or implements a specific abstract data type. The present disclosure may be implemented in a variety of system configurations, including handheld devices, consumer electronics, general-purpose computers, more specialized computing devices, etc. The present disclosure may also be implemented in a distributed computing environment, where tasks are performed by remote processing devices connected via a communication network.

[0080] like Figure 6 As shown, electronic device 600 may include a bus 610 that is directly or indirectly coupled to the following devices: one or more memories 612, one or more processors 614, one or more display elements 616, one or more input / output (I / O) ports 618, one or more input / output elements 620, and an example power supply 622. Bus 610 may represent one or more buses (e.g., an address bus, a data bus, or any combination thereof). Although Figure 6 The blocks are different. For clarity, Figure 6 The components in the figure are shown with lines, but in reality, the boundaries of the components are not specific. For example, a display element such as a display device can be considered as an I / O element, and a processor can include a memory.

[0081] The electronic device 600 generally includes various computer-readable media. Computer-readable media can be any available media that can be accessed by the electronic device 600, and include volatile and non-volatile media, removable and non-removable media. As an example and not limitation, computer-readable media can include computer storage media and communication media. Computer storage media can include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable commands, data structures, program modules or other data. Computer storage media can include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technology, read-only optical disk. Only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, cassette tape, magnetic tape, disk storage or other magnetic storage device, or any other can be used to store the required information and can be accessed by the electronic device 500. The computer storage medium itself may not include a signal.

[0082] Communication media typically embodies computer readable commands, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and includes any information delivery media. The term "modulated data signal" refers to a signal that has one or more characteristics set or changed in a manner that encodes the information in the signal. By way of example and not limitation, communication media include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media or any combination thereof.

[0083] Memory 612 may include computer storage media in the form of volatile and / or non-volatile memory. Memory may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memory, hard disks, optical drives, etc. Electronic device 600 includes one or more processors that read data from various entities such as memory 612 or I / O elements 620. Display element 616 presents data indication to a user or another device. Exemplary presentation elements include display devices, speakers, printing elements, vibrating elements, etc.

[0084] I / O port 618 allows computing device 600 to be logically coupled to other devices including I / O element 620, some of which may be embedded. Exemplary elements include microphones, joysticks, game handles, satellite antennas, scanners, printers, wireless devices, etc. I / O element 620 may provide a natural user interface (NUI) that processes gestures, sounds, or other interactive inputs generated by a user. For example, the input may be transmitted to an appropriate network element for further processing. NUI may be implemented to implement speech recognition, touch and stylus recognition, facial recognition, biometric recognition, gesture recognition on and near the screen, air gestures, head and eye tracking, touch recognition associated with a display on electronic device 600, or any combination thereof. Electronic device 500 may be equipped with a depth camera, such as a stereo camera system, an infrared camera system, an RGB camera system, or any combination thereof, to enable gesture detection and recognition. In addition, electronic device 600 may be equipped with an accelerometer or gyroscope to enable motion detection. The output of the accelerometer or gyroscope may be provided to the display of electronic device 600 to perform immersive augmented reality or virtual reality.

[0085] Furthermore, the processor 614 in the electronic device 600 may execute program code in the memory 612 to perform the actions and steps described above or otherwise described herein.

[0086] It should be understood that any particular order or hierarchy of steps in any disclosed process is an example of an example method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in a process can be rearranged while remaining within the scope of the present disclosure. The attached method claims present elements of the various steps in an example order and are not meant to be limited to the specific order or hierarchy presented.

[0087] The use of ordinal terms such as "first", "second", "third" and the like in the claims to modify claim elements does not in itself imply any priority, precedence or order of one claim element over another claim element or a temporal order of performing method actions, but serves merely as a label to distinguish one claim element with a particular name from another element with the same name (but using an ordinal term) to distinguish the claim elements.

[0088] Although the present disclosure has been described by way of example and according to preferred embodiments, it should be understood that the present disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A power saving method for a slave device, comprising: When the slave device enters a sleep mode, receiving a first switching request instructing to switch a clock source from a first clock to a second clock; Sending a first clock source signal to the register instructing to switch the clock source from the first clock to the second clock; as well as The clock source of the register is switched from the first clock to the second clock according to the first clock source signal.

2. The method according to claim 1, characterized in that Also includes: Check whether the SPMI bus is idle; as well as In response to the SPMI bus being idle, transmitting a first clock source signal to the register.

3. The method according to claim 2, characterized in that Also includes: In response to the SPMI bus being not idle, delaying sending the first clock source signal to the register until the SPMI bus is idle.

4. The method according to claim 1, characterized in that: Also includes: When the slave device enters the wake-up mode, receiving a second switching request instructing to switch a clock source from the second clock to the first clock; as well as A second clock source signal instructing to switch a clock source from the second clock to the first clock is transmitted to the register.

5. The method according to claim 4, characterized in that Also includes: The clock source of the register is switched from the second clock to the first clock according to the second clock source signal.

6. The method according to claim 1, characterized in that When the slave device is in the sleep mode, the slave device is timed by the second clock.

7. The method according to claim 1, characterized in that The slave device is an SPMI slave device.

8. The method according to claim 1, characterized in that: Also includes: An external device is allowed to access a register via the SPMI bus, wherein the register is clocked by a second clock when the slave device is in a sleep mode.

9. The method according to claim 7, characterized in that: The external device is an SPMI master device.

10. The method according to claim 1, characterized in that The first clock is a system clock, and the second clock is a system power management interface clock SCLK.

11. A power saving device, comprising: processor; register; as well as A dynamic clock source controller is coupled to the processor and the register, wherein the dynamic clock source controller is configured to: When the power saving device enters a sleep mode, receiving a first switching request instructing to switch a clock source from a first clock to a second clock; Sending a first clock source signal to the register instructing to switch a clock source from the first clock to the second clock; and The clock source of the register is switched from the first clock to the second clock according to the first clock source signal.

12. The power saving device according to claim 11, characterized in that: The dynamic clock source controller is also used for: Detecting whether the SPMI bus is idle; and In response to the SPMI bus being idle, transmitting the first clock source signal to the register.

13. The power saving device according to claim 12, characterized in that: The dynamic clock source controller is also used for: In response to the SPMI bus being not idle, delaying sending the first clock source signal to the register until the SPMI bus is idle.

14. The power saving device according to claim 11, characterized in that: The dynamic clock source controller is also used for: receiving a second switching request, instructing to switch a clock source from the second clock to the first clock when the power saving device enters a wake-up mode; as well as A second clock source signal instructing to switch a clock source from the second clock to the first clock is transmitted to the register.

15. The power saving device according to claim 14, characterized in that: The registers are also used for: According to the second clock source signal, the clock source is switched from the second clock to the first clock.

16. The power saving device according to claim 11, characterized in that: When the power saving device is in the sleep mode, the power saving device is clocked by the second clock.

17. The power saving device according to claim 11, wherein: The power saving device is a SPMI slave device.

18. The power saving device according to claim 11, characterized in that: The dynamic clock source controller is also used for: The external device is allowed to access the register via the SPMI bus, wherein the register is clocked by a second clock when the power saving device is in a sleep mode.

19. The power saving device according to claim 11, characterized in that: The first clock is a system clock, and the second clock is a system power management interface (SPMI) clock (SCLK).

20. A non-transitory computer-readable storage medium containing instructions that, when executed by a subsystem in a slave device, cause the slave device to perform a method for saving power, the method comprising: When the slave device enters a sleep mode, receiving a first switching request, the first switching request indicating switching a clock source from a system clock to a system power management interface (SPMI) clock (SCLK); Check whether the SPMI bus is idle; In response to the SPMI bus being idle, transmitting a first clock source signal indicating switching a clock source from a system clock to SCLK to the SPMI register; as well as The SPMI register switches the clock source from the system clock to SCLK according to the first clock source signal.

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