A comprehensive tool logic unit resource sharing optimization method, computer-readable storage medium, and electronic device

Abstract

An integrated tool logic unit resource sharing optimization method provided by the present invention includes traversing all logic units in the circuit, establishing a connection relationship graph G between the logic units and signals according to the input and output relationships between the logic units, and inserting all the logic units in the circuit into the logic unit set N for the next iteration; traversing all the logic units in the logic unit set N, for each logic unit c, calculating the hash value h of the logic unit c according to the parameters and port signals of the logic unit c, generating a key-value pair <c, h>, and inserting the key-value pair <c, h> into the mapping table M that hashes to the logic units; if the insertion is successful, continue to traverse the logic unit c in the logic unit set N and insert the key-value pair <c, h>; if the insertion fails, perform optimization processing on the logic unit c for which the key-value pair insertion fails, and update the connection relationship graph G.

Description

Technical Field

[0001] The present invention belongs to the technical field of logic synthesis tools for programmable logic devices, and particularly relates to an optimization method for sharing logic unit resources of a synthesis tool, a computer-readable storage medium, and an electronic device. Background Art

[0002] Logic synthesis is an important step in the FPGA EDA software design process. It converts a Verilog (a hardware description language, HDL) or VHDL circuit file at the behavioral level or register transfer level (RTL) input by a user (a hardware description language used to describe the hardware functions of an electronic system, VHSIC Hardware Description Language) into a netlist file composed of basic FPGA logic units such as look-up tables (Luts) and flip-flops (FFs). FPGA logic synthesis includes two stages: synthesis and mapping. Synthesis converts a circuit file at the behavioral level or RTL into a logic netlist composed of gate circuits; mapping maps the logic netlist composed of gate circuits into a netlist file composed of basic FPGA logic units.

[0003] Area, that is, the number of resources, is an important indicator of an FPGA logic synthesis tool. Reducing the number of resources after FPGA logic synthesis plays a very important role in improving the routing rate and timing performance of FPGA software. Resource sharing is a problem that a logic synthesis tool must handle. It combines logic units with the same input into one logic unit to achieve the purpose of resource sharing, thereby reducing the number of resources in the synthesis result. As the scale of the user circuit becomes larger and larger, the number of synthesized logic units is also very large, and performing complete resource sharing processing is a very time-consuming process. Therefore, quickly and accurately performing resource sharing and combining logic units with the same input is a technical problem. Summary of the Invention

[0004] The present invention provides an optimization method for sharing logic unit resources of a synthesis tool, a computer-readable storage medium, and an electronic device, which can accurately perform resource sharing, combine logic units with the same input, and improve the speed and efficiency of logic synthesis.

[0005] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0006] To achieve one or part or all of the above purposes or other purposes, an optimization method for sharing resources of integrated tool logic units provided by a technical solution of the present invention includes traversing all logic units in a circuit, establishing a connection relationship graph G between the logic units and signals according to the input and output relationships between the logic units, and inserting all the logic units in the circuit into the logic unit set N for the next iteration; traversing all the logic units in the logic unit set N, for each logic unit c, calculating the hash value h of the logic unit c according to the parameters and port signals of the logic unit c, and generating a key-value pair <c, h>, and inserting the key-value pair <c, h> into the mapping table M of the hash to the logic unit; if the insertion is successful, continue to traverse the logic unit c in the logic unit set N and insert the key-value pair <c, h>; if the insertion fails, find the equivalent logic unit c1 corresponding to the hash value h of the logic unit c where the insertion fails in the mapping table M of the hash to the logic unit; perform optimization processing on the logic unit c where the key-value pair insertion fails, and update the connection relationship graph G; insert the logic unit c2 corresponding to each output edge of the logic unit c where the insertion fails into the logic unit set N, and delete the logic unit c where the insertion fails in the current netlist and the logic unit set N. The beneficial effect of this technical solution is that logic units with the same input can be quickly merged into one logic unit to achieve the purpose of resource sharing, thereby reducing the resource quantity of the synthesis result of the application circuit and improving the performance of the application circuit.

[0007] If after deleting the logic unit c where the insertion fails in the current netlist and the set, when the number of logic units in the logic unit set N is greater than 0, continue to traverse the logic unit c in the logic unit set N and insert the key-value pair <c, h>; if the number of logic units in the logic unit set N is less than or equal to 0, exit the optimization.

[0008] Establishing a connection relationship graph G between the logic units and signals according to the input and output relationships between the logic units includes establishing a set T of logic unit types for resource sharing optimization; traversing all logic units c in the circuit, if the type of the logic unit c is in the set T of logic unit types, then traverse all port signals s of the logic unit c, if the port signal s is an input port signal, insert the port signal s into the input edge set of the logic unit c, and add the logic unit c to the output edge set of the port signal s; if the port signal s is not an input port signal, insert the port signal s into the output edge set of the logic unit c.

[0009] If the logic unit c in the set T of logic unit types has the keep attribute, do not process the logic unit c.

[0010] If the type of the logic unit c is not in the set T of logic unit types, continue to process the next logic unit c.

[0011] If all port signals s of logic unit c are processed, proceed to the processing of the next logic unit c; otherwise, continue to process the next port signal s of logic unit c.

[0012] The calculation of the hash value h of logic unit c includes checking whether there is a corresponding hash value for the current logic unit c in the mapping relationship set cache from logic units to hash values. If there is a hash value for the current logic unit c in the mapping relationship set cache, return the hash value of the current logic unit c and exit the calculation process; if there is no corresponding hash value, insert the type of logic unit c into the hash string hash_str; if the type of the logic unit c belongs to a binary operator, assign the signal with the smaller string to input A of the logic unit c and the signal with the larger string to input B of the logic unit c, and form a string by combining each port name and signal name of the logic unit c and insert it into the connection string set conn_str; if the type of the logic unit c does not belong to a binary operator, directly form a string by combining each port name and signal name of the logic unit c and insert it into the connection string set conn_str; sort the connection string set conn_str in ascending order of strings, insert each string in the sorted connection string set conn_str into the hash string hash_str, call the hash function to calculate the hash value h of the hash string hash_str, and return the calculated result.

[0013] When the key-value pair insertion fails, after finding the equivalent logic unit c1, perform optimization processing on the logic unit c where the key-value pair insertion fails and update the connection relationship graph G, including traversing each output port signal s of the logic unit c where the insertion fails, finding the signal s1 with the same port as the port signal s in the equivalent logic unit c1, and adding a connection edge from the port signal s to the port signal s1 in the current netlist; traversing each logic unit c2 corresponding to the output edge of the logic unit c where the insertion fails on the connection relationship graph G and inserting the logic unit c2 into the output edge set of the equivalent logic unit c1; traversing each logic unit c3 corresponding to the input edge of the logic unit c where the insertion fails on the connection relationship graph G and deleting the logic unit c where the insertion fails from the output edge set of the logic unit c3.

[0014] A computer-readable storage medium provided by another technical solution of the present invention stores program code, and the program code is called by a processor to execute the above-mentioned integrated tool logic unit resource sharing optimization method.

[0015] An electronic device provided by another technical solution of the present invention includes one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the comprehensive tool logic unit resource sharing optimization method described above.

[0016] Compared with the prior art, the beneficial effects of the present invention mainly include identifying logic units with the same input more quickly and comprehensively in an iterative manner, and merging them into one logic unit, so as to achieve the purpose of resource sharing.

[0017] To make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic flow chart of the logic unit resource sharing method of the present invention.

[0020] Figure 2 It is a schematic flow chart of establishing the connection relationship between the logic unit and the signal of the present invention.

[0021] Figure 3 It is a schematic flow chart of calculating the hash value of the logic unit of the present invention.

[0022] Figure 4 It is a schematic flow chart of processing the logic unit to be optimized and updating the connection relationship graph G of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0024] Embodiment 1 provides a comprehensive tool logic unit resource sharing optimization method. For the comprehensive tool logic unit resource sharing optimization method in Embodiment 1, refer to Figure 1, this method first traverses all the logic units c in the circuit, and based on the input-output relationships between the logic units c, establishes a connection relationship graph G between the logic units c and the signals; then inserts all the logic units c in the circuit into the logic unit set N for the next iteration, and then executes an iterative optimization process. In each iteration, a logic unit c is taken out from the set N. First, according to the parameters and port signals of c, the hash value h of the logic unit c is calculated; then a key-value pair is generated. Above, a connection relationship graph G between the logic unit and the signal is established. For the flowchart of this process, see Figure 2 , the specific steps are as follows:

[0025] S11: Establish a set T of logic unit types for resource sharing optimization.

[0026] S12: Traverse all the logic units c in the circuit. For each logic unit c, execute S13.

[0027] S13: If the type of the logic unit c is in the set T of logic unit types, then execute S14; otherwise, proceed to the processing of the next logic unit c.

[0028] S14: If the logic unit c has a keep attribute, where the keep attribute means that this logic unit needs to be retained and cannot be simplified, so this logic unit c does not need to be optimized, and start the processing of the next logic unit c; otherwise, execute S15.

[0029] S15: Traverse all the port signals of the logic unit c. For each port signal s, execute S16.

[0030] S16: If the port signal s is a signal of the input port, then insert the port signal s into the input edge set of the logic unit c, and add the logic unit c to the output edge set of the port signal s;

[0031] If the port signal s is not a signal of the input port, then insert the port signal s into the output edge set of the logic unit c.

[0032] S17: If all the ports of the logic unit c have been processed, then proceed to the processing of the next logic unit c; otherwise, continue to process the next port signal s of c.

[0033] For the calculation of the hash value h of the logic unit c in Embodiment 1, see Figure 3 the flowchart. The calculation of the hash value h is based on all the parameters and port signals of the logic unit c. Calculating the hash value h of the logic unit c is the basis for judging whether two logic units are equivalent, because two logic units with the same hash value are equivalent. The specific steps are as follows:

[0034] S21: Check if there is a corresponding hash value for the current logic unit c in the hash set cache, where cache is a set of mapping relationships from logic units to hash values.

[0035] S22: If there is a corresponding hash value for the logic unit c in the hash set cache, return the value of the logic unit c in cache (directly output the hash value of the logic unit c, combine key-value pairs), and exit the hash value calculation step; otherwise, execute step S23.

[0036] S23: Insert the type of the logic unit c into the hash string hash_str.

[0037] S24: Determine whether the type of c belongs to one of the binary operators such as and (AND operation), or (OR operation), xor (XOR operation), add (addition operation), logic_and (logical AND), logic_or (logical OR) (operators that perform operations with two operands). If so, execute step S25; otherwise, execute step S26.

[0038] S25: Compare the signals at ports A and B of the logic unit c, assign the signal with the smaller string to the input A end of the logic unit c, and assign the larger signal to the input B end of the logic unit c.

[0039] S26: Traverse each port signal of the logic unit c, form a string by combining each port name and signal name, and insert it into the connection string set conn_str.

[0040] S27: Sort the connection string set conn_str in ascending order of strings.

[0041] S28: Insert each string in the sorted connection string set conn_str into the hash string hash_str.

[0042] S29: Call the hash function to calculate the hash value h of the hash string hash_str, and return h.

[0043] For the optimization process of the logic unit c with insertion failure and the update of the connection relationship graph G, see Figure 4 the flowchart as follows:

[0044] S31: Traverse each output port signal s of the logic unit c with insertion failure, and execute S32.

[0045] S32: Find the signal s1 at the same port as the output port signal s in the equivalent logic unit c1.

[0046] S33: Add an edge connecting the output port signal s to the output port signal s1 in the current netlist.

[0047] S34: Traverse each logical unit c2 corresponding to the output edge of the logical unit c where the insertion fails in the connection relationship graph G, and execute S35.

[0048] S35: Insert the logical unit c2 into the output edge set of the equivalent logical unit c1.

[0049] S36: Traverse each logical unit c3 corresponding to the input edge of the logical unit c where the insertion fails in the connection relationship graph G, and execute S37.

[0050] S37: Delete the logical unit c where the insertion fails from the output edge set of the logical unit c3.

[0051] Embodiment 2 provides a computer-readable storage medium storing program code, which is called by a processor to execute the integrated tool logical unit resource sharing optimization method mentioned in Embodiment 1. By storing the program for implementing the integrated tool logical unit resource sharing optimization method in the computer-readable storage medium and calling and executing it by the processor, the execution efficiency of the integrated tool logical unit resource sharing optimization method can be effectively improved, and at the same time, it is ensured that there will be no errors in each execution.

[0052] Embodiment 3 provides an electronic device, which includes one or more processors, including a memory; and one or more application programs, where the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more application programs are configured to execute the integrated tool logical unit resource sharing optimization method in Embodiment 1.

[0053] The above has introduced in detail an integrated tool logical unit resource sharing optimization method, a computer-readable storage medium, and an electronic device provided by the present invention. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of the protection of the claims of the present invention.

Claims

1. A method for optimizing resource sharing of logic units of a synthesis tool, characterized in that: Including, traversing all logic units in the circuit, establishing a connection relationship graph G between logic units and signals according to the input and output relationship between the logic units, and inserting all logic units in the circuit into the logic unit set N of the next iteration; Traverse all logic units in the logic unit set N, for each logic unit c, calculate the hash value h of the logic unit c according to the parameters and port signals of the logic unit c, and generate a key-value pair 〈c, h〉, and insert the key-value pair 〈c, h〉 into the hash-to-logic unit mapping table M; If the insertion is successful, continue to traverse the logical unit c in the logical unit set N and insert the key-value pair 〈c, h〉; If the insertion fails, then find the equivalent logical unit c1 corresponding to the hash value h of the logical unit c where the insertion failed in the mapping table M from hash to logical unit; Optimizing the logic unit c where the key-value pair fails to be inserted, and updating the connection relationship graph G, including traversing each output port signal s of the logic unit c where the insertion fails, finding the signal s1 of the same port as the port signal s in the equivalent logic unit c1, and adding a connection edge from the port signal s to the port signal s1 in the current netlist; traversing the logic unit c2 corresponding to each output edge of the logic unit c where the insertion fails on the connection relationship graph G, and inserting the logic unit c2 into the output edge set of the equivalent logic unit c1; traversing the logic unit c3 corresponding to each input edge of the logic unit c where the insertion fails on the connection relationship graph G, and deleting the logic unit c where the insertion fails from the output edge set of the logic unit c3; The logic cell c2 corresponding to each output edge of the logic cell c that failed to be inserted is inserted into the logic cell set N, and the logic cell c that failed to be inserted is deleted from the current netlist and the logic cell set N.

2. A method for optimizing resource sharing of logic units of a synthesis tool according to claim 1, characterized in that: If the number of logic units in the logic unit set N is greater than 0 after deleting the logic unit c that failed to be inserted in the current netlist and set, then continue to traverse the logic unit c in the logic unit set N and insert the key-value pair 〈c, h〉; If the number of logic units in the logic unit set N is less than or equal to 0, the optimization is exited.

3. The method for optimizing resource sharing of logic units of a synthesis tool according to claim 1, characterized in that: According to the input and output relationships between the logic units, a connection relationship diagram G between the logic units and the signals is established, including establishing a resource sharing optimized logic unit type set T; Traverse all logic cells c in the circuit. If the type of logic cell c is in the logic cell type set T, traverse all port signals s of logic cell c. If port signal s is an input port signal, insert the port signal s into the input edge set of logic cell c, and add logic cell c to the output edge set of port signal s. If the port signal s is not an input port signal, the port signal s is inserted into the output edge set of the logic unit c.

4. A method for optimizing resource sharing of logic units of a synthesis tool according to claim 3, characterized in that: If the logical unit c in the logical unit type set T has the keep attribute, the logical unit c is not processed.

5. The method for optimizing resource sharing of logic units of a synthesis tool according to claim 3, characterized in that: If the type of the logic unit c is not in the logic unit type set T, the processing continues with the next logic unit c.

6. The method for optimizing resource sharing of logic units of a synthesis tool according to claim 1, characterized in that: If all port signals s of the logic unit c have been processed, the process proceeds to the next logic unit c; otherwise, the process continues to process the next port signal s of the logic unit c.

7. The method for optimizing resource sharing of logic units of a synthesis tool according to claim 1, characterized in that: The calculation of the hash value h of the logic unit c includes searching whether the current logic unit c has a corresponding hash value in the mapping relationship set cache of logic units to hash values. If the current logic unit c has a hash value in the mapping relationship set cache, the hash value of the current logic unit c is returned, and the calculation process is exited; If there is no corresponding hash value, the type of the logical unit c is inserted into the hash string hash_str; If the type of the logic unit c is a binary operator, the signal with a smaller string is assigned to the input A terminal of the logic unit c, and the larger signal is assigned to the input B terminal of the logic unit c, and each port name and signal name of the logic unit c is combined into a string and inserted into the string set conn_str; If the type of the logic unit c does not belong to a binary operator, directly combine each port name and signal name of the logic unit c into a string and insert it into the connection string set conn_str; The connection string set conn_str is sorted in ascending order, each string in the sorted connection string set conn_str is inserted into the hash string hash_str, a hash function is called to calculate a hash value h of the hash string hash_str, and the calculated result is returned.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the synthesis tool logic unit resource sharing optimization method as described in any one of claims 1-7.

9. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the synthesis tool logic unit resource sharing optimization method as described in any one of claims 1-7.

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