Quantum circuit processing method and device, computer, storage medium and program product

Abstract

The embodiment of the invention discloses a quantum circuit processing method and device, a computer, a storage medium and a program product, and the method comprises the steps: obtaining a to-be-analyzed quantum program, carrying out the quantum circuit analysis of the to-be-analyzed quantum program, and obtaining the circuit information of the to-be-analyzed quantum program; the circuit information comprises N quantum circuits and quantum gates included by the N quantum circuits; n is a positive integer; based on a gate dependency relationship among quantum gates included in the N quantum circuits, gate alignment processing is carried out on the quantum gates included in the N quantum circuits, and aligned quantum gate arrangement circuit data is obtained; and generating a quantum processing instruction according to the quantum gate arrangement line data. By adopting the quantum gate processing method and device, the accuracy and efficiency of quantum circuit processing can be improved, and the convenience of quantum gate processing is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a quantum circuit processing method, device, computer, storage medium and program product. Background Art

[0002] Superconducting quantum chips are currently in the noisy intermediate-scale quantum (NISQ) era, with the following characteristics: qubit coherence time is limited, qubit gates have errors (limited fidelity), and qubit measurement operations introduce systematic errors. Among them, superconducting quantum computing is realized by running quantum circuits on superconducting quantum chips. The circuits usually contain many single-qubit gates and double-qubit gates. Based on this, it is necessary to perform timing control on quantum circuits. At present, the timing control of quantum circuits is performed by users manually inputting a large number of restrictions, resulting in low efficiency in quantum circuit processing and complex quantum gate processing. Moreover, in the current timing control of quantum circuits, the rules for aligning quantum gates are restricted, resulting in poor flexibility of quantum circuits. Summary of the invention

[0003] The embodiments of the present application provide a quantum circuit processing method, device, computer, storage medium and program product, which can improve the accuracy and efficiency of quantum circuit processing and improve the convenience of quantum gate processing.

[0004] On the one hand, an embodiment of the present application provides a quantum circuit processing method, the method comprising:

[0005] Obtaining a quantum program to be analyzed, performing quantum circuit analysis on the quantum program to be analyzed, and obtaining circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer;

[0006] Based on the gate dependency relationship between the quantum gates included in the N quantum circuits, gate alignment processing is performed on the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data;

[0007] A quantum processing instruction is generated according to quantum gate arrangement circuit data; the quantum gates included in the N quantum circuits have a first execution timing in the quantum processing instruction that is different from a second execution timing in the quantum program to be analyzed.

[0008] On the one hand, an embodiment of the present application provides a quantum circuit processing device, which includes:

[0009] A program acquisition module is used to obtain the quantum program to be analyzed;

[0010] A program analysis module is used to perform quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer;

[0011] A quantum arrangement module, used to perform gate alignment processing on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits, and obtain aligned quantum gate arrangement circuit data;

[0012] The instruction generation module is used to generate quantum processing instructions according to quantum gate arrangement circuit data; the quantum gates included in the N quantum circuits have a first execution timing in the quantum processing instructions that is different from a second execution timing in the quantum program to be analyzed.

[0013] Among them, the program parsing module includes:

[0014] A language parsing unit, used to obtain the program language type of the quantum program to be parsed;

[0015] A key acquisition unit, used to acquire quantum keywords corresponding to the programming language type;

[0016] A code recognition unit is used to recognize a quantum code segment in a quantum program to be parsed based on quantum keywords; the quantum code segment includes M code statements; M is a positive integer;

[0017] The circuit analysis unit is used to perform quantum circuit analysis on the M code statements based on the statement sequence of the M code statements to obtain circuit information included in the quantum program to be analyzed; the circuit information is used to characterize the quantum circuit indicated by the M code statements.

[0018] Among them, the program parsing module includes:

[0019] A model parsing unit, used for inputting the quantum program to be parsed into the program parsing model for parsing, and determining the type of program language corresponding to the quantum program to be parsed;

[0020] A statement detection unit is used to detect the code statements included in the quantum program to be parsed based on the program language type in the program parsing model, and obtain the quantum gate processing statements in the code statements included in the quantum program to be parsed;

[0021] The information acquisition unit is used to perform quantum circuit analysis on the quantum gate processing statement based on the statement sequence of the quantum gate processing statement to obtain circuit information included in the quantum program to be analyzed; the circuit information is used to characterize the quantum circuit indicated by the quantum gate processing statement.

[0022] The device further comprises:

[0023] A directed construction module is used to use the quantum gates included in the N quantum circuits as nodes, determine the edges between the quantum gates included in the N quantum circuits based on circuit information, and construct the nodes and edges into a quantum directed graph model; the quantum directed graph model is used to indicate the gate dependency relationship between the quantum gates included in the N quantum circuits;

[0024] The quantum arrangement module is specifically used for:

[0025] Based on the quantum directed graph model, gate alignment is performed on the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data.

[0026] The quantum arrangement module includes:

[0027] A first arrangement unit is used to use the timing position corresponding to the first quantum gate among the quantum gates included in the N quantum circuits as the first reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, perform gate alignment processing on the quantum gates included in the N quantum circuits to the first reference timing position to obtain aligned quantum gate arrangement circuit data; the first quantum gate refers to the first processed quantum gate indicated by the circuit information; or,

[0028] The second arrangement unit is used to use the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits as the second reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, perform gate alignment processing on the quantum gates included in the N quantum circuits to the second reference timing position to obtain aligned quantum gate arrangement circuit data; the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

[0029] The quantum arrangement module includes:

[0030] A coherent analysis unit, used to obtain the bit coherence time of the quantum gates included in the N quantum circuits, and obtain the longest processing time corresponding to the N quantum circuits;

[0031] The second arrangement unit is further used for, if the bit coherence time is less than the longest processing time, taking the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits as the second reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, performing gate alignment processing on the quantum gates included in the N quantum circuits to the second reference timing position to obtain aligned quantum gate arrangement circuit data; the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

[0032] The quantum arrangement module includes:

[0033] A measurement acquisition unit, used to acquire M quantum measurement gates included in N quantum circuits; M is a positive integer; each quantum circuit does not include a quantum measurement gate or includes at least one quantum measurement gate;

[0034] The third arrangement unit is used to maintain the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits, align the M quantum measurement gates, and obtain the aligned quantum gate arrangement circuit data; the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame; the quantum bit gate refers to the quantum gate included in the N quantum circuits, except the M quantum measurement gates; the time frame is used to represent the execution order of the quantum gates included in the N quantum circuits.

[0035] The quantum arrangement module includes:

[0036] The measurement acquisition unit is also used to acquire M quantum measurement gates included in the N quantum circuits; M is a positive integer; each quantum circuit does not include a quantum measurement gate or includes at least one quantum measurement gate;

[0037] An initial arrangement unit is used to maintain the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits, align the M quantum measurement gates, and obtain measurement alignment data; the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame;

[0038] The fourth arrangement unit is used to keep the M quantum measurement gates in the same time frame in the measurement alignment data based on the gate dependency between the quantum gates included in the N quantum circuits, align the quantum bit gates, and obtain the aligned quantum gate arrangement circuit data.

[0039] The quantum arrangement module includes:

[0040] An optimization determination unit, used to obtain circuit operation data of the quantum circuit corresponding to the quantum program to be analyzed, and determine the circuit optimization direction of the quantum circuit based on the circuit operation data;

[0041] The gate arrangement unit is used to obtain the target quantum gate alignment method corresponding to the circuit optimization direction. Based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the target quantum gate alignment method is used to perform gate alignment processing on the quantum gates included in the N quantum circuits to obtain the aligned quantum gate arrangement circuit data.

[0042] The instruction generation module includes:

[0043] The gate analysis unit is used to obtain the P quantum gates included in the quantum gate arrangement circuit data, and the quantum circuit corresponding to each quantum gate; P is a positive integer;

[0044] The instruction generation unit is used to generate quantum processing instructions for the P quantum gates based on the target time frames where the P quantum gates are located in the quantum gate arrangement circuit data and the quantum circuit corresponding to each quantum gate.

[0045] The device further comprises:

[0046] An instruction execution module is used to execute quantum processing instructions, measure and process the quantum program to be analyzed, and obtain quantum information of the quantum corresponding to the quantum program to be analyzed;

[0047] Quantum application module, used to apply quantum using quantum information.

[0048] On the one hand, an embodiment of the present application provides a computer device, including a processor, a memory, and an input and output interface;

[0049] The processor is connected to the memory and the input / output interface respectively, wherein the input / output interface is used to receive and output data, the memory is used to store a computer program, and the processor is used to call the computer program so that a computer device including the processor executes the quantum circuit processing method in one aspect of an embodiment of the present application.

[0050] On the one hand, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program, and the computer program is suitable for being loaded and executed by a processor, so that a computer device having the processor executes the quantum circuit processing method in one aspect of the embodiment of the present application.

[0051] In one aspect, an embodiment of the present application provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in various optional ways in one aspect of the embodiment of the present application. In other words, when the computer instruction is executed by the processor, the method provided in various optional ways in one aspect of the embodiment of the present application is implemented.

[0052] Implementing the embodiments of the present application will have the following beneficial effects:

[0053] In the embodiment of the present application, a quantum program to be analyzed is obtained, and quantum circuit analysis is performed on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer; based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate aligned to obtain the aligned quantum gate arrangement circuit data; according to the quantum gate arrangement circuit data, quantum processing instructions are generated. Through the above process, the quantum circuit can be directly analyzed, that is, the quantum program to be analyzed corresponding to the quantum circuit, so that the automatic analysis of the quantum circuit can be realized, and based on the obtained quantum circuit, the alignment processing of each quantum gate is realized, and the timing control of the quantum gate is realized to suppress the noise influence caused by the characteristics of the quantum and improve the accuracy of the quantum calculation results. Moreover, according to the semantics of the input quantum program to be analyzed (i.e., circuit information), the gate dependency relationship of the quantum gate is independently modeled to improve the efficiency and accuracy of quantum circuit processing, and improve the convenience and flexibility of quantum gate processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 This is a network interaction architecture diagram for quantum circuit processing provided by an embodiment of the present application;

[0056] Figure 2 This is a schematic diagram of a quantum circuit processing scenario provided by an embodiment of the present application;

[0057] Figure 3 is a flow chart of a method for quantum circuit processing provided by an embodiment of the present application;

[0058] Figure 4 It is a schematic diagram of a program parsing process provided by an embodiment of the present application;

[0059] Figure 5 It is a schematic diagram of a circuit analysis scenario provided by an embodiment of the present application;

[0060] Figure 6 It is a schematic diagram of a directed graph construction scenario provided in an embodiment of the present application;

[0061] Figure 7 This is a schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. Figure 1 ;

[0062] Figure 8 This is a schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. Figure 2 ;

[0063] Fig. 9 This is a schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. Figure 3 ;

[0064] Fig.10 This is a schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. Figure 4 ;

[0065] Fig.11 This is a simplified flowchart of quantum analysis provided by an embodiment of the present application;

[0066] Fig.12 is a schematic diagram of a quantum circuit processing device provided in an embodiment of the present application;

[0067] Fig.13 It is a structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0069] Among them, if it is necessary to collect object (such as user, etc.) data in this application, a prompt interface or pop-up window will be displayed before and during the collection. The prompt interface or pop-up window is used to prompt the user that certain data is currently being collected, such as quantum programs to be parsed, etc. Only after the user confirms the prompt interface or pop-up window, the relevant steps of data acquisition are started, otherwise the process ends. Moreover, the acquired user data will be used in reasonable and legal scenarios or purposes. Optionally, in some scenarios where user data needs to be used but is not authorized by the user, authorization can be requested from the user, and the user data can be used when the authorization is passed.

[0070] In the examples of this application, see Figure 1 , Figure 1 is a network interaction architecture diagram of quantum circuit processing provided by an embodiment of the present application, such as Figure 1As shown, the computer device 101 can obtain the quantum program to be analyzed, perform quantum circuit analysis on the quantum program to be analyzed, model the quantum circuit corresponding to the quantum program to be analyzed, obtain quantum gate arrangement circuit data, and realize the timing control of the quantum circuit. Moreover, this process realizes the independent modeling of the quantum circuit, can adapt to different quantum languages, and can improve the flexibility of timing control. Then, the quantum gate arrangement circuit data is converted into a quantum processing instruction, which refers to an instruction at the physical level, wherein the quantum gates included in the N quantum circuits, the first execution timing in the quantum processing instruction is different from the second execution timing in the quantum program to be analyzed, and the timing arrangement of the quantum circuit is realized, the flexibility of quantum circuit management is improved, and the convenience and efficiency of quantum gate processing are improved. Optionally, the computer device 101 can obtain the quantum program to be analyzed from the local storage space; or, the quantum program to be analyzed can be obtained from any business device, such as business device 102a, business device 102b or business device 102c. For example, the computer device 101 can receive a quantum analysis request sent by the business device 102a, obtain the quantum program to be analyzed carried by the quantum analysis request, perform quantum circuit analysis on the quantum program to be analyzed, and perform quantum modeling based on the analysis results and the gate dependency relationship between quantum gates indicated by the quantum program to be analyzed, obtain quantum gate arrangement circuit data, convert the quantum gate arrangement circuit data into quantum processing instructions; and send the quantum processing instructions to the business device 102a, etc.

[0071] It is understandable that the business equipment mentioned in the embodiments of the present application can also be considered as a computer device, and the computer equipment in the embodiments of the present application includes but is not limited to terminal equipment or servers. In other words, the computer device can be a server or a terminal device, or it can be a system composed of a server and a terminal device. Among them, the terminal device mentioned above can be an electronic device, including but not limited to mobile phones, tablet computers, desktop computers, laptop computers, PDAs, vehicle-mounted equipment, augmented reality / virtual reality (Augmented Reality / Virtual Reality, AR / VR) equipment, helmet displays, smart TVs, wearable devices, smart speakers, digital cameras, cameras and other mobile Internet devices (mobile internet device, MID) with network access capabilities, or terminal devices in scenarios such as trains, ships, and flights. Such as Figure 1 As shown in , the terminal device may be a laptop computer (as shown in the business device 102b), a mobile phone (as shown in the business device 102c) or a business device (as shown in the object device 102a), etc. Figure 1Only some of the devices are listed. Optionally, the business device 102a refers to a device located in the vehicle 103. The server mentioned above can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, vehicle-road collaboration, content delivery networks (Content Delivery Network, CDN), and big data and artificial intelligence platforms. The computer device can be the above-mentioned terminal device or server, connected to the quantum circuit, or integrated with the quantum circuit; or the computer device can be a quantum device carrying quantum, such as a quantum chip.

[0072] For details, see Figure 2 , Figure 2 Schematic diagram of a quantum circuit processing scenario provided by an embodiment of the present application. Figure 2 As shown, the computer device can obtain the quantum program 201 to be analyzed, perform quantum circuit analysis on the quantum program to be analyzed, and obtain circuit information included in the quantum program 201 to be analyzed. The circuit information is used to represent relevant information of the quantum circuit 202 corresponding to the quantum program 201 to be analyzed, such as the N quantum circuits included in the quantum circuit 202, and the quantum gates 203 included in the N quantum circuits, etc. The circuit information is used to represent the quantum semantics of the quantum program 201 to be analyzed, that is, the composition information of the quantum circuit, etc. Furthermore, based on the gate dependency relationship between the quantum gates 203 included in the N quantum circuits, gate alignment processing can be performed on the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data 204, which is equivalent to realizing independent modeling of the quantum circuit 202 according to the quantum semantics of the quantum program 201 to be analyzed, so that the quantum gate arrangement circuit data 204 obtained by modeling not only conforms to the gate dependency relationship between the quantum gates 203 included in the N quantum circuits, but also realizes the timing control of the quantum gates 203 included in the N quantum circuits, that is, gate alignment processing, so that the process is equivalent to an independent module, which can be compatible with different quantum languages ​​and improve the flexibility and convenience of quantum gate processing. Furthermore, the quantum gate arrangement circuit data 204 can be converted into a quantum processing instruction 205. The first execution sequence of the quantum gates included in the N quantum circuits in the quantum processing instruction is different from the second execution sequence in the quantum program to be analyzed. The first execution sequence and the second execution sequence are both used to represent the execution order of the quantum gates included in the N quantum circuits, thereby realizing seamless expansion and translation of the model, realizing timing control and realization of the quantum circuit 202, and improving the accuracy and efficiency of quantum circuit processing.

[0073] Further, the key words involved in this application are explained as follows:

[0074] Quantum Circuit: An abstract concept that represents the circuit for operating quantum bits in a quantum computer, including the representation of quantum bit units, circuits (timelines), and the operations of various quantum logic gates. Finally, quantum measurements are usually required to read the results.

[0075] Quantum bit: a unit of measurement in quantum information science. Traditional computers use 0 and 1, and quantum computers also use 0 and 1 to represent information, but the difference is that a quantum bit can be 0 and 1 at the same time. This effect is called quantum superposition, which is also a unique feature of quantum computers.

[0076] Quantum gate: The quantum gate in this application is slightly different from the conventional quantum gate. The quantum gate in this application includes quantum bit gate and quantum measurement gate. For the sake of uniformity, quantum bit gate and quantum measurement gate are collectively referred to as quantum gate.

[0077] Among them, the qubit gate is a basic quantum circuit in quantum computing that operates a small number of qubits. Unlike traditional logic gates, quantum gates are reversible and can be represented by a unitary matrix, where the unitary matrix represents that the Hermitian conjugate matrix is ​​equal to the inverse matrix. Among them, quantum gates include but are not limited to Hadamard gates, quantum NOT (Pauli-X) gates, quantum rotation Y (Pauli-Y) gates, quantum rotation Z (Pauli-Z) gates, quantum swap (SWAP) gates, and controlled NOT (CNOT) gates.

[0078] Single-bit gate, two-bit gate, multi-bit gate: refers to the logic gates acting on a single quantum bit, two quantum bits, and multiple quantum bits, respectively. Among them, the single-bit gate may include but is not limited to the Hadamard gate, Pauli-X gate, Pauli-Y gate, and Pauli-Z gate, etc., which can be recorded as h gates; the two-bit gate may include but is not limited to the SWAP gate and CNOT, etc., which can be recorded as cx gates; the multi-bit gate may include but is not limited to the quantum Fredkin (CSWAP) gate, etc., which can be called CCNOT gate or ccx gate.

[0079] Quantum Language: Quantum language is a research direction of quantum computing. Its fields include building a set of standard assembly instruction sets based on the logic gate capabilities of quantum computers, and can continue to abstractly build more advanced computer languages. It can even mix the fields of classical computer languages ​​to create hybrid languages.

[0080] Decoherence: The full name is quantum decoherence, also known as decoherence, which is the effect that the quantum coherence of an open quantum system in quantum mechanics is gradually lost over time due to quantum entanglement with the external environment. Decoherence will cause the interference phenomenon between quantum states to disappear, and the quantum behavior of the system will be transformed into classical behavior.

[0081] Optionally, the data involved in the embodiments of the present application can be stored in a computer device, or the data can be stored based on cloud storage technology or a blockchain network, etc., which is not limited here.

[0082] For further information, see Figure 3 , Figure 3 This is a flow chart of a method for quantum circuit processing provided by an embodiment of the present application. Figure 3 As shown, the quantum circuit processing process includes the following steps:

[0083] Step S301, obtaining a quantum program to be analyzed, performing quantum circuit analysis on the quantum program to be analyzed, and obtaining circuit information included in the quantum program to be analyzed.

[0084] In an embodiment of the present application, a computer device can obtain a quantum program to be parsed, wherein each quantum program has its corresponding quantum language, and the grammatical rules of the quantum language are usually expressed in the form of a standard Extended Backus-Naur Form (EBNF), that is, a meta-grammar describing a context-free method of a computer programming language and a formal language. Wherein, the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer; each quantum gate is located in one or at least two quantum circuits, for example, a single-bit gate is located in one quantum circuit, a two-bit gate is located in two quantum circuits, and a multi-bit gate is located in two or more quantum circuits. Optionally, a multi-bit gate refers to a logic gate that acts on multiple quantum bits, which can be two or more (in this case, the multi-bit gate can be considered to include a two-bit gate), or three or more, which can be specifically defined based on needs. Wherein, the circuit information is used to represent the relevant information of the quantum circuit corresponding to the quantum program to be parsed, and is used to represent the initial time frame corresponding to the quantum gates included in the N quantum circuits in the quantum program to be parsed, etc., which is equivalent to the circuit expression of the quantum program to be parsed. Among them, the time frame is only used to indicate the processing order of the corresponding quantum gates, and is not used to indicate the processing duration of the corresponding quantum gates. That is, the duration between two different adjacent time frames may be different. For example, the duration from time frame 1 to time frame 2 may be the same as or different from the duration from time frame 2 to time frame 3.

[0085] Specifically, a program parsing method can be found in Figure 4 , Figure 4This is a schematic diagram of a program parsing process provided by an embodiment of the present application. Figure 4 As shown, the computer device can perform lexical analysis on the quantum program to be parsed to obtain quantum keywords in the quantum program to be parsed; perform syntax analysis on the quantum program to be parsed based on the quantum keywords to obtain circuit information included in the quantum circuit to be parsed. Optionally, the lexical analysis can be performed by a lexical analyzer, and the syntax analysis can be performed by a syntax analyzer, wherein the lexical analyzer and the syntax analyzer can be pre-built.

[0086] Optionally, the program language type of the quantum program to be parsed can be obtained, and the quantum keywords corresponding to the program language type can be obtained, wherein the quantum keywords can include gate processing keywords, and optionally, the quantum keywords can also include gate definition keywords, wherein the gate processing keywords are used to indicate the execution of the quantum gate, and the gate definition keywords are used to initialize the quantum gate. In other words, only the relevant code statements for indicating the execution of the quantum gate can be obtained, and on this basis, the code statements for initializing the quantum gate can also be obtained. For example, assuming that the program language type is an open quantum assembly language (openquantum assembly language, openQASM) type, the quantum keywords corresponding to the open quantum assembly language type can be obtained, and the quantum keywords can include gate processing keywords such as "h", "cx" and "measz", and optionally, the quantum keywords can also include gate definition keywords such as "qreg" and "creg". Further, the quantum code segment in the quantum program to be parsed can be identified based on the quantum keywords; the quantum code segment includes M code statements; M is a positive integer, for example, assuming that the quantum code segment is obtained:

[0087] qreg q[4]; / / indicates the definition of 4 quantum bits;

[0088] creg c[4]; / / represents the classical bit used to store the measurement result;

[0089] hq[1]; / / single-bit gate in quantum circuit q1;

[0090] cx q[1], q[2]; / / Two-bit gate located in quantum circuit q1 and quantum circuit q2;

[0091] cx q[0], q[1]; / / Two-bit gate located at quantum circuit q0 and quantum circuit q1;

[0092] hq[3]; / / single-bit gate in quantum circuit q3;

[0093] hq[0]; / / single-bit gate located in quantum circuit q0;

[0094] measz q[0]—>c[0]; / / Measure quantum circuit q0 and store the measurement result in c[0];

[0095] measz q[1]—>c[1]; / / Measure quantum circuit q1 and store the measurement result in c[1];

[0096] hq[2]; / / single-bit gate located in quantum circuit q2;

[0097] measz q[2]—>c[2]; / / Measure quantum circuit q2 and store the measurement result in c[2];

[0098] …

[0099] Since the program code is generally executed one code statement at a time, it can be considered that each of the above code statements corresponds to an initial time frame. Furthermore, based on the statement order of the M code statements, the M code statements can be subjected to quantum circuit analysis to obtain the circuit information included in the quantum program to be analyzed; the circuit information is used to characterize the quantum circuit indicated by the M code statements. For details, see Figure 5 , Figure 5 Schematic diagram of a circuit analysis scenario provided by an embodiment of the present application. Figure 5 As shown, quantum circuit analysis is performed on the quantum program 501 to be analyzed to obtain circuit information 502 included in the quantum program to be analyzed. Taking the above quantum code segment as an example, quantum circuit analysis is performed on M code statements to obtain circuit information 502 for visually expressing the quantum program to be analyzed. Specifically, from the code statement "qreg q[4]", it can be obtained that there are quantum circuits q0, quantum circuits q1, quantum circuits q2 and quantum circuits q3 in the quantum circuit, that is, taking N as 4 as an example, and the quantum gates included in the N quantum circuits are determined in sequence, such as quantum gate 50a located in quantum circuit q1, quantum gate 50b located in quantum circuit q1 and quantum circuit q2, quantum gate 50c located in quantum circuit q0 and quantum circuit q1, quantum gate 50d located in quantum circuit q3, quantum gate 50e located in quantum circuit q0, quantum gate 50f located in quantum circuit q0, quantum gate 50g located in quantum circuit q1, quantum gate 50h located in quantum circuit q2, and quantum gate 50i located in quantum circuit q2, etc. Among them, Figure 5 For example, the quantum gates included in the N quantum circuits include single-bit gates 5021 (such as quantum gates 50a and 50e), two-bit gates 5022 (such as quantum gates 50b and 50c), and quantum measurement gates 5023 (such as quantum gates 50f and 50g). Figure 5Some of the quantum gates in each quantum gate shown in . Optionally, the quantum gates included in the N quantum circuits may also include multi-bit gates located in at least three quantum circuits, etc., and single-bit gates and two-bit gates are used as examples for description here. The processing method of multi-bit gates can refer to the two-bit gate. Among them, since the two-bit gate and the multi-bit gate are located in multiple quantum circuits at the same time, the realization of a quantum circuit may depend on the situation of other quantum circuits, that is, the quantum gates included in the N quantum circuits cannot be directly controlled in timing, and step S302 can be executed.

[0100] Optionally, in a program parsing method, a computer device may input a quantum program to be parsed into a program parsing model for parsing, and determine the type of program language corresponding to the quantum program to be parsed. The program parsing model refers to a trained model that can parse code statements for processing quantum gates in a quantum program. Furthermore, in the program parsing model, the code statements included in the quantum program to be parsed are detected based on the type of program language, and quantum gate processing statements in the code statements included in the quantum program to be parsed are obtained. That is to say, the quantum gate processing statements can be directly obtained, and the number of the quantum gate processing statements is one or at least two. When there are at least two quantum gate processing statements, the at least two quantum gate processing statements may not be continuous in the quantum program to be parsed. Based on the statement order of the quantum gate processing statements, quantum circuit analysis is performed on the quantum gate processing statements to obtain circuit information included in the quantum program to be parsed; the circuit information is used to characterize the quantum circuit indicated by the quantum gate processing statement, such as Figure 5 As shown in the circuit information 502, each column in the circuit information 502 is equivalent to a time frame, and the time frame arrangement order of the quantum gates included in the N quantum circuits in the circuit information is the same as the statement order of the quantum gate processing statement.

[0101] Further optionally, the quantum gates included in the N quantum circuits can be used as nodes, and the edges between the quantum gates included in the N quantum circuits can be determined based on the circuit information, and the nodes and edges can be constructed into a quantum directed graph model; the quantum directed graph model is used to indicate the gate dependency relationship between the quantum gates included in the N quantum circuits, and the quantum directed graph model can be recorded as G = (V, E), V is used to represent the quantum gate, and E is used to represent the edge (i.e., directed edge) between the quantum gates included in the N quantum circuits, which is used to represent the gate dependency relationship between the quantum gates included in the N quantum circuits. For details, see Figure 6 , Figure 6 Schematic diagram of a directed graph construction scenario provided by an embodiment of the present application. Figure 6As shown, it is assumed that circuit information 601 is obtained. For example, the circuit information 601 may include a single-bit gate 6011, a two-bit gate 6012, and a quantum measurement gate 6013 in the quantum program to be analyzed, wherein the number of any quantum gate may be one or at least two. Optionally, the circuit information 601 may also include multi-bit gates in the quantum program to be analyzed. Here, single-bit gates, two-bit gates, and quantum measurement gates are used as examples for description, and only some possible quantum gates corresponding to the quantum program to be analyzed are listed. Further, the quantum gates included in the N quantum circuits are used as nodes, and the edges (i.e., directed edges) between the quantum gates included in the N quantum circuits are determined based on the circuit information 601, and the nodes and edges are constructed into a quantum directed graph model 602, wherein, Figure 6 H() shown in is used to represent a single-bit gate, cx() is used to represent a two-bit gate, and Measz() is used to represent a quantum measurement gate. For example, H(q1) is used to represent a single-bit gate located in quantum circuit q1. The directed edges between nodes in the quantum directed graph model 602 are irreversible, that is, based on the irreversible characteristic of the directed edges of the quantum directed graph model 602, the gate dependency relationship between the quantum gates included in the N quantum circuits is represented.

[0102] Step S302, based on the gate dependency relationship between the quantum gates included in the N quantum circuits, gate alignment processing is performed on the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data.

[0103] In an embodiment of the present application, a computer device may perform gate alignment processing on quantum gates included in N quantum circuits based on a quantum directed graph model to obtain aligned quantum gate arrangement circuit data.

[0104] Specifically, in a quantum gate arrangement method ①, the computer device can perform a pre-partial order alignment process on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits to obtain the aligned quantum gate arrangement circuit data. Among them, the pre-partial order alignment refers to aligning the first quantum gate in the quantum gates included in each quantum circuit, and arranging the quantum gates included in the N quantum circuits without changing the properties of the quantum circuits, that is, without changing the gate dependency relationship between the quantum gates included in the N quantum circuits.

[0105] Specifically, the timing position corresponding to the first quantum gate among the quantum gates included in the N quantum circuits can be used as the first reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate aligned to the first reference timing position to obtain the aligned quantum gate arrangement circuit data; the first quantum gate refers to the first processed quantum gate indicated by the circuit information. Figure 5 As an example, the circuit information 502 shown in FIG. 1 is used as the timing position corresponding to the first quantum gate among the quantum gates included in the N quantum circuits as the first reference timing position, that is, the first quantum gate can be kept unchanged, such as Figure 5 As shown, the first quantum gate is quantum gate 50a; further, while maintaining the gate dependency relationship of the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate-aligned to the first reference timing position to obtain Figure 7 The quantum gate arrangement circuit data 701 shown, Figure 7 This is a schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. Figure 1 . At this time, the gate dependency relationship between each quantum gate in the quantum gate arrangement circuit data 701 conforms to the quantum directed graph model, and each quantum gate is aligned to the first reference timing position (i.e., time frame 701a), which reduces the running time of the quantum circuit, and can make the running process of the quantum circuit under the condition of quantum bit coherence as much as possible, thereby reducing the error caused by the limited quantum bit coherence time, and reducing the error of the quantum bit gate to a certain extent, improving the accuracy and efficiency of quantum circuit processing, and improving the efficiency of quantum gate processing. Among them, in the quantum gate arrangement circuit data 701 at this time, in the same quantum circuit, two adjacent quantum gates without gate dependency constraints between quantum gates are also in adjacent time frames. For example, in the quantum circuit q0, there is no gate dependency constraint between other quantum gates between the adjacent quantum gates 50e and quantum gate 50f. Therefore, quantum gate 50e and quantum gate 50f correspond to adjacent time frames, i.e., time frame 701d and time frame 701e, etc.; for example, taking quantum gate 50c as an example, the quantum gate 50 a is the first quantum gate in quantum circuit q0, which should be aligned to the first reference timing position (i.e., time frame 701a), and quantum gate 50a depends on quantum gate 50b located in quantum circuit q1 and quantum circuit q2, and quantum gate 50b depends on quantum gate 50a also located in quantum circuit q1, therefore, quantum gate 50c should be located after time frame 701a of quantum gate 50a and time frame 701b of quantum gate 50b, that is, quantum gate 50c corresponds to time frame 701c, etc. Similarly, the pre-partial order alignment processing of quantum gates included in N quantum circuits can be implemented to obtain quantum gate arrangement circuit data.

[0106] In a quantum gate arrangement method ②, the computer device can perform post-partial order alignment processing on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits to obtain the aligned quantum gate arrangement circuit data. Among them, post-partial order alignment refers to aligning the last quantum gate in the quantum gates included in each quantum circuit, and arranging the quantum gates included in the N quantum circuits without changing the properties of the quantum circuits, that is, without changing the gate dependency relationship between the quantum gates included in the N quantum circuits.

[0107] Specifically, the timing position corresponding to the second quantum gate in the quantum gates included in the N quantum circuits is used as the second reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate aligned to the second reference timing position to obtain the aligned quantum gate arrangement circuit data; the second quantum gate refers to the last processed quantum gate indicated by the circuit information. Figure 5 As an example, the circuit information 502 shown in FIG. 1 is used as the timing position corresponding to the second quantum gate in the quantum gates included in the N quantum circuits as the second reference timing position, that is, the second quantum gate can be kept unchanged, such as Figure 5 As shown, the second quantum gate is quantum gate 50i; further, while maintaining the gate dependency relationship of the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate-aligned to the second reference timing position to obtain Figure 8 The quantum gate arrangement circuit data 801 shown, Figure 8 This is a schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. Figure 2. At this time, the gate dependency relationship between each quantum gate in the quantum gate arrangement circuit data 801 conforms to the quantum directed graph model, and each quantum gate is aligned to the second reference timing position (i.e., time frame 801e), which reduces the running time of the quantum circuit, and can make the running process of the quantum circuit under the condition of quantum bit coherence as much as possible, thereby reducing the error caused by the limited quantum bit coherence time, and reducing the error of the quantum bit gate to a certain extent, improving the accuracy and efficiency of quantum circuit processing, and improving the efficiency of quantum gate processing. Among them, in the quantum gate arrangement circuit data 801 at this time, in the same quantum circuit, two adjacent quantum gates without gate dependency constraints between quantum gates are also in adjacent time frames, such as quantum gate 50e and quantum gate 50f corresponding to adjacent time frames, i.e., time frame 801d and time frame 801e, etc. For example, taking quantum gate 50b as an example, quantum gate 50b is adjacent to quantum gate 50h in quantum circuit q2, and quantum gate 50b depends on quantum gate 50c, and quantum gate 50c depends on quantum gate 50e. Therefore, the time frame of quantum gate 50b should be located before time frame 801c of quantum gate 50c and time frame 801d of quantum gate 50e, that is, time frame 801b is not adjacent to time frame 801d of quantum gate 50h. Similarly, the post-partial order alignment processing of quantum gates included in N quantum circuits can be implemented to obtain quantum gate arrangement circuit data.

[0108] Among them, the gate dependency between the quantum gates included in the N quantum circuits can include pre-order dependency and post-order dependency. The pre-order dependency is used to indicate the quantum gates that need to wait for execution when each quantum gate is executed; the post-order dependency is used to indicate the quantum gates that can be triggered after each quantum gate is executed. The quantum gate arrangement method ① can be realized through the pre-order dependency; and the quantum gate arrangement method ② can be realized through the post-order dependency.

[0109] Optionally, in a quantum gate arrangement method ③, a computer device can obtain M quantum measurement gates included in N quantum circuits; M is a positive integer; each quantum circuit does not include a quantum measurement gate or includes at least one quantum measurement gate. Based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits is maintained, and the M quantum measurement gates are aligned to obtain the aligned quantum gate arrangement circuit data; the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame; the quantum bit gate refers to the quantum gate other than the M quantum measurement gates in the quantum gates included in the N quantum circuits; the time frame is used to represent the execution order of the quantum gates included in the N quantum circuits. For example, a possible implementation process can be seen in Fig. 9 , Fig. 9 This is a schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. Figure 3 ,like Fig. 9 As shown, the computer device can align the quantum measurement gates corresponding to the N quantum circuits (such as the quantum measurement gate 50f in the quantum circuit q0, the quantum measurement gate 50g in the quantum circuit q1, and the quantum measurement gate 50i in the quantum circuit q2) to obtain the initial measurement alignment model 901, delete the idle time frames in the N quantum circuits, and obtain the quantum gate arrangement circuit data 902. In other words, the quantum bit gates included in the N quantum circuits are kept, and the quantum measurement gates corresponding to the N quantum circuits are aligned and placed after the quantum bit gates included in the N quantum circuits to obtain the quantum gate arrangement circuit data 902, so that each quantum measurement gate in the quantum gate arrangement circuit data 902 is located in the same time frame. Through the above process, all quantum bit gates can be measured at the same time, which can reduce the system error introduced by the quantum bit measurement, and to a certain extent, can improve the accuracy of the quantum circuit operation results.

[0110] Further optionally, in a quantum gate arrangement method ④, M quantum measurement gates included in N quantum circuits can be obtained; M is a positive integer; each quantum circuit does not include a quantum measurement gate or includes at least one quantum measurement gate. Based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits is maintained, and the M quantum measurement gates are aligned to obtain measurement alignment data; the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame, wherein the acquisition process of the measurement alignment data can refer to the generation process of the quantum gate arrangement circuit data in the quantum gate arrangement method ③, such as in Figure 5 The measured alignment data obtained based on the example shown is Fig. 9 The quantum gate arrangement circuit data 902 shown in FIG. Further, based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the M quantum measurement gates can be kept in the same time frame in the measurement alignment data, and the quantum bit gates can be aligned to obtain the aligned quantum gate arrangement circuit data. For details, see Fig.10 , Fig.10 This is a schematic diagram of a quantum gate arrangement provided in an embodiment of the present application. Figure 4, the M quantum measurement gates can be kept in the same time frame in the measurement alignment data, and the quantum gate arrangement method ① is used to perform the pre-partial order alignment processing on the quantum bit gates to obtain the quantum gate arrangement circuit data 1001; or, the M quantum measurement gates can be kept in the same time frame in the measurement alignment data, and the quantum gate arrangement method ② is used to perform the post-partial order alignment processing on the quantum bit gates to obtain the quantum gate arrangement circuit data 1002. Through the above process, the time required for quantum circuit processing can be shortened, the efficiency of quantum circuit processing can be improved, the quantum failure caused by quantum bit decoherence can be avoided, the accuracy of quantum circuit processing can be improved, and the precision of quantum circuit operation can be improved.

[0111] Optionally, the computer device may obtain the bit coherence time of the quantum gates included in the N quantum circuits, and obtain the longest processing time corresponding to the N quantum circuits. If the bit coherence time is less than the longest processing time, the timing position corresponding to the second quantum gate in the quantum gates included in the N quantum circuits is used as the second reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate-aligned to the second reference timing position to obtain the aligned quantum gate arrangement circuit data; the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

[0112] Alternatively, the computer device can obtain the bit coherence time of the quantum gates included in the N quantum circuits and obtain the longest processing time corresponding to the N quantum circuits. If the bit coherence time is less than the longest processing time, that is, when the N quantum circuits are finally measured, some quantum gates may have decohered, then any one of the above-mentioned quantum gate arrangement method ①, quantum gate arrangement method ② or quantum gate arrangement method ④ is used to perform gate alignment processing on the quantum gates included in the N quantum circuits to obtain quantum gate arrangement circuit data. If the bit coherence time is greater than or equal to the longest processing time, any one of the above-mentioned quantum gate arrangement method ①, quantum gate arrangement method ②, quantum gate arrangement method ③ or quantum gate arrangement method ④ is used to perform gate alignment processing on the quantum gates included in the N quantum circuits to obtain quantum gate arrangement circuit data. Of course, it is optional that if the bit coherence time is less than the longest processing time, the above-mentioned quantum gate arrangement method ① or quantum gate arrangement method ② is used to perform gate alignment processing on the quantum gates included in the N quantum circuits to obtain quantum gate arrangement circuit data; if the bit coherence time is greater than or equal to the longest processing time, the above-mentioned quantum gate arrangement method ③ is used to perform gate alignment processing on the quantum gates included in the N quantum circuits to obtain quantum gate arrangement circuit data. Optionally, the bit coherence time of the quantum gate can be ignored, and the quantum gate arrangement method ④ can be directly used to perform gate alignment processing on the quantum gates included in the N quantum circuits to obtain quantum gate arrangement circuit data, etc. The calling conditions of the above-mentioned quantum gate arrangement methods can be updated based on needs, and there is no restriction here.

[0113] Alternatively, the computer device may obtain the circuit operation data of the quantum circuit corresponding to the quantum program to be analyzed, and determine the circuit optimization direction of the quantum circuit based on the circuit operation data. The circuit optimization direction may include but is not limited to the time optimization direction, the measurement optimization direction, and the overall optimization direction. Further, the target quantum gate alignment method corresponding to the circuit optimization direction may be obtained, and based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the target quantum gate alignment method is used to perform gate alignment processing on the quantum gates included in the N quantum circuits to obtain the aligned quantum gate arrangement circuit data. For example, the target quantum gate alignment method corresponding to the time optimization direction is the above-mentioned quantum gate arrangement method ①, and quantum gate arrangement method ②; the target quantum gate alignment method corresponding to the measurement optimization direction is the above-mentioned quantum gate arrangement method ③; the target quantum gate alignment method corresponding to the overall optimization direction is the above-mentioned quantum gate arrangement method ④, etc. Specifically, if the circuit optimization direction is the time optimization direction, the quantum gate arrangement mode ① or the quantum gate arrangement mode ② is determined as the target quantum gate alignment mode, etc. Specifically, the implementation process of the target quantum gate alignment mode can be based on the correspondence between the above circuit optimization direction and the quantum gate arrangement mode, see the implementation process of the above quantum gate arrangement mode ① to the quantum gate arrangement mode ④, which will not be repeated here. Through the above process, it is possible to adopt a quantum gate arrangement mode that is more in line with the requirements of the quantum circuit corresponding to the quantum program to be analyzed, perform gate alignment processing on the quantum program to be analyzed, and improve the accuracy of quantum circuit processing.

[0114] Alternatively, the computer device may obtain a timing control parameter, obtain a quantum gate arrangement corresponding to the timing control parameter, adopt the quantum gate arrangement corresponding to the timing control parameter, perform gate alignment processing on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits, and obtain the process of aligned quantum gate arrangement circuit data. For example, a timing control option may be output, and in response to a selection operation for a target timing control option in the timing control option, the timing control parameter carried by the target timing control option is obtained. This makes the quantum gate timing control of the quantum program to be parsed easier, and improves the flexibility and convenience of quantum circuit processing.

[0115] Step S303, generating quantum processing instructions according to the quantum gate arrangement circuit data.

[0116] In an embodiment of the present application, the P quantum gates included in the quantum gate arrangement circuit data and the quantum circuit corresponding to each quantum gate can be obtained; P is a positive integer. Based on the target time frames in which the P quantum gates are located in the quantum gate arrangement circuit data, and the quantum circuit corresponding to each quantum gate, quantum processing instructions for the P quantum gates are generated; the quantum gates included in the N quantum circuits, the first execution sequence in the quantum processing instructions, is different from the second execution sequence in the quantum program to be analyzed. Among them, the first execution sequence refers to the execution order of the quantum gates included in the N quantum circuits in the quantum processing instructions, such as which quantum gates are executed in the same time frame, the order of different time frames, etc.; the second execution sequence refers to the execution order of the quantum gates included in the N quantum circuits in the quantum program to be analyzed, etc., so as to achieve the timing rearrangement of the quantum gates in the quantum circuit. For example, the P quantum gates included in the quantum gate arrangement circuit data and the quantum circuit corresponding to each quantum gate can be obtained; the instruction generation language is obtained, and the instruction template corresponding to the instruction generation language is obtained. For example, the instruction generation language is eqasm, and the instruction template of the instruction generation language eqasm includes the declaration template: SMIS Sd (for declaring a single-bit gate) and SMIS Td (for declaring a double-bit gate), etc., where d is used to represent the label of the corresponding quantum gate; the instruction template can also include an execution template: H (for representing a single-bit gate), CNOT (for representing a double-bit gate), MEASZ (for representing a quantum measurement gate) and "|" (for dividing a quantum gate). Among them, the computer device can respond to the timing rearrangement operation for the quantum circuit and display the candidate instruction language option; respond to the selection operation for the instruction generation language in the candidate instruction language option to obtain the instruction generation language. Among them, the candidate instruction language option can refer to the language type supported by the device for executing the subsequently generated quantum processing instructions. Alternatively, the computer device can obtain a preset language configured by a business object (i.e., a business person who manages the quantum circuit, etc.), and determine the preset language as the instruction generation language. Alternatively, the computer device may directly determine a default language as the instruction generation language, where the default language refers to the language used by the computer device to generate instructions after re-arranging the timing of quantum gates in any quantum circuit.

[0117] by Fig.10 Taking the quantum gate arrangement circuit data 1001 shown as an example, the above declaration template can be used to generate declaration instructions for P quantum gates and the quantum circuits corresponding to each quantum gate to obtain quantum declaration instructions, as shown below:

[0118] SMIS S0, {0} / / is used to represent the single-bit gate S0 located in the quantum circuit q0 (i.e., {0}), i.e., the quantum gate 50e;

[0119] SMIS S1, {1} / / is used to represent the single-bit gate S1 located in the quantum circuit q1 (i.e., {1}), i.e., the quantum gate 50a;

[0120] SMIS S2, {2} / / is used to represent the single-bit gate S2 located in the quantum circuit q2 (i.e., {2}), i.e., quantum gate 50h;

[0121] SMIS S3, {3} / / is used to represent the single-bit gate S3 located in the quantum circuit q3 (i.e., {3}), i.e., the quantum gate 50d;

[0122] SMIT T1, {1, 2} / / is used to represent the two-bit gate T1 located in the quantum circuit q1 and the quantum circuit q2 (i.e., {1, 2}), i.e., the quantum gate 50b;

[0123] SMIT T2, {0, 1} / / is used to represent the two-bit gate T2 located in the quantum circuit q0 and the quantum circuit q1 (ie, {0, 1}), ie, the quantum gate 50c.

[0124] Using the above execution template, based on the target time frames of the P quantum gates in the quantum gate arrangement circuit data 1001, and the quantum circuits corresponding to each quantum gate, quantum execution instructions for the P quantum gates are generated, as shown below:

[0125] 0, H S1|H S3 / / is used to indicate that in the starting time frame (assuming it is time frame 1), the single-bit gate S1 and the single-bit gate S3 are executed, and 0 is used to indicate that a new time frame is not started;

[0126] 1, CNOT T1 / / is used to indicate that a new time frame (recorded as time frame 2) is started based on the previous time frame, and the two-bit gate T1 is executed. 1 is used to indicate the start of a new time frame;

[0127] 1, CNOT T2|H S2 / / is used to indicate that a new time frame (recorded as time frame 3) is started based on the previous time frame, and the double-bit gate T2 and the single-bit gate S2 are executed;

[0128] 1, H S0 / / is used to indicate that a new time frame (recorded as time frame 4) is started based on the previous time frame, and the single-bit gate S0 is executed;

[0129] 1, MEASZ S0|MEASZ S1|MEASZ S2 / / is used to indicate the measurement processing of quantum circuit q0, quantum circuit q1 and quantum circuit q2.

[0130] Further, the quantum declaration instruction and the quantum execution instruction are combined into a quantum processing instruction for P quantum gates. Optionally, a waiting instruction, such as QWAIT 10000, etc., can be inserted between the quantum declaration instruction and the quantum execution instruction to generate a quantum processing instruction for P quantum gates.

[0131] Furthermore, the quantum processing instruction can be executed to measure and process the quantum program to be analyzed, and obtain the quantum information of the quantum corresponding to the quantum program to be analyzed. Specifically, the quantum processing instruction is still an instruction for the above-mentioned quantum circuit, but it is processed after the quantum gates in the quantum circuit are reordered, and the connection mode between the quantum gates of the quantum circuit itself has not changed. In other words, it can be considered that the computer device executes the quantum processing instruction for the quantum circuit to realize the measurement and processing of the quantum program to be analyzed, specifically, the quantum gates included in the quantum circuit (that is, the quantum gates included in N quantum circuits) are measured and processed to obtain the quantum information of the quantum corresponding to the quantum program to be analyzed. Among them, the quantum information is used to represent the physical state and quantum properties of the quantum. Further, quantum information can be used to apply quantum. For example, in a quantum communication scenario, encryption parameters can be obtained based on the quantum information of the quantum and the measurement results of the measurement and processing of the quantum program to be analyzed, and the encryption parameters are used to encrypt the communication data to obtain encrypted data, and the encrypted data is transmitted. Among them, this method uses the non-replicability of quantum and the randomness of measurement to generate quantum cryptography (i.e. encryption parameters) to encrypt communication data. Of course, with the development of quantum research, the quantum information obtained in this application can also be applied to other scenarios, which will not be described in detail here.

[0132] Among them, the quantum circuit can be integrated in a computer device or in a target business device (in this case, the computer device can send the quantum processing instruction to the target business device). The target business device can be a business device with a quantum circuit integrated in the business device mentioned above. The device where the quantum circuit is located can be recorded as a quantum management device. When the quantum management device includes a quantum processing instruction, the quantum management device can execute the quantum processing instruction and measure the quantum circuit. Optionally, the quantum management device can respond to a quantum measurement request for the quantum circuit, call the quantum processing instruction, execute the quantum processing instruction, and measure the quantum circuit; or, when the quantum management device obtains the quantum processing instruction, it executes the quantum processing instruction and measures the quantum circuit, such as when the quantum management device is a computer device, when the computer device generates the quantum processing instruction, or when the quantum management device is a target business device, when the target business device receives the quantum processing instruction, etc. Alternatively, the quantum processing instruction is added to the code position where the quantum program to be parsed is located, and the quantum program to be parsed is annotated, which is equivalent to replacing the quantum program to be parsed with the quantum processing instruction. In this case, the triggering method of the quantum program to be parsed can be directly used to trigger the quantum processing instruction. Among them, annotation processing refers to changing the quantum program to be parsed from an executable state to a non-executable state.

[0133] Specifically, the above process can be simply summarized as follows: Fig.11 , Fig.11 This is a simplified flowchart of quantum analysis provided by the embodiment of the present application, such as Fig.11 As shown, the process may include the following steps:

[0134] Step S1101, performing quantum circuit analysis.

[0135] In the embodiments of the present application, please refer to the above Figure 3 As described in step S301, quantum circuit analysis is performed on the quantum program to be analyzed to obtain circuit information.

[0136] Step S1102, establishing a directed graph model.

[0137] In the embodiments of the present application, please refer to the above Figure 3 The related description in step S301 is to build a directed graph model based on the circuit information.

[0138] Step S1103, obtaining timing control parameters.

[0139] In the embodiments of the present application, please refer to the above Figure 3 According to the relevant description in step S302, the timing control parameters are obtained, and the quantum gate arrangement method for timing rearrangement of the quantum program to be analyzed is determined.

[0140] Step S1104, re-arrange the timing of the circuit information.

[0141] In the embodiments of the present application, please refer to the above Figure 3 According to the relevant description in step S302, the quantum gate arrangement method obtained in step S1103 is used to rearrange the circuit information in time sequence to generate quantum gate arrangement circuit data.

[0142] Step S1105: Generate quantum processing instructions.

[0143] In the embodiments of the present application, please refer to the above Figure 3 The relevant description in step S303 will not be repeated here.

[0144] In the embodiment of the present application, a quantum program to be analyzed is obtained, and quantum circuit analysis is performed on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer; based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate aligned to obtain the aligned quantum gate arrangement circuit data; according to the quantum gate arrangement circuit data, quantum processing instructions are generated. Through the above process, the quantum circuit can be directly analyzed, that is, the quantum program to be analyzed corresponding to the quantum circuit, so that the automatic analysis of the quantum circuit can be realized, and based on the obtained quantum circuit, the alignment processing of each quantum gate is realized, and the timing control of the quantum gate is realized to suppress the noise influence caused by the characteristics of the quantum and improve the accuracy of the quantum calculation results. Moreover, according to the semantics of the input quantum program to be analyzed (i.e., circuit information), the gate dependency relationship of the quantum gate is independently modeled to improve the efficiency and accuracy of quantum circuit processing, and improve the convenience and flexibility of quantum gate processing.

[0145] For further information, see Fig.12 , Fig.12 Schematic diagram of a quantum circuit processing device provided in an embodiment of the present application. The quantum circuit processing device may be a computer program (including program code, etc.) running in a computer device, for example, the quantum circuit processing device may be an application software; the device may be used to execute the corresponding steps in the method provided in an embodiment of the present application. Fig.12 As shown, the quantum circuit processing device 1200 can be used for Figure 3 The computer device in the corresponding embodiment, specifically, the device may include: a program acquisition module 11, a program analysis module 12, a quantum arrangement module 13 and an instruction generation module 14.

[0146] A program acquisition module 11 is used to acquire the quantum program to be analyzed;

[0147] The program analysis module 12 is used to perform quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer;

[0148] A quantum arrangement module 13 is used to perform gate alignment processing on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data;

[0149] The instruction generation module 14 is used to generate quantum processing instructions according to the quantum gate arrangement circuit data; the quantum gates included in the N quantum circuits have a first execution timing in the quantum processing instructions that is different from a second execution timing in the quantum program to be analyzed.

[0150] The program analysis module 12 includes:

[0151] A language parsing unit 12a, used to obtain the program language type of the quantum program to be parsed;

[0152] A key acquisition unit 12b is used to acquire quantum keywords corresponding to the programming language type;

[0153] A code recognition unit 12c is used to recognize a quantum code segment in a quantum program to be analyzed based on quantum keywords; the quantum code segment includes M code statements; M is a positive integer;

[0154] The circuit analysis unit 12d is used to perform quantum circuit analysis on the M code statements based on the statement order of the M code statements to obtain circuit information included in the quantum program to be analyzed; the circuit information is used to characterize the quantum circuit indicated by the M code statements.

[0155] The program analysis module 12 includes:

[0156] A model parsing unit 12e is used to input the quantum program to be parsed into the program parsing model for parsing, and determine the program language type corresponding to the quantum program to be parsed;

[0157] A statement detection unit 12f is used to detect the code statements included in the quantum program to be parsed based on the program language type in the program parsing model, and obtain the quantum gate processing statements in the code statements included in the quantum program to be parsed;

[0158] The information acquisition unit 12g is used to perform quantum circuit analysis on the quantum gate processing statement based on the statement sequence of the quantum gate processing statement to obtain circuit information included in the quantum program to be analyzed; the circuit information is used to characterize the quantum circuit indicated by the quantum gate processing statement.

[0159] The device 1200 further includes:

[0160] A directed construction module 15 is used to use the quantum gates included in the N quantum circuits as nodes, determine the edges between the quantum gates included in the N quantum circuits based on the circuit information, and construct the nodes and the edges into a quantum directed graph model; the quantum directed graph model is used to indicate the gate dependency relationship between the quantum gates included in the N quantum circuits;

[0161] The quantum arrangement module 13 is specifically used for:

[0162] Based on the quantum directed graph model, gate alignment is performed on the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data.

[0163] The quantum arrangement module 13 includes:

[0164] The first arrangement unit 13a is used to use the timing position corresponding to the first quantum gate among the quantum gates included in the N quantum circuits as the first reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, perform gate alignment processing on the quantum gates included in the N quantum circuits to the first reference timing position to obtain aligned quantum gate arrangement circuit data; the first quantum gate refers to the first processed quantum gate indicated by the circuit information; or,

[0165] The second arrangement unit 13b is used to use the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits as the second reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, perform gate alignment processing on the quantum gates included in the N quantum circuits to the second reference timing position to obtain the aligned quantum gate arrangement circuit data; the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

[0166] The quantum arrangement module 13 includes:

[0167] A coherent analysis unit 13c is used to obtain the bit coherence time of the quantum gates included in the N quantum circuits, and obtain the longest processing time corresponding to the N quantum circuits;

[0168] The second arrangement unit 13b is further used for, if the bit coherence time is less than the longest processing time, taking the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits as the second reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, performing gate alignment processing on the quantum gates included in the N quantum circuits to the second reference timing position to obtain aligned quantum gate arrangement circuit data; the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

[0169] The quantum arrangement module 13 includes:

[0170] The measurement acquisition unit 13d is used to acquire M quantum measurement gates included in the N quantum circuits; M is a positive integer; each quantum circuit does not include a quantum measurement gate or includes at least one quantum measurement gate;

[0171] The third arrangement unit 13e is used to maintain the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits, align the M quantum measurement gates, and obtain the aligned quantum gate arrangement circuit data; the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame; the quantum bit gate refers to the quantum gate included in the N quantum circuits, except the M quantum measurement gates; the time frame is used to represent the execution order of the quantum gates included in the N quantum circuits.

[0172] The quantum arrangement module 13 includes:

[0173] The measurement acquisition unit 13d is further used to acquire M quantum measurement gates included in the N quantum circuits; M is a positive integer; each quantum circuit does not include a quantum measurement gate or includes at least one quantum measurement gate;

[0174] The initial arrangement unit 13f is used to maintain the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits, align the M quantum measurement gates, and obtain measurement alignment data; the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame;

[0175] The fourth arrangement unit 13g is used to keep the M quantum measurement gates in the same time frame in the measurement alignment data based on the gate dependency between the quantum gates included in the N quantum circuits, align the quantum bit gates, and obtain the aligned quantum gate arrangement circuit data.

[0176] The quantum arrangement module 13 includes:

[0177] An optimization determination unit 13h, used to obtain circuit operation data of the quantum circuit corresponding to the quantum program to be analyzed, and determine the circuit optimization direction of the quantum circuit based on the circuit operation data;

[0178] The gate arrangement unit 13i is used to obtain the target quantum gate alignment method corresponding to the circuit optimization direction, and based on the gate dependency relationship between the quantum gates included in the N quantum circuits, use the target quantum gate alignment method to perform gate alignment processing on the quantum gates included in the N quantum circuits to obtain the aligned quantum gate arrangement circuit data.

[0179] The instruction generation module 14 includes:

[0180] The gate analysis unit 14a is used to obtain P quantum gates included in the quantum gate arrangement circuit data, and the quantum circuit corresponding to each quantum gate; P is a positive integer;

[0181] The instruction generation unit 14b is used to generate quantum processing instructions for the P quantum gates based on the target time frames where the P quantum gates are located in the quantum gate arrangement circuit data and the quantum circuit corresponding to each quantum gate.

[0182] The device 1200 further includes:

[0183] The instruction execution module 16 is used to execute the quantum processing instruction, measure and process the quantum program to be analyzed, and obtain the quantum information of the quantum corresponding to the quantum program to be analyzed;

[0184] The quantum application module 17 is used to apply quantum using quantum information.

[0185] The embodiment of the present application provides a quantum circuit processing device, which can obtain a quantum program to be analyzed, perform quantum circuit analysis on the quantum program to be analyzed, and obtain circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer; based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate aligned to obtain the aligned quantum gate arrangement circuit data; according to the quantum gate arrangement circuit data, a quantum processing instruction is generated. Through the above process, the quantum circuit can be directly analyzed, that is, the quantum program to be analyzed corresponding to the quantum circuit, so that the automatic analysis of the quantum circuit can be realized, and based on the obtained quantum circuit, the alignment processing of each quantum gate is realized, and the timing control of the quantum gate is realized to suppress the noise influence caused by the characteristics of the quantum and improve the accuracy of the quantum calculation results. Moreover, according to the semantics of the input quantum program to be analyzed (i.e., circuit information), the gate dependency relationship of the quantum gate is independently modeled to improve the efficiency and accuracy of quantum circuit processing, and improve the convenience and flexibility of quantum gate processing.

[0186] See also Fig.13 , Fig.13 Schematic diagram of the structure of a computer device provided in an embodiment of the present application. Fig.13 As shown, the computer device in the embodiment of the present application may include: one or more processors 1301, a memory 1302, and an input-output interface 1303. The processor 1301, the memory 1302, and the input-output interface 1303 are connected via a bus 1304. The memory 1302 is used to store a computer program, which includes program instructions. The input-output interface 1303 is used to receive data and output data, such as for data interaction between a computer device and a business device, or for data interaction between a computer device and a quantum device; the processor 1301 is used to execute the program instructions stored in the memory 1302.

[0187] The processor 1301 may perform the following operations:

[0188] Obtaining a quantum program to be analyzed, performing quantum circuit analysis on the quantum program to be analyzed, and obtaining circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer;

[0189] Based on the gate dependency relationship between the quantum gates included in the N quantum circuits, gate alignment processing is performed on the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data;

[0190] A quantum processing instruction is generated according to quantum gate arrangement circuit data; the quantum gates included in the N quantum circuits have a first execution timing in the quantum processing instruction that is different from a second execution timing in the quantum program to be analyzed.

[0191] In some feasible implementations, the processor 1301 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0192] The memory 1302 may include a read-only memory and a random access memory, and provide instructions and data to the processor 901 and the input / output interface 1303. A portion of the memory 1302 may also include a non-volatile random access memory. For example, the memory 1302 may also store information about the device type.

[0193] In a specific implementation, the computer device can execute the following operations through its built-in functional modules: Figure 3 For details on the implementation methods provided in each step, please refer to the Figure 3 The implementation methods provided in each step will not be repeated here.

[0194] The embodiment of the present application provides a computer device, including: a processor, an input / output interface, and a memory, wherein the processor obtains a computer program in the memory and executes the computer program. Figure 3 The various steps of the method shown in the embodiment of the present application are used to perform quantum circuit processing operations. The embodiment of the present application realizes obtaining the quantum program to be analyzed, performing quantum circuit analysis on the quantum program to be analyzed, and obtaining the circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and the quantum gates included in the N quantum circuits; N is a positive integer; based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate aligned to obtain the aligned quantum gate arrangement circuit data; according to the quantum gate arrangement circuit data, quantum processing instructions are generated. Through the above process, the quantum circuit can be directly analyzed, that is, the quantum program to be analyzed corresponding to the quantum circuit, so that the automatic analysis of the quantum circuit can be realized, and based on the obtained quantum circuit, the alignment processing of each quantum gate is realized, and the timing control of the quantum gate is realized to suppress the noise influence caused by the characteristics of the quantum and improve the accuracy of the quantum calculation results. Moreover, according to the semantics of the input quantum program to be analyzed (i.e., circuit information), the gate dependency relationship of the quantum gate is independently modeled to improve the efficiency and accuracy of quantum circuit processing, and improve the convenience and flexibility of quantum gate processing.

[0195] The present application also provides a computer-readable storage medium storing a computer program suitable for being loaded and executed by the processor. Figure 3 The quantum circuit processing methods provided in each step can be found in the Figure 3The implementation methods provided in each step are not repeated here. In addition, the description of the beneficial effects of adopting the same method is not repeated. For technical details not disclosed in the computer-readable storage medium embodiment involved in this application, please refer to the description of the method embodiment of this application. As an example, the computer program can be deployed to execute on one computer device, or on multiple computer devices located in one place, or on multiple computer devices distributed in multiple locations and interconnected by a communication network.

[0196] The computer-readable storage medium may be the quantum circuit processing device provided in any of the aforementioned embodiments or the internal storage unit of the computer device, such as the hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (smart media card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. equipped on the computer device. Further, the computer-readable storage medium may also include both the internal storage unit of the computer device and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

[0197] The present application also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes Figure 3 The methods provided in the various optional methods in the method can directly analyze the quantum circuit, that is, the quantum program to be analyzed corresponding to the quantum circuit, so that the automatic analysis of the quantum circuit can be realized, and based on the obtained quantum circuit, the alignment processing of each quantum gate is realized, and the timing control of the quantum gate is realized to suppress the noise influence caused by the characteristics of quantum and improve the accuracy of quantum computing results. Moreover, according to the semantics of the input quantum program to be analyzed (that is, circuit information), the gate dependency relationship of the quantum gate is independently modeled to improve the efficiency and accuracy of quantum circuit processing, and improve the convenience and flexibility of quantum gate processing.

[0198] The terms "first", "second", etc. in the description, claims, and drawings of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, device, product, or equipment that includes a series of steps or units is not limited to the listed steps or modules, but optionally includes steps or modules that are not listed, or optionally includes other step units inherent to these processes, methods, devices, products, or equipment.

[0199] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in this description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0200] The method and related apparatus provided by the embodiment of the present application are described with reference to the method flow chart and / or structural diagram provided by the embodiment of the present application. Specifically, each process and / or box in the method flow chart and / or structural diagram, as well as the combination of the processes and / or boxes in the flow chart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable quantum circuit processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable quantum circuit processing device generate instructions for implementing the process in the process. Figure 1 A process or multiple processes and / or structures Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable quantum circuit processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or structures Figure 1 These computer program instructions can also be loaded onto a computer or other programmable quantum circuit processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process. Figure 1 A flow or multiple flows and / or structures illustrate the steps of the functions specified in one block or multiple blocks.

[0201] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0202] The modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0203] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A quantum circuit processing method, characterized in that: The method comprises: Acquire a quantum program to be analyzed, perform quantum circuit analysis on the quantum program to be analyzed, and obtain circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer; Based on the gate dependency relationship between the quantum gates included in the N quantum circuits, gate alignment processing is performed on the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data; A quantum processing instruction is generated according to the quantum gate arrangement circuit data; a first execution sequence of the quantum gates included in the N quantum circuits in the quantum processing instruction is different from a second execution sequence in the quantum program to be analyzed.

2. The method according to claim 1, characterized in that The performing quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed includes: Obtaining a program language type of the quantum program to be parsed, and obtaining a quantum keyword corresponding to the program language type; Identify a quantum code segment in the quantum program to be analyzed based on the quantum keyword; the quantum code segment includes M code statements; M is a positive integer; Based on the statement order of the M code statements, the M code statements are subjected to quantum circuit analysis to obtain circuit information included in the quantum program to be analyzed; the circuit information is used to characterize the quantum circuit indicated by the M code statements.

3. The method according to claim 1, characterized in that The performing quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed includes: Inputting the quantum program to be parsed into a program parsing model for parsing, and determining a program language type corresponding to the quantum program to be parsed; In the program parsing model, code statements included in the quantum program to be parsed are detected based on the program language type to obtain quantum gate processing statements in the code statements included in the quantum program to be parsed; Based on the statement sequence of the quantum gate processing statements, the quantum gate processing statements are subjected to quantum circuit analysis to obtain circuit information included in the quantum program to be analyzed; the circuit information is used to characterize the quantum circuit indicated by the quantum gate processing statements.

4. The method according to claim 1, characterized in that The method further comprises: Taking the quantum gates included in the N quantum circuits as nodes, determining the edges between the quantum gates included in the N quantum circuits based on the circuit information, and constructing the nodes and the edges into a quantum directed graph model; the quantum directed graph model is used to indicate the gate dependency relationship between the quantum gates included in the N quantum circuits; The gate alignment process is performed on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, including: Based on the quantum directed graph model, gate alignment processing is performed on the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data.

5. The method according to claim 1, characterized in that The gate alignment process is performed on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, including: Taking the timing position corresponding to the first quantum gate among the quantum gates included in the N quantum circuits as the first reference timing position, based on the dependency relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate aligned to the first reference timing position to obtain aligned quantum gate arrangement circuit data; the first quantum gate refers to the first processed quantum gate indicated by the circuit information; or, Taking the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits as the second reference timing position, based on the dependency relationship between the quantum gates included in the N quantum circuits, gate alignment processing is performed on the quantum gates included in the N quantum circuits toward the second reference timing position to obtain aligned quantum gate arrangement circuit data; the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

6. The method according to claim 1, characterized in that The gate alignment process is performed on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, including: Obtaining bit coherence times of quantum gates included in the N quantum circuits, and obtaining the longest processing time corresponding to the N quantum circuits; If the bit coherence time is less than the longest processing time, the timing position corresponding to the second quantum gate among the quantum gates included in the N quantum circuits is used as the second reference timing position, and based on the dependency relationship between the quantum gates included in the N quantum circuits, the quantum gates included in the N quantum circuits are gate aligned to the second reference timing position to obtain aligned quantum gate arrangement circuit data; the second quantum gate refers to the last processed quantum gate indicated by the circuit information.

7. The method according to claim 1, characterized in that The gate alignment process is performed on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, including: Obtaining M quantum measurement gates included in the N quantum circuits; M is a positive integer; each quantum circuit does not include a quantum measurement gate or includes at least one quantum measurement gate; Based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits is maintained, and the M quantum measurement gates are aligned to obtain aligned quantum gate arrangement circuit data; the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame; the quantum bit gate refers to the quantum gate included in the N quantum circuits, except the M quantum measurement gates; the time frame is used to represent the execution order of the quantum gates included in the N quantum circuits.

8. The method according to claim 1, characterized in that The gate alignment process is performed on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, including: Obtaining M quantum measurement gates included in the N quantum circuits; M is a positive integer; each quantum circuit does not include a quantum measurement gate or includes at least one quantum measurement gate; Based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the execution order of the quantum bit gates in the quantum gates included in the N quantum circuits is maintained, and the M quantum measurement gates are aligned to obtain measurement alignment data; the M quantum measurement gates in the quantum gate arrangement circuit data are in the same time frame; Based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the M quantum measurement gates are kept in the same time frame in the measurement alignment data, and the quantum bit gates are aligned to obtain aligned quantum gate arrangement circuit data.

9. The method according to claim 1, characterized in that The gate alignment process is performed on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data, including: Acquiring circuit operation data of a quantum circuit corresponding to the quantum program to be analyzed, and determining a circuit optimization direction of the quantum circuit based on the circuit operation data; A target quantum gate alignment method corresponding to the circuit optimization direction is obtained, and based on the gate dependency relationship between the quantum gates included in the N quantum circuits, the target quantum gate alignment method is used to perform gate alignment processing on the quantum gates included in the N quantum circuits to obtain aligned quantum gate arrangement circuit data.

10. The method according to claim 1, characterized in that Generating a quantum processing instruction according to the quantum gate arrangement circuit data includes: Obtaining P quantum gates included in the quantum gate arrangement circuit data, and a quantum circuit corresponding to each quantum gate; P is a positive integer; Based on the target time frames where the P quantum gates are located in the quantum gate arrangement circuit data, and the quantum circuit corresponding to each quantum gate, quantum processing instructions for the P quantum gates are generated.

11. The method according to claim 1, characterized in that The method further comprises: Executing the quantum processing instruction, measuring and processing the quantum program to be analyzed, and obtaining quantum information of the quantum corresponding to the quantum program to be analyzed; The quantum information is used to apply the quantum.

12. A quantum circuit processing device, characterized in that: The device comprises: A program acquisition module is used to obtain the quantum program to be parsed; A program analysis module, used for performing quantum circuit analysis on the quantum program to be analyzed to obtain circuit information included in the quantum program to be analyzed; the circuit information includes N quantum circuits and quantum gates included in the N quantum circuits; N is a positive integer; A quantum arrangement module, configured to perform gate alignment processing on the quantum gates included in the N quantum circuits based on the gate dependency relationship between the quantum gates included in the N quantum circuits, and obtain aligned quantum gate arrangement circuit data; An instruction generation module is used to generate a quantum processing instruction according to the quantum gate arrangement circuit data; the quantum gates included in the N quantum circuits have a first execution timing in the quantum processing instruction that is different from a second execution timing in the quantum program to be analyzed.

13. A computer device, characterized in that: Includes processor, memory, input and output interfaces; The processor is connected to the memory and the input / output interface respectively, wherein the input / output interface is used to receive and output data, the memory is used to store a computer program, and the processor is used to call the computer program so that the computer device executes the method described in any one of claims 1-11.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is suitable for being loaded and executed by a processor, so that a computer device having the processor executes the method according to any one of claims 1 to 11.

15. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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