SoC interrupt processing method based on hardware Sequence

Abstract

The invention relates to the technical field of system-on-chip service interrupt processing, in particular to a hardware Sequence-based SoC interrupt processing method, which comprises the following steps of: pre-programming an interrupt processing instruction sequence into an instruction random access memory (RAM), and configuring an instruction set, a sequence processor and an interrupt priority strategy of a task scheduler Sequence; receiving the interrupt signal by a task scheduler, and selecting a corresponding sequence processor according to an interrupt type; for the interrupt with low priority, the Sequencer directly executes the pre-stored instruction sequence to complete the interrupt response; and for high-priority interruption, the Sequencer caches the state of the register and sends a message packet to notify the CPU to perform cooperative processing. According to the method, interrupt autonomous response is achieved through hardware Sequence, zero CPU intervention is achieved in low-priority interrupt, a lightweight message mechanism is adopted in high-priority interrupt, and bandwidth occupation and power consumption are reduced while efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of system on chip (SoC) service interrupt processing, and in particular to a SoC interrupt processing method based on a hardware sequencer. Background Art

[0002] In traditional SoC (System on Chip) systems, service interrupt handling primarily relies on the CPU's software response mechanism, with task switching and resource management implemented through operating system scheduling. This architecture is widely used in industrial control, communications equipment, and consumer electronics. Its core process includes interrupt triggering, context saving, interrupt service program (ISP) execution, and context restoration. However, with the surge in demand for real-time services (such as 5G baseband processing and high-frame-rate video capture) and low-power scenarios (such as IoT terminals), the traditional interrupt handling model has gradually exposed performance bottlenecks. Especially when handling high-frequency interrupts, the CPU needs to frequently save and restore the context state, resulting in a significant consumption of computing resources and memory bandwidth.

[0003] Existing solutions suffer from significant technical flaws: CPU context switching overhead becomes a major bottleneck in system performance. Each interrupt response requires saving and restoring context data, including registers and program state, consuming significant CPU cycles and DDR bandwidth. In high-frequency interrupt scenarios (e.g., 10,000 interrupts per second), context switching can cause a loss of over 5% in CPU computing power and increase DDR bus contention, impacting the real-time performance of critical services such as display and networking. Furthermore, frequent interrupt wakeups prevent the CPU from entering a low-power state, increasing overall system energy consumption.

[0004] Therefore, how to reduce context switching overhead and improve interrupt response efficiency has become a key challenge in optimizing SoC real-time performance and energy efficiency. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a SoC interrupt processing method based on a hardware sequencer.

[0006] The technical problem solved by the present invention can be achieved by adopting the following technical solutions: a SoC interrupt processing method based on hardware sequencer, comprising: step S1, pre-programming the interrupt processing instruction sequence into the instruction RAM, and configuring the instruction set, sequence processor and interrupt priority policy of the task scheduler sequencer; step S2, the task scheduler sequencer receives the interrupt signal and selects the corresponding sequence processor according to the interrupt type; step S3, for low-priority interrupts, the task scheduler sequencer directly executes the pre-stored instruction sequence to complete the interrupt response; for high-priority interrupts, the task scheduler sequencer caches the register status and sends a message packet to notify the CPU for collaborative processing.

[0007] Preferably, in step S1, the sequence processor includes: a sequence processor LP1, which is used for DMA interrupt processing and has a built-in "DMA status reading → interrupt clearing → data parsing triggering" standard processing pipeline; a sequence processor LP2, which is used for I / O device interrupt processing and dynamically adjusts the bus priority through a group enable mechanism; wherein, the sequence processor LP1 and the sequence processor LP2 are designed with a parallel architecture.

[0008] Preferably, in step S1, the interrupt priority strategy includes: a static strategy, in which DMA interrupts are processed by the sequence processor LP1 and I2C / SSD interrupts are processed by the sequence processor LP2; and a dynamic strategy, in which a high-priority device preempts the low-priority interrupt processing right.

[0009] Preferably, in step S1, the instruction set includes: control commands, timing instructions, wait trigger instructions, message trigger instructions and task sequence end commands; wherein each instruction corresponds to a unique operation code and is fixedly stored in the instruction RAM.

[0010] Preferably, in step S3, for low-priority interrupts, the task scheduler sequencer directly executes a pre-stored instruction sequence to complete the interrupt response, including: step S311, the task scheduler sequencer reads the pre-stored instruction sequence from the instruction RAM; step S312, directly executing the pre-stored instruction sequence through the hardware logic circuit of the task scheduler sequencer; step S313, marking the interrupt processing completion through the SEQSTAT register.

[0011] Preferably, the step S312 includes: reading a DMA status register, clearing an interrupt flag, and triggering a data parsing module.

[0012] Preferably, the step S313 includes: updating the interrupt processing timestamp register, releasing occupied hardware resources, and sending a processing completion notification to the system event monitoring module.

[0013] Preferably, in step S3, for high-priority interrupts, the task scheduler sequencer caches the register status and sends a message packet to notify the CPU for collaborative processing, including: step S321, the task scheduler sequencer reads the register status related to the current interrupt and caches it to the sequencer local register; step S322, generates a 128-bit message packet through a message trigger instruction; step S323, sends the message packet to the CPU interrupt queue through the bus, and sets the message sending status flag; step S324, after the CPU receives the message packet, it reads the cached data and performs logical judgment; step S325, after the CPU completes the processing, it sends a confirmation signal to the task scheduler sequencer, and the task scheduler sequencer clears the local register cache and resets the relevant status flags to complete the interrupt processing closed loop.

[0014] Preferably, in step S321, the register status includes a DMA address pointer and a transfer count.

[0015] Preferably, in step S323, the message packet includes an interrupt type, a cache address, and a timestamp.

[0016] Beneficial effects: Due to the adoption of the above technical solution, the present invention pre-programs the interrupt processing instruction sequence through the hardware sequencer, realizes the hardware autonomous response of low-priority interrupts, avoids the overhead of traditional CPU context switching, and significantly improves the processing efficiency in high-frequency interrupt scenarios; at the same time, it handles high-priority interrupts through a lightweight message notification mechanism, reduces the bandwidth occupied by register save / restore, and reduces system power consumption while ensuring real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flow chart of the method of the present invention; Figure 2 It is a RAM structure diagram including Sequencer instructions and Message instructions of the present invention; Figure 3 This is the overall structure diagram of the Sequencer of the present invention; Figure 4 This is the architecture diagram of the Message command processing module of the present invention. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0019] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0021] Reference Figure 1 The present invention provides a SoC interrupt processing method based on a hardware sequencer, comprising: step S1, pre-programming an interrupt processing instruction sequence into an instruction RAM, and configuring the instruction set, sequence processor, and interrupt priority policy of the task scheduler sequencer; step S2, the task scheduler sequencer receives an interrupt signal and selects a corresponding sequence processor according to the interrupt type; step S3, for low-priority interrupts, the task scheduler sequencer directly executes a pre-stored instruction sequence to complete the interrupt response; for high-priority interrupts, the task scheduler sequencer caches register status and sends a message packet to notify the CPU for collaborative processing.

[0022] Specifically, in an embodiment of the present invention, in order to solve the problems of high CPU context switching overhead, insufficient real-time performance and low energy efficiency in traditional SoC interrupt processing, a pre-programmed instruction execution mechanism of a hardware sequencer is introduced, combined with priority-driven interrupt diversion technology, thereby avoiding the waste of resources caused by the CPU frequently participating in low-priority interrupt processing, achieving zero context switching response in high-frequency interrupt scenarios, and through the hardware automatic state cache and message packet notification mechanism, significantly reducing the overall power consumption of the system while ensuring the real-time performance of high-priority interrupts.

[0023] As a preferred embodiment of the present invention, in the above step S1, a data structure is pre-programmed in the software so that the Sequencer can periodically process the instructions stored in the instruction RAM after receiving a specific trigger or interrupt signal. Figure 2 The software pre-programs the data structure of the instruction RAM that needs to be processed cyclically after the sequencer receives the corresponding trigger / interrupt.

[0024] Specifically, the software's pre-programmed data structure uses a hierarchical index design, where indexes 1, 2, and 3 represent different groups of instruction sequences. Each group contains several sequentially executed instructions, each with a specific opcode. Once triggered, the Sequencer periodically reads and executes instructions from the corresponding group based on the index. This structure supports multi-task triggering, quickly locates instruction sequences through indexing, and achieves efficient periodic processing.

[0025] As a preferred embodiment of the present invention, referring to Table 1, the hardware sequencer supports the following instruction sets: control command, timer instruction, waitTrigR instruction, message trigger instruction, list_end task sequence end instruction, and reserved instruction. Each instruction corresponds to a unique opcode and is permanently stored in the instruction RAM. The instruction set is shown in Table 1 below: Table 1 List of instructions supported by the hardware sequencer

[0026] The detailed instructions are explained as follows: Control command: Control command, used to assign a value of '0' or '1' to a numbered signal.

[0027]

[0028] Timer: Timing instruction

[0029] waitTrigR: Wait for trigger instruction

[0030] Message trigger: message trigger instruction

[0031] list_end: Task sequence end command

[0032] Specifically, the Sequencer executes instructions from the instruction RAM in sequence by decoding the opcode (such as 0x010 corresponding to waitTrigR) until it encounters the task sequence end command list_end or an external interrupt. Figure 2 The hierarchical index structure of the instruction sequence can be mapped to a combination of the above opcodes to achieve periodic or event-driven task scheduling.

[0033] In traditional SoC interrupt handling, if a high-priority interrupt (such as a hardware error) or a latency-sensitive interrupt is triggered while the CPU is restoring the context of a low-priority interrupt, the system is forced into a nested interrupt processing flow. This nested mechanism leads to two key problems: First, multi-level interrupt nesting significantly increases the depth of the operating system's call stack, potentially causing a stack overflow; second, frequent interrupt preemption disrupts the operating system's task scheduling, causing critical services to time out due to a lack of timely CPU resources.

[0034] To address this issue, and to optimize the system stability and real-time performance issues associated with nested interrupts, a preferred embodiment of the present invention employs a dual-sequence processor parallel architecture to isolate and process interrupt requests of different priorities. The sequence processors include: Sequence processor LP1, which handles DMA interrupts and features a standard "DMA status read → interrupt clear → data parsing trigger" processing pipeline; and Sequence processor LP2, which handles I / O device interrupts and dynamically adjusts bus priorities via a group enable mechanism. Sequence processors LP1 and LP2 utilize a parallel architecture to simultaneously handle different types of interrupt requests.

[0035] Specifically, in this embodiment of the present invention, dual sequence processors (LP1 and LP2) utilize a hardware-level task isolation mechanism to ensure that interrupt requests of different priorities can be processed in parallel, without relying on CPU software scheduling. Sequence processor LP1 optimizes fixed pipeline operations for DMA interrupts, automatically completing status reading, interrupt clearing, and data parsing triggering at the hardware level, reducing CPU intervention. Sequence processor LP2 optimizes the response efficiency of I / O device interrupts through dynamic bus priority adjustment, avoiding delays caused by bus contention.

[0036] Furthermore, this architecture employs a hardware arbitration strategy. When a high-priority interrupt (such as a hardware error) is triggered, the sequencer LP2 immediately preempts bus resources and caches the processing status of the current low-priority interrupt, ensuring that critical tasks are prioritized. Furthermore, pre-allocated interrupt stack space and a state snapshot recovery mechanism effectively prevent stack overflows caused by nested multi-level interrupts.

[0037] In particular, the hardware sequencer directly handles over 90% of regular interrupts, significantly reducing the frequent DDR read and write operations required by traditional methods. Actual measurement data shows that DDR bandwidth usage for regular interrupt processing has dropped from 40MB / s to under 4MB / s. The freed-up bandwidth significantly increases the throughput of key services such as video encoding by 15% (for example, from 1080p 30fps to 35fps).

[0038] As a preferred embodiment of the present invention, the hardware parallel architecture of the dual sequence processors (LP1 and LP2) provides a physical basis for the interrupt priority policy, and the interrupt priority policy includes: a static policy, in which DMA interrupts are handled by the sequence processor LP1 and I2C / SSD interrupts are handled by the sequence processor LP2; and a dynamic policy, in which a high-priority device preempts the processing right of a low-priority interrupt.

[0039] Specifically, in an embodiment of the present invention, the interrupt priority strategy adopts a hybrid scheduling mechanism that combines static and dynamic scheduling. Under the static strategy, DMA interrupts are fixedly assigned to sequence processor LP1 for processing, while storage device interrupts such as I2C and SSD are exclusively handled by sequence processor LP2. This hardware-level task division ensures efficient response to basic interrupts. At the same time, the dynamic strategy allows critical services to trigger instant preemption through priority tags. When a high-priority interrupt arrives, the current low-priority processing sequence will be automatically paused and the state will be saved. After the high-priority task is completed, execution will be automatically resumed.

[0040] As a preferred embodiment of the present invention, the task scheduler Sequencer receives an external interrupt signal through sequence triggers 1 to 8 (SeqTrig_1 to SeqTrig_8) and selects a corresponding sequence processor according to the interrupt type. Figure 3 Interrupt signals are input to the Sequencer through sequence triggers 1 (SeqTrig_1) through 8 (SeqTrig_8). Each trigger corresponds to a specific interrupt source type. The sequence trigger control module monitors the status of each trigger in real time. When a valid interrupt signal is detected, it first decodes the interrupt source using the trigger index (Trig IDX). Then, based on a preset static mapping, DMA interrupts are assigned to sequencer LP1 and I2C / SSD interrupts to sequencer LP2. This selection process is implemented directly through hardware wiring, requiring no software intervention, ensuring interrupt distribution latency is controlled within three clock cycles. Furthermore, manual register triggers and internal task scheduler triggers (Triggers from the Sequencer) can serve as backup paths for debugging or special scenarios.

[0041] As a preferred embodiment of the present invention, in step S3, for low-priority interrupts, the task scheduler sequencer directly executes a pre-stored instruction sequence to complete the interrupt response, including: step S311, the task scheduler sequencer reads the pre-stored instruction sequence from the instruction RAM; step S312, directly executing the pre-stored instruction sequence through the hardware logic circuit of the task scheduler sequencer, such as reading the DMA status register, clearing the interrupt flag bit and triggering the data parsing module; step S313, marking the interrupt processing completion through the SEQSTAT register; and updating the interrupt processing timestamp register, releasing the occupied hardware resources and sending a processing completion notification to the system event monitoring module.

[0042] Specifically, refer to Figure 3 In this embodiment of the present invention, when a low-priority interrupt is triggered, the task scheduler (Sequencer) directly reads a preprogrammed instruction sequence from the instruction random access memory (RAM) and executes operations such as reading the DMA status register and clearing the interrupt flag through a dedicated hardware path. During execution, the output buffer (OutputBuffer) coordinates hardware resources in real time via a set / clear control unit. Upon completion, the level signal generator triggers an update to the SEQSTAT register status and simultaneously triggers the ready indicator to send a completion notification to the system event monitoring module. The entire process is closed-loop at the hardware level, eliminating the need for the CPU to perform the following operations: 1) save the current task context to the DDR; 2) switch to the interrupt handler; and 3) restore the context and return to the original task.

[0043] Test data shows that this hardware processing mechanism significantly reduces interrupt response time from over 1000ns required by traditional software processing to less than 200ns (including the entire process of instruction sequence fetching and command execution), reducing latency by 80%. This purely hardware processing solution not only significantly improves system real-time performance but also avoids the overhead of CPU context switching, allowing the CPU to focus on high-priority tasks. Furthermore, the collaborative operation of dedicated hardware modules such as the output buffer and the set / clear control unit ensures deterministic and reliable interrupt handling, providing high-performance interrupt response for real-time systems.

[0044] As a preferred embodiment of the present invention, in step S3, for high-priority interrupts, the task scheduler sequencer caches the register status and sends a message packet to notify the CPU for collaborative processing, including: step S321, the task scheduler sequencer reads the register status related to the current interrupt and caches it to the sequencer local register; wherein the register status includes a DMA address pointer and a transfer count; step S322, generating a 128-bit message packet containing the interrupt type, cache address, and timestamp through a message trigger instruction; step S323, sending the message packet to the CPU interrupt queue via the bus, and setting the message sending status flag; step S324, after receiving the message packet, the CPU reads the cached data and performs logical judgment; step S325, after completing the processing, the CPU sends a confirmation signal to the task scheduler sequencer, and the task scheduler sequencer clears the local register cache and resets the relevant status flags to complete the interrupt processing closed loop.

[0045] Specifically, refer to Figure 3 and Figure 4 In this embodiment of the present invention, high-priority interrupt processing utilizes a hybrid mechanism combining hardware acceleration and CPU collaboration. When a high-priority interrupt is triggered, the task scheduler, the Sequencer, rapidly captures key register states (including the DMA address pointer and transfer count) through dedicated hardware channels and stores them in the local cache. Subsequently, the message triggers initiate a hardware-level message encapsulation process, where the Message Packer encodes key information such as the interrupt type, physical address, and timestamp into a standard 128-bit message packet. The Message Packer, integrated within the message processing unit, rapidly encapsulates the 128-bit message using hardware logic. This message packet is sent to the CPU interrupt queue via the Bus Interface as a high-priority transaction. Simultaneously, the Status Flags register within the message processing unit updates the transmission status in real time. Upon receiving the message through the dedicated interrupt channel, the CPU immediately triggers the exception handler. Upon completion of processing, it notifies the Sequencer through an acknowledgment signal to release hardware resources. Throughout this process, the CPU context save time is significantly reduced from 333ns in traditional solutions to 50ns. Furthermore, by transmitting only a simplified message packet rather than the full context, DDR bandwidth usage is reduced by 95%. This hardware-optimized collaborative processing mechanism not only ensures immediate response to high-priority interrupts, but also greatly reduces system resource overhead.

[0046] It can be seen that the present invention has achieved a huge breakthrough in interrupt processing performance. As shown in Table 2 below, compared with the existing technology, the present invention has brought significant performance improvements through an innovative hardware acceleration architecture: the single interrupt context switch time is significantly shortened from 333ns to 50ns, an improvement of up to 85%; the DDR bandwidth occupancy is reduced from 2-4KB to only 0-128bit, a reduction of 95%-100%, greatly alleviating the pressure on memory bandwidth. In terms of system resource utilization, the CPU computing power utilization rate is increased from less than 40% to more than 85%, an increase of 112%. At the same time, the system dynamic power consumption is reduced from 200mW to 120mW, and the energy efficiency is improved by 40%. More importantly, the real-time interrupt response delay is shortened from 3-5μs to less than 1μs, an improvement of 60%-80%, providing more reliable low-latency protection for real-time systems. The comprehensive improvement of these performance indicators gives the present invention a significant advantage in application scenarios with strict interrupt response requirements, such as embedded systems and real-time control systems, and provides an innovative interrupt processing solution for the next generation of high-performance SoC design.

[0047] Table 2 Comparison of performance indicators of hardware sequencer interrupt handling solutions

[0048] The following are two typical application examples: Example 1: CPU-free processing of NIC DMA transfer interrupts When the image sensor completes a frame of data acquisition and triggers a DMA interrupt: (1) Sequencer response phase 1.1. After the image sensor completes a frame of data acquisition, it sends an interrupt signal to the task scheduler Sequencer through the DMA controller, and selects the sequence processor LP1 according to the interrupt type; 1.2. Sequence processor LP1 automatically loads the pre-programmed sensor data interrupt processing instruction sequence from the fixed address (0x100) of the instruction RAM.

[0049] (2) Sequence execution phase 2.1. Sequencer LP1 sends a DMA_REG_READ command to read the transfer status from the DMA controller. 2.2. Execute the FIFO_CLEAR command to clear the sensor buffer FIFO; 2.3. Through the IMAGE_PROC_START message, directly notify the image processing module to start subsequent processing.

[0050] (3) Result feedback stage 3.1. The interrupt processing is marked as completed through the SEQSTAT register.

[0051] This process achieves full-link acceleration through pure hardware logic, with total latency strictly controlled within 50 nanoseconds. This process is completely independent of CPU scheduling, completely eliminating context switching overhead, and achieving zero physical layer access to DDR memory.

[0052] Example 2: Real-time response optimization of I2C device interrupts When an I2C slave device (temperature sensor / EEPROM) connected to the SoC triggers a transmission interrupt, traditional CPU processing risks response timeout due to operating system scheduling delays. For example, the SMBus protocol requires an ACK response time of ≤12μs. However, the hardware sequencer, directly connected to the bus controller at the physical layer, enables deterministic, low-latency responses. The specific process is as follows: (1) Interrupt capture and status reading 1.1. The I2C controller detects that the device is sending data and triggers an interrupt signal (such as a change in the SDA line level). The sequence processor LP2 captures the interrupt within 100ns and reads the I2C status register to obtain the slave address, data length, etc. 1.2. Cache the current I2C bus status (such as the I2C clock counter value) to the sequencer local register.

[0053] (2) Hardware sequence fast response 2.1. Sequence processor LP2 executes the predefined "I2C interrupt processing sequence": sends the I2C_ACK_GENERATE command to generate an ACK response signal; triggers the DATA_FETCH command to read data from the I2C data register; and stores the data into the SoC internal FIFO through the FIFO_WRITE command.

[0054] 2.2. CPU lightweight collaboration: If the data needs further processing (such as temperature threshold determination), the task scheduler Sequencer sends a message packet containing a summary of information such as interrupt type, cache address, timestamp, etc. to the CPU through MESSAGE_TRIGGER.

[0055] (3) CPU executes non-real-time logic 3.1. After receiving the message packet, the CPU reads the cached data and performs logical judgment; 3.2. After the CPU completes the processing, it sends a confirmation signal to the task scheduler sequencer. The task scheduler sequencer clears the local register cache and resets the relevant status flags to complete the interrupt processing closed loop.

[0056] This shows that through the hardware replacement mechanism of context switching, the CPU only needs to parse lightweight message packets and execute application logic (excluding the register save / restore process), and the single interrupt processing time is compressed from 3μs in the traditional solution to 500ns, achieving a 6-fold acceleration.

[0057] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A SoC interrupt processing method based on hardware sequencer, characterized in that: include: Step S1, pre-programming the interrupt handling instruction sequence into the instruction RAM, and configuring the instruction set, sequencer and interrupt priority strategy of the task scheduler sequencer; In step S2, the task scheduler sequencer receives an interrupt signal and selects a corresponding sequence processor according to the interrupt type. In step S3, for low-priority interrupts, the task scheduler sequencer directly executes a pre-stored instruction sequence to complete the interrupt response. For high-priority interrupts, the task scheduler sequencer caches register status and sends a message packet to notify the CPU for collaborative processing.

2. The SoC interrupt processing method based on hardware sequencer according to claim 1, characterized in that: In step S1, the sequence processor includes: a sequence processor LP1 for DMA interrupt processing, with a built-in "DMA status reading → interrupt clearing → data parsing trigger" standard processing pipeline; a sequence processor LP2 for I / O device interrupt processing, dynamically adjusting bus priority through a group enable mechanism; wherein, the sequence processor LP1 and the sequence processor LP2 are designed with a parallel architecture.

3. The SoC interrupt processing method based on hardware sequencer according to claim 2, characterized in that: In step S1, the interrupt priority strategy includes: a static strategy, in which DMA interrupts are processed by the sequence processor LP1 and I2C / SSD interrupts are processed by the sequence processor LP2; and a dynamic strategy, in which a high-priority device preempts the low-priority interrupt processing right.

4. The SoC interrupt processing method based on hardware sequencer according to claim 1, characterized in that: In step S1, the instruction set includes: control commands, timing instructions, wait trigger instructions, message trigger instructions and task sequence end commands; wherein each instruction corresponds to a unique operation code and is fixedly stored in the instruction RAM.

5. The SoC interrupt processing method based on hardware sequencer according to claim 1, characterized in that: In step S3, for low-priority interrupts, the task scheduler sequencer directly executes a pre-stored instruction sequence to complete the interrupt response, including: step S311, the task scheduler sequencer reads the pre-stored instruction sequence from the instruction RAM; step S312, directly executing the pre-stored instruction sequence through the hardware logic circuit of the task scheduler sequencer; step S313, marking the interrupt processing completion through the SEQSTAT register.

6. The SoC interrupt processing method based on hardware sequencer according to claim 5, characterized in that: The step S312 includes: reading the DMA status register, clearing the interrupt flag, and triggering the data analysis module.

7. The SoC interrupt processing method based on hardware sequencer according to claim 6, characterized in that: The step S313 includes: updating the interrupt processing timestamp register, releasing occupied hardware resources, and sending a processing completion notification to the system event monitoring module.

8. The SoC interrupt processing method based on hardware sequencer according to claim 1, characterized in that: In step S3, for high-priority interrupts, the task scheduler sequencer caches the register status and sends a message packet to notify the CPU for collaborative processing, including: step S321, the task scheduler sequencer reads the register status related to the current interrupt and caches it to the sequencer local register; step S322, generates a 128-bit message packet through a message trigger instruction; step S323, sends the message packet to the CPU interrupt queue through the bus, and sets the message sending status flag; step S324, after the CPU receives the message packet, reads the cached data and performs logical judgment; step S325, after the CPU completes the processing, it sends a confirmation signal to the task scheduler sequencer, and the task scheduler sequencer clears the local register cache and resets the relevant status flags to complete the interrupt processing closed loop.

9. The SoC interrupt processing method based on hardware sequencer according to claim 8, characterized in that: In step S321, the register status includes a DMA address pointer and a transfer count.

10. The SoC interrupt processing method based on hardware sequencer according to claim 9, characterized in that: In step S323, the message packet includes an interrupt type, a cache address, and a timestamp.

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