Return address backup method and device, computer equipment and storage medium

Abstract

The invention provides a return address backup method and device, computer equipment and a storage medium, and the method comprises the steps: obtaining a return address stack (RAS) corresponding to a first pipeline processing unit, and configuring RASs corresponding to at least one second pipeline processing unit; obtaining a to-be-processed instruction sequence, and performing pipeline processing on the to-be-processed instruction sequence; in the process of performing assembly line processing on the instruction sequence to be processed, responding to assembly line flushing operation initiated by a target assembly line processing unit, copying an RAS corresponding to the target assembly line processing unit into an RAS corresponding to the first assembly line processing unit, the target assembly line processing unit is one of the at least one second assembly line processing unit. Based on the scheme of the invention, the RAS backup can be realized by setting the RAS in the second assembly line processing unit, so that the influence of assembly line scouring on the RAS is eliminated, and the accuracy of the RAS for predicting the return address is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor micro-architecture, in particular to a return address backup method and device, computer equipment and storage medium. BACKGROUND

[0002] In the field of processor micro-architecture, RAS (Return Address Stack) can well solve the prediction problem of the return address of the RETURN instruction. However, once an instruction such as a conditional jump instruction that can initiate a pipeline flush operation is encountered, the RAS prediction error of the return address of the RETURN instruction occurs, and a method is needed to avoid the influence of the pipeline flush and improve the accuracy of the RAS prediction of the return address. SUMMARY

[0003] The present application provides a return address backup method, device, computer equipment and storage medium.

[0004] The first aspect of the present application provides a return address backup method applied to a processor, the processor including a plurality of pipeline processing units, the plurality of pipeline processing units including a first pipeline processing unit at a first pipeline stage and at least one second pipeline processing unit supporting the initiation of a pipeline flush operation, and the method comprising: obtaining a return address stack (RAS) corresponding to the first pipeline processing unit and configuring a respective RAS corresponding to each of the at least one second pipeline processing unit; obtaining a sequence of instructions to be processed and performing pipeline processing on the sequence of instructions to be processed; in the process of performing pipeline processing on the sequence of instructions to be processed, in response to a pipeline flush operation initiated by a target pipeline processing unit, copying the RAS corresponding to the target pipeline processing unit to the RAS corresponding to the first pipeline processing unit, the target pipeline processing unit being one of the at least one second pipeline processing unit.

[0005] In an optional embodiment of the present application, in the process of performing pipeline processing on the sequence of instructions to be processed, after the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit in response to the pipeline flush operation initiated by the target pipeline processing unit, the method further comprises: performing return address prediction according to the RAS corresponding to the first pipeline processing unit.

[0006] In an optional embodiment of the present application, the sequence of instructions to be processed includes a CALL instruction, a RETURN instruction and a return address prediction interference instruction, and the return address prediction interference instruction includes a conditional jump instruction.

[0007] In an optional embodiment of the present application, the pipeline processing is performed on the instruction sequence to be processed, including: determining an instruction input sequence according to the instruction sequence to be processed, and inputting the CALL instruction, the RETURN instruction and the conditional jump instruction in the instruction sequence to be processed into the processor in sequence according to the instruction input sequence for instruction processing, wherein the CALL instruction controls the in-stack operation on the RAS, the RETURN instruction controls the out-stack operation on the RAS, and the conditional jump instruction controls the branch processing operation of the processor.

[0008] In an optional embodiment of the present application, the RAS corresponding to each of the at least one second pipeline processing unit is configured, including: allocating an independent address stack heap storage space for each of the at least one second pipeline processing unit when the processor is initialized, so as to configure the RAS corresponding to each of the at least one second pipeline processing unit.

[0009] In an optional embodiment of the present application, the return address prediction is performed according to the RAS corresponding to the first pipeline processing unit, including: obtaining a target return address from the RAS corresponding to the first pipeline processing unit in response to the received RETURN instruction; performing the return address prediction according to the target return address.

[0010] In an optional embodiment of the present application, further including: maintaining the synchronization update of the RAS corresponding to the first pipeline processing unit and the at least one second pipeline processing unit when the processor normally executes instructions.

[0011] A second aspect of the embodiments of the present application provides a return address backup device applied to a processor, the processor including a plurality of pipeline processing units, the plurality of pipeline processing units including a first pipeline processing unit at a first pipeline stage and at least one second pipeline processing unit supporting the initiation of a pipeline flushing operation, including: a configuration module configured to obtain a return address stack heap RAS corresponding to the first pipeline processing unit, and configure the RAS corresponding to each of the at least one second pipeline processing unit; a processing module configured to obtain an instruction sequence to be processed, and perform pipeline processing on the instruction sequence to be processed, wherein, in the process of performing pipeline processing on the instruction sequence to be processed, in response to a pipeline flushing operation initiated by a target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied as the RAS corresponding to the first pipeline processing unit, and the target pipeline processing unit is one of the at least one second pipeline processing unit.

[0012] In a third aspect, the present application provides a computer device, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the steps of any of the above methods when executing the computer program.

[0013] In a fourth aspect, the present application provides a computer readable storage medium, storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above methods. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings: Figure 1 An application scenario of instruction call in processor microarchitecture provided by an embodiment of the present application; Figure 2 A flowchart of RAS stack-in and stack-out provided by an embodiment of the present application; Figure 3 A principle diagram of return address prediction error provided by an embodiment of the present application; Figure 4 A flowchart of return address backup provided by an embodiment of the present application; Figure 5 A principle diagram of RAS backup mechanism in five-stage pipeline processor provided by an embodiment of the present application; Figure 6 A flowchart of return address prediction provided by an embodiment of the present application; Figure 7 A detailed step diagram of performing return address prediction provided by an embodiment of the present application; Figure 8 A structure diagram of return address backup device provided by an embodiment of the present application; Figure 9 A structure diagram of computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0015] The technical solutions in the present application will be described clearly and exhaustively below with reference to the drawings. In the description of the embodiments of the present application, unless otherwise specified, “ / ” represents or, for example, A / B can represent A or B: “and / or” in the text only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, in the description of the embodiments of the present application, “multiple” means two or more than two.

[0016] Hereinafter, the terms "first" and "second" are used only for the purpose of description, and cannot be understood as implying or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features.

[0017] Please refer to Figure 1 In the processor micro-architecture, RAS is a commonly used return address prediction technology, which is generally used for the prediction of function return addresses. Function call and return use CALL instruction and RETURN respectively, wherein the address of the CALL instruction for calling the subroutine (such as the starting address of a certain function) is fixed each time, but the subroutine can be called at many places in the main program, so the address of return will change; the target address of the RETURN instruction is always the next instruction of the CALL instruction last time. As shown in Figure 1 , the main program calls the subroutine 1 through the Call Mul instruction, and calls the subroutine 2 through Call Sub in the subroutine 1.

[0018] Referring to Figure 2 , the processor uses a last-in first-out memory to save the address of the next CALL instruction of the current CALL instruction return address, and the return address stored in the memory is popped out when the RETURN instruction is executed to realize the jump prediction of the RETURN instruction. The memory and the stack work in the same way, so it is called return address stack (RAS), and the return address is stored when the CALL instruction is executed, and the return address is obtained when the RETURN instruction is executed. As shown in Figure 2 , the address of Mul is first pushed into the stack, followed by the address of Add, and finally the address of Sub, and when the RETURN instruction is executed, the addresses are taken out in the reverse order.

[0019] However, referring to Figure 3For example, in a classic five-stage pipelined processor, when the first CALL instruction comes, the RAS unit of the IFU fills the return address of the CALL instruction into the stack. Then the processor fetches the conditional branch instruction and makes a branch prediction, the result of which is not to branch. Then the processor fetches instructions sequentially and fetches the second CALL instruction, the RAS fills the return address of the second CALL instruction into the stack. When the EXU (execution unit) finds that the branch direction prediction of the conditional branch instruction by the IFU is wrong, the actual should be branch, the ALU (arithmetic logic unit) flushes the CALL instruction of the DEC (decoding unit) and executes the destination address of the conditional branch instruction, the second CALL instruction is not actually executed, however, the RAS in the IFU has been updated by the second CALL instruction and contains two return addresses. When the first CALL instruction executes the RETURN instruction to return, the return address provided by the RAS is actually the return address of the second CALL instruction which is flushed, not the return address of the first CALL instruction, eventually leading to a return address prediction error.

[0020] To solve the above problems, the main scheme provided by the application includes: in order to meet the demand for return address prediction accuracy, the stored return address needs to be updated synchronously when RAS encounters pipeline flushing, and through research, a backup return address stack is designed for each pipeline processing unit that can initiate flushing pipeline, and the backup return stack will also perform stack and de-stack operations respectively when encountering CALL and RETURN instructions, maintaining the return address stack of the corresponding pipeline processing unit. Once the pipeline initiates the flushing flow operation, the backup RAS of the corresponding pipeline processing unit will restore the RAS content to the RAS of the IFU, ensuring that the RAS stack of the IFU always saves the RAS content at the time of flushing flow, and does not include the influence caused by the stack and de-stack of the CALL and RETURN instructions flushed in the previous stage flow. The method of the application is applied to a processor, the processor includes a plurality of pipeline processing units, the plurality of pipeline processing units include a first pipeline processing unit at a first pipeline stage, and at least one second pipeline processing unit supporting initiation of a pipeline flushing operation, and the specific implementation steps include: first, obtaining a return address stack RAS corresponding to the first pipeline processing unit, and configuring at least one second pipeline processing unit corresponding to the RAS; obtaining a to-be-processed instruction sequence, and performing pipeline processing on the to-be-processed instruction sequence; then, in the process of pipeline processing on the to-be-processed instruction sequence, in response to a pipeline flushing operation initiated by a target pipeline processing unit, copying the RAS corresponding to the target pipeline processing unit as the RAS corresponding to the first pipeline processing unit, and the target pipeline processing unit is one of the at least one second pipeline processing unit. By using the method provided by the application, the backup of the RAS can be realized, so as to eliminate the influence of pipeline flushing on the RAS and improve the accuracy of the return address prediction of the RAS.

[0021] Based on Figure 1 the scene shown in the figure, the return address backup method provided by the embodiment of the application will be described in detail. Figure 4 - Figure 7 , the return address backup method provided by the embodiment of the application will be described in detail.

[0022] Please refer to Figure 4 , Figure 4 is a flowchart of a return address backup method provided by the embodiment of the application. As Figure 4 shown, applied to a processor, the processor includes a plurality of pipeline processing units, the plurality of pipeline processing units include a first pipeline processing unit at a first pipeline stage, and at least one second pipeline processing unit supporting initiation of a pipeline flushing operation, the method of the embodiment of the application can include the following steps S101-S103.

[0023] S101, acquire a return address stack RAS corresponding to the first pipeline processing unit, and configure a respective RAS corresponding to each of the at least one second pipeline processing unit.

[0024] Specifically, the processor referred to in the embodiment refers to a central processing unit (CPU) adopting a pipeline architecture, which includes a plurality of sequentially connected pipeline processing units; the pipeline processing unit refers to a hardware module in the processor pipeline that completes a specific processing function, including a fetch unit, a decode unit, an execution unit, etc.; the first pipeline stage refers to the pipeline stage in the processor pipeline that first processes instructions; the first pipeline processing unit refers to the processing unit located at the first pipeline stage, which is responsible for the initial processing of instructions; the second pipeline processing unit refers to the processing unit located after the first pipeline stage, which can detect and handle branch prediction error and other abnormal situations; the pipeline flush operation refers to the operation of clearing instructions in the subsequent pipeline and re-fetching instructions when a branch prediction error or an abnormality is detected.

[0025] In a possible implementation, acquiring the RAS corresponding to the first pipeline processing unit and configuring the respective RAS corresponding to each of the at least one second pipeline processing unit refers to: in the initialization stage of the processor, allocating a main return address stack storage space for the first pipeline processing unit, and allocating an independent backup return address stack storage space for each second pipeline processing unit; in the running process of the processor, keeping the return address stack of the first pipeline processing unit and the return address stack of each second pipeline processing unit updated synchronously.

[0026] S102, acquire a to-be-processed instruction sequence, and pipeline process the to-be-processed instruction sequence.

[0027] Specifically, the to-be-processed instruction sequence referred to in the embodiment refers to a program instruction stream containing function call instructions, function return instructions, and other instructions that can affect return address prediction.

[0028] In a possible implementation, acquiring a to-be-processed instruction sequence and pipeline processing the to-be-processed instruction sequence refers to: the processor sequentially reads instructions from an instruction cache, processes the instructions through pipeline stages such as fetch, decode, and execution; when a function call instruction is encountered, a return address is pushed into the return address stack of the first pipeline processing unit and the return address stacks of each second pipeline processing unit; when a function return instruction is encountered, a predicted return address is popped from the return address stack.

[0029] S103, in the process of pipelining the to-be-processed instruction sequence, in response to a pipeline flush operation initiated by a target pipelining processing unit, copying the RAS corresponding to the target pipelining processing unit to the RAS corresponding to the first pipelining processing unit, the target pipelining processing unit being one of the at least one second pipelining processing unit.

[0030] Specifically, the target pipelining processing unit referred to in the embodiment refers to a second pipelining processing unit that detects a branch prediction error or an exception and triggers a pipeline flush operation; the RAS corresponding to the target pipelining processing unit refers to a backup return address stack maintained by the second pipelining processing unit; and the RAS corresponding to the first pipelining processing unit refers to a main return address stack.

[0031] In a possible implementation, in the process of pipelining the to-be-processed instruction sequence, in response to a pipeline flush operation initiated by a target pipelining processing unit, copying the RAS corresponding to the target pipelining processing unit to the RAS corresponding to the first pipelining processing unit, the target pipelining processing unit being one of the at least one second pipelining processing unit refers to: when a certain second pipelining processing unit detects a branch prediction error, first saving the current processor state, then copying the content of the backup return address stack maintained by the second pipelining processing unit to the main return address stack of the first pipelining processing unit in its entirety, and finally performing a pipeline flush operation and re-fetching instructions.

[0032] More specifically, with reference to Figure 5 In the scheme proposed in the present application, a backup return address stack is designed for each flow stage that can initiate a flush pipeline, and the backup return stacks also perform stack-in and stack-out operations when encountering CALL and RETURN instructions, thereby maintaining the return address stacks of the corresponding pipelines. Once the pipeline initiates a flush pipeline operation, the backup RAS of the corresponding flow stage will restore the RAS content to the RAS of the IFU in its entirety, ensuring that the RAS stack of the IFU always stores the RAS content at the time of flush pipeline, and does not contain the impact caused by the stack-in and stack-out of the CALL and RETURN instructions that are flushed in the previous stage pipeline. Thus, the RAS of the IFU can avoid the impact caused by the pipeline flush, and ensure the accuracy of the return address prediction of the RAS.

[0033] In this embodiment, by configuring an independent backup return address stack for each second pipelined processing unit, and copying the backup return address stack of the detected abnormal second pipelined processing unit to the main return address stack of the first pipelined processing unit during a pipeline flush operation, the problem of inaccurate return address prediction after pipeline flushing in traditional processors is effectively solved. More specifically, this embodiment ensures the reliability of the return address stack through a multi-copy mechanism, enabling accurate recovery even in the event of branch prediction errors, thereby eliminating the impact of pipeline flushing on the RAS and improving the accuracy of return address prediction by the RAS.

[0034] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating the return address prediction process provided in one embodiment of this application. Figure 6 As shown, the method in this application embodiment may include the following step S104, which can be used as a step in... Figure 4 The example shown is executed after step S103.

[0035] S104, predict the return address based on the RAS corresponding to the first pipeline processing unit.

[0036] Specifically, the return address prediction involved in this application embodiment refers to the process of predicting and obtaining the address of the next instruction to be executed in advance based on the historical return address information stored in the return address stack when the processor executes a function return instruction. This prediction process is used to reduce pipeline pauses caused by waiting for the actual return address calculation and improve processor execution efficiency.

[0037] In one possible implementation, predicting the return address based on the RAS corresponding to the first pipeline processing unit means that when the pipeline processing unit encounters a function return instruction, it pops the return address stored at the top of the stack from the main return address stack corresponding to the first pipeline processing unit and sends this address as the prediction result to the instruction fetch unit. The instruction fetch unit prefetches instructions from the instruction cache based on the predicted return address and continues to execute subsequent pipeline processing. At the same time, the execution unit calculates the actual return address in parallel. If the predicted address is inconsistent with the actual address, a pipeline flushing operation is triggered and the return address stack is corrected.

[0038] In this embodiment, return address prediction is performed based on the RAS corresponding to the first pipeline processing unit. Through the synchronization and recovery mechanism of the multi-level return address stack, the accuracy of return address prediction and the execution efficiency of the processor are effectively improved.

[0039] based on Figure 4 The embodiment shown illustrates another embodiment of this application.

[0040] In this embodiment of the application, the sequence of instructions to be processed includes a CALL instruction, a RETURN instruction, and a return address prediction interference instruction, wherein the return address prediction interference instruction includes a conditional jump instruction.

[0041] Specifically, in the embodiments of this application, the CALL instruction refers to an instruction used to trigger a function call, the execution process of which includes pushing the return address onto the return address stack (RAS) and jumping to the target function address; the RETURN instruction refers to an instruction used to return from a function, the execution process of which includes popping the return address from the return address stack and jumping to that address; the return address prediction interference instruction refers to an instruction that may affect the accuracy of the return address stack, including but not limited to conditional jump instructions, indirect jump instructions, and exception handling instructions.

[0042] In one possible implementation, identifying the instruction type in the sequence of instructions to be processed and performing the corresponding operation means: When a CALL instruction is detected, the address of the next instruction of the current instruction is used as the return address and is simultaneously pushed onto the main return address stack corresponding to the first pipeline processing unit and the backup return address stack corresponding to each second pipeline processing unit. Alternatively, when a RETURN instruction is detected, the top return address is popped from the main return address stack corresponding to the first pipeline processing unit as the predicted address, and a prefetch operation is performed based on that address. Alternatively, when a return address prediction interference instruction is detected, the update operation of the return address stack is paused until the actual execution path of the instruction is determined; if the conditional jump instruction jumps and the target address is inconsistent with the current function call stack, a correction operation is performed on the return address stack.

[0043] In another possible implementation Figure 4 Step S102 in the illustrated embodiment involves pipelined processing of the instruction sequence to be processed, including: The instruction input order is determined according to the sequence of instructions to be processed. The CALL instruction, RETURN instruction, and conditional jump instruction in the sequence of instructions to be processed are sequentially input into the processor for instruction processing according to the instruction input order. The CALL instruction is used to control the execution of a push operation on the RAS, the RETURN instruction is used to perform a pop operation on the RAS, and the conditional jump instruction is used by the processor to perform a branch processing operation.

[0044] Specifically, the instruction input order described in this application embodiment refers to the original execution order of the instruction sequence to be processed in the program flow. The processor processes the CALL instruction, RETURN instruction and conditional jump instruction in sequence according to this order, and dynamically maintains the synchronization state of RAS.

[0045] Furthermore, during the CALL instruction processing stage, after the processor recognizes the CALL instruction, it first calculates the address of its next sequential instruction as the return address; then, it synchronously pushes the return address into the main RAS of the main pipelined processing unit and the backup RAS of other pipelined processing units; finally, it updates the stack top pointer and depth counter of all RAS.

[0046] During the RETURN instruction processing phase, the processor pops the return address from the top of the stack from the main RAS as the prediction target address; the processor can prefetch instructions based on the prediction address using the instruction fetch unit, and the execution unit verifies the address correctness in parallel; if a prediction error occurs, the backup RAS is used for state recovery.

[0047] During the conditional jump instruction processing phase, it is necessary to monitor the actual jump target address of the conditional jump instruction. When the jump target does not match the current function call chain, the push / pop operation of the main RAS is first paused. Then, the affected RAS entries are cleared. Finally, the stack state of each pipeline processing unit is resynchronized through the backup RAS.

[0048] This embodiment achieves high-precision RAS state management through strict adherence to instruction sequence and dynamic maintenance mechanisms. Specifically, the integrity of the function call chain is guaranteed through atomic stack operations of CALL / RETURN instructions.

[0049] based on Figure 4 The embodiment shown illustrates another embodiment of this application.

[0050] In the embodiments of this application, Figure 4 Step S101 in the implementation shown includes configuring the RAS corresponding to each of the at least one second pipeline processing unit, including: During processor initialization, independent address stack storage space is allocated for each of the at least one second pipeline processing unit to configure the RAS corresponding to each of the at least one second pipeline processing unit.

[0051] In the embodiments of the application, the independent address stack storage space refers to a physical storage unit allocated separately in the processor storage area for each second pipeline processing unit. This storage unit is used to store the RAS data of the corresponding pipeline processing unit, including the return address sequence, stack pointer, and status flag bits. The capacity configuration of each independent address stack storage space is consistent with the main return address stack of the first pipeline processing unit, and it has an independent access control circuit.

[0052] In one possible implementation, during processor initialization, independent address stack storage space is allocated to each of the at least one second pipelined processing unit to configure the RAS corresponding to each of the at least one second pipelined processing unit. This refers to the hardware resource management unit allocating a dedicated register group or on-chip SRAM storage block for each second pipelined processing unit according to the processor architecture configuration parameters. The stack pointers of each return address stack are zeroed and the historical status flags are cleared through the microcode initialization program. A mapping table between the main return address stack and each backup return address stack is established, recording the base address and capacity information of each storage space.

[0053] based on Figure 4 The embodiment shown illustrates another embodiment of this application.

[0054] The return address backup method in this application embodiment further includes: While the processor is executing instructions normally, the RAS corresponding to the first pipeline processing unit is kept synchronized with the at least one second pipeline processing unit.

[0055] Specifically, in this embodiment of the application, maintaining the synchronous update of the RAS corresponding to the first pipeline processing unit and the at least one second pipeline processing unit when the processor is executing instructions normally refers to sending the same operation instructions and data to the RAS corresponding to each of the second pipeline processing units in real time through a bus broadcast mechanism or a dedicated data path when the main return address stack of the first pipeline processing unit performs push or pop operations, so as to ensure that the stack top data, pointer position and depth counter of each stack remain strictly consistent.

[0056] Please see Figure 7 , Figure 7 This is a detailed flowchart illustrating the execution return address prediction process according to one embodiment of this application. Figure 7 As shown, the method in this embodiment may include the following steps S201-S202, and steps S201-S202 may be used as a method for... Figure 6 The detailed steps of step S104 in the illustrated embodiment.

[0057] S201, in response to the received RETURN instruction, obtain the target return address from the RAS corresponding to the first pipeline processing unit; S202, predict the return address based on the target return address.

[0058] Specifically, in the embodiments of this application, the target return address refers to the instruction memory address read from the top of the main return address stack of the first pipeline processing unit. This address corresponds to the address of the next sequential instruction corresponding to the most recent CALL instruction that has not returned, and is used to predict the program jump target after the RETURN instruction is executed.

[0059] In one possible implementation, obtaining the target return address from the RAS corresponding to the first pipeline processing unit in response to the received RETURN instruction means that the instruction decoding unit triggers a return address prediction request when it detects the RETURN instruction opcode; or, the main return address stack controller outputs the return address stored at the top of the stack during the pipeline decoding stage; or, the target return address is transmitted to the instruction fetch unit through a dedicated data path; predicting the return address based on the target return address means that the processor first writes the target return address into the program counter through the instruction fetch unit, then the instruction cache module prefetches subsequent instructions based on this address, and finally, the execution unit verifies the consistency between the actual return address and the predicted address during the pipeline commit stage. If a deviation occurs, pipeline flushing is triggered and the backup return address stack state is restored.

[0060] This embodiment achieves high-precision prediction of the processor in complex control flow scenarios through the collaborative management mechanism of multi-level return address stacks. In addition, the synchronization update mechanism realizes atomic operation of the primary and backup stacks through a dedicated data path, which can achieve zero-cycle latency synchronization in multi-level pipelined processors.

[0061] Please see Figure 8 One embodiment of this application provides a return address backup device 800 applied to a processor. The processor includes multiple pipelined processing units, including a first pipelined processing unit at a first pipeline stage, and at least one second pipelined processing unit supporting the initiation of a pipeline flushing operation. The configuration module 810 is used to obtain the return address stack (RAS) corresponding to the first pipeline processing unit and configure the RAS corresponding to each of the at least one second pipeline processing unit. The processing module 820 is used to acquire a sequence of instructions to be processed and to perform pipelined processing on the sequence of instructions to be processed. During the pipelined processing of the sequence of instructions to be processed, in response to a pipeline flushing operation initiated by a target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit. The target pipeline processing unit is one of at least one of the second pipeline processing units.

[0062] Optionally, the return address backup device 800 is further configured to: predict the return address based on the RAS corresponding to the first pipeline processing unit.

[0063] Optionally, the instruction sequence to be processed includes a CALL instruction, a RETURN instruction, and a return address prediction interference instruction, wherein the return address prediction interference instruction includes a conditional jump instruction.

[0064] Optionally, the return address backup device 800 is further configured to: determine the instruction input order according to the instruction sequence to be processed, and sequentially input the CALL instruction, RETURN instruction and conditional jump instruction in the instruction sequence to be processed into the processor for instruction processing according to the instruction input order, wherein the CALL instruction controls the execution of a push operation on the RAS, the RETURN instruction controls the execution of a pop operation on the RAS, and the conditional jump instruction controls the execution of a branch processing operation by the processor.

[0065] Optionally, the return address backup device 800 is further configured to: allocate independent address stack storage space for each of the at least one second pipeline processing unit during processor initialization, so as to configure the RAS corresponding to each of the at least one second pipeline processing unit.

[0066] Optionally, the return address backup device 800 is further configured to: in response to a received RETURN instruction, obtain a target return address from the RAS corresponding to the first pipeline processing unit; and perform return address prediction based on the target return address.

[0067] Optionally, the return address backup device 800 is further configured to: maintain the synchronous update of the RAS corresponding to the first pipeline processing unit and the at least one second pipeline processing unit when the processor is executing instructions normally.

[0068] For the effects achievable in this embodiment, please refer to the relevant embodiments of the above-mentioned return address backup method, which will not be repeated here.

[0069] For specific limitations regarding the aforementioned return address backup device, please refer to the limitations of the return address backup method described above, which will not be repeated here. Each module in the aforementioned return address backup device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0070] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 9As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements a return address backup method as described above. It includes: memory and a processor; the memory stores a computer program; and the processor executes the computer program to implement any step of the return address backup method described above.

[0071] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, can perform any of the steps in the above-described return address backup method.

[0072] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0073] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0074] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0075] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 Figure 1 The steps of the function specified in one or more boxes.

[0076] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0077] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for backing up a return address, characterized in that, Applied to a processor, the processor including multiple pipelined processing units, the multiple pipelined processing units including a first pipelined processing unit in a first pipeline stage, and at least one second pipelined processing unit supporting the initiation of a pipeline flushing operation, the method includes: Obtain the return address stack (RAS) corresponding to the first pipeline processing unit, and configure the RAS corresponding to each of the at least one second pipeline processing unit. Obtain the sequence of instructions to be processed, and perform pipeline processing on the sequence of instructions to be processed; During the pipelined processing of the instruction sequence to be processed, in response to the pipeline flushing operation initiated by the target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit, wherein the target pipeline processing unit is one of at least one of the second pipeline processing units.

2. The method according to claim 1, characterized in that, During the pipelined processing of the instruction sequence to be processed, in response to a pipeline flushing operation initiated by the target pipeline processing unit, after copying the RAS corresponding to the target pipeline processing unit to the RAS corresponding to the first pipeline processing unit, the process includes: Return address prediction is performed based on the RAS corresponding to the first pipeline processing unit.

3. The method according to claim 1, characterized in that, The sequence of instructions to be processed includes CALL instructions, RETURN instructions, and return address prediction interference instructions, the return address prediction interference instructions including conditional jump instructions.

4. The method according to claim 3, characterized in that, The pipelined processing of the instruction sequence to be processed includes: The instruction input order is determined according to the sequence of instructions to be processed. The CALL instruction, RETURN instruction, and conditional jump instruction in the sequence of instructions to be processed are sequentially input into the processor for instruction processing according to the instruction input order. The CALL instruction is used to control the execution of a push operation on the RAS, the RETURN instruction is used to perform a pop operation on the RAS, and the conditional jump instruction is used by the processor to perform a branch processing operation.

5. The method according to claim 1, characterized in that, The configuration of the RAS corresponding to each of the at least one second pipeline processing unit includes: During processor initialization, independent address stack storage space is allocated for each of the at least one second pipeline processing unit to configure the RAS corresponding to each of the at least one second pipeline processing unit.

6. The method according to claim 2, characterized in that, The step of predicting the return address based on the RAS corresponding to the first pipeline processing unit includes: In response to the received RETURN instruction, the target return address is obtained from the RAS corresponding to the first pipeline processing unit; Predict the return address based on the target return address.

7. The method according to claim 1, characterized in that, The method further includes: While the processor is executing instructions normally, the RAS corresponding to the first pipeline processing unit is kept synchronized with the at least one second pipeline processing unit.

8. A return address backup device, characterized in that, Applied to a processor, the processor including multiple pipelined processing units, the multiple pipelined processing units including a first pipelined processing unit at a first pipeline stage, and at least one second pipelined processing unit supporting the initiation of a pipeline flushing operation, including: The configuration module is used to obtain the return address stack (RAS) corresponding to the first pipeline processing unit and configure the RAS corresponding to each of the at least one second pipeline processing unit. The processing module is used to acquire a sequence of instructions to be processed and to perform pipelined processing on the sequence of instructions to be processed. During the pipelined processing of the sequence of instructions to be processed, in response to a pipeline flushing operation initiated by a target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit. The target pipeline processing unit is one of at least one of the second pipeline processing units.

9. A computer device, comprising: The method includes a memory and a processor, the memory storing a computer program, characterized in that the processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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