Display device

Abstract

A display device is provided. The display device includes: a display panel including a first area and a second area; and a panel driver configured to drive the display panel to provide a first mode control signal to the pixels in the first region, and to provide a second mode control signal to the pixels in the second region, in which the first region is configured to drive in a first mode to display an image having a first viewing angle based on the first mode control signal, and the second region is configured to drive in a second mode based on the second mode control signal. Or driven in a second mode to display an image having a second viewing angle narrower than the first viewing angle, and wherein the second region is configured to be driven in the first mode or the second mode based on a second mode control signal.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure relate to a display device. Background Art

[0002] The display device can display visual information to the user in the form of an image. The display device can be driven in a public mode, in which not only a user located in the front but also a user at the side (or not in the center) can view the image, or in a private mode, in which only a user located in the front can view the image by controlling the viewing angle of the image displayed on the display device.

[0003] Recently, for application to display systems used in vehicles and the like, consumer demands for display devices that control a public mode and a private mode for each partial area of ​​a display area are increasing.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some embodiments of the present disclosure relate to a display device. For example, aspects of some embodiments relate to a display device for controlling a viewing angle of an image.

[0006] Aspects of some embodiments include a display device in which the viewing angle of an image is controlled.

[0007] According to some embodiments, a display device may include: a display panel including a first area and a second area; and a panel driver driving the display panel to provide a first mode control signal to pixels in the first area and a second mode control signal to pixels in the second area. The first area may be driven in a first mode based on the first mode control signal to display an image with a first viewing angle, or driven in a second mode to display an image with a second viewing angle narrower than the first viewing angle. The second area may be driven in the first mode or the second mode based on the second mode control signal.

[0008] According to some embodiments, the first region and the second region may be driven independently of each other in the first mode or the second mode.

[0009] According to some embodiments, each of the first mode control signal and the second mode control signal may include a common gate signal and a private gate signal. According to some embodiments, each of the first region and the second region may be driven in a first mode based on the common gate signal. According to some embodiments, each of the first region and the second region may be driven in a second mode based on the private gate signal.

[0010] According to some embodiments, each of the pixels in the first region and the second region may include: a first light-emitting element that emits light having a first viewing angle; a second light-emitting element that emits light having a second viewing angle; an emission transistor that is turned on in response to an emission signal; a first mode control transistor that is connected between the first light-emitting element and the emission transistor and is turned on in response to a common gate signal; and a second mode control transistor that is connected between the second light-emitting element and the emission transistor and is turned on in response to a private gate signal.

[0011] According to some embodiments, in the second mode, the first light emitting element may not emit light, and the second light emitting element may emit light.

[0012] According to some embodiments, in the first mode, the first light emitting element may emit light and the second light emitting element may not emit light.

[0013] According to some embodiments, in the first mode, the first light emitting element may emit light and the second light emitting element may emit light.

[0014] According to some embodiments, each of the pixels in the first region and the second region may further include: a driving transistor connected between the driving voltage line and the first node and including a gate electrode connected to the second node; a writing transistor connected between the data voltage line and the third node and turned on in response to a writing gate signal; a compensation transistor connected between the first node and the second node and turned on in response to the compensation gate signal; an initialization transistor connected between the first initialization voltage line and the second node and turned on in response to the initialization gate signal; a reference transistor connected between the reference voltage line and the third node and turned on in response to the compensation gate signal; a first capacitor connected between the second node and the third node; and a second capacitor connected between the driving voltage line and the third node.

[0015] According to some embodiments, each of the pixels in the first region and the second region may also include: a first bypass transistor, connected between the second initialization voltage line and a fourth node, and turned on in response to a bypass gate signal, the fourth node being between the first light-emitting element and the first mode control transistor; and a second bypass transistor, connected between the second initialization voltage line and a fifth node, and turned on in response to the bypass gate signal, the fifth node being between the second light-emitting element and the second mode control transistor.

[0016] According to some embodiments, the display panel may further include a peripheral area surrounding the first area and the second area. According to some embodiments, the panel driver may provide a third mode control signal to pixels in the peripheral area. According to some embodiments, the peripheral area may be driven in the first mode or the second mode based on the third mode control signal.

[0017] According to some embodiments, the peripheral area may be driven only in the first mode.

[0018] According to some embodiments, the display panel may further include a first side region adjacent to at least one side of the first region. According to some embodiments, the panel driver may provide a third mode control signal to pixels in the first side region. According to some embodiments, the first side region may be driven in the first mode or the second mode based on the third mode control signal.

[0019] According to some embodiments, when the first region is driven in the first mode, the first side region may be driven only in the first mode.

[0020] According to some embodiments, when the first region is driven in the second mode, the first side region may be driven in the first mode or the second mode.

[0021] According to some embodiments, the display panel may further include a second side region adjacent to at least one side of the second region. According to some embodiments, the panel driver may provide a fourth mode control signal to pixels in the second side region. According to some embodiments, the second side region may be driven in the first mode or the second mode based on the fourth mode control signal.

[0022] According to some embodiments, the display panel may further include a peripheral area surrounding the first area, the second area, the first side area, and the second side area. According to some embodiments, the panel driver may provide a fifth mode control signal to pixels in the peripheral area. According to some embodiments, the peripheral area may be driven in the first mode or the second mode based on the fifth mode control signal.

[0023] According to some embodiments, the panel driver may include: a scan driver that provides a scan signal to pixels in the first area and the second area; an emission driver that provides an emission signal to pixels in the first area and the second area; a data driver that provides a data voltage to pixels in the first area and the second area; and a mode driver that provides a first mode control signal to pixels in the first area and provides a second mode control signal to pixels in the second area.

[0024] A display device according to some embodiments may include: a display panel including a plurality of pixels and divided into a first region to a kth region, wherein k is a natural number greater than or equal to 2; and a panel driver driving the display panel and providing a first mode control signal to a kth mode control signal to the first region to the kth region, respectively. Each of the first mode control signal to the kth mode control signal may include a common gate signal and a private gate signal. Each of the pixels includes: a first light emitting element emitting light having a first viewing angle; a second light emitting element emitting light having a second viewing angle narrower than the first viewing angle; an emission transistor turned on in response to an emission signal; a first mode control transistor connected between the first light emitting element and the emission transistor and turned on in response to a common gate signal; and a second mode control transistor connected between the second light emitting element and the emission transistor and turned on in response to a private gate signal.

[0025] According to some embodiments, the first to kth mode control signals may be independent of each other.

[0026] According to some embodiments, each of the pixels may further include: a driving transistor connected between a driving voltage line and a first node and including a gate electrode connected to a second node; a writing transistor connected between a data voltage line and a third node and turned on in response to a writing gate signal; a compensation transistor connected between the first node and the second node and turned on in response to a compensation gate signal; an initialization transistor connected between a first initialization voltage line and the second node and turned on in response to the initialization gate signal; a reference transistor connected between a reference voltage line and a third node and turned on in response to the compensation gate signal; a first capacitor connected between the second node and the third node; and a second capacitor connected between the driving voltage line and the third node.

[0027] In a display device according to some embodiments, areas of the display panel can be independently driven based on mode control signals, so that each of the areas can be independently driven in a first mode (public mode) for displaying a wide-viewing angle image or a second mode (private mode) for displaying a narrow-viewing angle image. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a block diagram illustrating a display device according to some embodiments.

[0030] Figure 2 is a plan view showing a pixel according to some embodiments.

[0031] Figure 3is a diagram showing some embodiments of the present invention. Figure 2 Circuit diagram of a pixel in .

[0032] Figure 4 , Figure 5 and Figure 6 is used to describe the Figure 3 A graph of the emission of pixels in .

[0033] Figure 7 is a plan view showing a display panel according to some embodiments.

[0034] Figure 8 , Fig. 9 , Fig.10 and Fig.11 is used to describe the Figure 7 Figure 4 shows the driver diagram of the display panel.

[0035] Fig.12 is a plan view showing a display panel according to some embodiments.

[0036] Fig.13 is a plan view showing a display panel according to some embodiments.

[0037] Fig.14 , Fig.15 and Fig.16 is used to describe the Fig.13 Figure 4 shows the driver diagram of the display panel.

[0038] Fig.17 is a plan view showing a display panel according to some embodiments.

[0039] Fig.18 is a block diagram illustrating an electronic device according to some embodiments.

[0040] Fig.19 is a diagram showing a method according to some embodiments Fig.18 FIG. 1 is a diagram of an example in which the electronic device is implemented as an automobile display system. DETAILED DESCRIPTION

[0041] Hereinafter, a display device according to some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals will be used for the same elements in the drawings.

[0042] Figure 1 is a block diagram illustrating a display device 100 according to some embodiments.

[0043] Reference Figure 1 , the display device 100 may include a display panel 110 and a panel driver PD.

[0044] The display panel 110 may include pixels PX. According to some embodiments, the pixels PX may include a first pixel emitting light having a first color, a second pixel emitting light having a second color, and a third pixel emitting light having a third color. For example, the first color, the second color, and the third color may be red, green, and blue, respectively.

[0045] The display panel 110 may include first to k-th regions A1 to Ak (k is a natural number equal to or greater than 2). In other words, the display panel 110 may be divided into the first to k-th regions A1 to Ak. Each of the first to k-th regions A1 to Ak may include a plurality of pixels PX.

[0046] The panel driver PD may drive the display panel 110. The panel driver PD may provide first to k-th mode control signals MCS1 to MCSk to the first to k-th regions A1 to Ak, respectively. The panel driver PD may include a scan driver 120, an emission driver 130, a data driver 140, a mode driver 150, and a controller 160.

[0047] The scan driver 120 may provide a scan signal SS to the pixel PX. According to some embodiments, the scan driver 120 may sequentially generate first to n-th (n is a natural number equal to or greater than 2) scan signals SS corresponding to the first to n-th pixel rows, respectively, based on the first control signal CNT1. The first control signal CNT1 may include a scan clock signal, a scan start signal, and the like.

[0048] The emission driver 130 may provide an emission signal EM to the pixel PX. According to some embodiments, the emission driver 130 may sequentially generate first to nth emission signals EM corresponding to the first to nth pixel rows, respectively, based on the second control signal CNT2. The second control signal CNT2 may include an emission clock signal, an emission start signal, and the like.

[0049] The data driver 140 may provide a data voltage VDAT to the pixel PX. According to some embodiments, the data driver 140 may generate first to mth (m is a natural number equal to or greater than 2) data voltages VDAT corresponding to the first to mth pixel columns, respectively, based on the second image data IMD2 and the third control signal CNT3. According to some embodiments, the second image data IMD2 may include grayscale values ​​corresponding to the pixels PX, respectively. The third control signal CNT3 may include a data clock signal, a horizontal start signal, a load signal, etc.

[0050] The mode driver 150 may provide first to k-th mode control signals MCS1 to MCSk to the first to k-th regions A1 to Ak, respectively. The mode driver 150 may provide the first mode control signal MCS1 to the pixels PX in the first region A1, and may provide the k-th mode control signal MCSk to the pixels PX in the k-th region Ak. The mode driver 150 may generate first to k-th mode control signals MCS1 to MCSk corresponding to the first to k-th regions Ak, respectively, based on the fourth control signal CNT4. The first to k-th mode control signals MCS1 to MCSk may be independent of each other. The first to k-th regions A1 to Ak may be independently driven in a first mode (e.g., a public mode) or a second mode (e.g., a private mode) based on the first to k-th mode control signals MCS1 to MCSk, respectively, the first mode displaying an image having a first viewing angle, and the second mode displaying an image having a second viewing angle narrower than the first viewing angle.

[0051] The controller 160 may control the operation (or driving) of the scan driver 120, the operation (or driving) of the emission driver 130, the operation (or driving) of the data driver 140, and the operation (or driving) of the mode driver 150. The controller 160 may generate a first control signal CNT1, a second control signal CNT2, a second image data IMD2, a third control signal CNT3, and a fourth control signal CNT4 based on the first image data IMD1 and the control signal CNT. According to some embodiments, the first image data IMD1 may include grayscale values ​​corresponding to the pixels PX, respectively. The controller 160 may convert the first image data IMD1 into the second image data IMD2. The control signal CNT may include a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and the like.

[0052] Figure 2 is a plan view showing a pixel PX according to some embodiments. Figure 2 The pixel PX in can be Figure 1 One of the pixels PX included in the display device 100 in the display device 100.

[0053] Reference Figure 2 , the pixel PX may include a first emission part EP1 and a second emission part EP2. The first emission part EP1 may emit light at a first viewing angle, and the second emission part EP2 may emit light at a second viewing angle narrower than the first viewing angle.

[0054] Figure 3 It is shown Figure 2 Circuit diagram of pixel PX in FIG.

[0055] Reference Figure 1 , Figure 2 and Figure 3 , the pixel PX may include a first transistor (driving transistor) T1, a second transistor (writing transistor) T2, a third transistor (compensation transistor) T3, a fourth transistor (initialization transistor) T4, a fifth transistor (reference transistor) T5, a sixth transistor (emitting transistor) T6, a seventh transistor (first bypass transistor) T7, an eighth transistor (second bypass transistor) T8, a ninth transistor (first mode control transistor) T9, a tenth transistor (second mode control transistor) T10, a first capacitor C1, a second capacitor C2, a first light emitting element EL1, and a second light emitting element EL2. The scan signal SS may include a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, and a bypass gate signal GB. Each of the first mode control signal MCS1 to the kth mode control signal MCSk may include a common gate signal GS_PU and a private gate signal GS_PR.

[0056] The first transistor T1 may be connected between a driving voltage line transmitting the driving voltage ELVDD and a first node N1. The first transistor T1 may include a first electrode connected to the driving voltage line, a second electrode connected to the first node N1, and a gate electrode connected to a second node N2. The first transistor T1 may generate a driving current corresponding to a difference between a voltage of the second node N2 and the driving voltage ELVDD.

[0057] The second transistor T2 may be connected between a data voltage line transmitting a data voltage VDAT and a third node N3, and may be turned on in response to a write gate signal GW. The second transistor T2 may include a first electrode connected to the data voltage line, a second electrode connected to the third node N3, and a gate electrode receiving the write gate signal GW. The second transistor T2 may transmit the data voltage VDAT to the third node N3 in response to the write gate signal GW.

[0058] The third transistor T3 may be connected between the first node N1 and the second node N2 and may be turned on in response to the compensation gate signal GC. The third transistor T3 may include a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate electrode receiving the compensation gate signal GC. The third transistor T3 may connect the first node N1 and the second node N2 in response to the compensation gate signal GC.

[0059] The fourth transistor T4 may be connected between the first initialization voltage line transmitting the first initialization voltage VINT and the second node N2, and may be turned on in response to the initialization gate signal GI. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line, a second electrode connected to the second node N2, and a gate electrode receiving the initialization gate signal GI. The fourth transistor T4 may transmit the first initialization voltage VINT to the second node N2 in response to the initialization gate signal GI.

[0060] The fifth transistor T5 may be connected between a reference voltage line transmitting a reference voltage VREF and the third node N3, and may be turned on in response to a compensation gate signal GC. The fifth transistor T5 may include a first electrode connected to the reference voltage line, a second electrode connected to the third node N3, and a gate electrode receiving the compensation gate signal GC. The fifth transistor T5 may transmit the reference voltage VREF to the third node N3 in response to the compensation gate signal GC.

[0061] The sixth transistor T6 may be connected between the first node N1 and the sixth node N6 and may be turned on in response to the emission signal EM. The sixth transistor T6 may include a first electrode connected to the first node N1, a second electrode connected to the sixth node N6, and a gate electrode receiving the emission signal EM. The sixth transistor T6 may connect the first node N1 and the sixth node N6 in response to the emission signal EM.

[0062] The seventh transistor T7 may be connected between the second initialization voltage line transmitting the second initialization voltage VAINT and the fourth node N4, and may be turned on in response to the bypass gate signal GB. The seventh transistor T7 may include a first electrode connected to the second initialization voltage line, a second electrode connected to the fourth node N4, and a gate electrode receiving the bypass gate signal GB. The seventh transistor T7 may transmit the second initialization voltage VAINT to the fourth node N4 in response to the bypass gate signal GB.

[0063] The eighth transistor T8 may be connected between the second initialization voltage line and the fifth node N5, and may be turned on in response to the bypass gate signal GB. The eighth transistor T8 may include a first electrode connected to the second initialization voltage line, a second electrode connected to the fifth node N5, and a gate electrode receiving the bypass gate signal GB. The eighth transistor T8 may transmit the second initialization voltage VAINT to the fifth node N5 in response to the bypass gate signal GB.

[0064] The ninth transistor T9 may be connected between the sixth node N6 and the fourth node N4 and may be turned on in response to the common gate signal GS_PU. The ninth transistor T9 may include a first electrode connected to the sixth node N6, a second electrode connected to the fourth node N4, and a gate electrode receiving the common gate signal GS_PU. The ninth transistor T9 may connect the sixth node N6 and the fourth node N4 in response to the common gate signal GS_PU.

[0065] The tenth transistor T10 may be connected between the sixth node N6 and the fifth node N5 and may be turned on in response to the private gate signal GS_PR. The tenth transistor T10 may include a first electrode connected to the sixth node N6, a second electrode connected to the fifth node N5, and a gate electrode receiving the private gate signal GS_PR. The tenth transistor T10 may connect the sixth node N6 and the fifth node N5 in response to the private gate signal GS_PR.

[0066] Figure 3 An embodiment in which each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 is a P-type transistor (e.g., a PMOS transistor) is shown, but embodiments of the present disclosure are not limited thereto. According to some embodiments, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may be an N-type transistor (e.g., an NMOS transistor).

[0067] The first capacitor C1 may be connected between the second node N2 and the third node N3. The first capacitor C1 may maintain a voltage of the second node N2 and a voltage of the third node N3, and electrically couple the second node N2 and the third node N3.

[0068] The second capacitor C2 may be connected between the driving voltage line and the third node N3. The second capacitor C2 may maintain the voltage of the third node N3.

[0069] Figure 3 An embodiment in which the pixel PX includes 10 transistors and 2 capacitors is shown, but embodiments according to the present disclosure are not limited thereto. According to some embodiments, the pixel PX may include 5 to 9, 11 or more transistors and / or 1 or 3 or more capacitors. In addition, according to some embodiments, without departing from the spirit and scope of embodiments according to the present disclosure, the pixel PX may include additional components (e.g., transistors, capacitors, etc.) or fewer components.

[0070] The first light emitting element EL1 may be connected between the fourth node N4 and a common voltage line transmitting the common voltage ELVSS. The first light emitting element EL1 may be positioned in the first emission part EP1. The first light emitting element EL1 may emit light at a first viewing angle.

[0071] The second light emitting element EL2 may be connected between the fifth node N5 and the common voltage line. The second light emitting element EL2 may be positioned in the second emission portion EP2. The second light emitting element EL2 may emit light at a second viewing angle.

[0072] According to some embodiments, each of the first light emitting element EL1 and the second light emitting element EL2 may be an organic light emitting diode. According to some embodiments, each of the first light emitting element EL1 and the second light emitting element EL2 may be an inorganic light emitting diode, a micro light emitting diode or a quantum dot light emitting diode.

[0073] Figure 4 , Figure 5 and Figure 6 is used to describe the Figure 3 Graph of the emission of pixel PX.

[0074] Reference Figure 3 and Figure 4 According to some embodiments, in the first mode, the first light emitting element EL1 may emit light, and the second light emitting element EL2 may not emit light. A common gate signal GS_PU having a turn-on voltage level (e.g., a low voltage level) and a private gate signal GS_PR ​​having a turn-off voltage level (e.g., a high voltage level) may be provided to the pixel PX, and therefore, the ninth transistor T9 may be turned on and the tenth transistor T10 may be turned off. When the sixth transistor T6 is turned on, the driving current generated by the first transistor T1 may be provided to the first light emitting element EL1 through the ninth transistor T9, and the first light emitting element EL1 may emit light at a first viewing angle (wide viewing angle). Therefore, in the first mode, the pixel PX may emit light at a first viewing angle.

[0075] Reference Figure 3 and Figure 5According to some embodiments, in the first mode, the first light emitting element EL1 may emit light, and the second light emitting element EL2 may emit light. A common gate signal GS_PU having a turn-on voltage level and a private gate signal GS_PR ​​having a turn-on voltage level may be provided to the pixel PX, and therefore, the ninth transistor T9 may be turned on and the tenth transistor T10 may be turned on. When the sixth transistor T6 is turned on, the driving current generated by the first transistor T1 may be provided to the first light emitting element EL1 through the ninth transistor T9, and the first light emitting element EL1 may emit light at a first viewing angle. In addition, when the sixth transistor T6 is turned on, the driving current generated by the first transistor T1 may be provided to the second light emitting element EL2 through the tenth transistor T10, and the second light emitting element EL2 may emit light at a second viewing angle (narrow viewing angle). Therefore, in the first mode, the pixel PX may emit light at a first viewing angle and a second viewing angle.

[0076] Reference Figure 3 and Figure 6 , in the second mode, the first light emitting element EL1 may not emit light, and the second light emitting element EL2 may emit light. A common gate signal GS_PU having a cut-off voltage level and a private gate signal GS_PR ​​having a turn-on voltage level may be provided to the pixel PX, and therefore, the ninth transistor T9 may be turned off and the tenth transistor T10 may be turned on. When the sixth transistor T6 is turned on, the driving current generated by the first transistor T1 may be provided to the second light emitting element EL2 through the tenth transistor T10, and the second light emitting element EL2 may emit light at a second viewing angle. Therefore, in the second mode, the pixel PX may emit light at a second viewing angle.

[0077] Figure 7 is a plan view showing a display panel 200 according to some embodiments. Figure 7 The display panel 200 in the embodiment may be Figure 1 An example of a display panel 110 included in a display device 100 in FIG.

[0078] Reference Figure 1 and Figure 7 , the display area DA of the display panel 200 may include a first area A1 and a second area A2, and each of the first area A1 and the second area A2 may include a plurality of pixels PX. In other words, the display area DA may be divided into the first area A1 and the second area A2. The non-display area NDA of the display panel 200 may surround the display area DA.

[0079] The mode driver 150 may provide a first mode control signal MCS1 and a second mode control signal MCS2 to a global signal line GSL positioned in the non-display area NDA. The first mode control signal MCS1 may include a first common gate signal GS1_PU and a first private gate signal GS1_PR, and the second mode control signal MCS2 may include a second common gate signal GS2_PU and a second private gate signal GS2_PR. The first common gate signal GS1_PU and the first private gate signal GS1_PR may be provided to the pixels PX in the first area A1 through the global signal line GSL, and the second common gate signal GS2_PU and the second private gate signal GS2_PR may be provided to the pixels PX in the second area A2 through the global signal line GSL.

[0080] The first area A1 can be driven in the first mode or the second mode based on the first mode control signal MCS1. The first area A1 can be driven in the first mode based on the first common gate signal GS1_PU, and can be driven in the second mode based on the first private gate signal GS1_PR. The second area A2 can be driven in the first mode or the second mode based on the second mode control signal MCS2. The second area A2 can be driven in the first mode based on the second common gate signal GS2_PU, and can be driven in the second mode based on the second private gate signal GS2_PR. Therefore, the first area A1 and the second area A2 can be driven independently of each other in the first mode or the second mode.

[0081] Figure 8 , Fig. 9 , Fig.10 and Fig.11 is used to describe the Figure 7 FIG. 2 is a diagram showing a driving process of the display panel 200. FIG.

[0082] Reference Figure 7 and Figure 8 According to some embodiments, the first area A1 and the second area A2 may be driven in the first mode MD1. In this case, a first common gate signal GS1_PU having a turn-on voltage level may be provided to the pixel PX in the first area A1, and a second common gate signal GS2_PU having a turn-on voltage level may be provided to the pixel PX in the second area A2. Therefore, the first area A1 and the second area A2 may display an image at a first viewing angle.

[0083] Reference Figure 7 and Fig. 9According to some embodiments, the first area A1 may be driven in the second mode MD2, and the second area A2 may be driven in the first mode MD1. In this case, the first common gate signal GS1_PU having a cut-off voltage level and the first private gate signal GS1_PR having a turn-on voltage level may be provided to the pixel PX in the first area A1, and the second common gate signal GS2_PU having a turn-on voltage level may be provided to the pixel PX in the second area A2. Therefore, the first area A1 may display an image at a second viewing angle, and the second area A2 may display an image at a first viewing angle.

[0084] Reference Figure 7 and Fig.10 According to some embodiments, the first area A1 may be driven in the first mode MD1, and the second area A2 may be driven in the second mode MD2. In this case, the first common gate signal GS1_PU having a turn-on voltage level may be provided to the pixel PX in the first area A1, and the second common gate signal GS2_PU having a turn-off voltage level and the second private gate signal GS2_PR having a turn-on voltage level may be provided to the pixel PX in the second area A2. Therefore, the first area A1 may display an image at a first viewing angle, and the second area A2 may display an image at a second viewing angle.

[0085] Reference Figure 7 and Fig.11 According to some embodiments, the first area A1 and the second area A2 may be driven in the second mode MD2. In this case, a first common gate signal GS1_PU having a cut-off voltage level and a first private gate signal GS1_PR having a turn-on voltage level may be provided to the pixel PX in the first area A1, and a second common gate signal GS2_PU having a cut-off voltage level and a second private gate signal GS2_PR having a turn-on voltage level may be provided to the pixel PX in the second area A2. Therefore, the first area A1 and the second area A2 may display an image at a second viewing angle.

[0086] Fig.12 is a plan view showing a display panel 300 according to some embodiments. Fig.12 The display panel 300 in the embodiment may be Figure 1 An example of a display panel 110 included in a display device 100 in FIG.

[0087] Reference will be omitted Fig.12 The display panel 300 described with reference to Figure 7 Components of the display panel 200 are described as being substantially the same as or similar to those described herein.

[0088] Reference Figure 1 and Fig.12, the display area DA of the display panel 300 may include a first area A1, a second area A2, and a peripheral area A3, and each of the first area A1, the second area A2, and the peripheral area A3 may include a plurality of pixels PX. In other words, the display area DA may be divided into the first area A1, the second area A2, and the peripheral area A3. The peripheral area A3 may surround the first area A1 and the second area A2.

[0089] The mode driver 150 may provide a first mode control signal MCS1, a second mode control signal MCS2, and a third mode control signal MCS3 to the global signal line GSL positioned in the non-display area NDA. The third mode control signal MCS3 may include a third common gate signal GS3_PU and a third private gate signal GS3_PR. The third common gate signal GS3_PU and the third private gate signal GS3_PR may be provided to the pixels PX in the peripheral area A3 through the global signal line GSL.

[0090] The peripheral area A3 can be driven in the first mode or the second mode based on the third mode control signal MCS3. The peripheral area A3 can be driven in the first mode based on the third common gate signal GS3_PU, and can be driven in the second mode based on the third private gate signal GS3_PR. Therefore, the first area A1, the second area A2 and the peripheral area A3 can be driven independently of each other in the first mode or the second mode.

[0091] According to some embodiments, the peripheral area A3 may be driven only in the first mode. In this case, the third common gate signal GS3_PU having the on voltage level may be provided to the pixels PX in the peripheral area A3. Therefore, the peripheral area A3 may display an image at the first viewing angle.

[0092] Fig.13 is a plan view showing a display panel 400 according to some embodiments. Fig.13 The display panel 400 in the embodiment may be Figure 1 An example of a display panel 110 included in a display device 100 in FIG.

[0093] Reference will be omitted Fig.13 The display panel 400 described with reference to Figure 7 Components of the display panel 200 are described as being substantially the same as or similar to those described herein.

[0094] Reference Figure 1 and Fig.13, the display area DA of the display panel 400 may include a first area A1, a second area A2, a first side area A3, and a second side area A4, and each of the first area A1, the second area A2, the first side area A3, and the second side area A4 may include a plurality of pixels PX. In other words, the display area DA may be divided into the first area A1, the second area A2, the first side area A3, and the second side area A4. The first side area A3 may be adjacent to at least one side of the first area A1, and the second side area A4 may be adjacent to at least one side of the second area A2. According to some embodiments, as Fig.13 As shown in , the first side area A3 may be adjacent to an opposite side of the first area A1, and the second side area A4 may be adjacent to an opposite side of the second area A2.

[0095] The mode driver 150 may provide a first mode control signal MCS1, a second mode control signal MCS2, a third mode control signal MCS3, and a fourth mode control signal MCS4 to the global signal line GSL positioned in the non-display area NDA. The third mode control signal MCS3 may include a third common gate signal GS3_PU and a third private gate signal GS3_PR, and the fourth mode control signal MCS4 may include a fourth common gate signal GS4_PU and a fourth private gate signal GS4_PR. The third common gate signal GS3_PU and the third private gate signal GS3_PR may be provided to the pixels PX in the first side area A3 through the global signal line GSL, and the fourth common gate signal GS4_PU and the fourth private gate signal GS4_PR may be provided to the pixels PX in the second side area A4 through the global signal line GSL.

[0096] The first side area A3 can be driven in the first mode or the second mode based on the third mode control signal MCS3. The first side area A3 can be driven in the first mode based on the third common gate signal GS3_PU, and can be driven in the second mode based on the third private gate signal GS3_PR. The second side area A4 can be driven in the first mode or the second mode based on the fourth mode control signal MCS4. The second side area A4 can be driven in the first mode based on the fourth common gate signal GS4_PU, and can be driven in the second mode based on the fourth private gate signal GS4_PR. Therefore, the first area A1, the second area A2, the first side area A3 and the second side area A4 can be driven independently of each other in the first mode or the second mode.

[0097] Fig.14 , Fig.15 and Fig.16 is used to describe the Fig.13 FIG. 4 is a diagram showing the driving of the display panel 400.

[0098] Reference Fig.13 and Fig.14 According to some embodiments, when the first area A1 is driven in the first mode MD1, the first side area A3 is driven only in the first mode MD1. In other words, when the first area A1 is driven in the first mode MD1, the first side area A3 may not be driven in the second mode MD2. In this case, the first common gate signal GS1_PU having the turn-on voltage level may be provided to the pixel PX in the first area A1, and the third common gate signal GS3_PU having the turn-on voltage level may be provided to the pixel PX in the first side area A3. Therefore, the first area A1 and the first side area A3 may display an image at a first viewing angle.

[0099] Reference Fig.13 , Fig.15 and Fig.16 According to some embodiments, when the first area A1 is driven in the second mode MD2, the first side area A3 may be driven in the first mode MD1 or the second mode MD2. In this case, a first common gate signal GS1_PU having a turn-off voltage level and a first private gate signal GS1_PR having a turn-on voltage level may be provided to the pixels PX in the first area A1.

[0100] According to some embodiments, Fig.15 As shown in , when the first side area A3 is driven in the second mode MD2, the third common gate signal GS3_PU having a cut-off voltage level and the third private gate signal GS3_PR having a turn-on voltage level may be provided to the pixel PX in the first side area A3. Therefore, the first area A1 and the first side area A3 may display an image at a second viewing angle. For example, the display panel 400 may display an image having a ratio of 21:9 at a second viewing angle through the first area A1 and the first side area A3.

[0101] According to some embodiments, Fig.16 As shown in , when the first side area A3 is driven in the first mode MD1, the third common gate signal GS3_PU having the on voltage level may be provided to the pixel PX in the first side area A3. Therefore, the first area A1 may display an image at the second viewing angle, and the first side area A3 may display an image at the first viewing angle. For example, the display panel 400 may display an image having a 16:9 ratio at the second viewing angle through the first area A1.

[0102] Fig.14 , Fig.15 and Fig.16The second area A2 and the second side area A4 are shown to be driven in the first mode MD1, but the second area A2 and the second side area A4 may be driven substantially the same as or similar to the first area A1 and the first side area A3, respectively. According to some embodiments, when the second area A2 is driven in the first mode MD1, the second side area A4 may be driven only in the first mode MD1. According to some embodiments, when the second area A2 is driven in the second mode MD2, the second side area A4 may be driven in the first mode MD1 or the second mode MD2.

[0103] Fig.17 is a plan view showing a display panel 500 according to some embodiments. Fig.17 The display panel 500 in the embodiment may be Figure 1 An example of a display panel 110 included in a display device 100 in FIG.

[0104] References can be omitted Fig.17 The display panel 500 described with reference to Figure 7 The display panel 200 described and the reference Fig.13 The display panel 400 is described with substantially the same or similar components as those described above.

[0105] Reference Figure 1 and Fig.17 , the display area DA of the display panel 500 may include a first area A1, a second area A2, a first side area A3, a second side area A4, and a peripheral area A5, and each of the first area A1, the second area A2, the first side area A3, the second side area A4, and the peripheral area A5 may include a plurality of pixels PX. In other words, the display area DA may be divided into the first area A1, the second area A2, the first side area A3, the second side area A4, and the peripheral area A5. The peripheral area A5 may surround the first area A1, the second area A2, the first side area A3, and the second side area A4.

[0106] The mode driver 150 may provide a first mode control signal MCS1, a second mode control signal MCS2, a third mode control signal MCS3, a fourth mode control signal MCS4, and a fifth mode control signal MCS5 to the global signal line GSL positioned in the non-display area NDA. The fifth mode control signal MCS5 may include a fifth common gate signal GS5_PU and a fifth private gate signal GS5_PR. The fifth common gate signal GS5_PU and the fifth private gate signal GS5_PR may be provided to the pixels PX in the peripheral area A5 through the global signal line GSL.

[0107] The peripheral area A5 can be driven in the first mode or the second mode based on the fifth mode control signal MCS5. The peripheral area A5 can be driven in the first mode based on the fifth common gate signal GS5_PU, and can be driven in the second mode based on the fifth private gate signal GS5_PR. Therefore, the first area A1, the second area A2, the first side area A3, the second side area A4 and the peripheral area A5 can be driven independently of each other in the first mode or the second mode.

[0108] According to some embodiments, the peripheral area A5 may be driven only in the first mode. In this case, the fifth common gate signal GS5_PU having a turn-on voltage level may be provided to the pixels PX in the peripheral area A5. Therefore, the peripheral area A5 may display an image at the first viewing angle.

[0109] Fig.18 is a block diagram illustrating an electronic device 1000 according to some embodiments. Fig.19 It shows that Fig.18 The electronic device 1000 in the figure is implemented as an example of an automobile display system.

[0110] Reference Fig.18 and Fig.19 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be connected to Figure 1 The electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, and the like.

[0111] According to some embodiments, Fig.19 As shown in , the electronic device 1000 can be implemented as a car display system. For example, the electronic device 1000 may include a first area A1, a second area A2, and a peripheral area A3, and the first area A1, the second area A2, and the peripheral area A3 may be connected to Fig.12 The first area A1, the second area A2 and the peripheral area A3 of the display panel 300 correspond to each other. However, the embodiments of the present disclosure are not limited thereto, and according to some embodiments, the electronic device 1000 may be implemented as a television, a mobile phone, a video phone, a smart tablet, a smart watch, a tablet PC, an automatic navigation, a laptop computer, a head-mounted display device, etc.

[0112] The processor 1010 may perform calculations or tasks. According to some embodiments, the processor 1010 may be a microprocessor, a central processing unit (CPU), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. According to some embodiments, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. According to some embodiments, the processor 1010 may provide a display device 1060 with a display device 1060. Figure 1 The first image data IMD1 and Figure 1 The control signal CNT in.

[0113] The memory device 1020 may store data for operation of the electronic device 1000. According to some embodiments, the memory device 1020 may include a nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc. and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.

[0114] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1040 may include an input device such as a keyboard, a keypad, a touch pad, a touch screen, a mouse device, etc. and an output device such as a speaker, a printer, etc. The power supply 1050 may supply power required for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication links.

[0115] In the display device 1060, the areas of the display panel can be driven independently based on the mode control signal, so that each of the areas can be driven independently in a first mode (public mode) for displaying a wide-viewing angle image or a second mode (private mode) for displaying a narrow-viewing angle image.

[0116] The display device according to the embodiment may be applied to a display device included in a car display system, a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, and the like.

[0117] Although aspects of the display device according to some embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by a person skilled in the relevant technical field without departing from the technical spirit described in the claims and their equivalents.

Claims

1. A display device, the display device include: The display panel comprises a first area and a second area; as well as a panel driver configured to drive the display panel to provide a first mode control signal to pixels in the first area and to provide a second mode control signal to pixels in the second area, The first area is configured to be driven in a first mode to display an image having a first viewing angle, or driven in a second mode to display an image having a second viewing angle narrower than the first viewing angle, based on the first mode control signal. The second region is configured to be driven in the first mode or the second mode based on the second mode control signal.

2. The display device according to claim 1, in, The first region and the second region are configured to be driven independently of each other in the first mode or the second mode.

3. The display device according to claim 1, in, Each of the first mode control signal and the second mode control signal includes a common gate signal and a private gate signal, wherein each of the first region and the second region is configured to be driven in the first mode based on the common gate signal, and Each of the first region and the second region is configured to be driven in the second mode based on the private gate signal.

4. The display device according to claim 3, in, Each of the pixels in the first area and the second area includes: a first light emitting element configured to emit light having the first viewing angle; a second light emitting element configured to emit light having the second viewing angle; an emission transistor configured to be turned on in response to an emission signal; a first mode control transistor connected between the first light emitting element and the emission transistor and configured to be turned on in response to the common gate signal; and A second mode control transistor is connected between the second light emitting element and the emission transistor and is configured to be turned on in response to the private gate signal.

5. The display device according to claim 4, in, In the second mode, the first light emitting element is configured not to emit light, and the second light emitting element is configured to emit light.

6. The display device according to claim 5, in, In the first mode, the first light emitting element is configured to emit light, and the second light emitting element is configured not to emit light.

7. The display device according to claim 5, in, In the first mode, the first light emitting element is configured to emit light, and the second light emitting element is configured to emit light.

8. The display device according to claim 4, in, Each of the pixels in the first region and the second region further includes: a driving transistor connected between the driving voltage line and the first node and including a gate electrode connected to the second node; a write transistor connected between the data voltage line and the third node and configured to be turned on in response to a write gate signal; a compensation transistor connected between the first node and the second node and configured to be turned on in response to a compensation gate signal; an initialization transistor connected between a first initialization voltage line and the second node and configured to be turned on in response to an initialization gate signal; a reference transistor connected between a reference voltage line and the third node and configured to be turned on in response to the compensation gate signal; A first capacitor connected between the second node and the third node; and The second capacitor is connected between the driving voltage line and the third node.

9. The display device according to claim 8, in, Each of the pixels in the first region and the second region further includes: a first bypass transistor connected between a second initialization voltage line and a fourth node between the first light emitting element and the first mode control transistor and configured to be turned on in response to a bypass gate signal; and A second bypass transistor is connected between the second initialization voltage line and a fifth node between the second light emitting element and the second mode control transistor and is configured to be turned on in response to the bypass gate signal.

10. The display device according to claim 1, in, The display panel further includes a peripheral area surrounding the first area and the second area, wherein the panel driver is configured to provide a third mode control signal to pixels in the peripheral area, and The peripheral area is configured to be driven in the first mode or the second mode based on the third mode control signal.

11. The display device according to claim 10, in, The peripheral region is configured to be driven only in the first mode.

12. The display device according to claim 1, in, The display panel further includes a first side region adjacent to at least one side of the first region. wherein the panel driver is configured to provide a third mode control signal to pixels in the first side area, and The first side region is configured to be driven in the first mode or the second mode based on the third mode control signal.

13. The display device according to claim 12, in, The first side region is configured to be driven in the first mode based on the first region being driven in the first mode and only in the first mode.

14. The display device according to claim 12, in, The first side region is configured to be driven in the first mode or the second mode based on the first region being driven in the second mode.

15. The display device according to claim 12, in, The display panel further includes a second side region adjacent to at least one side of the second region, wherein the panel driver is configured to provide a fourth mode control signal to the pixels in the second side area, and The second side region is configured to be driven in the first mode or the second mode based on the fourth mode control signal.

16. The display device according to claim 15, in, The display panel further includes a peripheral area surrounding the first area, the second area, the first side area, and the second side area. wherein the panel driver is configured to provide a fifth mode control signal to pixels in the peripheral area, and The peripheral area is configured to be driven in the first mode or the second mode based on the fifth mode control signal.

17. The display device according to claim 1, in, The panel driver comprises: a scan driver configured to provide scan signals to the pixels in the first area and the second area; an emission driver configured to provide emission signals to the pixels in the first area and the second area; a data driver configured to provide data voltages to the pixels in the first area and the second area; and A mode driver is configured to provide the first mode control signal to the pixels in the first area and provide the second mode control signal to the pixels in the second area.

18. A display device, the display device include: A display panel including a plurality of pixels and divided into first to k-th regions, wherein k is a natural number greater than or equal to 2; and a panel driver configured to drive the display panel and provide first to k-th mode control signals to the first to k-th regions, respectively; wherein each of the first mode control signal to the kth mode control signal comprises a common gate signal and a private gate signal, and Each of the pixels includes: a first light emitting element configured to emit light having a first viewing angle; a second light emitting element configured to emit light having a second viewing angle narrower than the first viewing angle; an emission transistor configured to be turned on in response to an emission signal; a first mode control transistor connected between the first light emitting element and the emission transistor and configured to be turned on in response to the common gate signal; and A second mode control transistor is connected between the second light emitting element and the emission transistor and is configured to be turned on in response to the private gate signal.

19. The display device according to claim 18, in, The first to kth mode control signals are independent of each other.

20. The display device according to claim 18, in, Each of the pixels further comprises: a driving transistor connected between the driving voltage line and the first node and including a gate electrode connected to the second node; a write transistor connected between the data voltage line and the third node and configured to be turned on in response to a write gate signal; a compensation transistor connected between the first node and the second node and configured to be turned on in response to a compensation gate signal; an initialization transistor connected between a first initialization voltage line and the second node and configured to be turned on in response to an initialization gate signal; a reference transistor connected between a reference voltage line and the third node and configured to be turned on in response to the compensation gate signal; A first capacitor connected between the second node and the third node; and The second capacitor is connected between the driving voltage line and the third node.

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