Display panel and display terminal

Abstract

Embodiments of the present application disclose a display panel and a display terminal. The display panel comprises M rows of pixels and M cascaded gate drive circuits. Each gate drive circuit is connected to one row of pixels. Each gate drive circuit comprises a reset transistor. The gate of K continuously arranged reset transistors is connected to a first metal trace. The gate of M-K continuously arranged reset transistors is connected to a reset signal line. The first metal trace and the reset signal line are in a disconnected state. The display panel provided by the embodiments of the present application can realize the re-cutting of the reset transistor of the panel by one-time cutting. At least the technical problems of low cutting efficiency and low panel yield caused by the multiple cutting times of the connection between the drain of the N reset transistors and the signal line of the preset low potential are solved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a display terminal. Background Technology

[0002] Gate on Array (GOA) circuitry is a technology used in liquid crystal display panels. It achieves progressive scan driving functionality by integrating gate driving circuitry onto the array substrate. Each GOA unit contains a reset transistor to ensure that the gate signal is correctly reset to its initial state at the beginning of each frame, preparing for the driving of a new row of pixels.

[0003] In a GOA circuit with multiple clock signals (N CKs), the first N GOA units are used for pre-charging, thus eliminating the need for reset transistors. In existing panel cutting processes, if all GOA units in the finished panel contain reset transistors, the connection between the drains of the first N reset transistors and the preset low-potential signal lines needs to be cut again. This results in numerous cuts, leading to low cutting efficiency, and multiple cuts can easily affect other traces, thereby impacting the yield of the finished panel. Summary of the Invention

[0004] The embodiments of this application provide a display panel and a display terminal to at least solve the technical problems of low cutting efficiency and low panel yield caused by the repeated cutting of the connection between the drain of N reset transistors and the preset low potential signal line.

[0005] On one hand, embodiments of this application provide a display panel, including: M rows of pixels; M cascaded gate driving circuits, each gate driving circuit corresponding to a row of pixels, each gate driving circuit including a reset transistor; wherein, the gates of K consecutively arranged reset transistors are connected to a first metal trace, the gates of MK consecutively arranged reset transistors are connected to a reset signal line, the first metal trace and the reset signal line are in an open state, M and K are positive integers, and K < M.

[0006] In one embodiment, the first metal trace and the reset signal line are in the same layer and made of the same material.

[0007] In one embodiment, every N cascaded gate driving circuits along the scanning direction of the pixels from top to bottom form a group; wherein, K consecutively arranged reset transistors belong to the first group of gate driving circuits, N represents the number of driving clock signals corresponding to the display panel, K≤N, and M is an integer multiple of N.

[0008] In one embodiment, the gates of the M reset transistors share a second metal trace, and the reset signal line is disposed on the side close to the Mth reset transistor, with the second metal trace connected to the reset signal line.

[0009] In one embodiment, the second metal trace is disconnected between the Kth reset transistor and the (K+1)th reset transistor.

[0010] In one embodiment, the first metal trace and the reset signal line both belong to a third metal trace, and the third metal trace is in an open state at the position of the Kth reset transistor.

[0011] In one embodiment, the third metal trace between the gate of the Kth reset transistor and the gate of the (K+1)th reset transistor is in an open state.

[0012] In one embodiment, K = N / 2.

[0013] In one embodiment, K = N.

[0014] On the other hand, embodiments of this application also provide a display terminal, including the display panel described in any of the above embodiments.

[0015] The beneficial effects provided by the embodiments of this application include at least the following:

[0016] This application provides a display panel including M rows of pixels; M cascaded gate driving circuits, each gate driving circuit corresponding to one row of pixels, and each gate driving circuit including a reset transistor; wherein, the gates of K consecutively arranged reset transistors are connected to a first metal trace, and the gates of MK consecutively arranged reset transistors are connected to a reset signal line, the first metal trace and the reset signal line are disconnected, M and K are positive integers, and K < M. With the display panel provided by this application, the gates of the K consecutively arranged reset transistors are disconnected from the gates of other reset transistors, the other reset transistors are respectively connected to the reset signal line, and the K consecutively arranged reset transistors are not connected to the reset signal line. If the first metal trace and the reset signal line are the same trace, it can be achieved through a single cutting method, at least solving the technical problem of low cutting efficiency and low panel yield caused by the multiple cutting operations between the drains of N reset transistors and the preset low-potential signal line. The panel structure provided in this application can be achieved with only one cutting, effectively improving panel cutting efficiency and panel yield.

[0017] Other beneficial effects of the embodiments of this application will be further explained in the following specific embodiments. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a GOA circuit provided in an optional embodiment of this application;

[0019] Figure 2 This is a scanning schematic diagram of a GOA circuit in a display panel provided in an optional embodiment of this application;

[0020] Figure 3 This is a schematic diagram of a scanning of the GOA circuit in a cut display panel provided in an optional embodiment of this application;

[0021] Figure 4 This is a schematic diagram of the structure of a display panel provided in an optional embodiment of this application;

[0022] Figure 5 This is a schematic diagram of a cutting of a display panel provided in an optional embodiment of this application;

[0023] Figure 6 This is a schematic diagram of another display panel cut according to an optional embodiment of this application.

[0024] Figure 7 This is a schematic diagram of the structure of a display terminal provided in an optional embodiment of this application.

[0025] Explanation of reference numerals in the attached figures

[0026] 1. Display terminal;

[0027] 10, Display panel; 11, First metal trace; 12, Reset signal line; 13, Second metal trace; 14, Third metal trace;

[0028] 101, Pull-down module; 102, Download module; 103, Pull-up module; 104, Pull-down module; 20, Terminal main body. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0030] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0032] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0033] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, and this application does not limit the dimensions and thicknesses of each component.

[0034] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0035] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0036] Reference Figure 1 As shown, in the GOA circuit designed by combining the frame start signal STV and the reset signal Reset, the non-starting GOA cells will have a Reset thin film transistor (TFT) designed on the Reset trace, such as... Figure 1 The Trst shown is connected to Q(N) and VSSQ (default low level). Figure 1 An optional GOA circuit diagram is provided. The GOA circuit includes a pull-up control transistor T11, a pull-down module 102, a pull-up module 103, a pull-down module 104, a pull-down sustaining module 101, and a bootstrap capacitor Cbt. The pull-up control transistor T11 is connected to the (N-6)th stage transmission signal ST(N-6) and the (N-6)th stage scan signal G(N-6), and is electrically connected to the first node Q(N) to pull up the potential of the first node Q(N). The pull-down module 102 is connected to a low-level signal VSSQ and a clock signal CLK to output the current stage transmission signal G(N). The pull-up module 103 is connected to the clock signal CLK and is electrically connected to the first node Q(N) and the second node M(N) to output the current stage scan signal G(N). Pull-down module 104 is connected to a low-level signal Vss and the (N+6)th level scan signal G(N+6), and electrically connected to the first node Q(N), the second node M(N), and the third node P(N), to pull down the potential of the first node Q(N) and the current level scan signal G(N). Pull-down sustaining module 101 is connected to a low-level signal VSSQ and electrically connected to the first node Q(N) and the third node P(N), to maintain the potential of the first node Q(N) at the potential of the low-level signal VSSQ after the pull-down module 104 pulls down the potential of the first node Q(N). The first terminal of the bootstrap capacitor Cbt is electrically connected to the first node Q(N), and the second terminal is electrically connected to the second node M(N). Reset transistor Trst is connected to the low-level signal VSSQ and the control signal Reset, and electrically connected to the first node Q(N). Reset transistor Trst is used to further pull down the potential of the first node Q(N) to the potential of the low-level signal VSSQ under the control of the control signal Reset.

[0037] It should be noted that the GOA circuit structure provided in the embodiments of this application is only for better understanding the principle of this application and should not be construed as a limitation of this application. Furthermore, the specific circuit connections in the pull-down sustaining module 101, the downlink module 102, the pull-up module 103, and the pull-down module 104 can be set according to actual needs, and this application does not impose any specific limitations on them.

[0038] Reference Figure 2As shown, to avoid Q(N) not being able to charge effectively, the first GOA usually omits the Reset TFT (Trst), that is, the first GOA of a conventional display does not have a Reset TFT. In the embodiments of this application, the first GOA can be understood as the first N rows of the first group of cascaded gate drive circuits according to the row scanning order of the GOA, where N corresponds to the number of clock signals, that is, N signals are scanned in a cyclic manner as a group, and the first group can be defined as the first GOA.

[0039] To meet the need for customized resolutions on existing displays, a laser re-cutting method will be used, referring to... Figure 3 As shown, a GOA display screen that has been cut once is cut again to obtain a display screen of the required size. Figure 3 As shown, in the reverse scan mode GOA display, the first end of the GOA will be cut during the secondary cutting (e.g. Figure 3 As shown in the dashed box, the GOA head Reset trace of the cut bar display row will have a Trst design. When Trst is turned on, it will pull down the point of Q(N), which will cause the Q(N) head of the cut bar display GOA to be unable to charge effectively, affecting the display effect.

[0040] The current solution is to use a laser to disconnect the drain of the first N stages of the Trst in the cut strip screen, thus disconnecting it from the VSSQ. This prevents the Trst from turning on properly, thereby avoiding the ineffective charging of the first N stages of Q(N). However, this method requires cutting in N places, which is labor-intensive. Furthermore, due to the small size of the Trst, its drain is difficult to cut, and it is easy to cut other traces, thereby reducing the yield of the cut strip screen.

[0041] To address the aforementioned problems, embodiments of this application provide a display panel. (Refer to...) Figure 4 As shown, the display panel 10 includes: M rows of pixels P1 to P2. M and M cascaded gate drive circuits G1 to G M Each gate drive circuit is connected to a corresponding row of pixels.

[0042] Each gate drive circuit includes a reset transistor (T1 to T2). M ); where K consecutively arranged reset transistors (T1 to T) K The gate of the transistor is connected to the first metal trace 11, and MK consecutively arranged reset transistors (T) K+1 To T M The gate of the first metal trace 11 is connected to the reset signal line 12. The first metal trace 11 and the reset signal line 12 are disconnected. M and K are positive integers, and K < M.

[0043] It should be noted that M is the number of pixel rows on the cut display panel. In actual use, gate driving scanning can be performed in the order from the first row to the Mth row, or in the order from the Mth row to the first row. This application embodiment does not limit this.

[0044] In the display panel provided by the embodiments of this application, the gates of the K consecutively arranged reset transistors are disconnected from the gates of other reset transistors. The other reset transistors are connected to the reset signal line, while the K consecutively arranged reset transistors are not connected to the reset signal line. If the first metal trace and the reset signal line are the same trace, it can be achieved by a single cut. This solves at least the technical problem of low cutting efficiency and low panel yield caused by the multiple cuts between the drains of the existing N reset transistors and the preset low potential signal line. The panel structure provided in the embodiments of this application can be achieved by a single cut, which effectively improves the panel cutting efficiency and panel yield.

[0045] The driving principle of the GOA circuit is similar to that of a shift register. It outputs a high-level voltage signal when the scan row is selected and a low-level voltage signal when it is not selected. GOA units are connected in a cascaded manner, with the output signal of one row serving as both the reset signal of the previous row and the input signal of the next row. In the design of GOA, in order to solve the problem of clock signal (CLK signal) attenuation during transmission on large-size panels, a multi-CLK signal line design is usually adopted, such as a 4CLK, 6CLK, or 8CLK signal line design, to reduce the load and improve efficiency.

[0046] In one embodiment, every N cascaded gate drive circuits along the scanning direction of the pixels from top to bottom form a group; wherein, K consecutively arranged reset transistors belong to the first group of gate drive circuits, N represents the number of drive clock signals corresponding to the display panel 10, K≤N, and M is an integer multiple of N.

[0047] For example, in a GOA circuit designed with 4CLK signal lines, N is 4, and the first four GOA circuits can be regarded as the first GOA. In a GOA circuit designed with 6CLK signal lines, N is 6, and the first six GOA circuits can be regarded as the first GOA.

[0048] In this embodiment, gate drive scanning is performed in the order from the first row to the Mth row for illustrative purposes.

[0049] In one embodiment, the first metal trace 11 and the reset signal line 12 are on the same layer and made of the same material, that is, the first metal trace 11 and the reset signal line 12 are located on the same layer and are made of the same material. The first metal trace 11 and the reset signal line 12 can be the same metal trace, which is broken at a specific location. This can be achieved by laser cutting or by other panel processes to break the metal layer.

[0050] Reference Figure 5 As shown, in an optional embodiment, one possible structure of the display panel 10 is as follows: the gates of M reset transistors share a second metal trace 13, and a reset signal line 12 is disposed on the side close to the Mth reset transistor. The second metal trace 13 is connected to the reset signal line 12. The second metal trace 13 is in an open state between the Kth reset transistor and the (K+1)th reset transistor, as shown. Figure 5 As shown in L1.

[0051] exist Figure 5 In the example shown, the second metal trace 13 runs through the entire display panel 10 along the row scan direction, and the gates of the M reset transistors are all formed through the metal layer where the second metal trace 13 is located. The reset signal line 12 is located at the bottom of the display panel 10, that is, below the Mth row of pixels, which can also be understood as below the Mth GOA. The second metal trace 13 can be connected to the reset signal line 12 through vias. In this way, the M reset transistors can obtain the reset signal through the reset signal line 12, and the reset signal propagates from bottom to top.

[0052] In order to disable the reset transistor at the first end GOA of the cut display panel 10, the second metal trace 13 between the Kth reset transistor and the (K+1)th reset transistor can be disconnected. In this way, the first K reset transistors will not be able to obtain the reset signal and the reset transistors will not work properly.

[0053] It should be noted that K can be any positive integer less than N. If K is 1, the first reset transistor cannot work properly, and Q(1) can be charged normally. If K is 2, the first two reset transistors cannot work properly, and Q(1) and Q(2) can be charged normally. This application does not specifically limit the value of K, but only provides an optional implementation method. In this implementation method, the closer the value of K is to N, the better the charging effect of the first terminal GOA is.

[0054] In one example, if N is 6, then K is an integer less than 6. For example, K can be 2, 3, 4 or 5, or K can be equal to 6, as long as at least 2 Q points can be charged normally.

[0055] In the display panel provided by the embodiments of this application, the gates of the K consecutively arranged reset transistors are disconnected from the gates of other reset transistors. The other reset transistors are connected to the reset signal line, while the K consecutively arranged reset transistors are not connected to the reset signal line. If the first metal trace and the reset signal line are the same trace, it can be achieved by a single cut. This solves at least the technical problem of low cutting efficiency and low panel yield caused by the multiple cuts between the drains of the existing N reset transistors and the preset low potential signal line. The panel structure provided in the embodiments of this application can be achieved by a single cut, which effectively improves the panel cutting efficiency and panel yield.

[0056] Disconnecting the gate signal of the N / 2th stage reset transistor before the display row prevents it from functioning properly, thus avoiding the ineffective charging of the first N / 2 stages Q(N). Similarly, cutting the Nth display row by disconnecting the trace using laser or other cutting methods disconnects the gate signal of the Nth stage reset transistor before the display row, preventing it from functioning properly and thus avoiding the ineffective charging of the first N stages Q(N). Regardless of which row is being cut, only one location of the second metal trace 13 needs to be cut, which is simple and efficient, reduces the cutting workload, and improves the re-cutting yield and display effect of the GOA display.

[0057] Reference Figure 6 As shown, in an optional embodiment, an optional structure of the display panel 10 is as follows: the first metal trace 11 and the reset signal line 12 both belong to the third metal trace 14, and the third metal trace 14 is in an open state at the position of the Kth reset transistor, as shown. Figure 6 As shown in L2.

[0058] Figure 6 In the panel structure shown, the first metal trace 11 and the reset signal line 12 are the same metal trace, namely the third metal trace 14. This can be understood as follows: after one cut, the gates of all M reset transistors in the display panel 10 are connected to the third metal trace 14. In this case, the third metal trace 14 can be considered the reset signal line for the entire display panel 10. Figure 6 In the panel structure shown, the reset signal line (i.e., the third metal trace 14) runs through the entire display panel from top to bottom along the row scanning direction. After two cuts, the third metal trace 14 is broken at the position of the Kth reset transistor, thus splitting into the first metal trace 11 and the reset signal line 12. The third metal trace 14 serves as the reset signal line, directly connected to the reset signal. The reset signal propagates from bottom to top, that is, from the Mth reset transistor towards the first reset transistor.

[0059] In one embodiment, disconnecting the third metal trace 14 at the location of the Kth reset transistor can be achieved by disconnecting the third metal trace 14 between the gate of the Kth reset transistor and the gate of the (K+1)th reset transistor.

[0060] In order to disable the reset transistor at the first end GOA of the cut display panel 10, the third metal trace 14 between the Kth reset transistor and the (K+1)th reset transistor can be disconnected. In this way, the first K reset transistors will not be able to obtain the reset signal and the reset transistors will not work properly.

[0061] It should be noted that K can be any positive integer less than N. If K is 1, the first reset transistor cannot work properly, and Q(1) can be charged normally. If K is 2, the first two reset transistors cannot work properly, and Q(1) and Q(2) can be charged normally. This application does not specifically limit the value of K, but only provides an optional implementation method. In this implementation method, the closer the value of K is to N, the better the charging effect of the first terminal GOA is.

[0062] In one example, if N is 8, then K is an integer less than 8. For example, K can be 2, 3, 4, 5, 6 or 7, or K can be equal to 8, as long as at least 2 Q points can be charged normally.

[0063] In the display panel provided by the embodiments of this application, the gates of the K consecutively arranged reset transistors are disconnected from the gates of other reset transistors. The other reset transistors are connected to the reset signal line, while the K consecutively arranged reset transistors are not connected to the reset signal line. If the first metal trace and the reset signal line are the same trace, it can be achieved by a single cut. This solves at least the technical problem of low cutting efficiency and low panel yield caused by the multiple cuts between the drains of the existing N reset transistors and the preset low potential signal line. The panel structure provided in the embodiments of this application can be achieved by a single cut, which effectively improves the panel cutting efficiency and panel yield.

[0064] Disconnecting the gate signal of the N / 2th stage reset transistor before the display row prevents it from functioning properly, thus avoiding the ineffective charging of the Q(N) transistors in the first N / 2 stages. Similarly, cutting the Nth display row by disconnecting the trace using laser or other cutting methods disconnects the gate signal of the Nth stage reset transistor before the display row, preventing it from functioning properly and thus avoiding the ineffective charging of the Q(N) transistors in the first N stages. Regardless of which row is being cut, only one location on the third metal trace 14 needs to be cut, which is simple and efficient, reduces the cutting workload, and improves the re-cutting yield and display effect of the GOA display.

[0065] Reference Figure 7As shown, another embodiment of this application also provides a display terminal 1, including a display panel 10 and a terminal body 20 as described in any of the above embodiments, wherein the display panel 1 and the terminal body 20 are integrated into one unit. The terminal body 20 may include a backlight module, which is disposed on the side of the substrate of the display panel 10 opposite to the GOA circuit. The backlight module is used to provide a light source for the display panel 1.

[0066] The display terminal can be any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, or navigators.

[0067] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: M rows of pixels; M cascaded gate driving circuits, each gate driving circuit being connected to a row of pixels, and each gate driving circuit including a reset transistor. In this configuration, the gates of K consecutively arranged reset transistors are connected to a first metal trace, and the gates of MK consecutively arranged reset transistors are connected to a reset signal line. The first metal trace and the reset signal line are disconnected. M and K are positive integers, and K < M. The gate driving circuits cascaded from top to bottom along the scanning direction of the pixels constitute a group of N; wherein, the K consecutively arranged reset transistors belong to the first group of gate driving circuits, N represents the number of driving clock signals corresponding to the display panel, K≤N, and M is an integer multiple of N; The gates of the M reset transistors share a second metal trace, and the reset signal line is disposed on the side close to the Mth reset transistor, with the second metal trace connected to the reset signal line; The second metal trace is in an open state between the Kth reset transistor and the (K+1)th reset transistor.

2. The display panel according to claim 1, characterized in that, The first metal trace is in the same layer and made of the same material as the reset signal line.

3. The display panel according to claim 1, characterized in that, The first metal trace and the reset signal line both belong to the third metal trace, which is in an open state at the position of the Kth reset transistor.

4. The display panel according to claim 3, characterized in that, The third metal trace between the gate of the Kth reset transistor and the gate of the (K+1)th reset transistor is in an open state.

5. The display panel according to claim 1, characterized in that, K=N / 2.

6. The display panel according to claim 1, characterized in that, K=N.

7. A display terminal, characterized in that, The display panel includes any one of claims 1 to 6.

Images