Driving module, driving circuit, display panel and display device

Abstract

A driving module, a driving circuit, a display panel and a display device, wherein the driving module includes an anti-reverse unit, a working unit and an input line, wherein the anti-reverse unit includes a switch element and a resistor element, wherein the resistor element is connected to a source and a drain of the switch element, the working unit is connected to the drain of the switch element, and the input line is connected to a source and a gate of the switch element, wherein the input line is suitable for inputting a first voltage to the anti-reverse unit to open the switch element, wherein when the working unit inputs a second voltage greater than the first voltage to the anti-reverse unit, the switch element is closed, thereby ensuring the safety and stability of the driving module in the LPWG mode.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal panels, and in particular to a driving module, a driving circuit, a display panel and a display device. Background Art

[0002] With the development of consumer electronic products, major display brand manufacturers are constantly innovating, the functions of display screens are also expanding, and low power wake-up gesture (LPWG) is becoming more and more popular. When the display screen is in LPWG mode, users can use gesture recognition to wake up the screen or perform specific operations such as checking the time and receiving notifications without directly touching the screen, which greatly improves the convenience and user experience of the device, and the power consumption of the display screen is low.

[0003] When a display device in the prior art works for a long time in the LPWG mode, there is a problem of current backflow causing circuit damage. Summary of the invention

[0004] The object of the present invention is to provide a driving module, a driving circuit, a display panel and a display device, so as to solve the problem in the prior art that when the display device works for a long time in the LPWG mode, current backflow may cause circuit damage.

[0005] To achieve the purpose of the present invention, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides a driving module, comprising: an anti-reverse unit, comprising a switch element and a resistor element, wherein the resistor element is connected to a source and a drain of the switch element; a working unit, connected to the drain of the switch element; an input line, connected to a source and a gate of the switch element, wherein the input line is suitable for inputting a first voltage to the anti-reverse unit to open the switch element; wherein, when the working unit inputs a second voltage greater than the first voltage to the anti-reverse unit, the switch element is closed.

[0007] In one embodiment, the first voltage is V1, the second voltage is V2, the resistance value of the resistor is R1, the resistance value of the connecting wire connecting the input line, the resistor and the working unit is R2, and the maximum withstand voltage of the connecting wire is V3, satisfying: R1≥R2(V2-V1-V3) / V3.

[0008] In one embodiment, the switch element includes a first thin film transistor and a second thin film transistor, the resistor element includes a first resistor and a second resistor, the first resistor is connected to the source and drain of the first thin film transistor, the second resistor is connected to the source and drain of the second thin film transistor, the drain of the first thin film transistor and the drain of the second thin film transistor are both connected to the working unit; the input line includes a first power line and a clock line, the source of the first thin film transistor is connected to the first power line, and the source of the second thin film transistor is connected to the clock line.

[0009] In one embodiment, the working unit includes: a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor and a sixth thin film transistor, the source of the third thin film transistor is electrically connected to the first thin film transistor, the drain of the third thin film transistor is electrically connected to the gate of the fourth thin film transistor and the drain of the sixth thin film transistor, the source of the fourth thin film transistor is electrically connected to the drain of the second thin film transistor, the drain of the fourth thin film transistor is electrically connected to the drain of the fifth thin film transistor, the source of the fifth thin film transistor is electrically connected to the source of the sixth thin film transistor, the gate of the third thin film transistor, the gate of the fifth thin film transistor and the gate of the sixth thin film transistor are respectively connected to a driving line; a second power line is electrically connected to the source of the fifth thin film transistor and the source of the sixth thin film transistor; a scan line is electrically connected to the drain of the fourth thin film transistor and the drain of the fifth thin film transistor.

[0010] In one embodiment, the working unit further includes a capacitor, one end of the capacitor is electrically connected to the gate of the fourth thin film transistor, and the other end of the capacitor is electrically connected to the drain of the fourth thin film transistor.

[0011] In one embodiment, the driving line includes a first line and a second line, the first line is connected to the gate of the third thin film transistor, and the second line is connected to the gate of the fifth thin film transistor and the gate of the sixth thin film transistor.

[0012] In a second aspect, the present invention further provides a driving circuit, comprising a pixel electrode and a driving module according to any one of the various implementations of the first aspect, wherein the pixel electrode is connected to the working unit.

[0013] In one embodiment, the driving module includes a scan line and a first routing line, the scan line is connected to the pixel electrode, there are N driving modules, and the first routing line of the Nth driving module is connected to the scan line of the N-4th driving module.

[0014] In a third aspect, the present invention further provides a display panel, comprising a signal line and a driving circuit as described in any one of the various embodiments of the second aspect, wherein the signal line is connected to the pixel electrode.

[0015] In a fourth aspect, the present invention further provides a display device, comprising a housing and a display panel according to any one of the various embodiments of the third aspect, wherein the display panel is installed in the housing.

[0016] An anti-reverse unit is provided, the anti-reverse unit includes a switch element and a resistor element, the resistor element is connected to the source and drain of the switch element, the working unit is connected to the drain of the switch element, the input line is connected to the source and gate of the switch element, and the input line is suitable for inputting a first voltage to the anti-reverse unit to open the switch element, wherein when the working unit inputs a second voltage greater than the first voltage to the anti-reverse unit, the switch element is closed, so that when the second voltage generated by the accumulated potential of the working unit is backflowed to the input line, the switch element will be quickly closed under the joint action of the first voltage and the second voltage, thereby ensuring that the second voltage can only flow to the input line through the resistor element, and the voltage dividing effect of the resistor element reduces the amplitude of the second voltage, avoiding the risk of burns caused by excessively high input line potential, and ensuring the safety and stability of the drive module in LPWG mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a schematic diagram of a display device according to an embodiment;

[0019] Figure 2 is a schematic diagram of a display panel of an embodiment;

[0020] Figure 3 is a schematic diagram of a driving module of an embodiment;

[0021] Figure 4 It is a schematic diagram of a comparative driving module.

[0022] Description of reference numerals:

[0023] 1000-display device;

[0024] 100-display panel;

[0025] 10- driving circuit;

[0026] GOA-driver module;

[0027] 20-anti-reversal unit, 21-first unit, T1-first thin film transistor, Ra-first resistor, 22-second unit, T2-second thin film transistor, Rb-second resistor;

[0028] 30-working unit, T3-third thin film transistor, T4-fourth thin film transistor, T5-fifth thin film transistor, T6-sixth thin film transistor, Gate-scanning line, C-capacitor;

[0029] 40-input line, 41-first power line, 42-clock line;

[0030] VGL-second power line, L1-first line, L2-second line, P-pixel electrode, Q-first node, VS-signal line;

[0031] 200-Housing. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there can be a central component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there can be a central component at the same time.

[0034] Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in the present invention includes any and all combinations of one or more of the related listed items.

[0035] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0036] Please refer to Figure 1The present invention provides a display device 1000, including a housing 200 and a display panel 100 in an embodiment of the present invention, and the display panel 100 is installed in the housing 200. The display device 1000 can be an e-reader, an e-book, a display, a mobile phone, etc., without limitation. The display device 1000 provided by the present invention adopts the housing 200 and the display panel 100 in an embodiment of the present invention. When the display device 1000 is in LPWG mode, the user can wake up the display panel 100 or perform specific operations such as checking the time and receiving notifications by gesture recognition without touching the display panel 100 or operating buttons, which greatly improves the convenience and user experience of the display device 1000, and the display device 1000 can achieve low power consumption operation by reducing the frequency of the scanning signal and adjusting the waveform of the scanning signal.

[0037] Please refer to Figure 2 The present invention further provides a display panel 100, comprising a signal line VS and a driving circuit 10 in an embodiment of the present invention, wherein the signal line VS is connected to a pixel electrode P. Optionally, there are multiple signal lines VS, and each signal line VS is connected to at least one pixel electrode P. Optionally, the pixel electrode P is connected to a scan line Gate of a driving module GOA of the driving circuit 10. Optionally, there are N driving modules GOA (N is a positive integer ≥ 2), then there are N scan lines Gate, and each scan line Gate is respectively connected to at least one pixel electrode P.

[0038] Optionally, the display panel 100 is a liquid crystal panel (TFT-LCD panel), and the display panel 100 includes an upper substrate, liquid crystal and an array substrate. The signal line VS and the driving circuit 10 in the embodiment of the present invention are both arranged on the array substrate. The driving circuit 10 changes the pixel voltage between the upper substrate and the array substrate by changing the output voltage to control the arrangement direction of the liquid crystal or the physical state of the liquid crystal. The light output by the external light source or the backlight source of the display panel 100 forms polarized light through the polarization function of the liquid crystal, and then is projected onto the panel to produce a picture. Optionally, there are multiple pixel electrodes P, and the multiple pixel electrodes P are arranged in an array. Optionally, the array substrate includes a substrate, a driving circuit layer, a passivation layer and a pixel electrode P layer stacked in sequence, the signal line VS and the driving circuit 10 in the embodiment of the present invention are arranged in the driving circuit layer, and the pixel electrode P is arranged in the pixel electrode layer.

[0039] The display panel 100 provided by the present invention adopts a signal line VS and a driving circuit 10 in an embodiment of the present invention, wherein the signal line VS is connected to the pixel electrode P, so that when the display device 1000 works for a long time in the LPWG mode, the backflow voltage generated by the driving circuit 10 will not damage the circuit.

[0040] Please refer to Figure 2The present invention further provides a driving circuit 10, comprising a pixel electrode P and a driving module GOA in an embodiment of the present invention, wherein the pixel electrode P is connected to a working unit 30. Optionally, the driving circuit 10 comprises N driving modules GOA, which are sequentially connected and each of which is connected to at least one pixel electrode P. The driving circuit 10 provided by the present invention adopts the pixel electrode P and the driving module GOA in an embodiment of the present invention, wherein the pixel electrode P is connected to the working unit 30, so that when the display device 1000 works for a long time in the LPWG mode, the backflow voltage generated by the driving module GOA will not damage the circuit.

[0041] Please refer to Figure 3 The present invention also provides a driving module GOA, including an anti-reverse unit 20, a working unit 30 and an input line 40, the anti-reverse unit 20 includes a switch element and a resistor element, the resistor element is connected to the source and drain of the switch element, the working unit 30 is connected to the drain of the switch element, the input line 40 is connected to the source and gate of the switch element, the input line 40 is suitable for inputting a first voltage to the anti-reverse unit 20 to open the switch element, wherein when the working unit 30 inputs a second voltage greater than the first voltage to the anti-reverse unit 20, the switch element is closed.

[0042] Among them, when the display device 1000 is in the LPWG mode, the input line 40 always inputs the first voltage to the switch element to turn on the switch element. At this time, the switch element short-circuits the two ends of the resistor element, and the first voltage is all input to the working unit 30 through the switch element, so that the display panel 100 can respond quickly when the user controls the display device 1000 through gestures.

[0043] Please refer to Figure 4 , Figure 4 The figure shows a schematic diagram of a comparative driving module GOA. Since the working unit 30 always receives the first voltage input by the input line 40, when the internal potential of the working unit 30 accumulates and reaches the second voltage, the potential of the working unit 30 is greater than the potential of the input line 40, causing the second voltage on the working unit 30 to flow back to the input line 40, resulting in an increase in the potential on the input line 40. According to Joule's law and the thermal effect of current, the input line 40 generates a large amount of heat, causing the input line 40 to be burned and damaged.

[0044] By setting an anti-reverse unit 20, the anti-reverse unit 20 includes a switch element and a resistor element, the resistor element is connected to the source and drain of the switch element, the working unit 30 is connected to the drain of the switch element, the input line 40 is connected to the source and gate of the switch element, and the input line 40 is suitable for inputting a first voltage to the anti-reverse unit 20 to open the switch element, wherein when the working unit 30 inputs a second voltage greater than the first voltage to the anti-reverse unit 20, the switch element is closed, so that when the second voltage generated by the accumulated potential of the working unit 30 is backflowed to the input line 40, the switch element will be quickly closed under the joint action of the first voltage and the second voltage, thereby ensuring that the second voltage can only flow to the input line 40 through the resistor element, and the voltage dividing effect of the resistor element reduces the amplitude of the second voltage, avoiding the risk of burns caused by excessive potential of the input line 40, and ensuring the safety and stability of the driving module GOA in the LPWG mode.

[0045] Please refer to Figure 3 The switch element includes a first thin film transistor T1 and a second thin film transistor T2, the resistor element includes a first resistor Ra and a second resistor Rb, the first resistor Ra is connected to the source and the drain of the first thin film transistor T1, the second resistor Rb is connected to the source and the drain of the second thin film transistor T2, the drain of the first thin film transistor T1 and the drain of the second thin film transistor T2 are both connected to the working unit 30, the input line 40 includes a first power line 41 (VDD) and a clock line 42 (CLK), the source of the first thin film transistor T1 is connected to the first power line 41, and the source of the second thin film transistor T2 is connected to the clock line 42.

[0046] Optionally, the anti-reversal unit 20 includes a first unit 21 and a second unit 22 , the first unit 21 includes a first thin film transistor T1 and a first resistor Ra, and the second unit 22 includes a second thin film transistor T2 and a second resistor Rb.

[0047] Optionally, the first thin film transistor T1 includes a first conductor (not shown), a second conductor (not shown) and a first semiconductor (not shown) in the array substrate, the first conductor and the second conductor are arranged at intervals, the first semiconductor connects the first conductor and the second conductor, the first conductor constitutes the source of the first thin film transistor T1, the second conductor constitutes the drain of the first thin film transistor T1, and the first semiconductor constitutes the gate of the first thin film transistor T1. Optionally, the structure of the second thin film transistor T2 is similar to that of the first thin film transistor T1, and can be referred to and will not be repeated.

[0048] Optionally, the first power line 41 is arranged and connected to the first conductor in the array substrate at the same layer, and is also connected to the first semiconductor. Optionally, the first power line 41 is used to input a first high level to the gate and source of the first thin film transistor T1 in the LPWG mode, so that the first thin film transistor T1 is always in a fully turned on or partially turned on state.

[0049] Optionally, the clock line 42 is arranged and connected in the same layer as the conductor of the second thin film transistor T2 as the source in the array substrate, and is also connected to the semiconductor of the second thin film transistor T2 as the gate. Optionally, the clock line 42 is used to input the second high level to the gate and source of the second thin film transistor T2 in the LPWG mode, so that the second thin film transistor T2 is always in a fully open or partially open state, and the second high level is output to the corresponding pixel electrode P through the working unit 30. Optionally, the first high level and the second high level may be equal or unequal, without limitation.

[0050] Specifically, when the display device 1000 is in the LPWG mode, the working unit 30 simultaneously inputs a second voltage to the drain of the first thin film transistor T1 and the drain of the second thin film transistor T2. The second voltage is transmitted to the source and gate of the first thin film transistor T1 through the drain of the first thin film transistor T1 on the one hand, and is transmitted to the source and gate of the second thin film transistor T2 through the drain of the second thin film transistor T2 on the other hand.

[0051] Since the second voltage is in opposite directions to the first high level and the second high level, the second voltage pulls down the voltage of the source and the gate of the first thin film transistor T1 to the first low level, and pulls down the source and the gate of the second thin film transistor T2 to the second low level, so that both the first thin film transistor T1 and the second thin film transistor T2 are turned off, and the second voltage can only flow to the first power line 41 through the first resistor Ra, and can only flow to the clock line 42 through the second resistor Rb.

[0052] Since the first resistor Ra is connected in series with the first power line 41 and the working unit 30, and the second resistor Rb is connected in series with the clock line 42 and the working unit 30, only a lower voltage is input to the first power line 41 and the clock line 42 after the second voltage is divided by the first resistor Ra and the second resistor Rb, so that the first power line 41 and the clock line 42 will not generate much heat and cause burns.

[0053] In this process, since the first thin film transistor T1 and the second thin film transistor T2 are both turned off, the voltage flowing to the gate and source of the first thin film transistor T1 through the first resistor Ra is small, so that the first thin film transistor T1 is reopened or not completely opened, and the voltage flowing to the gate and source of the second thin film transistor T2 through the second resistor Rb is small, so that the second thin film transistor T2 is reopened or not completely opened. At this time, the first thin film transistor T1 and the second thin film transistor T2 repeat the above-mentioned closing process under the backflow of the second voltage, so that the second voltage cannot continue to flow to the first power line 41 and the clock line 42 through the first thin film transistor T1 and the second thin film transistor T2, so as to avoid the first power line 41 and the clock line 42 always being in a high potential state, so that the heat generated by the first power line 41 and the clock line 42 when the first thin film transistor T1 and the second thin film transistor T2 are in the open or incompletely open state can be quickly dissipated, so as to prevent the first power line 41 and the clock line 42 from being burned.

[0054] By setting the switch element to include a first thin film transistor T1 and a second thin film transistor T2, the resistor element to include a first resistor Ra and a second resistor Rb, the first resistor Ra is connected to the source and drain of the first thin film transistor T1, the second resistor Rb is connected to the source and drain of the second thin film transistor T2, the drain of the first thin film transistor T1 and the drain of the second thin film transistor T2 are both connected to the working unit 30, the input line 40 includes a first power line 41 and a clock line 42, the source of the first thin film transistor T1 is connected to the first power line 41, and the source of the second thin film transistor T2 is connected to the clock line 42, so that the backflow voltage generated by the working unit 30 will not damage the first power line 41 under the action of the first thin film transistor T1 and the first resistor Ra, and will not damage the clock line 42 under the action of the second resistor Rb of the second thin film transistor T2.

[0055] Please refer to Figure 3The working unit 30 includes a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a second power line VGL and a scan line Gate, a source of the third thin film transistor T3 is electrically connected to a drain of the first thin film transistor T1, a drain of the third thin film transistor T3 is electrically connected to a gate of the fourth thin film transistor T4 and a drain of the sixth thin film transistor T6, a source of the fourth thin film transistor T4 is electrically connected to a drain of the second thin film transistor T2, a drain of the fourth thin film transistor T4 is electrically connected to a drain of the fifth thin film transistor T5, a source of the fifth thin film transistor T5 is electrically connected to a source of the sixth thin film transistor T6, a gate of the third thin film transistor T3, a gate of the fifth thin film transistor T5 and a gate of the sixth thin film transistor T6 are respectively connected to a driving line, a second power line VGL is electrically connected to a source of the fifth thin film transistor T5 and a source of the sixth thin film transistor T6, and a scan line Gate is electrically connected to a drain of the fourth thin film transistor T4 and a drain of the fifth thin film transistor T5.

[0056] Optionally, the structures of the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 in the array substrate are similar to the structure of the first thin film transistor T1, which can be referred to and will not be described in detail. Optionally, the second power line VGL is arranged and connected to the conductor of the fifth thin film transistor T5 as the source and the conductor of the sixth thin film transistor T6 as the source in the array substrate. Optionally, the scan line Gate is arranged and connected to the conductor of the fourth thin film transistor T4 as the drain and the conductor of the fifth thin film transistor T5 as the drain.

[0057] Optionally, the source of the fifth thin film transistor T5 and the source of the sixth thin film transistor T6 may share the same conductor. The gate of the fifth thin film transistor T5 and the gate of the sixth thin film transistor T6 may share the same semiconductor. Optionally, the drain of the fourth thin film transistor T4 and the drain of the fifth thin film transistor T5 may share the same conductor. Optionally, the drain of the third thin film transistor T3 and the drain of the sixth thin film transistor T6 may share the same conductor.

[0058] Among them, the driving line always inputs the third high level to the gate of the third thin film transistor T3 in the LPWG mode, so that the third thin film transistor T3 is always in an open or partially open state, so that the first high level input by the first power line 41 can be input to the gate of the fourth thin film transistor T4 through the first thin film transistor T1 and the third thin film transistor T3, so that the fourth thin film transistor T4 is always in an open or partially open state, and then the second high level input by the clock line 42 is input to the scanning line Gate through the second thin film transistor T2 and the fourth thin film transistor T4. At the same time, the driving line always inputs the fourth high level to the gate of the fifth thin film transistor T5 and the gate of the sixth thin film transistor T6 in the LPWG mode, so that the fifth thin film transistor T5 and the sixth thin film transistor T6 are always in an open or partially open state.

[0059] The second power line VGL is used to input a third low level to the source of the fifth thin film transistor T5 and the source of the sixth thin film transistor T6, so that when the display device 1000 is not in the LPWG mode, the second high level output by the scanning line Gate of this stage is pulled down to the third low level. When the display device 1000 is in the LPWG mode, since the fifth thin film transistor T5 and the sixth thin film transistor T6 are always turned on or not fully turned on, the first high level input by the first power line 41 and the second high level input by the clock line 42 are continuously accumulated in the working unit 30 to generate the aforementioned second voltage and flow back to the first power line 41 and the clock line 42.

[0060] By setting the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the second power line VGL and the scan line Gate to form a working unit 30, the driving module GOA can input the second high level from the clock line 42 to the aforementioned pixel electrode P through the scan line Gate, thereby realizing image display in the corresponding frame.

[0061] Please refer to Figure 3 , the first voltage is V1, the second voltage is V2, the resistance value of the resistor is R1, the resistance value of the connecting wire connecting the input line 40, the resistor and the working unit 30 is R2, and the maximum withstand voltage of the connecting wire is V3, satisfying: R1≥R2(V2-V1-V3) / V3.

[0062] Specifically, the first voltage includes the aforementioned first high level and the second high level, the first high level is V11, and the second high level is V12. The connection point of the drain of the aforementioned sixth thin film transistor T6, the drain of the third thin film transistor T3, and the gate of the fourth thin film transistor T4 is the first node Q, the connecting line includes the third line and the fourth line, the starting points of the third line and the fourth line are both the first node Q, the voltage of the first node Q is the second voltage, the third line is connected in series with the first power line 41, the first resistor Ra, the source of the third thin film transistor T3, the drain of the third thin film transistor T3, and the first node Q in sequence, and the fourth line is connected in series with the clock line 42, the second resistor Rb, the source of the fourth thin film transistor T4, the drain of the fourth thin film transistor T4, part of the clock line 42, the drain of the fifth thin film transistor T5, the source of the fifth thin film transistor T5, the source of the sixth thin film transistor T6, the drain of the sixth thin film transistor T6, and the first node Q in sequence.

[0063] Then the resistance value of the third line is R21 and the maximum withstand voltage is V31, the resistance value of the fourth line is R22 and the maximum withstand voltage is V32, the resistance value of the first resistor Ra is R11, and the resistance value of the second resistor Rb is R12, satisfying: R11 ≥ R21 (V2-V11-V31) / V31, R12 ≥ R22 (V2-V12-V32) / V32. Among them, R11 is the minimum value of the first resistor Ra that satisfies the first power line 41 is not damaged, and R12 is the minimum value of the second resistor Rb that satisfies the clock line 42 is not damaged.

[0064] By setting the first voltage to V1, the second voltage to V2, the resistance value of the resistor to R1, the resistance value of the connecting wire connecting the input line 40, the resistor and the working unit 30 to R2, and the maximum withstand voltage of the connecting wire to V3, it satisfies: R1≥R2(V2-V1-V3) / V3, so that the resistor can divide the second voltage so that the voltage on the input line 40 will not be too high, thereby avoiding excessive potential on the input line 40 and heat damage to the input line 40.

[0065] Please refer to Figure 3 The working unit 30 further includes a capacitor C, one end of which is electrically connected to the gate of the fourth thin film transistor T4, and the other end of which is electrically connected to the drain of the fourth thin film transistor T4. Optionally, the capacitor C includes a first electrode plate (not shown), a first insulating plate (not shown) and a second electrode plate (not shown) overlapping in sequence in the array substrate, the first electrode plate and the second electrode plate are arranged opposite to each other, the first electrode plate is connected to the semiconductor serving as the gate of the fourth thin film transistor T4, and the second electrode plate is arranged in the same layer and connected to the conductor serving as the drain of the fourth thin film transistor T4.

[0066] The capacitor C is used to charge under the action of the first high level output by the first power line 41, and discharge to the gate of the fourth thin film transistor T4 after charging, so as to increase the opening speed of the fourth thin film transistor T4 when the first power line 41 controls the fourth thin film transistor T4 to turn on.

[0067] By setting the working unit 30 to also include a capacitor C, one end of the capacitor C is electrically connected to the gate of the fourth thin film transistor T4, and the other end of the capacitor C is electrically connected to the drain of the fourth thin film transistor T4, the opening speed of the fourth thin film transistor T4 is improved, and the image output delay of the display panel 100 is reduced.

[0068] Please refer to Figure 3 The driving wires include a first wire L1 and a second wire L2 . The first wire L1 is connected to the gate of the third thin film transistor T3 . The second wire L2 is connected to the gate of the fifth thin film transistor T5 and the gate of the sixth thin film transistor T6 .

[0069] The first wiring L1 is used to input the aforementioned third high level to the gate of the third thin film transistor T3 to turn on the third thin film transistor T3, and also to input a low level to the gate of the third thin film transistor T3 to turn off the third thin film transistor T3. The second wiring L2 is used to input the aforementioned fourth high level to the gate of the fifth thin film transistor T5 and the gate of the sixth thin film transistor T6 to turn on the fifth thin film transistor T5 and the sixth thin film transistor T6, and also to input a low level to the gate of the fifth thin film transistor T5 and the gate of the sixth thin film transistor T6 to turn off the fifth thin film transistor T5 and the sixth thin film transistor T6.

[0070] Specifically, the first line L1 always inputs the third high level to the gate of the third thin film transistor T3 in the LPWG mode, and the second line L2 always inputs the fourth high level to the gates of the fifth thin film transistor T5 and the sixth thin film transistor T6 in the LPWG mode.

[0071] By setting the driving line to include the first line L1 and the second line L2, the first line L1 is connected to the gate of the third thin film transistor T3, and the second line L2 is connected to the gate of the fifth thin film transistor T5 and the gate of the sixth thin film transistor T6, so that the third thin film transistor T3 can be turned on or off under the drive of the first line L1, and the third thin film transistor T3 is always controlled to be turned on in the LPWG mode, the fifth thin film transistor T5 and the sixth thin film transistor T6 can be turned on or off under the drive of the second line L2, and the fifth thin film transistor T5 and the sixth thin film transistor T6 are always controlled to be turned on in the LPWG mode, so as to realize the display function of the display panel 100.

[0072] Please refer to Figure 2The driving module GOA includes a scanning line Gate and a first wiring L1. There are N driving modules GOA. The first wiring L1 of the Nth driving module GOA is connected to the scanning line Gate of the N-4th driving module GOA.

[0073] Specifically, the number of driving modules GOA is N, so the number of first lines L1 and the number of scanning lines Gate are also N. In order to conveniently distinguish the connection relationship between the N first lines L1, the N scanning lines Gate and the N driving modules GOA, Figure 2 In the example, the first driver module is GOA1, and the N-4th driver module is GOA N-4 , the Nth driver module is GOA N Similarly, the first line of the Nth driver module GOA is L1. N , the scan line of the Nth driver module GOA is Gate N , and so on, I will not go into details.

[0074] Optionally, the first line L1 of the Nth driving module GOA and the scanning line Gate of the N-4th driving module GOA may be the same line, or may be connected through an intermediate line, without limitation.

[0075] By setting the driving module GOA to include a scan line Gate and a first wiring L1, there are N driving modules GOA, and the first wiring L1 of the Nth driving module GOA is connected to the scan line Gate of the N-4th driving module GOA, so that the driving circuit 10 can control the opening and closing of the third thin film transistor T3 without adding additional wiring, so that the structure of the driving circuit 10 is simple and the production cost is low.

[0076] In the description of the embodiments of the present invention, it should be noted that the orientation or positional relationship of terms such as "center", "up", "down", "left", "right", "vertical", "horizontal", "inside" and "outside" are based on the orientation or positional relationship described in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0077] What is disclosed above is only a preferred embodiment of the present invention, and it certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope covered by the present invention.

Claims

1. A driving module, characterized in that: A driving circuit for a display panel, the driving module comprising: an anti-reversal unit, comprising a switch element and a resistor element, wherein the switch element comprises a first thin film transistor and a second thin film transistor, and the resistor element comprises a first resistor and a second resistor, wherein the first resistor is connected to a source electrode and a drain electrode of the first thin film transistor, and the second resistor is connected to a source electrode and a drain electrode of the second thin film transistor; a working unit connected to the drain electrode of the first thin film transistor and the drain electrode of the second thin film transistor; An input line, comprising a first power line and a clock line, wherein the first power line is connected to a source and a gate of the first thin film transistor, the clock line is connected to a source and a gate of the second thin film transistor, the first resistor is connected in series to the first power line and the working unit, the second resistor is connected in series to the clock line and the working unit, the first power line is used to input a first high level to the gate and the source of the first thin film transistor in an LPWG mode, so that the first thin film transistor is always in a fully turned on or partially turned on state, and the clock line is used to input a second high level to the gate and the source of the second thin film transistor in the LPWG mode, so that the second thin film transistor is always in a fully turned on or partially turned on state; Among them, when the working unit inputs a second voltage greater than the first high level and the second high level to the anti-reverse unit, the first thin film transistor and the second thin film transistor are both turned off; since the first thin film transistor and the second thin film transistor are both turned off, and the voltage flowing to the gate and source of the first thin film transistor through the first resistor is small, and the voltage flowing to the gate and source of the second thin film transistor through the second resistor is small, the first power line inputs the first high level to the gate and source of the first thin film transistor so that the first thin film transistor is reopened or not fully opened, and the clock line inputs the second high level to the gate and source of the second thin film transistor so that the second thin film transistor is reopened or not fully opened. At this time, the first thin film transistor and the second thin film transistor repeat the above-mentioned closing process under the backflow of the second voltage, so that the first power line and the clock line will not generate a lot of heat and burn.

2. The driving module according to claim 1, characterized in that: The first voltage is V1, the second voltage is V2, the resistance value of the resistor is R1, the resistance value of the connecting wire connecting the input line, the resistor and the working unit is R2, the maximum withstand voltage of the connecting wire is V3, and it satisfies: R1≥R2(V2-V1-V3) / V3.

3. The driving module according to claim 1, characterized in that: The working unit comprises: a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor and a sixth thin film transistor, wherein the source of the third thin film transistor is electrically connected to the first thin film transistor, the drain of the third thin film transistor is electrically connected to the gate of the fourth thin film transistor and the drain of the sixth thin film transistor, the source of the fourth thin film transistor is electrically connected to the drain of the second thin film transistor, the drain of the fourth thin film transistor is electrically connected to the drain of the fifth thin film transistor, the source of the fifth thin film transistor is electrically connected to the source of the sixth thin film transistor, and the gates of the third thin film transistor, the fifth thin film transistor and the sixth thin film transistor are respectively connected to a driving trace; a second power line electrically connected to the source electrode of the fifth thin film transistor and the source electrode of the sixth thin film transistor; The scan line is electrically connected to the drain of the fourth thin film transistor and the drain of the fifth thin film transistor.

4. The driving module according to claim 3, characterized in that: The working unit further includes a capacitor, one end of which is electrically connected to the gate of the fourth thin film transistor, and the other end of which is electrically connected to the drain of the fourth thin film transistor.

5. The driving module according to claim 3, characterized in that: The driving wiring includes a first wiring and a second wiring, the first wiring is connected to the gate of the third thin film transistor, and the second wiring is connected to both the gate of the fifth thin film transistor and the gate of the sixth thin film transistor.

6. A driving circuit, characterized in that: It comprises a pixel electrode and a driving module as claimed in any one of claims 1 to 5, wherein the pixel electrode is connected to the working unit.

7. The driving circuit according to claim 6, characterized in that: The driving module includes a scan line and a first wiring, the scan line is connected to the pixel electrode, there are N driving modules, and the first wiring of the Nth driving module is connected to the scan line of the N-4th driving module.

8. A display panel, characterized in that: It comprises a signal line and a driving circuit as claimed in claim 6 or 7, wherein the signal line is connected to the pixel electrode.

9. A display device, characterized in that: The invention comprises a housing and the display panel as claimed in claim 8, wherein the display panel is installed in the housing.

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