Artificial intelligence system for wafer defect detection

Abstract

The invention relates to an artificial intelligence system for wafer defect detection, and the system can comprise a complementary metal oxide semiconductor image sensing device which is installed on track equipment and is used for transmitting an image obtained by scanning a wafer to a database; and a server which learns the scanned image to distinguish the defects of the wafer by defect types, learns the defects generated in the exposure apparatus and the track apparatus by types and performs real-time monitoring, and when the defects of the wafer are generated, detects the defects generated in the exposure apparatus and the track apparatus. The server can change a periodic sampling inspection mode into a full inspection mode through the CMOS image sensing device.

Description

Technical Field

[0001] The present invention relates to an artificial intelligence (AI) system for wafer defect detection, and more particularly, to an artificial intelligence analysis system for detecting wafer defects generated in a semiconductor photolithography process and a machine vision complementary metal oxide semiconductor image sensor (CIS) device. Background Art

[0002] A wafer is a disc-shaped silicon substrate used in the semiconductor manufacturing process. Its diameter is usually between 6 inches and 12 inches. In order to form fine circuits and structures, it undergoes multiple processes for the manufacture of semiconductor chips.

[0003] Wafer defects generated in the semiconductor photolithography process are very diverse due to the complexity of the manufacturing process. Therefore, only by quickly and accurately detecting defective products in the semiconductor manufacturing process can the yield be prevented from decreasing. Summary of the invention

[0004] The object of the present invention is to provide an artificial intelligence system for wafer defect detection.

[0005] The object of the present invention is to provide an artificial intelligence analysis system and a machine vision complementary metal oxide semiconductor image sensor device for detecting wafer defects generated in a semiconductor photolithography process.

[0006] Furthermore, an object of the present invention is to prevent a decrease in yield by quickly and accurately detecting defective products in a semiconductor manufacturing process.

[0007] An artificial intelligence system for wafer defect detection according to one embodiment of the present invention may include: a complementary metal oxide semiconductor image sensor device, installed on a track device, for transmitting images obtained by scanning the wafer to a database; and a server, which learns the scanned images to distinguish the defects of the wafer according to defect categories, learns the defects generated in the exposure equipment and the track equipment according to types and performs real-time monitoring. When defects of the wafer occur, the server changes the periodic sampling inspection to a full inspection mode through the complementary metal oxide semiconductor image sensor device.

[0008] According to an embodiment, the present invention may further include a monitoring personal computer (PC), which controls the operation process of the exposure equipment and the track equipment by linking with the server, and sends or receives information management and inspection results of the wafer.

[0009] Furthermore, according to the embodiment, when it is determined that a defect occurs in the exposure device or the track device, the server is controlled to stop the operation of the device that has the defect through interlock.

[0010] Furthermore, the above-mentioned server may include: a first server, used as a manufacturing execution system (MES) server of the wafer defect inspection monitoring system; a second server, used to store the scanned image; and a third server, arranged between the above-mentioned first server and the above-mentioned second server, used as a data migration service (DMS) server for performing data processing on the image of the above-mentioned wafer.

[0011] In an embodiment, the images detected as defective chips in the scanned images can be stored separately in the first server of the wafer defect inspection monitoring system, and the images detected as defective chips can be learned separately on the third server, and the results and data related to the separately performed learning can be transmitted from the third server to the wafer defect inspection monitoring system.

[0012] In an embodiment, when a trigger sensor is installed on the track device, the image can be acquired as the trigger sensor detects. When there is no trigger sensor, the entry of the wafer can be confirmed and the image can be acquired through a visual algorithm. The acquired image and defect image can be transmitted to the first server of the wafer defect inspection monitoring system through a secure file transfer communication protocol (SFTP) or a network file system (NFS) based on a secure shell. The inspection result of the defective wafer can be transmitted from the third server to the first server in response to an end signal indicating the end of the wafer inspection work, or in units of the wafer or in units of the wafer LOT as the wafer batch.

[0013] In an embodiment, the third server can remove noise generated by structural errors in the exposure device or the track device, obtain image differences for each adjacent chip in the wafer in units of picture elements, and use a deep learning program to learn normal chip images and defective chip images. When a defective chip is generated based on the image difference, the normal chip and the defective chip can be directly distinguished and registered based on the results of the learning, taking the chip in the wafer as a unit.

[0014] Furthermore, in an embodiment, the server can perform pre-processing for defect detection within the wafer by adjusting the color and brightness of the wafer in a manner consistent with the size of the wafer; the server can classify and display the scanned image of the wafer in a manner that distinguishes three color channels of red, green, and blue to confirm the defect detection characteristic colors; the server can perform brightness correction on the scanned image of the wafer; and can map and display each primitive intensity value of the scanned image of the wafer to a color according to a table or function.

[0015] Furthermore, in an embodiment, when the drive control system works through a complementary metal oxide semiconductor image sensor module ready trigger (CIS MODULE READY TRIGGER) or is located at a specific first position, the complementary metal oxide semiconductor image sensor device mentioned above can obtain information related to the above-mentioned wafer, including a device identification code (DEVICE ID), a layer identification code (LAYERID), a process job identification code (PROCESS JOB ID), a recipe identification code (RECIPE ID), a wafer identification code (Wafer ID) and a slot identification code (SLOT ID); when the above-mentioned drive control system works through a frame grabber trigger program (FRAME GRABBER TRIGGER) or is located at a specific second position, the above-mentioned complementary metal oxide semiconductor image sensor device can obtain an image related to the above-mentioned wafer.

[0016] In an embodiment, in a first mode as a defect detection mode, the monitoring device may cumulatively display the X-coordinates and Y-coordinates of defect detection positions of a plurality of wafers undergoing the same process in a coordinate image of the wafer displayed on a display; in a second mode as an error checking mode, based on the images of the plurality of wafers, the results of measurements from the end portion of the wafer to the position where the pattern is removed may be displayed according to the recipe settings of each process; in a third mode as an instant wafer defect determination mode, based on an image of a specific area of ​​the wafer being processed, the results related to wafer defects may be displayed.

[0017] According to an embodiment of the present invention, an artificial intelligence system for wafer defect detection may be provided.

[0018] According to an embodiment of the present invention, an artificial intelligence analysis system for detecting wafer defects generated in a semiconductor photolithography process and a machine vision complementary metal oxide semiconductor image sensing device can be provided.

[0019] According to the embodiments of the present invention, the yield reduction can be prevented by quickly and accurately detecting defective products in a semiconductor manufacturing process.

[0020] According to an embodiment of the present invention, an artificial intelligence system for wafer defect detection generated in the lithography process of the semiconductor manufacturing process can be developed to combine with artificial intelligence deep learning (AI Deep Learning) and machine learning (Machine Learning) and achieve real-time monitoring.

[0021] According to an embodiment of the present invention, defects generated in an exposure device and a track device can be learned by type and statistics and the like can be provided to users through real-time monitoring.

[0022] According to an embodiment of the present invention, a system can be developed that prevents continuous generation of defects by immediately interrupting operation through self-interlocking.

[0023] The features and effects of the present invention are further clarified through the detailed description related to the accompanying drawings below, so that ordinary technicians in the technical field to which the present invention belongs can easily implement the technical ideas of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The coating defect, imaging defect, scratch-based defect and defocus-based defect products related to the wafer defect detection of the present invention are shown;

[0025] Figure 2 The structure of the artificial intelligence system for wafer defect detection of the present invention is shown;

[0026] Figure 3 Shown in Figure 2 The structure of multiple servers connected to the monitoring device in the artificial intelligence system;

[0027] Figure 4A A structure that can be linked with multiple servers to realize automatic data status management in an artificial intelligence system for wafer defect detection of this specification is shown;

[0028] Figure 4B A conceptual diagram showing data collection that enables defect detection in units of chips in a specific area of ​​a wafer;

[0029] Figure 5A as well as Figure 5B A flowchart showing that the artificial intelligence system for wafer defect detection in this specification is designed by an image acquisition and transmission system and is designed into an artificial intelligence inspection program based on deep learning;

[0030] Fig. 6A An example of the results of the measurement functions and preprocessing steps related to data preprocessing is shown;

[0031] Figure 6B showing a wafer color map and a wafer heat map related to data preprocessing;

[0032] Fig. 7A as well as Figure 7B A structural diagram showing a complementary metal oxide semiconductor image sensor drive control system;

[0033] Figure 8 A side view of a track equipment unit having an average height and a perspective view of an exemplary complementary metal oxide semiconductor image sensor device mounted on the track equipment are shown;

[0034] 9A to 9C A user interface (UI) screen displayed on a monitoring device in a plurality of modes of the embodiment is shown. DETAILED DESCRIPTION

[0035] For the multiple embodiments of the concepts of the present invention disclosed in this specification, the description of specific structures or functions is merely an example for illustrating the multiple embodiments based on the concepts of the present invention. The multiple embodiments based on the concepts of the present invention can be implemented in a variety of ways and are not limited to the multiple embodiments described in this specification.

[0036] The following describes in detail several embodiments of the present invention with reference to the drawings in this specification. Figure 1 Coating defects, imaging defects, scratch-based and defocused defect products related to wafer defect detection of the present invention are shown.

[0037] Reference Figure 1 , since the photosensitive agent cannot maintain a liquid state until it is applied to the substrate and used, coating defects may occur. Development defects may occur due to the collapse of the photoresist (PR) pattern. Relatedly, when the part exposed to light is developed, it changes from insoluble to soluble in the developer, which may cause chain breakage. Scratches may be generated in the equipment due to particles. Defocused development may occur due to defects that are not defined as the desired image pattern in the wafer.

[0038] Figure 2 The structure of the artificial intelligence system for wafer defect detection of the present invention is shown. On the other hand, Figure 3 Shown in Figure 2 The structure of multiple servers connected to the monitoring device in the artificial intelligence system.

[0039] Reference Figure 2 as well as Figure 3, the artificial intelligence system for wafer defect detection may include an apparatus 100, a complementary metal oxide semiconductor image sensor device 200, and a server 300. The apparatus 100 may include a track device and / or an exposure device, the track device is used to transfer the wafer and track the transfer status, and the exposure device is used to perform exposure (exposure) of the photolithography process. The artificial intelligence system for wafer defect detection may also include a monitoring device 400. The apparatus 100 may include an apparatus control unit 110 that controls the process of the apparatus 100 and controls the drive.

[0040] The complementary metal oxide semiconductor image sensor device 200 may include an image sensor and a control unit for driving the same. As an example, it may include a complementary metal oxide semiconductor (CMOS) image sensor and a control unit for driving the same. The complementary metal oxide semiconductor image sensor device 200 may refer to an image sensor. The complementary metal oxide semiconductor image sensor device 200 may be installed on a track device to transmit an image obtained by scanning a wafer to the database 350, 352. The server 300 may distinguish the defects of the wafer by defect category by learning the scanned image.

[0041] The server 300 can learn the defects generated in the exposure equipment and the track equipment by type and perform real-time monitoring. When the above-mentioned wafer defects occur, the server 300 can change the periodic sampling inspection to the full inspection mode through the complementary metal oxide semiconductor image sensor device 200.

[0042] The CMOS image sensor device 200 can obtain images from one camera or multiple cameras for obtaining images. In this regard, the wafer image can be displayed in the form of front or front / back. Through structural design, even if the camera configuration of the visual part is changed, it will not affect the overall system.

[0043] The monitoring device 400 can control the operation process of the exposure equipment and the track equipment by linking with the server 300, and can send or receive information management and inspection results of the wafer. The monitoring device 400 can be a personal computer, a notebook computer or a mobile device linked with the server 300.

[0044] When it is determined that a defect occurs in the exposure device or the track device, the server 300 can control the device with the defect to stop operating through interlocking. To this end, the server 300 can control the corresponding device with the defect to stop operating by receiving the interlock generated in the monitoring device 400.

[0045] The server 300 may include a first server 310, a second server 320, and a third server 330. The first server 310 may be used as a manufacturing execution system server of a wafer defect inspection monitoring system. The second server 320 may store the scanned image. The third server 330 may be configured between the first server 310 and the second server 320. The third server 330 may be used as a data migration service server for data processing of images of wafers.

[0046] The images detected as defective chips among the scanned images may be stored separately in the first server 310 of the wafer defect inspection monitoring system or in the database 351 linked to the first server 310. The images detected as defective chips may be learned separately in the third server 330. The results and data related to the above-mentioned learning performed separately are transmitted from the third server 330 to the first server 310 of the wafer defect inspection monitoring system and the monitoring device 400 connected to the first server 310 in an operable manner.

[0047] The interface between the runtime personal computer (RUNTIME PC) of the monitoring device 400 linked to the first server 310 constituting the wafer defect analysis monitoring system and the first server 310 as the manufacturing execution system server may include an operation process control function, an inspection wafer information management function, and an inspection result sending and receiving function.

[0048] The first server 310 as a manufacturing execution system server uses the semiconductor equipment communication standard (SECS, SEMI Equipment Communication Standard / GEM, General Equipment Model). However, since it uses its own communication format or database (DB), the communication simulation device can be designed to have a common corresponding structure.

[0049] When a wafer inspection result defect occurs, in the wafer defect analysis monitoring system, an interlock is generated to the first server 310 as a manufacturing execution system server to stop the device where the defect is detected.

[0050] The third server 330 used as a data migration service server may have multiple interfaces. The third server 330 may include a camera (CAM) interface, a server interface, and a user interface. The third server 330 may realize image acquisition and storage through the camera interface. The third server 330 may realize common data management (Common Data Management) by linking with the first server 310 as a manufacturing execution system server through the server interface.

[0051] The third server 330 may acquire process-related data from a database 351 linked to the first server 310 , and may acquire an image acquired by scanning the wafer from a database 352 linked to the second server 320 .

[0052] On the other hand, the artificial intelligence system for wafer defect detection in this specification can be linked with multiple servers to realize data collection and defect detection in units of chips in a specific area of ​​the wafer.

[0053] Relatedly, Figure 4A A structure that can be linked with multiple servers in order to realize automated data status management in an artificial intelligence system for wafer defect detection in this specification is shown. Figure 4B A conceptual diagram showing data collection that enables defect detection in units of chips in a specific area of ​​a wafer.

[0054] Reference Figure 3 as well as Figure 4A The inspection function of the third server 330 as a data migration service server can be controlled by communicating with the first server 310 as a manufacturing execution system server. During the inspection, in order to maintain LOT information in LOT units as a batch of wafers, it is possible to connect to the plurality of servers 310, 320, and 330 in various ways. Inspection results and FDC (Fault Detection & Classification) data can be exchanged with the plurality of servers 310, 320, and 330.

[0055] In the case of supporting server communication based on the semiconductor equipment communication standard (SECS, SEMI Equipment Communication Standard / GEM, General Equipment Model) protocol, the wafer inspection work can be started according to the crystal box start (Cassette Start) signal as the start signal. And, the wafer inspection work can be ended according to the crystal box end (Cassette End) signal as the end signal. On the other hand, after the start, if there is no end signal after the set time and no inspection is performed, the inspection work can be automatically stopped.

[0056] Reference Figure 4B , the wafer 10 will be made of silicon raw material and has various diameters and thicknesses, with typical diameters being 200 mm and 300 mm. The thickness of the wafer is typically 0.725 mm ± 0.02, and the size of each chip may vary depending on the diameter and thickness of the wafer 10. The number of achievable chip designs may vary depending on the size of the wafer 10 and the size of the chip, and may also vary depending on the precision of the technology and equipment used in the semiconductor manufacturing process.

[0057] For example, if chips are manufactured using 10nm technology in a wafer with a diameter of 300mm, several thousand chips can be manufactured from one wafer. Based on this characteristic, data required for learning images of a wafer including multiple chips can be collected.

[0058] In terms of normal chip images, each process or equipment engineer of a chip manufacturing company registers the following information to the wafer defect inspection monitoring system: Figure 4B The normal chip image 1 and the standard wafer image are shown. After that, the system will inspect the chip unit. When performing defect detection, the corresponding position is marked in a way that can be easily distinguished visually.

[0059] The images of the chips detected as defective can be stored separately in the server of the wafer defect inspection monitoring system, and the defective images can be learned separately, and the learned content can be transmitted from the server to the wafer defect inspection monitoring system.

[0060] On the other hand, the artificial intelligence system for wafer defect detection of the present specification can be designed as an image acquisition and transmission system, and can be designed as an artificial intelligence inspection program based on deep learning.

[0061] Figure 5A as well as Figure 5B A flowchart showing that the artificial intelligence system for wafer defect detection of the present invention is designed by an image acquisition and transmission system and is designed into an artificial intelligence inspection program based on deep learning.

[0062] Reference Figure 5A , it can be determined whether the wafer is loaded and arranged at a specific position (step S510). If the wafer is loaded and arranged at a specific position, the wafer inspection work can be started according to the Cassette Start signal as a start signal (step S520). And, it can then be determined whether the operation for all wafers is completed (step S530). If the operation for all wafers is completed, the image acquisition and transmission will be terminated (step S540).

[0063] In this regard, when a trigger sensor is installed on the track device, the image of the wafer can be acquired based on the sensing of the trigger sensor. If there is no trigger sensor, the image of the wafer can be acquired by confirming the entry of the wafer through a visual algorithm.

[0064] Reference Figure 3 as well as Figure 5A, report to the cassette end through the semiconductor equipment communication standard (SECS / GEM) protocol, and the images and defect images obtained after inspection can be transmitted to the first server 310 of the wafer defect inspection monitoring system through a secure file transfer communication protocol based on a secure shell or a network file system. The inspection results can be transmitted to the first server 310 as a manufacturing execution system server according to the semiconductor equipment communication standard (SECS / GEM) protocol. Basically, it can be designed as follows, that is, the image is transmitted according to the cassette end, but the transmission of wafers or LOT units is also supported.

[0065] The images and defect images acquired per wafer or a specific area of ​​the wafer may be transmitted to the first server 310 of the wafer defect inspection monitoring system via a secure file transfer communication protocol or a network file system based on a secure shell.

[0066] In response to an end signal indicating the end of the wafer inspection work, the inspection result of the defective chips may be transmitted from the third server 330 to the first server 310 in units of the wafers or in units of LOT which is a batch of the wafers.

[0067] Reference Figure 5B The system of the present invention can basically adopt a convolutional neural network (CNN) structure for image or video data processing. The convolutional neural network structure focuses on detecting multiple parts of an image rather than the entire image, and analyzing the correlation between one frame of an image and multiple surrounding frames.

[0068] On the other hand, when the wafer trasfer arm is driven, the variable factors caused by the characteristics of the semiconductor lithography equipment, such as minute jitter, wafer tilt, and wafer warping, are not sufficient to compare the difference between the existing normal wafer and the defective wafer.

[0069] Therefore, the present invention adopts a novel artificial intelligence algorithm by chip to chip correction and comparison of multiple images.

[0070] In terms of the evaluation method, 1) a wafer is manufactured for defect type learning once. 2) An artificial intelligence deep learning program is used to directly distinguish and register good and defective products in chip units. The learning method is to learn the specified normal chip images and defective chip images through artificial intelligence learning. On the other hand, the wafer defect detection method of the present invention does not perform image learning on a wafer, but learns the normal chips / defective chips in the wafer. Therefore, a maximum of more than 1,000 images are learned in a wafer, and when 1LOT (25 wafers) are learned, more than 25,000 image learning effects will be generated. 4) Another 100 evaluation wafers required for learning result inspection can be manufactured. 5) More than 85% of the inspection results can be ensured by the wafers in 4).

[0071] Reference Figure 3 as well as Figure 5B The third server 330 may perform a preparation step of removing noise generated by structural errors in the exposure device or the track device (step S510b). The third server 330 may perform a step of acquiring image differences for each adjacent chip in the wafer in units of picture elements (step S520b).

[0072] The third server 330 may use a deep learning program to learn the normal chip image and the defective chip image, and may determine whether a defective chip is generated based on the image difference (step S530b).

[0073] Based on the learning result, the third server 330 can directly distinguish and register normal chips and defective chips in units of chips in the wafer (step S540b). Furthermore, when it is determined that a defect occurs in the exposure device or the track device (step S550b), the third server 330 can control the operation of the defective device to be stopped through interlocking (step S560b).

[0074] On the other hand, the artificial intelligence system for wafer defect detection of the present invention can perform preprocessing for defect detection within the wafer. Fig. 6A shows examples of measurement functions related to data preprocessing and the results of the preprocessing steps, Figure 6B Wafer color map and wafer heat map related to data pre-processing are shown.

[0075] Reference Fig. 6A , the notch or flat zone reference alignment color can be adjusted in a manner that matches the wafer size to perform preprocessing for improving wafer defect detection images. In this regard, the data preprocessing system can be designed in a manner that can measure multiple functions such as the size, length, and width of the wafer.

[0076] Reference Figure 6B, RGB color separation is performed by distinguishing the three color channels of red, green, and blue to classify and display them in a way that confirms the defect detection characteristic color. Various brightness correction functions such as gamma collection and brightness distortion can be performed. By mapping each intensity value to color according to a table or function through a pseudo-color image, it is possible to provide an explanation in a way that can be easily recognized by magnifying the color changes that vary slightly according to the derived thickness in the gray tone image. For this purpose, color functions such as blue for thin parts and red for thick parts can be performed.

[0077] Reference Figure 3 , Fig. 6A as well as Figure 6B The server 300 can perform preprocessing for defect detection in the wafer by adjusting the color and brightness of the wafer in a manner that matches the size of the wafer. The server 300 can classify and display the scanned image of the wafer in a manner that distinguishes the three color channels of red, green, and blue to confirm according to the color of the defect detection characteristics. The server 300 can perform brightness correction of the scanned image of the wafer. The server 300 can map the intensity values ​​of each primitive of the scanned image of the wafer to a color according to a table or function and display it.

[0078] On the other hand, the artificial intelligence system for wafer defect detection in this specification may include a machine vision complementary metal oxide semiconductor image sensor drive control system. In this regard, Fig. 7A as well as Figure 7B Shows the structural diagram of the complementary metal oxide semiconductor image sensor drive control system. Figure 8 A side view of a track equipment unit having an average height and a perspective view of an exemplary CMOS image sensor device mounted on the track equipment are shown.

[0079] Reference Fig. 7A as well as Figure 7B , the complementary metal oxide semiconductor image sensor module ready trigger can form and design the complementary metal oxide semiconductor image sensor ready signal (CIS READY SIGNAL) working scheme when it is located at a specific position of the robot (ROBOT) through the semiconductor equipment communication standard (SECS) communication. The device identification code / level identification code / process operation identification code / recipe identification code / wafer identification code / slot identification code is formed in a way that the wafer information can be obtained through the semiconductor equipment communication standard. When the frame grabber trigger program is located at the robot working or specific position through the semiconductor equipment communication standard (SECS) communication, the frame grabber (FRAME GRABBER) image capture signal (CAPTURE SIGNAL) working scheme can be formed and designed.

[0080] Reference FIG. 7A to FIG. 8When the height of the complementary metal oxide semiconductor image sensor device 200 is increased from 47.8mm to 80.0mm, the "L" portion of No. ① is also changed to 40mm, and can be changed in a manner without protruding parts. Therefore, collision can be prevented during the transportation of wafers in the complementary metal oxide semiconductor image sensor drive control system. On the other hand, if the "L" portion is not easy to change to 40mm due to the internal board, then in the case of a longitudinally arranged board, the horizontal length of No. ① can be changed from 45.0mm to 40.0mm, and the horizontal length of No. ② can also be changed to 230mm. Therefore, the height of the complementary metal oxide semiconductor image sensor device 200 can be made greater than 80.0mm.

[0081] The optimal form design of the CMOS image sensor device 200 can be designed to have a field of view (FOV) area of ​​less than 40 mm, and can scan a wafer of up to 300 mm in size. In addition, the CMOS image sensor device 200 can ensure the best performance of 4K resolution without image distortion. The CMOS image sensor device 200 can be installed in a position that takes into account the position where there is no heat interference and all wafers move.

[0082] Reference Figure 3 , Figure 7 and Figure 8 When the drive control system works through the CMOS image sensor module ready trigger or is located at a specific first position, the CMOS image sensor device 200 can obtain information related to the wafer including a device identification code, a level identification code, a process operation identification code, a recipe identification code, a wafer identification code, and a slot identification code. When the drive control system works through the frame grab trigger program or is located at a specific second position, the CMOS image sensor device 200 can obtain an image related to the wafer.

[0083] On the other hand, the CMOS image sensor device 200 of the artificial intelligence system for wafer defect detection of the present invention can form a CMOS image sensor structure specifically suitable for semiconductor photolithography process. In this regard, the photolithography process is a patterning process using light, using a wavelength below 365nm.

[0084] Therefore, the commonly used white illumination may cause damage to the pattern based on the same wavelength band. In addition, since color images are needed to distinguish and analyze the defect types in various wafers, red, green, and blue light-emitting diodes (R, G, B LED) above 365nm can be used for illumination. In addition, in order to overcome the limitation that the structure in the lithography equipment cannot be installed due to the narrow structure, a complementary metal oxide semiconductor image sensor structure optimized for the lithography equipment can be realized.

[0085] Specifically, the photolithography process is a process for coating and pattern exposure. If exposed to ultraviolet rays with a wavelength below 365nm, the pattern may disappear. Therefore, in pattern exposure, the use of light wavelengths of 365nm to 126nm should be avoided. As the illumination of the complementary metal oxide semiconductor image sensor used in the photolithography process, R, G, and B illumination are used, which have wavelengths of 630nm, 520nm, and 465nm, respectively, and can be composed of visible light wavelengths that do not cause any problems for wafer pattern formation.

[0086] In connection therewith, two rows of red, green, and blue light emitting diodes may be formed inside the complementary metal oxide semiconductor image sensor device 200. On the other hand, 16 complementary metal oxide semiconductor sensors may be built into a 200mm wafer in a manner consistent with the wafer size of the semiconductor, and 22 complementary metal oxide semiconductor sensors may be built into a 300mm wafer. Due to the space and width limitations of the photolithography process equipment, the board and sensor portion serving as the complementary metal oxide semiconductor image sensor control portion may be separated at a secondary level. Furthermore, the design and space limitations may be eliminated by making the width of the complementary metal oxide semiconductor sensor reach 40mm. Considering the wafer transfer height, the field of view (FOV) of the complementary metal oxide semiconductor image sensor may be designed to be an optimal 14.8mm, and the field of view of ordinary machine vision may be reflected as a value smaller than 450mm.

[0087] On the other hand, the monitoring device of the artificial intelligence system for wafer defect detection of the present invention can work in multiple modes to display on the screen. 9A to 9C The user interface screens displayed on the monitoring device in the multiple modes of the embodiment are shown.

[0088] Reference Fig.9A , by showing overlapping graphs, the cause of the defect can be specifically determined according to the defect type. The X-coordinate and Y-coordinate of the defect position can be accumulated and displayed in the coordinate image of one wafer in the form of 1LOT (25 wafers) or wafers that undergo the same process within a specified time. Therefore, the user interface can be constructed in a way that can be based on the defect location and distribution of specific defect units, so that engineers can perform intuitive analysis.

[0089] Reference Figure 3 as well as Fig.9A In the first mode as the defect detection mode, the monitoring device 400 can cumulatively display the X coordinates and Y coordinates of the defect detection positions of a plurality of wafers undergoing the same process in the coordinate image of the wafer displayed on the display.

[0090] Reference Fig. 9B, the edge bead removal (EBR) data of the wafer image in progress can be confirmed. When a specific layer identification code (LAYER ID) or LOT identification code (select slot) is selected, the edge bead removal trend can be confirmed. In connection with the edge bead removal measurement mode of the wafer, when the wafer coating process is performed, the photoresist can be applied while rotating. In the case of rotational eccentricity, as unnecessary parts of the wafer are removed by using a solvent, the uneven edge bead removal size causes the photoresist on the chip part to be removed, which will cause chip defects. Therefore, it is necessary to periodically perform edge bead removal size measurement.

[0091] On the other hand, Fig. 9B As shown, based on the acquired image, according to the process recipe setting, the edge glue drop removal size is measured from the end part of the wafer to the position of the removal pattern, and a user interface is constructed in a trend management manner, so that it is possible to manage whether eccentricity occurs when the wafer is rotated.

[0092] Reference Figure 3 as well as Fig. 9B In the second mode as the error check mode, based on images of a plurality of wafers, the monitoring device 400 can display a plurality of results measured from the end portions of the plurality of wafers to the positions where the patterns are removed according to the recipe settings of each process.

[0093] Reference Fig. 9C , which can instantly determine the normal and defective wafers. Based on the image of the wafer in progress, the normal determination results and defect determination results are displayed in the corresponding slot (SLOT), and the defective wafer information can be transmitted to the manufacturing plant host (FAB HOST) in a way that the operator or engineer can immediately confirm when the defect occurs. In addition, a display screen that can communicate with the host in real time can be designed to stop (stop) or pause (LOT HOLD, design the system in a way that suits the production line) the operation of the equipment in a way that suits the situation of the manufacturing plant.

[0094] Reference Figure 3 as well as Fig. 9C In the third mode, which is an immediate wafer defect determination mode, the monitoring device 400 may display results related to wafer defects based on an image of a specific area of ​​the wafer being processed.

[0095] The above is a description of the artificial intelligence system for wafer defect detection of the present invention. The technical effects of the artificial intelligence system for wafer defect detection of the present invention can be summarized as follows, but are not limited thereto.

[0096] According to an embodiment of the present invention, an artificial intelligence system for wafer defect detection may be provided.

[0097] According to an embodiment of the present invention, an artificial intelligence analysis system for detecting wafer defects generated in a semiconductor photolithography process and a machine vision complementary metal oxide semiconductor image sensing device can be provided.

[0098] According to the embodiments of the present invention, it is possible to prevent yield reduction by quickly and accurately detecting defective products in a semiconductor manufacturing process.

[0099] According to an embodiment of the present invention, an artificial intelligence system for wafer defect detection generated in a photolithography process in a semiconductor manufacturing process can be developed to combine with artificial intelligence deep learning and machine learning and achieve real-time monitoring.

[0100] According to an embodiment of the present invention, defects generated in an exposure device and a track device can be learned by type and statistics and the like can be provided to users through real-time monitoring.

[0101] According to an embodiment of the present invention, a system can be developed that prevents continuous generation of defects by immediately interrupting operation through self-interlocking.

[0102] The above detailed description related to the accompanying drawings makes the features and effects of the present invention more clear, so that ordinary technicians in the technical field to which the present invention belongs can easily implement the technical ideas of the present invention.

[0103] According to the above detailed description, the additional scope of the applicability of the present invention will be clear. However, those skilled in the art of the present invention will clearly understand that various changes and modifications can be implemented within the concept and scope of the present invention, so the detailed description and specific embodiments such as the preferred embodiments of the present invention should be understood as examples only.

Claims

1. An artificial intelligence system for wafer defect detection, in, include: A complementary metal oxide semiconductor image sensor device, mounted on the track device, for transmitting an image acquired by scanning the wafer to a database; as well as The server learns the scanned image to distinguish the defects of the wafer by defect category, learns the defects generated in the exposure equipment and the track equipment by type and performs real-time monitoring, When a defect occurs in the wafer, the server changes the periodic sampling inspection to a full inspection mode through the complementary metal oxide semiconductor image sensor device.

2. The artificial intelligence system for wafer defect detection according to claim 1, wherein: It also includes a monitoring personal computer, which controls the operating procedures of the exposure equipment and the track equipment by linking with the server, and sends or receives information management and inspection results of the wafer.

3. The artificial intelligence system for wafer defect detection according to claim 2, wherein: When it is determined that a defect occurs in the exposure device or the track device, the server controls the device that has the defect to stop operating through interlocking.

4. The artificial intelligence system for wafer defect detection according to claim 3, wherein: The server comprises: A first server, used as a manufacturing execution system server of a wafer defect inspection monitoring system; A second server, configured to store the scanned image; and The third server is configured between the first server and the second server and is used as a data migration service server for performing data processing on the image of the wafer.

5. The artificial intelligence system for wafer defect detection according to claim 4, wherein: The image detected as a defective chip in the scanned image is stored separately in the first server of the wafer defect inspection monitoring system, and the image detected as the defective chip is learned separately in the third server. Results and data related to the learning performed separately are transmitted from the third server to the wafer defect inspection monitoring system.

6. The artificial intelligence system for wafer defect detection according to claim 5, wherein: When the trigger sensor is installed on the track device, the image is acquired as the trigger sensor detects. When the trigger sensor is not present, the entry of the wafer is confirmed by a visual algorithm and the image is acquired. The acquired image and defect image are transmitted to the first server of the wafer defect inspection monitoring system via a secure file transfer communication protocol or a network file system based on a secure shell. In response to an end signal indicating the end of the inspection work of the wafer, the inspection result of the defective chip is transmitted from the third server to the first server, either in units of the wafer or in units of LOT which is a batch of the wafer.

7. The artificial intelligence system for wafer defect detection according to claim 4, wherein: The third server removes noise caused by structural errors generated in the exposure device or the track device, obtains image differences for each adjacent chip in the wafer in units of picture elements, and uses a deep learning program to learn normal chip images and defective chip images. When a defective chip is generated according to the image difference, based on the learning results, the normal chips and defective chips are directly distinguished and registered in units of chips in the wafer.

8. The artificial intelligence system for wafer defect detection according to claim 4, wherein: The server performs pre-processing for defect detection within the wafer by adjusting the color and brightness of the wafer in a manner consistent with the size of the wafer, The server can classify and display the scanned image of the wafer in a manner that the three color channels are red, green, and blue to confirm the defect detection characteristic colors, perform brightness correction on the scanned image of the wafer, and map and display each element intensity value of the scanned image of the wafer to color according to a table or function.

9. The artificial intelligence system for wafer defect detection according to claim 4, wherein: When the drive control system works through the complementary metal oxide semiconductor image sensor module ready trigger or is located at a specific first position, the complementary metal oxide semiconductor image sensor device obtains information related to the wafer including an equipment identification code, a level identification code, a process operation identification code, a recipe identification code, a wafer identification code and a slot identification code. When the drive control system works through the frame capture trigger program or is located at a specific second position, the complementary metal oxide semiconductor image sensor device obtains an image related to the wafer.

10. The artificial intelligence system for wafer defect detection according to claim 9, wherein: In the first mode as the defect detection mode, the monitoring device cumulatively displays the X-coordinates and Y-coordinates of the defect detection positions of multiple wafers undergoing the same process in the coordinate image of the wafer displayed on the display. In the second mode as the error verification mode, based on the images of the multiple wafers, the results of measurements from the end portion of the wafer to the position where the pattern is removed are displayed according to the recipe settings of each process. In the third mode as the real-time wafer defect judgment mode, based on the image of a specific area of ​​the wafer in progress, the results related to wafer defects are displayed.

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