A complementary field effect transistor and a manufacturing method thereof, a static random access memory

Abstract

The application provides a complementary field effect transistor and a manufacturing method thereof, and a static random access memory. The method comprises the following steps: providing a substrate, forming a stack structure, forming a second type work function layer in a plurality of to-be-filled gaps, filling a protection material to form a protection layer, etching the protection layer by an anisotropic process to a first thickness, continuing to etch the protection layer by an isotropic process to a second thickness, and a difference between the second thickness and 1 / 2 of a width of the to-be-filled gap is less than a target threshold value, that is, the protection layer is precisely etched by etching the protection layer by the anisotropic process to the first thickness and then continuing to etch the protection layer by the isotropic process to the second thickness. Therefore, the precise etching of the protection layer can be realized by combining the anisotropic etching with the isotropic etching, the position of the protection layer can be precisely controlled, and the risk of the work function layer covering the wrong transistor and the risk of the transistor type confusion can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a complementary field-effect transistor and its manufacturing method, and a static random access memory. Background Technology

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate Fin Field-Effect Transistors (FinFETs) are limited at nodes below 3 nanometers (nm). Nanosheet-Gate all-round Fin Field-Effect Transistors (Nanosheet-GAAFETs) have been developed, which are not limited by the 3 nm node. Furthermore, Complementary Field-Effect Transistors (CFETs) have received widespread attention and research because they have broken through the 1 nm node limitation.

[0003] Currently, complementary field-effect transistors (CFTs) can be used to form the memory cells of static random access memory (SRAM), thereby significantly reducing the area of ​​SRAM. (Reference) Figure 1 The diagram shown is a circuit schematic of a storage cell in a static random access memory (SRAM). (Refer to...) Figure 2 and Figure 3 The diagram shows the structural layout of the memory cells for two types of static random access memory (SRAM). In other words, by changing the design of the memory cells from planar transistors to complementary field-effect transistors (CFPTs), the length of the memory cells has been shortened from 240nm to 156nm, significantly reducing the area of ​​the SRAM memory cells.

[0004] Current complementary field-effect transistors (CFPTs) include different types of transistors stacked one on top of the other. When manufacturing different types of transistors, a protective layer is used to wrap one type of transistor in order to manufacture another type of high-k dielectric layer or work function layer. However, the position of the protective layer cannot be precisely controlled, which leads to the risk of transistor type confusion. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a complementary field-effect transistor and its manufacturing method, and a static random access memory, which can precisely control the position of the protective layer through the process, thereby reducing the risk of transistor type confusion.

[0006] This application provides a method for manufacturing a complementary field-effect transistor, the method comprising:

[0007] A substrate is provided, and a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer are formed on one side of the substrate. Along a direction perpendicular to the plane of the substrate, the stacked structures include a buffer layer located in the middle region.

[0008] The stacked structure and a substrate of a certain thickness are etched to form a fin structure, the fin structure including a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure being separated by the buffer layer, and a buried power line being formed between the two substrate structures;

[0009] The top structure, the buffer layer, and the bottom structure are etched to form a top source region, a top drain region, a bottom source region, and a bottom drain region. A top channel region is formed between the top source region and the top drain region, and a bottom channel region is formed between the bottom source region and the bottom drain region. Inner sidewalls are formed on the sidewalls of the top structure and the sidewalls of the bottom structure.

[0010] A bottom source and a bottom drain are formed in the bottom source region and the bottom drain region;

[0011] An embedded power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode are formed on the bottom source and the bottom drain. The embedded power connection layer and the embedded power line are electrically connected.

[0012] A top source and a top drain are formed on the embedded power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode, and the second storage bottom electrode;

[0013] The first semiconductor layer of the top channel region and the bottom channel region is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers. A second type of work function layer is formed in the plurality of gaps to be filled.

[0014] A protective material is filled into multiple gaps to be filled to form a protective layer. The protective layer of a first thickness is etched using an anisotropic process. The protective layer of a second thickness is then etched using an isotropic process. Along a plane direction perpendicular to the line connecting the bottom source and the bottom drain, the difference between the second thickness and half the width of the gap to be filled is less than a target threshold.

[0015] Remove the second type of work function layer from the gaps to be filled that are not covered by the protective layer, and form a first type of work function layer in the gaps to be filled that are not covered by the protective layer;

[0016] Remove the protective layer;

[0017] A gate is filled in a plurality of the gaps to be filled, the gate surrounds the second semiconductor layer, and the stack of the plurality of second semiconductor layers respectively forms a top channel structure and a bottom channel structure;

[0018] A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode are formed on the top source and the top drain, respectively, and the top ground connection layer and the bottom ground connection layer are connected.

[0019] Optionally, forming inner sidewalls on the sidewalls of the top structure and the bottom structure includes:

[0020] Etching away portions of the first semiconductor layer on the sidewalls of the top structure and the sidewalls of the bottom structure, and etching away the buffer layer, respectively forming a concave structure and a buffer isolation structure;

[0021] An inner wall is formed in the concave structure, and an isolation layer is formed in the buffer isolation structure.

[0022] Optionally, etching the protective layer of a first thickness using an anisotropic process and then etching the protective layer of a second thickness using an isotropic process includes:

[0023] The protective layer, with a thickness equal to half the width of the gap to be filled, is etched using an anisotropic process.

[0024] Continue etching the second thickness of the protective layer using an isotropic process up to 1 / 2 of the position of the isolation layer.

[0025] Optionally, before forming a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain, the method further includes:

[0026] A target sidewall is formed, which covers the sidewall of the inner sidewall;

[0027] A first dielectric layer is formed, which covers the top structure and the target sidewall;

[0028] The first dielectric layer on both sides of the top structure is etched to form a first groove, the first groove exposing the bottom source and the bottom drain;

[0029] The formation of a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first memory bottom electrode, and a second memory bottom electrode on the bottom source and the bottom drain includes:

[0030] A buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode are formed on the bottom source and bottom drain exposed in the first groove.

[0031] The method further includes:

[0032] A second dielectric layer is formed in the first groove;

[0033] Etch the first dielectric layer and the second dielectric layer to the surface of the isolation layer away from the substrate;

[0034] Etch the target sidewall to the surface of the isolation layer away from the substrate;

[0035] The formation of a top source and a top drain on the embedded power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first memory bottom electrode, and the second memory bottom electrode includes:

[0036] A top source and a top drain are formed on the first dielectric layer and the second dielectric layer, which cover the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first memory bottom electrode, and the second memory bottom electrode.

[0037] Optionally, before forming a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode on the top source and the top drain, respectively, the method further includes:

[0038] A third dielectric layer is formed on the top source and the top drain;

[0039] The third dielectric layer on both sides of the top structure is etched to form a second groove, which exposes the top source and the top drain.

[0040] The top source and the top drain are respectively formed with a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode, including:

[0041] A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode are formed on the top source and the top drain exposed in the second groove, respectively.

[0042] This application provides a complementary field-effect transistor, the complementary field-effect transistor comprising:

[0043] Substrate;

[0044] A top source, a top drain, a top channel structure, a bottom source, a bottom drain, and a bottom channel structure are disposed on one side of the substrate. In a direction perpendicular to the plane of the substrate, the top source and the bottom source overlap, the top drain and the bottom drain overlap, and the top channel structure and the bottom channel structure overlap. The top channel structure is located between the top source and the top drain, and the bottom channel structure is located between the bottom source and the bottom drain. The top channel structure and the bottom channel structure comprise a stack of multiple nanosheets.

[0045] A gate, the gate surrounding the nanosheet;

[0046] The nanosheets of the top channel structure are surrounded by a first type of work function layer, and the nanosheets of the bottom channel structure are surrounded by a second type of work function layer;

[0047] The top ground connection layer is in contact with the top source electrode, the bottom ground connection layer is in contact with the bottom source electrode, and the top ground connection layer and the bottom ground connection layer are connected.

[0048] Optionally, an isolation layer is provided between the top channel structure and the bottom channel structure.

[0049] Optionally, the sidewalls of the isolation layer are provided with target sidewalls.

[0050] Optionally, along a direction perpendicular to the plane of the substrate, halfway down the sidewall of the isolation layer is the boundary between the first type of work function layer and the second type of work function layer.

[0051] This application provides a static random access memory (SRAM) including a plurality of memory cells, wherein the memory cells include complementary field-effect transistors as described in any one of the preceding claims.

[0052] This application provides a method for manufacturing a complementary field-effect transistor. The method includes: providing a substrate; forming a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer on one side of the substrate; the stacked structures including a buffer layer in an intermediate region along a direction perpendicular to the plane of the substrate; etching the stacked structures and a portion of the substrate to form a fin structure; the fin structure including a top structure, a bottom structure, and a substrate structure; the top structure and the bottom structure being separated by the buffer layer; and forming buried power lines between the two substrate structures. The top structure, buffer layer, and bottom structure are etched to form a top source region, a top drain region, a bottom source region, and a bottom drain region. A top channel region is formed between the top source region and the top drain region, and a bottom channel region is formed between the bottom source region and the bottom drain region. Inner sidewalls are formed on the sidewalls of the top and bottom structures. Bottom source and bottom drain electrodes are formed in the bottom source and bottom drain regions. A buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first memory bottom electrode, and a second memory bottom electrode are formed on the bottom source and bottom drain electrodes. The buried power connection layer and buried power lines are electrically connected. The buried power connection layer, bottom ground connection layer, bottom word line connection layer, bottom bit line connection layer, and first memory bottom electrode are also formed on these layers. A top source and a top drain are formed on the bottom electrode and the second storage electrode. The first semiconductor layer in the top channel region and the bottom channel region is removed. Multiple gaps to be filled are formed between the second semiconductor layers. A second type of work function layer is formed in the multiple gaps to be filled. A protective material is filled in the multiple gaps to form a protective layer. The protective layer of a first thickness is etched using an anisotropic process. The protective layer of a second thickness is then etched using an isotropic process. Along the plane direction perpendicular to the line connecting the bottom source and the bottom drain, the difference between the second thickness and half the width of the gap to be filled is less than the target threshold. That is, by first etching the first thickness of the protective layer using anisotropic process and then continuing to etch the second thickness of the protective layer using isotropic process, the protective layer is precisely etched. The second type of work function layer in the gaps to be filled that are not covered by the protective layer is removed, and a first type of work function layer is formed in the gaps to be filled that are not covered by the protective layer. The protective layer is then removed, and gates are filled in multiple gaps to be filled. The gates surround a second semiconductor layer, and the stack of multiple second semiconductor layers forms a top channel structure and a bottom channel structure, respectively. A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first memory top electrode, and a second memory top electrode are formed on the top source and top drain, respectively. The top ground connection layer and the bottom ground connection layer are connected. Therefore, this application can achieve precise etching of the protective layer by using anisotropic etching combined with isotropic etching, thereby achieving precise control of the protective layer's position and avoiding the work function layer covering the wrong transistor, reducing the risk of transistor type confusion. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 A circuit diagram of a storage cell of a static random access memory is shown.

[0055] Figure 2 The diagram shows the structural layout corresponding to the storage cell of a static random access memory.

[0056] Figure 3 The diagram shows the structural layout corresponding to the memory cell of another static random access memory;

[0057] Figure 4 A schematic flowchart of a method for manufacturing a complementary field-effect transistor according to an embodiment of this application is shown;

[0058] Figure 5 This illustration shows a structural layout diagram corresponding to a storage cell of a static random access memory provided in an embodiment of this application;

[0059] Figure 6 It shows Figure 5 The top-level schematic diagram of the provided structural layout;

[0060] Figure 7 It shows Figure 5 A schematic diagram of the underlying structure layout provided;

[0061] Figure 8 A three-dimensional structural schematic diagram of a complementary field-effect transistor provided in an embodiment of this application is shown;

[0062] Figures 9-40 show schematic diagrams of the structure of a complementary field-effect transistor manufactured according to the manufacturing method of the complementary field-effect transistor provided in the embodiments of this application. Detailed Implementation

[0063] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0064] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0065] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0066] refer to Figure 1 The diagram shows a circuit diagram of a storage cell in a Static Random Access Memory (SRAM). A storage cell in SRAM is called a byte (bit), which can only store one signal, 0 or 1. One bit consists of six transistors: two P-type metal-oxide-semiconductor field-effect transistors (PMOS) and four N-type metal-oxide-semiconductor field-effect transistors (NMOS). The PMOS is... Figure 1 PU1 and PU2 in the NMOS are Figure 1 In this context, PD1, PD2, AC1, and AC2, Q and QB represent storage bits. Figure 1 In this context, VDD represents the power supply terminal, VSS represents the ground terminal, WL represents the word line, and BL represents the bit line.

[0067] refer to Figure 2 and Figure 3 The diagram shows the structural layout of the memory cells for two types of static random access memory. Figure 2 The middle part is a planar transistor with only one layer (One-tier). Figure 3 The middle layer is a complementary field-effect transistor with a two-tier structure: a top-tier NMOS and a bottom-tier PMOS. In other words, by changing the design of the memory cell from planar transistors to complementary field-effect transistors, the length of the memory cell has been shortened from 240nm to 156nm, which has significantly reduced the area of ​​the memory cell in static random access memory.

[0068] Current complementary field-effect transistors (CFPTs) consist of different types of transistors stacked one on top of the other. When manufacturing these different types of transistors, a protective layer is used to encase one type of transistor in order to fabricate the other type of high-k dielectric layer or work function layer. Currently, isotropic etching is used to etch the protective layer to a fixed position; however, the position of the protective layer cannot be precisely controlled, leading to the risk of transistor type confusion.

[0069] Based on this, this application provides a method for manufacturing a complementary field-effect transistor, the method comprising: providing a substrate; forming a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer on one side of the substrate; the stacked structure including a buffer layer in the middle region along a direction perpendicular to the plane of the substrate; etching the stacked structure and a portion of the substrate to form a fin structure; the fin structure including a top structure, a bottom structure and a substrate structure; the top structure and the bottom structure being separated by the buffer layer; and forming a buried power line between the two substrate structures. The top structure, buffer layer, and bottom structure are etched to form a top source region, a top drain region, a bottom source region, and a bottom drain region. A top channel region is formed between the top source region and the top drain region, and a bottom channel region is formed between the bottom source region and the bottom drain region. Inner sidewalls are formed on the sidewalls of the top and bottom structures. Bottom source and bottom drain electrodes are formed in the bottom source and bottom drain regions. A buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first memory bottom electrode, and a second memory bottom electrode are formed on the bottom source and bottom drain electrodes. The buried power connection layer and buried power lines are electrically connected. The buried power connection layer, bottom ground connection layer, bottom word line connection layer, bottom bit line connection layer, and first memory bottom electrode are also formed on these layers. A top source and a top drain are formed on the bottom electrode and the second storage electrode. The first semiconductor layer in the top channel region and the bottom channel region is removed. Multiple gaps to be filled are formed between the second semiconductor layers. A second type of work function layer is formed in the multiple gaps to be filled. A protective material is filled in the multiple gaps to form a protective layer. The protective layer of a first thickness is etched using an anisotropic process. The protective layer of a second thickness is then etched using an isotropic process. Along the plane direction perpendicular to the line connecting the bottom source and the bottom drain, the difference between the second thickness and half the width of the gap to be filled is less than the target threshold. That is, by first etching the first thickness of the protective layer using anisotropic process and then continuing to etch the second thickness of the protective layer using isotropic process, the protective layer is precisely etched. The second type of work function layer in the gaps to be filled that are not covered by the protective layer is removed, and a first type of work function layer is formed in the gaps to be filled that are not covered by the protective layer. The protective layer is then removed, and gates are filled in multiple gaps to be filled. The gates surround a second semiconductor layer, and the stack of multiple second semiconductor layers forms a top channel structure and a bottom channel structure, respectively. A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first memory top electrode, and a second memory top electrode are formed on the top source and top drain, respectively. The top ground connection layer and the bottom ground connection layer are connected. Therefore, this application can achieve precise etching of the protective layer by using anisotropic etching combined with isotropic etching, thereby achieving precise control of the protective layer's position and avoiding the work function layer covering the wrong transistor, reducing the risk of transistor type confusion.

[0070] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0071] See Figure 4 The figure is a schematic flowchart of a method for manufacturing a complementary field-effect transistor according to an embodiment of this application.

[0072] The embodiments of this application are in accordance with Figure 5 Complementary field-effect transistors are fabricated using the structural layout corresponding to the storage cells of the static random access memory shown. Figure 5 The memory cell structure consists of two layers, with the top layer being NMOS, as referenced. Figure 6 As shown, the bottom layer is PMOS, reference... Figure 7 As shown. By Figure 7 It is known that buried power lines (VDD) can be designed to achieve the power connection of complementary field-effect transistors.

[0073] Figure 8 The diagram shown is a three-dimensional structural schematic of a complementary field-effect transistor provided in an embodiment of this application. By taking cross-sections in the directions of XX', YY', Y1-Y1', Y2-Y2', and Y3-Y3' of the three-dimensional structural schematic, cross-sectional structural schematics of complementary field-effect transistors A, B, C, D, and E are obtained respectively. Figure 24B , Figure 25C , Figure 27C and Figure 40C Let D be the cross section in the Y2-Y2' direction. Figure 25B , Figure 26B , Figure 27B and Figure 40B Let C be the cross section in the Y1-Y1' direction. Figure 25D , Figure 27D , Figure 39B and Figure 40D Let E be the cross section in the Y3-Y3' direction.

[0074] The method for manufacturing a complementary field-effect transistor provided in this application includes the following steps:

[0075] S101, a substrate is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer and a second semiconductor layer is formed on one side of the substrate. Along a direction perpendicular to the plane of the substrate, the stacked structure includes a buffer layer in the middle region. (Refer to...) Figure 9A and Figure 9B As shown.

[0076] In the embodiments of this application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0077] As an example, the desired well depth can be achieved by implanting impurities into a bulk silicon substrate and then annealing it to form a highly doped well region. The doping type of the substrate 110 varies depending on the device type. For P-type semiconductor devices, the highly doped well region is an N-well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions. For N-type semiconductor devices, the highly doped well region is a p-well, and the implanted impurities are p-type impurity ions, such as boron (B) ions.

[0078] In embodiments of this application, a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 can be formed on one side of the substrate 110, as shown in the reference. Figure 9A and Figure 9B As shown.

[0079] Specifically, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same. For example, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. Alternatively, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon-germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon.

[0080] Considering that two transistors with different doping types can be formed by stacking layers, different doping types of silicon can also be used when the material is silicon. For example, the material of the second semiconductor layer 122 at the top is P-type doped silicon, and the material of the second semiconductor layer 122 at the bottom can be N-type doped silicon.

[0081] Along a direction perpendicular to the plane of the substrate 110, the stacked structure includes a buffer layer 123 located in the middle region. The buffer layer 123 is used to separate two stacked transistors of different doping types that are subsequently formed. The material of the buffer layer 123 can be the same as the material of the first semiconductor layer 121, and both sides of the surface of the buffer layer 123 are the first semiconductor layer 121.

[0082] As one possible implementation, along a direction perpendicular to the plane of the substrate 110, if the material of the first semiconductor layer 121 is silicon-germanium, the proportion of Ge in the first semiconductor layer 121 in the stacked structure gradually increases and then decreases, with the buffer layer 123 having the highest proportion of Ge. As an example, the proportion of Ge increases from 30% to 60% and then decreases to 30%.

[0083] In practical applications, silicon oxide may be formed on the substrate 110. The stacked structure can be formed after the silicon oxide on the substrate 110 is removed and the substrate 110 is cleaned.

[0084] S102, etching is performed on the stacked structure and a partially thick substrate to form a fin structure. The fin structure includes a top structure, a bottom structure, and a substrate structure. The top and bottom structures are separated by a buffer layer, and a buried power line is formed between the two substrate structures. (Reference) Figure 10A and Figures 10B to 16A and Figure 16B As shown.

[0085] In the embodiments of this application, two fin structures can be formed by etching the stacked structure and a partially thick substrate 110. The fin structures include a top structure 510, a bottom structure 520, and a substrate structure 530, wherein the top structure 510 and the bottom structure 520 are separated by a buffer layer 123. After forming the fin structures, buried power lines 310 can be formed between the substrate structures 530 included in the two fin structures, without forming buried ground lines. The process flow for forming the fin structures and the buried power lines 310 is described in detail below.

[0086] S1021, Sidewall Transfer Process, Reference Figure 10A and Figure 10B As shown.

[0087] In the embodiments of this application, a self-aligned sidewall transfer process is used to form the first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is as follows: a sacrificial layer 202 is covered on the stacked structure. The material of the sacrificial layer 202 can be polycrystalline silicon or amorphous silicon. Part of the sacrificial layer 202 is etched away using photolithography to form a pattern. Silicon nitride material is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 202, so that only the first sidewall 201 on the stacked structure remains. The first sidewall 201 plays the role of a hard mask in the subsequent photolithography for forming fins.

[0088] S1022, forming a fin structure, reference. Figure 11A and Figure 11B As shown.

[0089] In the embodiments of this application, the stacked structure and a portion of the substrate thickness can be etched using an etching process to form multiple periodically distributed fins, as shown in the reference. Figure 11A and Figure 11BAs shown. Etching is performed using the first sidewall 201 as a mask to form a fin with a stacked structure. The upper part of the fin consists of a top structure 510 and a bottom structure 520 formed by the stacked structure, separated by a buffer layer 123. The top structure 510 and bottom structure 520 form a channel region. The lower part of the fin is a substrate 110, forming a structure as shown. Figure 11B The fin shown is not only a stacked structure but also includes a single-crystal silicon structure extending into the substrate 110. The etching process can be dry etching or wet etching, and in one embodiment, reactive ion etching can be used. The fin structure will be used to form nanosheets for complementary field-effect transistors. Although Figure 11B Two fins are shown, and it should be understood that any suitable number and shape of fins can be used in practical applications.

[0090] In practical applications, the first sidewall 201 can be removed after the fin structure is formed.

[0091] S1023, forming the embedded power line 310, reference. Figure 12A and Figures 12B to 15A and Figure 15B As shown.

[0092] In embodiments of this application, buried power lines 310 can be formed between two finned substrate structures 530. Specifically, a dielectric insulating material can be deposited first, followed by a planarization process, such as CMP, to form an insulating layer 410, as described above. Figure 12A and Figure 12B The insulating layer 410 between the two fin structures is etched to the depth of the area where the substrate structure 530 is located, forming a recess, as referenced. Figure 13A and Figure 13B The etched depressions are filled with a metallic material, such as tungsten (W), followed by planarization and etch-back processes to form the embedded power line 310. (Refer to...) Figure 14A and Figure 14B Finally, dielectric insulating material is deposited, followed by a planarization process to fill the depressions, as per reference. Figure 15A and Figure 15B As shown.

[0093] In practical applications, the embedded power line 310 can also be a grounding wire (VSS) or other power voltage plane (VCC).

[0094] S1024, forming shallow trench isolation 203 (STI). (See reference...) Figure 16A and Figure 16B As shown.

[0095] In embodiments of this application, shallow trench isolation 203 can be formed between different fins. Specifically, a selective etch-back process is performed on the insulating layer 410 formed in S1023 to expose the three-dimensional fins, specifically exposing the top structure 510 and the bottom structure 520, thereby forming shallow trench isolation 203 adjacent to the fin structure. The surface of the shallow trench isolation 203 away from the substrate 110 can be flush with, or higher than, the surface of the stacked structure in the fin structure near the substrate 110. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fin structures.

[0096] S103, etching the top structure, buffer layer, and bottom structure to form the top source region, top drain region, bottom source region, and bottom drain region. The top channel region is between the top source region and the top drain region, and the bottom channel region is between the bottom source region and the bottom drain region. Inner sidewalls are formed on the sidewalls of the top and bottom structures. (Refer to...) Figure 17A and Figures 17B to 20A and Figure 20B As shown.

[0097] In the embodiments of this application, considering that two transistors with different doping types need to be formed stacked on top of each other, it is necessary to form the source and drain of the two transistors respectively. First, the source and drain regions of the two transistors need to be formed, and then the inner sidewalls are formed. The specific process is described in detail below.

[0098] S1031, forming a false gate 204 and a second sidewall 205, reference Figure 17A and Figure 17B As shown.

[0099] In the embodiments of this application, a dummy gate stack is formed on the exposed fin structure in a direction perpendicular to the fin lines, i.e., the XX direction. The dummy gate stack is a multi-layer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). The dummy gate stack can be formed using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The dummy gate stack spans the stack structure above the fin structure, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 can be polycrystalline silicon or amorphous silicon. The material of the hard mask layer can be oxides, carbides, organic materials, etc.

[0100] In the embodiments of this application, second sidewalls 205 can be provided on both sides of the dummy gate stack along the fin direction, i.e., the YY direction, and the thickness of the second sidewalls 205 on both sides is the same. The material of the second sidewalls 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0101] S1032, etch the top structure 510, buffer layer 123, and bottom structure 520 to form the top source region 1101, top drain region 1102, bottom source region 1201, and bottom drain region 1202. (Reference) Figure 18A As shown.

[0102] In the embodiments of this application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source and drain etching on the stacked structure through an etching process. Specifically, source and drain etching is performed on the top structure 510, the buffer layer 123, and the bottom structure 520 to form a top source region 1101, a top drain region 1102, a bottom source region 1201, and a bottom drain region 1202. The top channel region 1103 is located between the top source region 1101 and the top drain region 1102, and the bottom channel region 1203 is located between the bottom source region 1201 and the bottom drain region 1202. After etching, the top source region 1101, the top drain region 1102, the bottom source region 1201, and the bottom drain region 1202 no longer have a stacked structure. Figure 18A As shown.

[0103] S1033, forming a concave structure, reference. Figure 19A and Figure 19B As shown.

[0104] In the embodiments of this application, along the YY direction, the first semiconductor layer 121 located in the top structure 510 and the bottom structure 520 is selectively etched, that is, the portion of the first semiconductor layer 121 located in the top structure 510 and the bottom structure 520 is etched away, without damaging the second semiconductor layer 122. Along the YY direction, the portion of the first semiconductor layer 121 that is missing from the second semiconductor layer 122 forms a concave structure, that is, pull-back etching is performed, and the portion of the first semiconductor layer 121 from the bottom source region 1201 and the bottom drain region 1202 to the bottom channel region 1203 and the portion from the top source region 1101 and the top drain region 1102 to the top channel region 1103 is etched away.

[0105] While selectively etching the first semiconductor layer 121 in the top structure 510 and the bottom structure 520, the buffer layer 123 is also etched away to form a buffer isolation structure. (Refer to...) Figure 19A As shown.

[0106] S1034, forming inner wall 206, reference Figure 20A and Figure 20B As shown.

[0107] In the embodiments of this application, after the first semiconductor layer 121 is etched, a dielectric material is deposited on the bottom structure 520 of the bottom channel region 1203 and the top structure 510 of the top channel region 1103, i.e., the periphery of the fins. The dielectric material is etched to form an inner sidewall 206. The inner sidewall 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane of the substrate 110. That is, the concave structure caused by etching S1033 is filled by the inner sidewall 206. The material of the inner sidewall 206 can be silicon nitride or silicon oxide.

[0108] In addition to filling the concave structure, the dielectric material also fills the buffer isolation structure, thus forming an isolation layer 200.

[0109] S104 forms the bottom source and bottom drain in the bottom source and bottom drain regions, respectively. (Refer to...) Figure 21A Show.

[0110] In embodiments of this application, after etching the stacked structure to form the bottom source region 1201 and the bottom drain region 1202, a bottom source 131 and a bottom drain 132 can be formed in the bottom source region 1201 and the bottom drain region 1202, respectively. (Refer to...) Figure 21A As shown. The surfaces of the bottom source 131 and bottom drain 132 away from the substrate 110 can be flush with the surface of the isolation layer 200 near the substrate 110.

[0111] Specifically, the source and drain materials may differ for different types of semiconductor devices. For P-type semiconductor devices, the source and drain materials are boron-doped germanium silicon, i.e., SiGe:B. For N-type semiconductor devices, the source and drain materials are carbon-doped silicon, i.e., Si:C.

[0112] S105, a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first memory bottom electrode, and a second memory bottom electrode are formed on the bottom source and bottom drain electrodes. The buried power connection layer and the buried power line are electrically connected. (Refer to...) Figures 22A to 28A , Figure 27B , Figure 27C and Figure 27D As shown.

[0113] In the embodiments of this application, considering that both transistors stacked on top of each other need to be electrically led out, after forming the bottom source 131 and bottom drain 132, a buried power connection layer 320, a bottom ground connection layer 331, a bottom word line connection layer, a bottom bit line connection layer 351, a first storage bottom electrode 361, and a second storage bottom electrode 371 can be formed on the bottom source 131 and bottom drain 132. The buried power connection layer 320 and the buried power line 310 are electrically connected. The specific formation process is described in detail below.

[0114] S1051, forming a target sidewall 300, reference. Figure 22A As shown.

[0115] In the embodiments of this application, after forming the bottom source 131 and the bottom drain 132, a target sidewall 300 can also be formed. The target sidewall 300 covers the sidewall of the inner sidewall 206, that is, the target sidewall 300 is respectively provided on both sides of the inner sidewall 206 along the fin direction, i.e., the YY direction, and the target sidewall 300 on both sides has the same thickness. The material of the target sidewall 300 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0116] S1052, forming a first dielectric layer 420, the first dielectric layer 420 covering the top structure 510 and the target sidewall 300, reference. Figure 23A and Figure 23B .

[0117] In embodiments of this application, after forming the target sidewall 300, a dielectric material can be deposited, and a planarization process can be performed to form a first dielectric layer 420. The first dielectric layer 420 covers the top structure 510 and the target sidewall 300. (Refer to...) Figure 23A and Figure 23B .

[0118] S1053, etch the first dielectric layer 420 on both sides of the top structure 510 to form a first groove 610, the first groove 610 exposing the bottom source 131 and the bottom drain 132. Reference Figure 24A and Figure 24B .

[0119] In embodiments of this application, after forming the first dielectric layer 420, the first dielectric layer 420 on both sides of the top structure 510 can be etched down to the bottom source 131 and the bottom drain 132 to form a first groove 610. The first groove 610 exposes the bottom source 131 and the bottom drain 132. (See reference...) Figure 24A As shown. The first groove 610 also exposes the embedded power cable 310, see reference. Figure 24B As shown.

[0120] S1054, a buried power connection layer 320, a bottom ground connection layer 331, a bottom word line connection layer, a bottom bit line connection layer 351, a first storage bottom electrode 361, and a second storage bottom electrode 371 are formed on the bottom source 131 and bottom drain 132 exposed in the first recess 610. (Reference) Figure 25A , Figure 25B , Figure 25C and Figure 25D As shown.

[0121] In embodiments of this application, after forming a first groove 610 exposing the bottom source 131 and bottom drain 132, a bottom ground connection layer 331, a first storage bottom electrode 361, and a bottom bit line connection layer 351 can be formed on the bottom source 131 and bottom drain 132 exposed by the first groove 610. (Refer to...) Figure 25A As shown. A first storage bottom electrode 361 and a second storage bottom electrode 371 are formed on the bottom source 131 and bottom drain 132 exposed in the first recess 610, as shown in the figure. Figure 25D As shown. A buried power connection layer 320 and a bottom ground connection layer 331 are formed on the bottom source 131 and bottom drain 132 exposed in the first recess 610. The buried power connection layer 320 and the buried power line 310 are electrically connected. (Refer to...) Figure 25B and Figure 25C As shown. At the same time, a bottom word line connection layer is formed on the bottom source 131 and bottom drain 132 exposed in the first groove 610.

[0122] S1055, a second dielectric layer 430 is formed in the first groove 610, reference Figure 26A and Figure 26B As shown.

[0123] In the embodiments of this application, after forming the buried power connection layer 320, the bottom ground connection layer 331, the bottom word line connection layer, the bottom bit line connection layer 351, the first storage bottom electrode 361, and the second storage bottom electrode 371, a dielectric material can be deposited in the first groove 610, followed by a planarization process to form the second dielectric layer 430. (Refer to...) Figure 26A and Figure 26B As shown. The first dielectric layer 420 and the second dielectric layer 430 can be made of the same material.

[0124] S1056, etch the first dielectric layer 420 and the second dielectric layer 430 to the surface of the buffer layer 123 away from the substrate 110, reference Figure 27A , Figure 27B , Figure 27C and Figure 27D As shown.

[0125] In the embodiments of this application, after the second dielectric layer 430 is formed, the first dielectric layer 420 and the second dielectric layer 430 can be etched back to the side of the buffer layer 123 away from the substrate 110. The etched first dielectric layer 420 and the second dielectric layer 430 cover the buried power connection layer 320, the bottom ground connection layer 331, the bottom word line connection layer, the bottom bit line connection layer 351, the first storage bottom electrode 361 and the second storage bottom electrode 371. (Refer to...) Figure 27A , Figure 27B , Figure 27C and Figure 27D As shown.

[0126] S1057, etch the target sidewall 300 to the surface of the isolation layer 200 away from the substrate 110, reference. Figure 28A As shown.

[0127] In the embodiments of this application, after forming the buried power connection layer 320, the bottom ground connection layer 331, the bottom word line connection layer, the bottom bit line connection layer 351, the first storage bottom electrode 361 and the second storage bottom electrode 371, the target sidewall 300 can also be etched to the side surface of the isolation layer 200 away from the substrate 110, that is, the target sidewall 300 is only provided on the sidewall of the isolation layer 200.

[0128] S106, a top source and a top drain are formed on the buried power connection layer, bottom ground connection layer, bottom word line connection layer, bottom bit line connection layer, first memory bottom electrode, and second memory bottom electrode. (Reference) Figure 29A As shown.

[0129] In embodiments of this application, after forming the buried power connection layer 320, bottom ground connection layer 331, bottom word line connection layer, bottom bit line connection layer 351, first storage bottom electrode 361, and second storage bottom electrode 371, a top source 133 and a top drain 134 can be formed on the buried power connection layer 320, bottom ground connection layer 331, bottom word line connection layer, bottom bit line connection layer 351, first storage bottom electrode 361, and second storage bottom electrode 371, so as to form the source and drain of the upper transistor in two stacked transistors, see reference. Figure 29A As shown. The top source 133 and the top drain 134 can be specifically located on the first dielectric layer 420 and the second dielectric layer 430.

[0130] Specifically, the source and drain materials may differ for different types of semiconductor devices. For P-type semiconductor devices, the source and drain materials are boron-doped germanium silicon, i.e., SiGe:B. For N-type semiconductor devices, the source and drain materials are carbon-doped silicon, i.e., Si:C.

[0131] S107, the first semiconductor layer in the top and bottom channel regions is removed, and multiple gaps to be filled are formed between the second semiconductor layers. A second type of work function layer is formed in the multiple gaps to be filled. (Refer to...) Figure 30A and Figures 30B to 32A and Figure 32B As shown.

[0132] In embodiments of this application, the first semiconductor layer 121 of the top channel region 1103 and the bottom channel region 1203 can be removed, i.e., a nanosheet channel release process can be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layer 122, see reference. Figure 31A and Figure 31B As shown. Then, a second type of work function layer 710 is formed in multiple gaps 402 to be filled, as referenced. Figure 32A and Figure 32B As shown.

[0133] Specifically, the first semiconductor layer 121 in the stacked structure located in the top channel region 1103 and the bottom channel region 1203 can be selectively etched to release the nanosheet channel. That is, the stacked structure exposed by the fins is processed to remove the first semiconductor layer 121 of each layer, which is the sacrificial layer, to release the nanosheet formed by the second semiconductor layer 122.

[0134] In the embodiments of this application, there are several possible ways to achieve nanosheet channel release for different types of devices:

[0135] In a first possible implementation, for both P-type and N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-laminated nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0136] In a second possible implementation, for a P-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon. Silicon is selectively removed, leaving the second semiconductor layer 122, i.e., silicon-germanium, to form a silicon-germanium stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon at a faster rate than silicon-germanium can be used.

[0137] In a third possible implementation, for N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0138] In the embodiments of this application, before removing the first semiconductor layer 121 of the top channel region 1103 and the bottom channel region 1203, the dummy gate 204 can be removed first. The specific process flow is as follows.

[0139] S1071, Remove dummy gate 204, Reference Figure 30A and Figure 30B As shown.

[0140] In embodiments of this application, a spacer layer 207 can be deposited on the surfaces of the dummy gate 204, the top source 133, and the top drain 134 to prevent short circuits between the dummy gate 204 and the top source 133 or the top drain 134 in subsequent steps. The spacer layer 207 is then subjected to a chemical mechanical polishing process to planarize it. Then, as... Figure 30A and Figure 30B As shown, the dummy gate 204 formed by the aforementioned polycrystalline silicon or amorphous silicon is etched or etched away by selective etching or etching processes, that is, the dummy gate 204 is removed.

[0141] In embodiments of this application, after forming a plurality of gaps 402 to be filled, an interface layer can be formed on the surface of the second semiconductor layer 122, and the interface between the interface layer and the second semiconductor layer 122 can be passivated. Specifically, the material of the interface layer can be silicon oxide.

[0142] In embodiments of this application, after forming the interface layer, a high-k dielectric layer can be formed on the surface of the interface layer, with the high-k dielectric layer surrounding the surface of the interface layer. Specifically, the material of the high-k dielectric layer can be HfO2 or HfSiO2. x , HfON, HfSiON, HfAlOx, HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0143] To form transistors of different types, it is necessary to use isolation layers to isolate different types of transistors and different types of work function layers to realize different types of transistors. The specific process flow is introduced below.

[0144] S1072, forming a second type of work function layer 710 in all the gaps 402 to be filled, reference. Figure 32A and Figure 32B As shown.

[0145] In embodiments of this application, a second type of work function layer 710 can be formed in all the gaps 402 to be filled, the second type of work function layer 710 surrounding the surface of the high-k dielectric layer. Specifically, the second type of work function layer 710 is a P-type work function layer (P-WFL).

[0146] S108, a protective material is filled into multiple gaps to form a protective layer. A first-thickness protective layer is etched using an anisotropic etching process. A second-thickness protective layer is then etched using an isotropic etching process. Along a plane perpendicular to the line connecting the bottom source and bottom drain, the difference between the second thickness and half the width of the gap to be filled is less than a target threshold. Figure 33A and Figures 33B to 35A and Figure 35BAs shown.

[0147] In the embodiments of this application, a protective layer 730 can be formed by filling multiple gaps 402 to be filled with protective material. The protective layer 730 of a first thickness is etched using an anisotropic process, and the protective layer 730 of a second thickness is etched using an isotropic process. The difference between the second thickness and half the width of the gap 402 to be filled is less than a target threshold along the plane direction perpendicular to the line connecting the bottom source 131 and the bottom drain 132. That is, the first thickness of the protective layer 730 is precisely etched using anisotropic process so that the second thickness of the protective layer 730 can be etched using isotropic process. The protective layer 730 is etched to half the position of the isolation layer 200, thereby achieving precise etching of the protective layer 730 and reducing the risk of forming the same work function layer covering different transistors in the future.

[0148] S1081, using an anisotropic process, a protective layer 730 of half the width and thickness of the gap 402 to be filled is etched, reference. Figure 34A and Figure 34B As shown.

[0149] In embodiments of this application, the first thickness can be half the width of the gap 402 to be filled. A protective layer 730 with a thickness equal to half the width of the gap 402 to be filled can be etched using an anisotropic process, i.e., etched from the side of the protective layer 730 away from the substrate 110. The etching rate of the anisotropic process in the direction perpendicular to the surface of the substrate 110 is greater than the etching rate in the direction parallel to the surface of the substrate 110. Therefore, when the protective layer 730 is etched using anisotropic technology, the protective layer 730 between adjacent second semiconductor layers 122 may not be completely etched away.

[0150] As an example, anisotropic etching processes can be reactive ion etching (RIE), remote plasma source (RPS), atomic layer etching (ALE), or physical milling.

[0151] S1082, continue etching the second thickness of the protective layer 730 to half the position of the isolation layer 200 using an isotropic etching process, referencing... Figure 35A and Figure 35B As shown.

[0152] In the embodiments of this application, since anisotropic etching processes are prone to incomplete etching of the protective layer 730 between adjacent second semiconductor layers 122, an isotropic process is used to continue etching the protective layer 730 up to half the distance of the isolation layer 200. The half-distance of the isolation layer 200 is the half-distance in the direction perpendicular to the plane of the substrate 110. Because the isotropic process has the same etching rate in all directions, it can etch not only the protective layer 730 in the direction perpendicular to the surface of the substrate 110, but also the protective layer 730 between adjacent second semiconductor layers 122.

[0153] Considering that the difference between the second thickness and half the width of the gap 402 to be filled is less than the target threshold, the target threshold can be 0. Thus, when the protective layer 730 is etched using the isotropic process, the protective layer 730 can be etched to half the position of the isolation layer 200, and the protective layer 730 between adjacent second semiconductor layers 122 can also be removed. This means that the etching position of the protective layer 730 can be precisely controlled, and the protective layer 730 between nanosheets can be effectively removed, avoiding the residue of the protective layer 730.

[0154] refer to Figure 35A and Figure 35B As shown, the protective layer 730 fills the gap 402 to be filled in the bottom structure 520.

[0155] As an example, isotropic etching processes can be wet etching, RPS, chemical dry etching, or ALE.

[0156] S109, Remove the second type of work function layer from the gap to be filled that is not covered by the protective layer, and form a first type of work function layer in the gap to be filled that is not covered by the protective layer, refer to Figure 36A and Figure 36B For reference Figure 37A and Figure 37B As shown.

[0157] In the embodiments of this application, using the protective layer 730 as a mask, the second type of work function layer 710 in the gap 402 to be filled that is not covered by the protective layer 730 is removed, and a first type of work function layer 720 is formed in the gap 402 to be filled that is not covered by the protective layer 730. That is, the second type of work function layer 710 in the gap 402 to be filled located in the top structure 510 is removed, and a first type of work function layer 720 is formed in the gap 402 to be filled located in the top structure 510, thereby forming a top structure 510 with a first type of work function layer 720 and a bottom structure 520 with a second type of work function layer 710. (Refer to...) Figure 36A and Figure 36BAs shown. Specifically, the first type of work function layer 720 is an N-type work function layer (N-WFL). The second type of work function layer 710 located in the gap 402 to be filled in the top structure 510 can be removed by an etching process.

[0158] S1091, Remove protective layer 730, Reference Figure 37A and Figure 37B As shown.

[0159] In the embodiments of this application, after forming the first type of work function layer 720 and the second type of work function layer 710, the protective layer 730 can be removed.

[0160] In practical applications, the protective layer 730 can be removed first, and then the first type of work function layer 720 can be formed in all the gaps 402 to be filled. That is, the second type of work function layer 710 is formed first in the gaps 402 to be filled in the bottom structure 520, and then the first type of work function layer 720 is formed.

[0161] S110, a gate is filled in multiple gaps to be filled, the gate surrounds a second semiconductor layer, and the stack of multiple second semiconductor layers forms a top channel structure and a bottom channel structure, respectively. (Reference) Figure 38A and Figure 38B As shown.

[0162] In the embodiments of this application, after the nanosheet channel is released, there are multiple gaps 402 to be filled between the multiple second semiconductor layers 122. A gate 160 can be filled into these gaps 402. The gate 160 surrounds the second semiconductor layers 122, forming a ring gate structure. Specifically, the gate 160 surrounds a first type work function layer 720 and a second type work function layer 710. The stack of multiple second semiconductor layers 122 forms a top channel structure and a bottom channel structure, i.e., forms a nanosheet channel for a complementary field-effect transistor. (Refer to...) Figure 38A and Figure 38B As shown.

[0163] In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 also covers the spacer layer 207 and the space after the dummy gate 204 is removed. The gate 160 covered by the spacer layer 207 can be chemically mechanically polished to perform planarization.

[0164] S120, a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first memory top electrode, and a second memory top electrode are formed on the top source and top drain, respectively. The top ground connection layer and the bottom ground connection layer are connected. (Refer to...) Figure 39A and Figures 39B to 40A , Figure 40B , Figure 40C and Figure 40D As shown.

[0165] In embodiments of this application, after forming the gate 160, a top ground connection layer 332, a top word line connection layer, a top bit line connection layer 352, a first storage top electrode 362, and a second storage top electrode 372 can be formed on the top source 133 and the top drain 134, respectively. The top ground connection layer 332 and the bottom ground connection layer 331 are connected. (Refer to...) Figure 40A , Figure 40B , Figure 40C and Figure 40D As shown below, the specific formation process will be described in detail.

[0166] S121, a third dielectric layer 440 is formed on the top source 133 and the top drain 134.

[0167] In the embodiments of this application, after forming the top source 133 and the top drain 134, a dielectric material can be deposited and a planarization process can be performed to form a third dielectric layer 440, which covers the top source 133 and the top drain 134.

[0168] S122, etch the third dielectric layer 440 on both sides of the top structure 510 to form a second groove 620, the second groove 620 exposing the top source 133 and the top drain 134, reference. Figure 39A and Figure 39B As shown.

[0169] In embodiments of this application, after forming the third dielectric layer 440, the third dielectric layer 440 on both sides of the top structure 510 can be etched to the top source 133 and the top drain 134 to form a second groove 620. The second groove 620 exposes the top source 133 and the top drain 134. (Refer to...) Figure 39A As shown. The second groove 620 also exposes the first storage bottom electrode 361 and the second storage bottom electrode 371, as shown in the reference. Figure 39B As shown.

[0170] S123, a top ground connection layer 332, a top word line connection layer, a top bit line connection layer 352, a first storage top electrode 362, and a second storage top electrode 372 are formed on the top source 133 and top drain 134 exposed in the second recess 620, respectively. (Reference) Figure 40A , Figure 40B , Figure 40C and Figure 40D As shown.

[0171] In embodiments of this application, after forming a second recess 620 exposing the top source 133 and the top drain 134, a top ground connection layer 332, a first storage top electrode 362, and a top bit line connection layer 352 can be formed on the top source 133 and the top drain 134 exposed by the second recess 620. (Refer to...) Figure 40A As shown. A first storage top electrode 362 and a second storage top electrode 372 are formed on the top source 133 and top drain 134 exposed in the second recess 620, as shown in the figure. Figure 40D As shown. A top ground connection layer 332 and a top bit line connection layer 352 are formed on the top source 133 and top drain 134 exposed in the second recess 620. The top ground connection layer 332 and the bottom ground connection layer 331 are electrically connected. (Refer to...) Figure 40B and Figure 40C As shown. At the same time, a top word line connection layer is formed on the top source 133 and top drain 134 exposed in the second groove 620.

[0172] In practical applications, the first storage electrode includes a first storage top electrode 362 and a first storage bottom electrode 361, and the first storage electrode can be a Q storage electrode. The second storage electrode includes a second storage top electrode 372 and a second storage bottom electrode 371, and the second storage electrode can be a QB storage electrode.

[0173] The embodiments of this application utilize anisotropic etching combined with isotropic etching to achieve not only precise layering of work function layers using a precisely positioned protective layer, but also precise layering of gate or high-k dielectric layers. This also enables the layering of different types and thicknesses of gate or high-k dielectric layers in stacked transistors. Therefore, this application, by utilizing anisotropic etching combined with isotropic etching, achieves precise etching of the protective layer, avoiding vertical overlays and accurately controlling the position of the protective layer. This prevents transistors with incorrect coverage of different types of work function layers, high-k dielectric layers, and gates, reducing the risk of transistor type confusion. Furthermore, this application, by utilizing anisotropic etching combined with isotropic etching, can effectively remove the protective layer between nanosheet layers, thus avoiding protective layer residue.

[0174] Based on the manufacturing method of the complementary field-effect transistor provided in the above embodiments, this application also provides a complementary field-effect transistor, the working principle of which will be described in detail below with reference to the accompanying drawings.

[0175] See Figure 40A , Figure 40B , Figure 40C and Figure 40D As shown in the figure, this figure is a schematic cross-sectional view of the complementary field-effect transistor provided in an embodiment of this application.

[0176] The complementary field-effect transistor provided in this embodiment includes:

[0177] Substrate 110;

[0178] A top source 133, a top drain 134, a top channel structure, a bottom source 131, a bottom drain 132, and a bottom channel structure are disposed on one side of the substrate. In a direction perpendicular to the plane of the substrate, the top source 133 and the bottom source 131 overlap, the top drain 134 and the bottom drain 132 overlap, and the top channel structure and the bottom channel structure overlap. The top channel structure is located between the top source 133 and the top drain 134, and the bottom channel structure is located between the bottom source 131 and the bottom drain 132. The top channel structure and the bottom channel structure comprise a stack of multiple nanosheets.

[0179] Gate 160, the gate 160 surrounding the nanosheet;

[0180] The nanosheets of the top channel structure are surrounded by a first type of work function layer 720, and the nanosheets of the bottom channel structure are surrounded by a second type of work function layer 710.

[0181] The top ground connection layer 332 is in contact with the top source electrode 133, the bottom ground connection layer 331 is in contact with the bottom source electrode 131, and the top ground connection layer 332 and the bottom ground connection layer 331 are connected.

[0182] As one possible implementation, an isolation layer 200 is provided between the top channel structure and the bottom channel structure.

[0183] As one possible implementation, the sidewall of the isolation layer 200 is provided with a target sidewall 300.

[0184] As one possible implementation, along a direction perpendicular to the plane of the substrate 110, the halfway point of the sidewall of the isolation layer 200 is the junction of the first type of work function layer 720 and the second type of work function layer 710.

[0185] Based on the complementary field-effect transistor provided in the above embodiments, this application also provides a static random access memory (SRAM). The SRAM includes a plurality of memory cells, and the memory cells include the complementary field-effect transistor described in any one of the above embodiments.

[0186] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the structural embodiments. The structural embodiments described above are merely illustrative, and those skilled in the art can understand and implement them without creative effort.

[0187] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for manufacturing a complementary field-effect transistor, characterized in that, The method includes: A substrate is provided, and a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer are formed on one side of the substrate. Along a direction perpendicular to the plane of the substrate, the stacked structures include a buffer layer located in the middle region. The stacked structure and a substrate of a certain thickness are etched to form a fin structure, the fin structure including a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure being separated by the buffer layer, and a buried power line being formed between the two substrate structures; The top structure, the buffer layer, and the bottom structure are etched to form a top source region, a top drain region, a bottom source region, and a bottom drain region. A top channel region is formed between the top source region and the top drain region, and a bottom channel region is formed between the bottom source region and the bottom drain region. Inner sidewalls are formed on the sidewalls of the top structure and the sidewalls of the bottom structure. A bottom source and a bottom drain are formed in the bottom source region and the bottom drain region; An embedded power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode are formed on the bottom source and the bottom drain. The embedded power connection layer and the embedded power line are electrically connected. A top source and a top drain are formed on the embedded power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first storage bottom electrode, and the second storage bottom electrode; The first semiconductor layer of the top channel region and the bottom channel region is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers. A second type of work function layer is formed in the plurality of gaps to be filled. A protective material is filled into multiple gaps to be filled to form a protective layer. The protective layer of a first thickness is etched using an anisotropic process. The protective layer of a second thickness is then etched using an isotropic process. Along a plane direction perpendicular to the line connecting the bottom source and the bottom drain, the difference between the second thickness and half the width of the gap to be filled is less than a target threshold. Remove the second type of work function layer from the gaps to be filled that are not covered by the protective layer, and form a first type of work function layer in the gaps to be filled that are not covered by the protective layer; Remove the protective layer; A gate is filled in a plurality of the gaps to be filled, the gate surrounds the second semiconductor layer, and the stack of the plurality of second semiconductor layers respectively forms a top channel structure and a bottom channel structure; A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode are formed on the top source and the top drain, respectively, and the top ground connection layer and the bottom ground connection layer are connected.

2. The manufacturing method according to claim 1, characterized in that, The formation of inner sidewalls on the sidewalls of the top structure and the sidewalls of the bottom structure includes: Etching away portions of the first semiconductor layer on the sidewalls of the top structure and the sidewalls of the bottom structure, and etching away the buffer layer, respectively forming a concave structure and a buffer isolation structure; An inner wall is formed in the concave structure, and an isolation layer is formed in the buffer isolation structure.

3. The manufacturing method according to claim 2, characterized in that, The step of etching the protective layer of a first thickness using an anisotropic process and then etching the protective layer of a second thickness using an isotropic process includes: The protective layer, with a thickness equal to half the width of the gap to be filled, is etched using an anisotropic process. Continue etching the second thickness of the protective layer using an isotropic process up to 1 / 2 of the position of the isolation layer.

4. The manufacturing method according to claim 3, characterized in that, Before forming a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode on the bottom source and the bottom drain, the method further includes: A target sidewall is formed, which covers the sidewall of the inner sidewall; A first dielectric layer is formed, which covers the top structure and the target sidewall; The first dielectric layer on both sides of the top structure is etched to form a first groove, the first groove exposing the bottom source and the bottom drain; The formation of a buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first memory bottom electrode, and a second memory bottom electrode on the bottom source and the bottom drain includes: A buried power connection layer, a bottom ground connection layer, a bottom word line connection layer, a bottom bit line connection layer, a first storage bottom electrode, and a second storage bottom electrode are formed on the bottom source and bottom drain exposed in the first groove. The method further includes: A second dielectric layer is formed in the first groove; Etch the first dielectric layer and the second dielectric layer to the surface of the isolation layer away from the substrate; Etch the target sidewall to the surface of the isolation layer away from the substrate; The formation of a top source and a top drain on the embedded power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first memory bottom electrode, and the second memory bottom electrode includes: A top source and a top drain are formed on the first dielectric layer and the second dielectric layer, which cover the buried power connection layer, the bottom ground connection layer, the bottom word line connection layer, the bottom bit line connection layer, the first memory bottom electrode, and the second memory bottom electrode.

5. The manufacturing method according to claim 1, characterized in that, Before forming a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode on the top source and the top drain, respectively, the method further includes: A third dielectric layer is formed on the top source and the top drain; The third dielectric layer on both sides of the top structure is etched to form a second groove, which exposes the top source and the top drain. The top source and the top drain are respectively formed with a top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode, including: A top ground connection layer, a top word line connection layer, a top bit line connection layer, a first storage top electrode, and a second storage top electrode are formed on the top source and the top drain exposed in the second groove, respectively.

6. A complementary field-effect transistor, characterized in that, The complementary field-effect transistor includes: Substrate; A top source, a top drain, a top channel structure, a bottom source, a bottom drain, and a bottom channel structure are disposed on one side of the substrate. In a direction perpendicular to the plane of the substrate, the top source and the bottom source overlap, the top drain and the bottom drain overlap, and the top channel structure and the bottom channel structure overlap. The top channel structure is located between the top source and the top drain, and the bottom channel structure is located between the bottom source and the bottom drain. The top channel structure and the bottom channel structure comprise a stack of multiple nanosheets. A gate, the gate surrounding the nanosheet; The nanosheets of the top channel structure are surrounded by a first type of work function layer, and the nanosheets of the bottom channel structure are surrounded by a second type of work function layer; The top ground connection layer is in contact with the top source electrode, the bottom ground connection layer is in contact with the bottom source electrode, and the top ground connection layer and the bottom ground connection layer are connected; An isolation layer is provided between the top channel structure and the bottom channel structure; along a direction perpendicular to the plane of the substrate, half of the sidewall of the isolation layer is the junction of the first type of work function layer and the second type of work function layer.

7. The complementary field-effect transistor according to claim 6, characterized in that, The isolation layer has a target sidewall on its sidewall.

8. A static random access memory, characterized in that, It includes multiple memory cells, each of which includes a complementary field-effect transistor as described in any one of claims 6-7.

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