Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method of manufacturing the semiconductor device capable of reducing generation of voids in transfer molding. A semiconductor device (50) is provided with: a laminated substrate (5) on which a semiconductor chip (1) is mounted; a circuit board (9) provided with wiring between the semiconductor chips (1) and wiring between the semiconductor chips (1) and the external output terminals (12); and a sealing resin (10) that seals the laminated substrate (5) and the circuit substrate (9). A flow rate control pin (14) is provided on the circuit board (9) on the side opposite to the laminated substrate (5) side.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, there is known a semiconductor device in which a fluid pressure regulating member that is movable up and down is provided in a first flow path having a larger flow path cross-sectional area among two flow paths (for example, refer to Patent Document 1 listed below).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 7-74193 Summary of the invention

[0006] Technical issues

[0007] In conventional semiconductor devices, there is a problem that when semiconductor elements are sealed by transfer molding, bubbles (voids) are generated at the point where the flow surfaces of the resin merge with each other due to the entrainment of air, which deteriorates the semiconductor device. The object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that can reduce the generation of voids in transfer molding.

[0008] Technical Solution

[0009] In order to solve the above problems and achieve the purpose of the present invention, the semiconductor device of the present invention has the following features. The semiconductor device comprises: a laminate substrate on which a semiconductor chip is mounted; a circuit substrate on which wiring between the semiconductor chips and wiring between the semiconductor chips and external output terminals are provided; and a sealing resin that seals the laminate substrate and the circuit substrate. A flow rate control pin is provided on the circuit substrate on the side opposite to the laminate substrate side.

[0010] In addition, the semiconductor device of the present invention is characterized in that the flow rate control pin is provided at an end portion of the circuit substrate in the above invention.

[0011] In addition, in the semiconductor device of the present invention, based on the above invention, the flow rate control pin is provided at an end portion of the circuit substrate and in a middle portion between the end portions.

[0012] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the flow rate control pin is made of a resin having an elastic modulus lower than that of the sealing resin.

[0013] In order to solve the above problems and achieve the purpose of the present invention, the manufacturing method of the semiconductor device of the present invention has the following characteristics. As a manufacturing method of a semiconductor device using a mold for transfer molding, first, a first step is performed to form a module, wherein the module has a laminated substrate on which a semiconductor chip is mounted, and a circuit substrate on which wiring between the semiconductor chips and wiring between the semiconductor chips and external output terminals are provided. Then, a second step is performed to mount the module on the mold. Then, a third step is performed to inject a sealing resin from an injection gate of the mold. On the circuit substrate, a flow rate control pin is arranged in parallel perpendicular to the flow direction of the sealing resin on the side opposite to the laminated substrate side.

[0014] In addition, the method for manufacturing a semiconductor device according to the present invention is characterized in that the flow rate control pin is arranged at an end portion of the circuit board on the injection gate side.

[0015] In addition, the semiconductor device manufacturing method of the present invention is characterized in that the flow rate control pin is arranged at the end of the circuit substrate close to the injection gate side and the end on the side opposite to the gate side.

[0016] In addition, the manufacturing method of the semiconductor device of the present invention is characterized in that, based on the above invention, the flow rate control pin is arranged at the end of the circuit substrate close to the injection gate side, the end on the side opposite to the end on the gate side, and in the middle between the ends.

[0017] In addition, a method for manufacturing a semiconductor device according to the present invention is characterized in that:

[0018] When the distance from the surface of the circuit substrate to the surface of the molding die is set to L, the width of the molding die perpendicular to the flow direction of the sealing resin is set to W, the number of the flow control pins is set to n, the width of the flow control pin when projected in the flow direction of the sealing resin is set to d, and the height of the flow control pin is set to h, the projection density ndh / LW of the flow blocked by the flow control pin relative to the cross-sectional area LW of the flow path of the sealing resin is greater than 10% and less than 48%.

[0019] In addition, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the flow rate control pin is made of a resin having an elastic modulus lower than that of the sealing resin.

[0020] In addition, the method for manufacturing a semiconductor device according to the present invention is characterized in that, based on the above invention, the cross-sectional shape of the flow rate control pin is an ellipse whose major axis is located on the flow direction side of the sealing resin.

[0021] Technical Effects

[0022] According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to reduce the generation of voids during transfer molding. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0024] Figure 2 1 is a plan view showing the structure of the semiconductor device according to the first embodiment, and is a view viewed from the circuit board side.

[0025] Figure 3 It is a side view showing the structure of the semiconductor device according to the first embodiment.

[0026] Figure 4 This is a cross-sectional view (part 1) showing the filling of the sealing resin in the method for manufacturing the semiconductor device according to the first embodiment.

[0027] Figure 5 This is a cross-sectional view (part 2) showing the filling of the sealing resin in the method for manufacturing the semiconductor device according to the first embodiment.

[0028] Figure 6 This is a cross-sectional view (part 3) showing the filling of the sealing resin in the method for manufacturing the semiconductor device according to the first embodiment.

[0029] Figure 7 This is a cross-sectional view (part 4) showing the filling of the sealing resin in the method for manufacturing the semiconductor device according to the first embodiment.

[0030] Figure 8 This is a cross-sectional view (part 5) showing the filling of the sealing resin in the method for manufacturing the semiconductor device according to the first embodiment.

[0031] Fig. 9 It is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0032] Fig.10 It is a plan view showing the structure of a semiconductor device according to the second embodiment.

[0033] Fig.11 This is a cross-sectional view (Part 1) showing stress relaxation during manufacture of the semiconductor device according to the second embodiment.

[0034] Fig.12This is a cross-sectional view (part 2) showing stress relaxation during manufacture of the semiconductor device according to the second embodiment.

[0035] Fig.13 This is a cross-sectional view (part 1) showing a method for evaluating voids in Examples.

[0036] Fig.14 This is a cross-sectional view (part 2) showing the void evaluation method in the example.

[0037] Fig.15 This is a cross-sectional view (part 3) showing the void evaluation method in the example.

[0038] Fig.16 It is a cross-sectional view showing the evaluation of the back clearance of the flow rate control pin in the example.

[0039] Fig.17 : is a cross-sectional view of a platform with warpage showing a fastening test in the embodiment.

[0040] Fig.18 is a cross-sectional view showing warpage of the semiconductor device in the embodiment.

[0041] Fig.19 It is a cross-sectional view showing a fastening test of the semiconductor device in the embodiment.

[0042] Fig. 20 is a cross-sectional view showing the shape of a flow rate control pin of the semiconductor device in the embodiment.

[0043] Fig.21 This is a cross-sectional view showing the filling of a sealing resin in a conventional method of manufacturing a semiconductor device (Part 1).

[0044] Fig. 22 This is a cross-sectional view showing the filling of the sealing resin in the conventional method of manufacturing a semiconductor device (part 2).

[0045] Fig.23 This is a cross-sectional view showing the filling of the sealing resin in the conventional method of manufacturing a semiconductor device (Part 3).

[0046] Fig.24 This is a cross-sectional view showing the filling of the sealing resin in the conventional method of manufacturing a semiconductor device (Part 4).

[0047] Fig.25 This is a cross-sectional view showing the filling of the sealing resin in the conventional method of manufacturing a semiconductor device (Part 5).

[0048] Fig.26 This is a cross-sectional view showing the occurrence of warping in a conventional semiconductor device.

[0049] Fig. 27This is a cross-sectional view showing stress generated during manufacture of a conventional semiconductor device.

[0050] Fig.28 This is a cross-sectional view showing the occurrence of resin cracks during manufacture of a conventional semiconductor device.

[0051] Explanation of symbols

[0052] 1.101 Power semiconductor chips

[0053] 2. First insulating substrate

[0054] 3. First conductive plate

[0055] 4 Second conductive plate

[0056] 5. 105 laminated substrate

[0057] 6. Second insulating substrate

[0058] 7 Third conductive plate

[0059] 8 Fourth conductive plate

[0060] 9, 109 Circuit board

[0061] 10, 110 Sealing resin

[0062] 11 Wiring pins

[0063] 12 External output terminals

[0064] 13 Solder

[0065] 14 Flow rate control pin

[0066] 15, 115 gap

[0067] 16, 116 Metal Plate

[0068] 17, 117 Fixing screws

[0069] 18, 118 mold cavity

[0070] 20, 120 gate

[0071] 21, 121 Exhaust duct

[0072] 22 threaded holes

[0073] 23 Warped Platform

[0074] 24 Observation surface

[0075] 50 Semiconductor devices DETAILED DESCRIPTION

[0076] Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below.

[0077] (Implementation Method 1)

[0078] First, the problems of conventional semiconductor devices are described. Conventional semiconductor devices have a structure in which semiconductor chips 101, aluminum wire wiring, lead frame wiring, etc. mounted on a laminate substrate 105 are sealed with a sealing resin 110 by transfer molding. In particular, in recent years, with the high compactness of semiconductor devices, laminated structure modules in which a circuit substrate 109 is further provided on top of the laminate substrate 105 and part of the wiring is moved to the circuit substrate 109 are increasing.

[0079] Transfer molding is a construction method of injecting molten liquid sealing resin 110 into mold cavity 118 . Figure 21 to Figure 25 1 is a cross-sectional view showing the filling of sealing resin in a conventional method for manufacturing a semiconductor device. First, a module is produced in which a circuit substrate 109 is provided on a laminate substrate 105 on which a semiconductor chip 101 is mounted. Fig.21 As shown, the module is set with the back side facing upward in the mold cavity 118. The sealing resin 110 flows from the gate 120 to the exhaust channel 121. The exhaust channel 121 is provided to allow the air in the mold cavity to escape, and in order to exert the function of the exhaust channel 121, it is preferred that the sealing resin 110 merges in the area S1.

[0080] Then, if Fig. 22 and Fig.23 As shown in FIG. 1 , sealing resin 110 is injected into mold cavity 118 in the direction of the arrow. Since sealing resin 110 is a high-viscosity fluid, sealing resin 110 flows only a small amount in the isthmus between laminated substrate 105 and circuit substrate 109 compared to between circuit substrate 109 and mold cavity 118, so a flow speed difference occurs above and below circuit substrate 109. Therefore, as shown in FIG. Fig.24 As shown in FIG. 1 , the sealing resin 110 merges at a location other than the region S1. In this case, the sealing resin 110 merges at a region S2 away from the exhaust passage 121, and the air cannot escape from the exhaust passage 121, resulting in the generation of the gap 115. Fig.25 As shown in FIG. 1 , if a void 115 is generated near the semiconductor chip 101, there is a problem that the semiconductor device becomes defective due to the void 115. Specifically, the semiconductor device becomes defective in strength, insulation, etc.

[0081] In the prior art, it is difficult to control the flow rate of resin. In particular, in the case of the laminated structure modules that have been increasing in recent years, the resin needs to flow to the isthmus between two substrates, which has caused a problem of high difficulty in adjusting the flow rate.

[0082] Hereinafter, a semiconductor device according to a first embodiment that solves the above-mentioned problems will be described. Figure 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device 50 shown represents a power semiconductor module. The semiconductor device 50 comprises: a stacked substrate 5 having a stacked structure in which a first conductive plate 3 and a second conductive plate 4 are stacked on a first insulating substrate 2, and a power semiconductor chip 1 is mounted thereon; and a circuit substrate 9 having a stacked structure in which a third conductive plate 7 and a fourth conductive plate 8 are stacked on a second insulating substrate 6, and the power semiconductor chip 1 is bonded to the first conductive plate 3 by solder 13. It should be noted that in this specification, the circuit substrate 9 is disposed above the power semiconductor chip 1 (at the Figure 1 However, it may be arranged below the power semiconductor chip 1 and on the opposite side of the laminate substrate 5. Figure 1 The semiconductor device 50 and the power semiconductor chip 1 are in the form of being taken out of the mold after transfer molding. When in use, they are sometimes turned upside down and connected to a cooler (not shown), wiring (not shown), etc. In addition, in this specification, the semiconductor device 50 and the power semiconductor chip 1 are in the form of being taken out of the mold after transfer molding. Figure 1 The bottom of the paper is indicated in FIG. 5 , and the bottom of the semiconductor device 50 and the power semiconductor chip 1 is Figure 1 The middle refers to the top on the paper.

[0083] The first conductive plate 3 and the second conductive plate 4 are, for example, copper (Cu) plates, and the first insulating substrate 2 is a ceramic insulating substrate. In addition, the third conductive plate 7 and the fourth conductive plate 8 are, for example, metal patterns, and the second insulating substrate 6 is an epoxy substrate. The circuit substrate 9 is provided with wiring between the power semiconductor chips 1 and wiring between the power semiconductor chip 1 and the external output terminal 12. A through hole is opened in the circuit substrate 9, and a wiring pin 11 of nickel (Ni) / Cu for wiring is inserted into the through hole using a pin terminal insertion tool, and the wiring pin 11 is connected to the power semiconductor chip 1 using solder 13 to perform wiring. These components are transfer-sealed by a sealing resin 10, for example, an epoxy resin with a Tg (glass transition temperature) of 200°C at a mold temperature of 175°C.

[0084] The semiconductor device 50 of the first embodiment is not limited to the pin structure in which the laminated substrate 5 and the circuit substrate 9 are wired using the wiring pins 11, and the resin flow path control effect of the present invention shown below can be obtained as long as the structure has two layers of the laminated substrate 5 and the circuit substrate 9. For example, it may be a lead frame structure or a wire wiring component in which the electrical connection between the laminated substrate 5 and the circuit substrate 9 is wired using a Cu plate and / or block instead of the wiring pins 11.

[0085] The power semiconductor chip 1 is a power chip such as an IGBT (Insulated Gate Bipolar Transistor) or a diode chip, and can be a silicon (Si) device, or a wide bandgap semiconductor device such as a silicon carbide (SiC) device, a gallium nitride (GaN) device, a diamond device, or a zinc oxide (ZnO) device. In addition, these devices can also be used in combination. For example, a hybrid module using Si-IGBT and SiC-SBD can be used. The number of power semiconductor chips 1 can be one or more.

[0086] The laminated substrate 5 can be composed of a first insulating substrate 2, a first conductive plate 3 formed on one main surface of the first insulating substrate 2, and a second conductive plate 4 formed on the other main surface of the first insulating substrate 2. As the first insulating substrate 2, a material with excellent electrical insulation and thermal conductivity can be used. As the material of the first insulating substrate 2, for example, Al2O3, AlN, SiN, etc. can be listed, and it can also be a thermosetting resin such as epoxy resin. In particular, in high-voltage applications, it is preferred to have a material that takes into account both electrical insulation and thermal conductivity. AlN and SiN can be used, but are not limited to these. As the first conductive plate 3 and the second conductive plate 4, metal materials such as Cu and Al with excellent processability can be used. In addition, the first conductive plate 3 and the second conductive plate 4 can also be Cu and Al that have been treated with Ni plating or the like for the purpose of rust prevention. As a method for arranging the first conductive plate 3 and the second conductive plate 4 on the first insulating substrate 2, a direct copper bonding method or an active metal brazing method can be listed. In addition, the power semiconductor chip 1 is mounted on the first conductive plate 3 by being bonded with a bonding material such as solder 13 .

[0087] The transfer molded sealing resin 10 includes a thermosetting resin and an inorganic filler contained in the thermosetting resin. The thermosetting resin, for example, includes at least one selected from the group including epoxy resin, phenolic resin, and melamine resin as a main component. The thermosetting resin preferably includes epoxy resin as a main component. In addition, a highly insulating and highly thermally conductive inorganic material is used as the inorganic filler. The inorganic material, for example, includes at least one selected from the group including aluminum oxide, aluminum nitride, silicon nitride, and boron nitride as a main component. The inorganic filler preferably includes silicon oxide as a main component. By using silicon oxide, it also acts as a release agent. In addition, high flame retardancy can be maintained without mixing halogen-based, antimony-based, metal hydroxide-based, and other flame retardants. The inorganic filler is more than 70 vol% and less than 90 vol% of the entire sealing raw material.

[0088] The shear viscosity of the sealing resin 10 used for transfer molding when melted is, for example, 10 to 4000 Pa·s (shear rate 0.06 (1 / s)), preferably about 100 to 2000 Pa·s.

[0089] In addition, in addition to thermosetting resin and inorganic filler, sealing resin 10 can also arbitrarily and selectively include curing agent, curing accelerator, and additive. As curing agent, as long as it can react and solidify with thermosetting resin main agent, preferably epoxy resin main agent, it is not particularly limited, and it is preferred to use anhydride curing agent. As anhydride curing agent, for example, aromatic anhydride can be listed, specifically, phthalic anhydride, pyromellitic anhydride, trimellitic anhydride, etc. can be listed. Or, cyclic aliphatic anhydride, specifically tetrahydrophthalic anhydride, methyltetrahydrophthalic anhydride, hexahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylnadic anhydride, etc. can be listed, or aliphatic anhydride, specifically succinic anhydride, polyadipic anhydride, polysebacic anhydride, polyazepam anhydride, etc. can be listed.

[0090] As a curing accelerator, imidazole or its derivatives, tertiary amines, boric acid esters, Lewis acids, organic metal compounds, organic acid metal salts, etc. can be appropriately mixed. As additives, for example, flame retardants, pigments for coloring resins, plasticizers for improving crack resistance, and silicone elastomers can be listed, but are not limited to these. These arbitrary components and their addition amounts can be appropriately determined by those skilled in the art according to the specifications required by the semiconductor device 50 and the sealing resin 10.

[0091] Figure 2 FIG. 1 is a top view showing the structure of the semiconductor device according to the first embodiment, and is a view viewed from the circuit substrate side. Figure 2As shown, in the first embodiment, in order to adjust the resin confluence position, flow rate control pins 14 are provided in the through holes additionally opened at the end A and the end B of the circuit substrate 9. A plurality of flow rate control pins 14 are provided on the surface opposite to the laminated substrate 5 side (end A) near the edge E1 of the circuit substrate 9 which is located closest to the surface where the gate 20 of the mold cavity 18 is located, and are arranged in parallel perpendicularly to the flow direction of the sealing resin 10 (hereinafter referred to as the resin flow direction). In addition, the flow rate control pins 14 can also be similarly arranged at the end B of the edge (edge ​​E2) located opposite to the edge E1. It should be noted that since the flow rate control pins 14 in the present invention are directly mounted on the semiconductor device 50, they continue to remain in the semiconductor device 50 after transfer molding. It should be noted that, Figure 2 , etc. are conceptual diagrams showing the flow rate control pin 14, and description of the external output terminal 12 and the like is omitted.

[0092] In addition, the material of the flow rate control pin 14 can utilize resin or metal. In particular, when using a flow rate control pin 14 having a lower elastic modulus than the sealing resin 10, the effect of improving the resin fracture resistance due to the stress relaxation effect can be obtained. Since it is necessary to be put into a high-temperature mold, when using a resin flow rate control pin 14, in order to prevent the elastic modulus from decreasing due to glass transition and thus losing the flow rate control function, it is necessary to use a resin whose glass transition temperature Tg is at least 15°C higher than the mold temperature during transfer molding. When using a metal flow rate control pin 14, a Ni / Cu pin can be used in the same manner as the wiring pin 11. It should be noted that the flow rate control pin 14 is arranged toward the side opposite to the laminated substrate 5 and is approximately perpendicular to the circuit substrate 9. In other words, the flow rate control pin 14 is arranged at the bottom (between the circuit substrate 9 and the mold cavity 18) of the circuit substrate 9. Figure 4 between the lower surfaces).

[0093] Figure 3 1 is a side view showing the structure of the semiconductor device of the first embodiment. The end of the circuit substrate 9 includes an end A and an end B. The end A is an end on the gate 20 side of the circuit substrate 9, more specifically, an area within 30% of the length of the circuit substrate 9 starting from the side E1 on the gate 20 side of the circuit substrate 9, and the end B is an end on the opposite side of the circuit substrate 9 to the gate 20 side, more specifically, an area within 30% of the length of the circuit substrate 9 starting from the side E2 on the opposite side of the circuit substrate 9 to the gate 20 (see FIG. 1 ). Figure 2 The resin flow direction refers to the direction from the side E1 on the gate 20 side toward the side E2 on the opposite side to the gate 20 ( Figure 5 , Figure 6 It should be noted that the same also applies to the case where the gate 20 and the exhaust channel 21 are located at positions offset in the diagonal direction of the mold in a plan view.

[0094] In the manufacturing method of the semiconductor device of the first embodiment, first, a power semiconductor chip 1 and the like are mounted on the laminated substrate 5, and a flow rate control pin 14 is installed on the circuit substrate 9. When the flow rate control pin 14 is a resin, the flow rate control pin 14 is installed on the circuit substrate 9, for example, by laser welding and / or adhesive to the metal pattern and / or glass epoxy substrate of the circuit substrate 9. In addition, the flow rate control pin 14 can also be inserted into a through hole or a recess in the circuit substrate 9. When the flow rate control pin 14 is a metal, for example, it can be carried out by welding and / or inserting it into a through hole or a recess opened in the circuit substrate 9, or an adhesive can be used. At this time, from the aspect of adhesion, it is preferred that the adhesive and the sealing resin 10 are of the same type. Next, a module (module before sealing) is prepared by joining the circuit substrate 9 to the laminated substrate 5 using the wiring pin 11. The process so far is referred to as the first process. Figures 4 to 8 1 is a cross-sectional view showing the filling of the sealing resin in the method for manufacturing the semiconductor device according to the first embodiment. Figures 4 to 8 The description of the wiring pins 11 and the like is omitted.

[0095] Then, if Figure 4 As shown in FIG. 1 , the module is placed in the mold cavity (molding mold) 18 with the back side facing upward (second step). Figure 5 and Figure 6 As shown, the sealing resin 10 is injected into the mold cavity 18 in the direction of the arrow (third process). The sealing resin 10 flows from the gate (injection gate) 20 in the direction of the exhaust channel 21. Since the sealing resin 10 is a high-viscosity fluid, the sealing resin 10 flows only a small amount in the isthmus between the laminated substrate 5 and the circuit substrate 9 compared to between the circuit substrate 9 and the mold cavity 18, so a flow speed difference occurs above and below the circuit substrate 9. However, in the first embodiment, a flow rate control pin 14 is provided between the circuit substrate 9 and the mold cavity 18 (bottom). Therefore, since the flow rate control pin 14 generates resistance when the sealing resin 10 flows through the flow rate control pin 14, the flow rate of the sealing resin 10 is reduced. As a result, the sealing resin 10 that is not easy to enter between the circuit substrate 9 and the mold cavity 18 will flow between the laminated substrate 5 and the circuit substrate 9 instead, so that the flow rate of the sealing resin 10 above and below the circuit substrate can be made consistent.

[0096] Therefore, if Figure 7 As shown, the entrained air can be released by making the sealing resin 10 merge near the exhaust passage 21 S. Figure 8As shown, the generation of voids can be reduced when filling the sealing resin 10. In addition, by appropriately disposing the flow rate control pin 14 according to the product shape, the resin flow rate can be controlled, for example, the confluence point of the sealing resin 10 can be moved to a location with a low risk of voids.

[0097] As described above, in the first embodiment, the flow rate control pins are arranged in parallel at the end portions in a manner perpendicular to the flow direction of the resin, so that the resin flows slowly while being subjected to resistance from the flow rate control pins when passing between the flow rate control pins. Thus, the confluence position of the resin can be adjusted, the generation of voids can be reduced, or the location where the voids are generated can be moved to a location where the risk caused by the voids is low.

[0098] (Implementation Method 2)

[0099] First, problems of conventional semiconductor devices will be described. Fig.26 FIG. 1 is a cross-sectional view showing warpage in a conventional semiconductor device. In a conventional semiconductor device, warpage may occur due to curing shrinkage of the sealing resin 110 after transfer molding. Fig.26 As shown, warpage of height I occurs between the upper portion of the laminate substrate 105 and the sealing resin 110 . Fig. 27 1 is a cross-sectional view showing stress generated during the manufacture of a conventional semiconductor device. When the semiconductor device is mounted on a metal plate 116 such as a cooler and fixed with fixing screws 117, tensile stress is generated at a portion D1 due to the screw fastening. Fig.28 FIG. 1 is a cross-sectional view showing the occurrence of resin cracks in the manufacture of a conventional semiconductor device. Fig.28 As shown, there is a problem that cracks occur in the resin at the portion C1, causing failure of the semiconductor device.

[0100] Hereinafter, a semiconductor device according to a second embodiment that solves the above-mentioned problems will be described. Fig. 9 2 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. Fig. 9 As shown, the semiconductor device 50 of the second embodiment differs from the semiconductor device 50 of the first embodiment in that a plurality of flow rate control pins 14 are also arranged in parallel perpendicular to the resin flow direction at a middle point (middle C) between end A and end B of the circuit substrate 9.

[0101] Fig.10 This is a top view showing the structure of the semiconductor device of the second embodiment. End A and end B are the same as those of the first embodiment. The middle C refers to an area starting from the side C1 that divides the circuit substrate 9 in half perpendicular to the resin flow direction and each area is 15% (30% in total) of the length of the circuit substrate 9.

[0102] Fig.11 and Fig.12 1 is a cross-sectional view showing stress relaxation in the manufacture of the semiconductor device of the second embodiment. After transfer molding, warpage caused by the curing shrinkage of the sealing resin 10 occurs. Fig.11 As shown in FIG. 1 , a warpage of height I occurs at the upper portion of the laminate substrate 5 and the sealing resin 10. Fig.12 As shown in FIG. 1 , if the semiconductor device 50 is mounted on the metal plate 16 and fixed by the fixing screw 17, tensile stress is generated at the D1 position due to the screw fastening. In the second embodiment, since the flow rate control pin 14 is arranged at the D1 position where tensile stress is generated, the flow rate control pin 14 can alleviate the stress generated by the screw fastening, and can avoid the resin from cracking at the C1 position, thereby improving the fault resistance. In addition, it is estimated that the rigidity of the power semiconductor module is also improved.

[0103] Here, in particular, by selecting the material of the flow rate control pin 14 to be a resin with an elastic modulus lower than that of the sealing resin 10 and well stretched, the internal stress generated in the sealing resin 10 can be alleviated, the resin cracking and damage can be avoided, and the fault resistance can be improved. In the case where the material of the flow rate control pin 14 is not resin but metal, the deformation suppression effect brought about by the high rigidity of the metal is also exerted, and the resin cracking and damage resistance can be avoided and the damage resistance can be improved. In the case where the material of the flow rate control pin 14 is metal and resin, the resin flow rate control pin 14 has a higher effect of improving the resin cracking and damage resistance. It should be noted that if the flow rate control pin 14 is arranged in the middle C, it also has the effect of reducing the gap generated near the power semiconductor chip 1.

[0104] As described above, in the second embodiment, a plurality of flow rate control pins are also provided at the middle position of the end of the circuit substrate, thereby alleviating the stress caused by the increase in rigidity or the tightening of screws, thereby improving the strength of the module to cope with deformation, avoiding resin cracking, and improving fault resistance.

[0105] (Example)

[0106] Hereinafter, examples of the height, shape, and arrangement of the flow rate control pin 14 in the first and second embodiments will be described. First, a method for evaluating the effect of the flow rate control pin 14 will be described. As an evaluation method, an insulation breakdown test is performed for gap evaluation, and a reliability test and a tightening test are performed for the strength of the module to cope with deformation.

[0107] (Gap Evaluation)

[0108] Figure 13 to Figure 152 is a cross-sectional view showing a method for evaluating voids in an embodiment. For voids 15, ultrasonic flaw detection (SAT: Scanning Acoustic Tomography) and transmission type X-ray image inspection are performed on the sample filled with sealing resin 10, and the SAT image or X-ray image at the height (observation surface 24) of the stacked substrate 5 and the power semiconductor chip 1 can be observed to evaluate the position where the void occurs.

[0109] The gap 15 is preferably located as far away as possible from the power semiconductor chip 1 to which a high voltage is applied. Therefore, the gap evaluation is performed at the gap position. In determining the gap position, the distance L1 (hereinafter referred to as the chip-gap distance L1) from the closest point of the gap 15 to the closest point to the terminal is used as a reference, and the gap is evaluated (refer to Fig.14 ), the edge being the edge that is located farthest from the gate 20 and through which the sealing resin 10 passes last.

[0110] As for the quality standard, if the chip-gap distance L1 is greater than 0.0mm (if a gap appears on the outside of the terminal chip), the insulation withstand voltage is satisfied and it is therefore considered a good product. If it is less than 0.0mm (a gap appears on the terminal chip), the insulation withstand voltage is not satisfied and it is therefore considered a bad product. In addition, in order to further improve the insulation withstand voltage, it is preferred that the chip-gap distance L1 is greater than the distance L2 between the edge of the terminal chip located farthest from the gate 20 and the edge of the laminated substrate 5 located farthest from the gate 20. The distance L2 is, for example, 7.5mm. It should be noted that regarding the distinguishing use of SAT images and X-ray images, in principle, the gap 15 on the laminated substrate 5 cannot be observed in the X-ray image, and the gap 15 outside the laminated substrate 5 cannot be observed in the SAT image. Therefore, only when there is no gap 15 in the SAT image, the presence and position of the gap based on the X-ray transmission image is evaluated separately.

[0111] (Dielectric breakdown test)

[0112] The effect of the gap 15 on the quality is evaluated by the insulation breakdown test between the external output terminal 12 on the front side of the semiconductor device 50 and the laminated substrate 5. The voltage is increased by 0.2 kV intervals to find the upper limit of the voltage that does not cause insulation breakdown even if applied for 60 seconds. For the quality standard, if the average withstand voltage of 5 units is 8.0 kV or more, it is considered to be qualified.

[0113] (Evaluation of the clearance inside the flow control pin)

[0114] Fig.16This is a cross-sectional view showing the evaluation of the gap on the inner side of the flow rate control pin in the embodiment. Regarding the gap 15 generated on the inner side of the flow rate control pin 14, SAT was performed on the sample filled with the sealing resin 10, and the SAT image at the height (observation surface 24) at which the circuit substrate 9 can be photographed was observed to evaluate the position where the gap was generated.

[0115] (Module's strength against deformation)

[0116] The module's resistance to deformation is evaluated by performing a fastening test on a platform with warping. Fig.17 2 is a cross-sectional view showing a warped platform in a tightening test in an embodiment. The warped platform 23 is a platform with variously changed values ​​of the initial warp I1 between the threaded holes 22. The initial warp I1 refers to the height to the top of the warped platform when the threaded hole 22 is used as a reference. Fig.18 2 is a cross-sectional view showing the warpage of the module in the embodiment. The warpage I2 of the module is the height to the top of the warpage surface of the module when the screw hole 22 is used as a reference.

[0117] Fig.19 2 is a cross-sectional view showing a tightening test of a semiconductor device in an embodiment. In the tightening test, by tightening the module to the warped platform 23, a larger deformation is imparted to the module than to a flat platform, and tensile stress is generated at the position D1 due to screw tightening. The tightening test is a strength test in which the modules are replaced one by one to the warped platform 23 with a large initial warp I1 and observation is performed until cracks are first generated in the module.

[0118] The evaluation index is the total deformation calculated from the sum of the module warpage I2 + the initial warpage I1 of the warped platform 23 between the threaded holes 22. The initial warpage I1 of the warped platform 23 is prepared in units of 20μm within the range of 0μm to 300μm. The appearance inspection is used to evaluate whether cracks are generated in the center of the module after the screws are tightened with a torque of 3.5Nm and held for 10 seconds. The total deformation when cracks are generated is the tightening failure deformation.

[0119] (Reliability test)

[0120] The effect of deformation of the semiconductor device 50 on the quality is measured through a power cycle (P / C) test. The conditions of power-on operation at 75-150°C (ΔTvj75°C) for 1 second (the current value is set in such a way that it becomes 150°C) and resting for 9-15 seconds (the current value is set in such a way that it becomes 75°C) are considered as one cycle. The number of cycles until the current or voltage changes by more than 25% from the predetermined value is taken as the P / C life. For the quality standard, if the average number of destructive cycles of the power cycle (P / C) test of five units is more than 1000kcyc, it is considered qualified.

[0121] (Experimental Example 1)

[0122] In Experimental Example 1, the effect of the position of the flow rate control pin 14 was confirmed. Here, as Comparative Example 1, a sample without the flow rate control pin 14 (conventional structure) was prepared, and as Examples 1-1 to 1-6, samples were prepared in which the flow rate control pin 14 of a Ni / Cu pin was added to one of the end A, end B, and middle C, or the flow rate control pin 14 of a Ni / Cu pin was added to a portion formed by combining the end A, end B, and middle C, and the effect brought about by the position of the flow rate control pin 14 was evaluated. In Examples 1-1 to 1-6, the flow rate control pin 14 was positioned 1 mm away from the end of the circuit substrate 9 at the end A and the end B, and was positioned in the middle of the length direction of the circuit substrate 9 at the middle C, and the distance from the surface of the circuit substrate 9 to the surface of the product was set to L = 2.5 mm, and in contrast, the height of the flow rate control pin 14 was set to h = 1.65 mm (for L and h, refer to Figure 1 , Figure 3 ). In addition, for a module width of W = 26.0 mm, cylindrical flow rate control pins 14 (number n = 22) with a diameter of d = 0.4 mm are arranged in parallel on the circuit board 9 at intervals of 0.5 mm (for W and d, refer to Figure 3 ). Thus, the resin flow cross-sectional area LW on the circuit board 9 = 2.5 mm × 26.0 mm = 65.0 mm 2 The area projected by the velocity control pin 14 is ndh = 22 × 0.4 mm × 1.65 mm = 14.5 mm 2 , the projection density (the ratio of the area occupied by the pin) is ndh / LW=14.5mm 2 / 65.0mm 2 =22.3%.

[0123] Table 1 shows the results of Experimental Example 1.

[0124]

Table 1

[0125]

[0126] According to Table 1, in Comparative Example 1, the chip-gap distance is in the negative direction, the dielectric breakdown voltage is low, and dielectric breakdown is likely to occur. Thus, in Comparative Example 1 without the flow rate control pin 14, the gap appears directly above the power semiconductor chip 1, and the dielectric breakdown withstand voltage does not reach the qualified standard.

[0127] On the other hand, in all the cases of Examples 1-1 to 1-6, the chip-gap distance was 0.0 mm or more, and the insulation withstand voltage was 8 kV or more, which was qualified. In the case where the flow rate control pin 14 was set only at one place (Examples 1-1 to 1-3), the gap position control effect became higher in the order of end A> middle C> end B. The closer the setting position of the flow rate control pin 14 is to the gate 20 where the resin flows in, the higher the effect of reducing the flow rate of the resin after passing through the flow rate control pin 14.

[0128] It can be seen that the gap position control effect when the setting positions of the flow rate control pin 14 are combined in two or more places (Examples 1-4 to 1-6) is A+B+C>A+C>A+B, and the more the flow rate control pin 14 is set, the higher the effect is. If the setting positions are the same, the effect is high when it is set near the gate 20. That is, it is preferred to configure the flow rate control pin 14 at a position including the end A. In particular, the gap position control effect in A+B+C is significant, and no gap is detected outside the laminated substrate 5. This is because the resin confluence position is successfully moved to the vicinity of the mold exhaust duct 21 due to the proper control of the resin flow rate, and the air involved in the gap can be properly discharged to the outside of the module. It should be noted that, except for Examples 1-6, the gap size is about 300μm in all examples, and it is confirmed that the location of the gap can be controlled by the flow rate control pin 14, not the size. The insulation breakdown test results also showed the same trend as the chip-gap distance. Comparative Example 1 failed but all the examples passed, confirming the improvement of insulation withstand voltage. In addition, it can be seen that in all the examples, there is an effect in the fastening test and P / C test. It is presumed that this is because the rigidity of the module is improved by the flow rate control pin 14 (metal), so the deformation suppression effect is achieved (reducing resin cracking) and the reliability (P / C life) is improved.

[0129] (Experimental Example 2)

[0130] In Experimental Example 2, the effect of the interval of the flow rate control pins 14 was confirmed. In Experimental Example 2, the length h and the number n of the flow rate control pins 14 were changed, and the flow path adjustment effect brought about by the density ndh / LW projected by the flow rate control pins 14 in the resin flow cross-sectional area LW was evaluated. As for the flow rate control pins 14, cylindrical Ni / Cu pins with a diameter of d=0.4 mm were used in the same manner as in Experimental Example 1. The flow rate control pins 14 were only provided at the end A, and the length, number and interval of the flow rate control pins 14 were manufactured under the conditions shown in Table 2. Evaluation was performed using the chip-gap distance.

[0131] The results of Experimental Example 2 are shown in Table 2. L and W in Table 2 are the distance from the surface of the circuit board 9 to the surface of the product and the module width, similarly to Experimental Example 1. It should be noted that the length h of the pin is expressed with L as a reference.

[0132]

Table 2

[0133]

[0134]

[0135] ※Minor cosmetic defects

[0136] According to Table 2 above, as the projection density ndh / LW of the flow rate control pin 14 increases, the chip-gap distance increases, and when the projection density is above 10%, the chip-gap distance becomes above +1mm, and the insulation withstand voltage is also good. If the projection density is set to above 22%, the chip-gap distance becomes above +4.5mm, which is particularly good. In addition, no gaps are found when the projection density is above 39.6%. It can be seen that the greater the projection density of the flow rate control pin 14, the higher the control effect of the resin flow rate. However, if the projection density becomes above 48%, although there are no gaps near the power semiconductor chip 1, the resin flow is excessively blocked by the flow rate control pin 14, so sometimes there will be slight resin unfilled areas (appearance defects) that are not practical obstacles. Above, the projection density is preferably above 10% and less than 48%, more preferably above 22%, and further preferably above 39.6% and less than 48%.

[0137] (Experimental Example 3)

[0138] In Experimental Example 3, the effect of the material of the flow rate control pin 14 was confirmed. In Experimental Example 3, an experiment was conducted on the case where a resin with a lower elastic modulus than the elastic modulus of the sealing resin 10 was used as the material of the flow rate control pin 14 (resin pin). The cured sealing resin 10 used in Experimental Examples 1 and 2 was an epoxy resin (Sumitomo Bakelite G720E) with a high Tg of 200°C, the mold temperature during transfer sealing was 175°C, and the elastic modulus after curing was about 16 GPa at 25°C. In Experimental Example 3, an example was evaluated in which a resin of the same epoxy system with a Tg of 200°C as the sealing resin 10 and whose elastic modulus was reduced to 6 GPa by removing filler components from the composition was used as the material of the flow rate control pin 14. It should be noted that the shape of the flow rate control pin 14 was a circle with a diameter of 0.4 mm as in Experimental Examples 1 and 2, and the density of the flow rate control pin 14 was fixed to 22 pins with a projection density of 22.3% with a pin interval of 0.5 mm as in Experimental Example 1.

[0139] Table 3 shows the results of Experimental Example 3.

[0140]

Table 3

[0141]

[0142] According to Table 3 above, the chip-gap distance and insulation breakdown test results are roughly equivalent to those of Experimental Example 1. It can be seen that the gap position adjustment effect brought by the flow rate control pin 14 does not change due to the material of the flow rate control pin 14. On the other hand, in the tightening test and P / C test results, improvements were found compared with Comparative Example 1. It is believed that this is because the stress relaxation effect caused by the configuration of a low-elastic resin pin that is easy to stretch on the upper part of the module where the tensile stress is concentrated by screw tightening works. In particular, when a low-elastic resin pin is configured in the center of the module (middle C) where stress is easily concentrated (Examples 3-1 to 3-6), the improvement in the damage resistance is significant. If Example 1-1 in which the flow rate control pin 14 is only configured at the end A is compared with Example 3-1, the tightening damage deformation and P / C life of Example 3-1 using the resin pin are significantly improved. It can be said that although both metal pins and resin pins have the effect of reducing resin cracking, the effect of the resin pin is higher.

[0143] (Experimental Example 4)

[0144] In Experimental Example 4, the effects of the shapes of the flow rate control pins 14 in Examples 4-1 to 4-4 were confirmed. As in Experimental Example 1-1, a Ni / Cu pin was arranged at the end A, and the shape of the flow rate control pin 14 (cross-sectional shape observed from the top surface) was prepared in addition to a cylindrical shape as in Experimental Examples 1 to 3, an elliptical cylinder and a regular quadrangular prism. Fig. 20 : is a cross-sectional view showing the shape of the flow rate control pin of the semiconductor device in the embodiment. It should be noted that the regular quadrangular prism is provided with a case where one of the diagonals of the square is perpendicular to the resin flow direction, and a case where one of the sides of the square is perpendicular to the resin flow direction. The length h of the flow rate control pin 14 is 1.65 mm, and in order to make the projection density uniform at 22.3%, the size of the flow rate control pin 14 shown in Table 4 is used in such a way that the projection of the part perpendicular to the resin flow direction becomes 0.4 mm. It should be noted that for the elliptical column, both have a uniform flattening rate of 50%. The elliptical column is provided with a case where the short axis is perpendicular to the resin flow direction, and a case where the long axis is perpendicular to the resin flow direction.

[0145] The results of Experimental Example 4 are shown in Table 4. In Table 4, verticality is represented by ⊥. For example, the resin flow direction of one of the diagonals ⊥ is a case where one of the diagonals of a square is perpendicular to the resin flow direction.

[0146]

Table 4

[0147]

[0148]

[0149] According to Table 4, the chip-gap distances were found to be substantially the same in all the examples. It can be seen that the resin flow rate control effect is constant regardless of the shape of the flow rate control pin 14. However, if the SAT image taken on the circuit board 9 is observed, it can be seen that the gap 15 appears on the inner side of the flow rate control pin 14 (see FIG. Fig.16 ). This is believed to be due to the confluence of the resin flow surface passing through the velocity control pin 14, which draws in air and causes air accumulation on the back side of the velocity control pin 14. The gap on the inner side of the velocity control pin 14 may impair reliability, so it is desirable that the gap be small. The size of the gap on the inner side of the velocity control pin 14 varies depending on the shape and / or installation direction of the velocity control pin 14, with cylinders and elliptical cylinders being less than regular quadrangular prisms, with elliptical cylinders being the most preferred (short axis ⊥ resin flow direction), and regular quadrangular prisms being the least preferred (sides ⊥ resin flow direction) (refer to Fig.17 ). Although the insulation breakdown voltage also roughly shows a correlation with the size of the gap on the inner side of the flow rate control pin 14, even if a new gap appears on the inner side of the flow rate control pin 14, the insulation breakdown voltage is improved compared with the insulation breakdown voltage of the comparative example, and it can be confirmed that no matter what the shape of the flow rate control pin 14 is, it is effective in improving the module performance.

[0150] As described above, the present invention can be variously modified without departing from the gist of the present invention. In the above-mentioned embodiments, for example, the size of each part, the impurity concentration, etc. are variously set according to the required specifications.

[0151] Industrial Applicability

[0152] As described above, the semiconductor device and the method for manufacturing the semiconductor device of the present invention are useful for power semiconductor modules used in power conversion devices such as inverters, power supply devices for various industrial machines, or ignition devices for automobiles.

Claims

1. A semiconductor device, characterized in that: have: a laminate substrate on which a semiconductor chip is mounted; a circuit substrate provided with wiring between the semiconductor chips and wiring between the semiconductor chips and external output terminals; as well as a sealing resin that seals the laminate substrate and the circuit substrate, The circuit substrate is provided with a flow rate control pin on a side opposite to the laminate substrate side.

2. The semiconductor device according to claim 1, wherein: The flow rate control pin is arranged at an end portion of the circuit substrate.

3. The semiconductor device according to claim 1, wherein: The flow rate control pin is disposed at the end portion of the circuit substrate and at a middle portion between the end portions.

4. The semiconductor device according to claim 1, wherein: The flow rate control pin is made of a resin having an elastic modulus lower than that of the sealing resin.

5. A method for manufacturing a semiconductor device, characterized in that: Transfer molding using a molding die, The method for manufacturing a semiconductor device comprises: A first step is to form a module, wherein the module has a laminate substrate on which semiconductor chips are mounted, and a circuit substrate provided with wiring between the semiconductor chips and wiring between the semiconductor chips and external output terminals; A second step is to install the module in the molding die; and The third step is to inject a sealing resin from the injection gate of the molding die. On the circuit substrate, flow rate control pins are arranged in parallel perpendicularly to the flow direction of the sealing resin on the side opposite to the laminated substrate side.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The flow rate control pin is arranged at an end portion of the circuit substrate on the injection gate side.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The flow rate control pin is arranged at an end portion of the circuit substrate on the injection gate side and an end portion on the side opposite to the gate side.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: The flow rate control pin is arranged at an end portion of the circuit substrate on the injection gate side, an end portion on the side opposite to the gate side, and a middle portion between the end portions.

9. The method for manufacturing a semiconductor device according to claim 5, wherein: When the distance from the surface of the circuit substrate to the surface of the molding die is set to L, the width of the molding die perpendicular to the flow direction of the sealing resin is set to W, the number of the flow control pins is set to n, the width of the flow control pin when projected in the flow direction of the sealing resin is set to d, and the height of the flow control pin is set to h, the projection density ndh / LW of the flow blocked by the flow control pin relative to the cross-sectional area LW of the flow path of the sealing resin is greater than 10% and less than 48%.

10. The method for manufacturing a semiconductor device according to claim 5, wherein: The flow rate control pin is made of a resin having an elastic modulus lower than that of the sealing resin.

11. The method for manufacturing a semiconductor device according to claim 5, wherein: The cross-sectional shape of the flow rate control pin is an ellipse whose major axis is located on the flow direction side of the sealing resin.

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