Semiconductor structure and its preparation method, packaging structure

Abstract

Embodiments of the present disclosure relate to the field of packaging and provide a semiconductor structure, a preparation method thereof, and a packaging structure. The semiconductor structure includes a substrate having a first surface and a second surface relative to each other, the substrate including an array area, wherein a plurality of grooves extending from the first surface to the second surface are formed in the array area; a first electrode plate is located on the first surface of the substrate and extends into the plurality of grooves; a first dielectric layer conformally covers the surface of the first electrode plate; a second electrode plate conformally covers the surface of the first dielectric layer, and the second electrode plate fills the plurality of grooves, and the second electrode plate has a horizontal surface; a second dielectric layer covers the surface of the second electrode plate; and a third electrode plate covers the surface of the dielectric layer of the second electrode plate.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of packaging, and in particular to a semiconductor structure, a preparation method thereof, and a packaging structure. Background Art

[0002] As chip integration continues to increase, the performance of capacitors also needs to be improved. The use of deep trench capacitors (DTCs) to replace traditional chip capacitors has become a general trend. Because deep trench capacitors still have high stability and low leakage current under high bias voltage, they are widely used in antenna matching, RF filtering, IC (Integrated Circuit) decoupling and related industrial fields.

[0003] However, the provision of deep trench capacitors does not fully utilize the surface area of ​​the substrate, resulting in a low integration density and low capacitance of the resulting semiconductor packaging structure, and the capacitance performance still needs to be improved. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, and a packaging structure, which are at least beneficial to improving the integration density and capacitor area of ​​the semiconductor packaging structure.

[0005] According to some embodiments of the present disclosure, on one hand, embodiments of the present disclosure provide a semiconductor structure, comprising: a substrate, the substrate having a first surface and a second surface relative to each other, the substrate including an array area, and a plurality of grooves extending from the first surface to the second surface being formed in the array area; a first electrode plate, located on the first surface of the substrate and extending into the plurality of grooves; a first dielectric layer, conformally covering the surface of the first electrode plate; a second electrode plate, conformally covering the surface of the first dielectric layer, and the second electrode plate fills the plurality of grooves, the second electrode plate having a horizontal surface; a second dielectric layer, covering the surface of the second electrode plate; and a third electrode plate, covering the surface of the second dielectric layer.

[0006] In some embodiments, the substrate further includes a first edge area and a second edge area adjacent to the array area, respectively, wherein the first electrode plate is continuously located in the first edge area, the array area, and the second edge area; the first dielectric layer is continuously located in the first edge area, the array area, and the second edge area; the second electrode plate is continuously located in the first edge area and the array area; the second dielectric layer is continuously located in the first edge area, the array area, and the second edge area, wherein the second dielectric layer covers the surface of the second electrode plate and the first dielectric layer to wrap the second electrode plate; and the third electrode plate is continuously located in the array area and the second edge area.

[0007] In some embodiments, the semiconductor structure further includes: an isolation structure continuously located in the first edge region, the array region, and the second edge region, the isolation structure covering the surface of the second dielectric layer and the third electrode plate; a plurality of first contact plugs located in the first edge region, the plurality of first contact plugs penetrating the isolation structure and contacting the second electrode plate; a plurality of second contact plugs located in the second edge region, the plurality of second contact plugs penetrating the isolation structure, the third electrode plate, the second dielectric layer, and the first dielectric layer and contacting the first electrode plate.

[0008] In some embodiments, the third electrode plate is flush with a surface away from the substrate, and includes a first portion located in the second edge area and a second portion located in the array area, wherein a thickness of the first portion is greater than or equal to a thickness of the second portion.

[0009] In some embodiments, the thickness of the second dielectric layer in the second edge region is less than or equal to the thickness of the second dielectric layer in the array region.

[0010] In some embodiments, the second dielectric layer includes a stacked first film layer and a second film layer, the first film layer is located in the array region, and the second film layer is located in the first edge region, the second edge region, and the array region.

[0011] In some embodiments, the aspect ratio of the trench is greater than or equal to 30.

[0012] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a method for preparing a semiconductor structure, including: providing a substrate, the substrate having a first surface and a second surface relative to each other, the substrate including an array area, and a plurality of grooves extending from the first surface to the second surface are formed in the array area; forming a first electrode plate, located on the first surface of the substrate and extending into the plurality of grooves; forming a first dielectric layer, conformally covering the surface of the first electrode plate; forming a second electrode plate, conformally covering the surface of the first dielectric layer, and the second electrode plate fills the plurality of grooves, the second electrode plate having a horizontal surface; forming a second dielectric layer, covering the surface of the second electrode plate; forming a third electrode plate, covering the surface of the second dielectric layer.

[0013] In some embodiments, the substrate further includes a first edge region and a second edge region adjacent to the array region, respectively, the first electrode plate is continuously located in the first edge region, the array region, and the second edge region; the first dielectric layer is continuously located in the first edge region, the array region, and the second edge region; wherein the process steps for forming the second electrode plate include: forming a first conductive film on the surface of the first dielectric layer, the first conductive film being located in the first edge region, the array region, and the second edge region; patterning the first conductive film in the second edge region to form a first groove, the bottom surface of the first groove exposing the surface of the first dielectric layer, and the remaining first conductive film serving as the second electrode Plate; wherein, the process steps for forming the third electrode plate include: forming a stacked second dielectric layer and a second conductive film on the surface of the second electrode plate; patterning the second conductive film in a portion of the first edge area to form a second groove, the bottom surface of the second groove exposing the surface of the second dielectric layer, and the remaining second conductive film serving as the third electrode plate; wherein, the process steps for forming the second dielectric layer include: forming a first film layer on the surface of the first conductive film; patterning the first conductive film and the first film layer in the second edge area; forming a second film layer on the surface of the first film layer, the second film layer covering the surface of the first film layer and the surface of the first dielectric layer, the first film layer and the second film layer serving as the second dielectric layer.

[0014] In some embodiments, it also includes: forming an isolation structure continuously located in the first edge area, the array area, and the second edge area, the isolation structure covering the surface of the second dielectric layer and the third electrode plate; forming a plurality of first contact plugs located in the first edge area, the plurality of first contact plugs penetrating the isolation structure and contacting the second electrode plate; forming a plurality of second contact plugs located in the second edge area, the plurality of second contact plugs penetrating the isolation structure, the third electrode plate, the second dielectric layer, and the first dielectric layer and contacting the first electrode plate.

[0015] In some embodiments, the plurality of first contact plugs and the plurality of second contact plugs are formed in the same process step.

[0016] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a packaging structure, including: a circuit board; a packaging substrate, located on the surface of the circuit board, the first surface of the packaging substrate being electrically connected to the circuit board; a semiconductor structure as described in any of the above embodiments, located on the second surface of the packaging substrate, the semiconductor structure being electrically connected to the second surface of the packaging substrate.

[0017] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0018] In the semiconductor structure provided by the embodiment of the present disclosure, the semiconductor structure includes a first electrode plate, a second electrode plate, a third electrode plate, a first dielectric layer and a second dielectric layer. The first electrode plate, the first dielectric layer and the second electrode plate constitute a first capacitor structure, and the second electrode plate, the second dielectric layer and the third electrode plate constitute a second capacitor structure, that is, the second capacitor structure and the first capacitor structure share the second electrode plate. The first capacitor structure is a deep trench capacitor structure, and the second capacitor structure is a planar capacitor structure. The embodiment of the present disclosure effectively utilizes the area of ​​the top surface of the deep trench capacitor structure to form a planar capacitor structure, effectively increases the capacitor area, realizes the construction of a multi-faceted capacitor, improves the deep trench capacitance value, and avoids the situation where a single deep trench capacitor is difficult to meet larger capacitance requirements.

[0019] In addition, a second dielectric layer is provided to cover the side surface of the second electrode plate, a second contact plug is passed through the third electrode plate and is in electrical contact with the first electrode plate, and the first contact plug is in electrical contact with the second electrode plate. In this way, it is not necessary to etch the film layers of the second capacitor structure and the isolation structure, and electrical contact between the second contact plug and the first electrode plate can be achieved in a one-step process, thereby reducing the number of mask plates and saving the preparation cost of the semiconductor structure preparation method.

[0020] The disclosed embodiment reasonably arranges the positions and connection relationships of the first capacitor structure, the second capacitor structure, the first contact plug, and the second contact plug, thereby realizing two capacitor structures connected in parallel within a limited area, thereby increasing the capacitance of the semiconductor packaging structure, and realizing separate control of the two capacitor structures and sharing the second electrode plate with the first capacitor structure, thereby increasing the integration density of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0023] Figure 2 for Figure 1 Schematic diagram of the cross-section structure along section A1-A2;

[0024] Figures 3 to 14A schematic structural diagram of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 15 A circuit diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 16 A schematic diagram of a packaging structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] As known from the background art, the integration density and capacitor area of ​​current semiconductor structures are poor.

[0028] An embodiment of the present disclosure provides a semiconductor structure, which includes a first electrode plate, a second electrode plate, a third electrode plate, a first dielectric layer, and a second dielectric layer. The first electrode plate, the first dielectric layer, and the second electrode plate constitute a first capacitor structure, and the second electrode plate, the second dielectric layer, and the third electrode plate constitute a second capacitor structure, that is, the second capacitor structure and the first capacitor structure share the second electrode plate. The first capacitor structure is a deep trench capacitor structure, and the second capacitor structure is a planar capacitor structure. The embodiment of the present disclosure effectively utilizes the area of ​​the top surface of the deep trench capacitor structure to form a planar capacitor structure, effectively increasing the capacitor area, realizing the construction of a multi-faceted capacitor, improving the deep trench capacitance value, and avoiding the situation where a single deep trench capacitor is difficult to meet higher capacitance requirements.

[0029] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0030] Figure 1 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along section A1-A2. Figure 15 A circuit diagram of a semiconductor structure provided by an embodiment of the present disclosure. To illustrate the positional relationship between the trench, the first contact plug, and the second contact plug, Figure 1 The isolation structure in FIG. 1 is a perspective view, that is, the trenches located within or below the isolation structure can be seen.

[0031] refer to Figure 1 and Figure 2 、 Figure 15According to some embodiments of the present disclosure, on the one hand, a semiconductor structure is provided, which includes: a substrate 100, the substrate 100 having a first surface 22 and a second surface 21 relative to each other, the substrate 100 including an array area 10, and a plurality of grooves 101 extending from the first surface 22 to the second surface 21 are formed in the array area 10.

[0032] In some embodiments, the substrate 100 further includes a first edge region 11 and a second edge region 12, respectively adjacent to the array region 10. The first edge region 11 and the second edge region 12 are used to functionally partition the substrate 100 for illustrating the positional relationship between the first capacitor structure 110 and the second capacitor structure 120, and the positional relationship between the first contact plug 131 and the second contact plug 132. The positional relationship between the first edge region 11 and the second edge region 12 may include the second edge region 12 and the first edge region 12 being located on opposite sides of the array region 10, the first edge region 11 and the second edge region 12 being adjacently disposed, the first edge region 11 surrounding the second edge region 12, etc. That is, the embodiments of the present disclosure do not specifically set the positional relationship between the first edge region 11 and the second edge region 12. Figure 1 The positional relationship between the first edge region 11 and the second edge region 12 is only an example.

[0033] In some embodiments, substrate 100 is a silicon interposer (SI), a silicon substrate made of silicon and organic materials. It serves as a conduit for transmitting electrical signals within a multi-chip module in an advanced package. It enables interconnection between chips and with the package substrate, acting as a bridge between multiple dies and a circuit board. The SI possesses high fine-pitch routing capabilities and reliable TSV (Through Silicon Via) technology, enabling high-density I / O (input / output) requirements.

[0034] In some embodiments, the substrate 100 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 100 can be a single-layer structure or a multi-layer structure. For example, the substrate 100 can be a III / V semiconductor substrate or a II / VI semiconductor substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, etc. For example, the substrate 100 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Those skilled in the art can select the substrate type according to the type of transistor formed on the substrate 100, so the type of substrate 100 should not limit the scope of protection of the embodiments of the present disclosure.

[0035] In some embodiments, the semiconductor structure includes: a first electrode plate 111, located on the first surface 22 of the substrate 10 and extending into the multiple grooves 101; a first dielectric layer 112, conformally covering the surface of the first electrode plate 111; a second electrode plate 113, conformally covering the surface of the first dielectric layer 112, and the second electrode plate 113 completely fills the multiple grooves 101, and the second electrode plate 113 has a horizontal surface; a second dielectric layer 121, covering the surface of the second electrode plate 113; and a third electrode plate 122, covering the surface of the second dielectric layer 121.

[0036] The first electrode plate 111 , the first dielectric layer 112 , and the second electrode plate 113 constitute a first capacitor structure 110 , while the second electrode plate 113 , the second dielectric layer 121 , and the third electrode plate 122 constitute a second capacitor structure 120 .

[0037] In some embodiments, the first capacitor structure 110 is a deep trench capacitor structure. Compared with some other capacitor types used in semiconductor integrated circuits, the deep trench capacitor structure has a higher power density. In the interposer structure, the deep trench capacitor structure is an important parameter. The deep trench capacitor structure can effectively improve the impedance and logic voltage drop of the PDN (power delivery network, power distribution network, power transmission network), and can also effectively improve the leakage current. The larger the capacitance value of the deep trench capacitor structure, the better its performance.

[0038] In some embodiments, the aspect ratio of the trench 101 is greater than or equal to 30, and the aspect ratio of the trench 101 may be 30, 33, 34, 36.5, 38, 42, or 45. Similarly, the aspect ratio of the first capacitor structure 110 is greater than or equal to 30. The aspect ratio of the first capacitor structure 110 may be 30, 33, 34, 36.5, 38, 42, or 45. When the aspect ratio of the trench 101 or the first capacitor structure 110 is within any of the above ranges or values, the number of film layers of the first capacitor structure 110 may be limited when preparing the first capacitor structure 110, that is, only a small number of deep trench capacitor structures can be prepared in the trench, thereby limiting the possibility of establishing more deep trench capacitor structures in the lateral space, thereby limiting the capacitor area and capacitance of the semiconductor structure. Therefore, the embodiment of the present disclosure increases the capacitor area and integration density of the semiconductor structure by preparing the second capacitor structure on the top surface of the first capacitor structure.

[0039] In some embodiments, the second capacitor structure 120 is a planar capacitor structure. The stacked capacitor structure formed between the first capacitor structure 110 and the second capacitor structure 120 allows two capacitor structures to be implemented within a limited area, thereby increasing the capacitance of the semiconductor package structure and achieving a parallel connection between the first capacitor structure 110 and the second capacitor structure 120 to increase capacitance.

[0040] In some embodiments, the first capacitor structure 110 and the second capacitor structure 120 share the second electrode plate 113, that is, the second electrode plate 113 serves as the upper electrode plate of the first capacitor structure 110, and the second electrode plate 113 also serves as the upper electrode plate of the second capacitor structure 120. In this way, the preparation process of at least one layer of electrode plates and the spacer layer between the first capacitor structure 110 and the second capacitor structure 120 can be reduced, thereby reducing the process difficulty and process steps of the preparation method of the semiconductor structure. The embodiment of the present disclosure reduces the preparation process of the spacer layer between the first capacitor structure 110 and the second capacitor structure 120, that is, the area occupied by the spacer layer does not need to be considered in the setting of the semiconductor structure. On the contrary, the area of ​​the second electrode plate 113 can be increased, thereby increasing the capacitance area of ​​the first capacitor structure 110 and the second capacitor structure 120, and improving the capacitance performance of the semiconductor structure.

[0041] Furthermore, by providing the second capacitor structure 120 on the first capacitor structure 110, a planar capacitor structure is provided on the top surface of the first capacitor structure 110, and the first capacitor structure 110 and the second capacitor structure 120 are connected in parallel, thereby increasing the capacitance of the semiconductor structure formed by the first capacitor structure 110 and the second capacitor structure 120. The upper electrode plate of the deep trench capacitor structure and the lower electrode plate of the planar capacitor structure are effectively separated by the second dielectric layer 121, thereby reducing leakage current between the two electrode plates and facilitating improved yield of the semiconductor structure.

[0042] In some embodiments, the first electrode plate 111 is continuously located in the first edge region 11 , the array region 10 , and the second edge region 12 .

[0043] In some embodiments, the first electrode plate 111 serves as the upper electrode plate of the first capacitor structure 110. The material of the first electrode plate 111 may include any one or more of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten.

[0044] In some embodiments, the first dielectric layer 112 is continuously located in the first edge region 11, the array region 10, and the second edge region 12. The material of the first dielectric layer 112 may include any one or more of silicon oxide, silicon nitride, and a high-k dielectric constant material. The high-k dielectric constant material may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate.

[0045] In some embodiments, the second electrode plate 113 is continuously located in the first edge region 11 and the array region 10 . The second electrode plate 113 serves as the upper electrode plate of the first capacitor structure 110 and also serves as the upper electrode plate of the second capacitor structure 120 .

[0046] In some embodiments, the material of the second electrode plate 113 may include any one or more of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten.

[0047] In some embodiments, the second dielectric layer 121 is continuously located in the first edge region 11 , the array region 10 , and the second edge region 12 , wherein the second dielectric layer 121 covers the surfaces of the second electrode plate 113 and the first dielectric layer 112 to wrap the second electrode plate 113 .

[0048] In some embodiments, the material of the second dielectric layer 121 may include any one or more of silicon oxide, silicon nitride, and high dielectric constant materials. The high dielectric constant materials may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate.

[0049] In some embodiments, the thickness of the second dielectric layer 121 located in the second edge region 12 is less than or equal to the thickness of the second dielectric layer 121 in the array region 10. The thickness of the second dielectric layer 121 located in the second edge region 12 is less than or equal to the thickness of the second dielectric layer 121 in the first edge region 11. When the thickness of the second dielectric layer 121 in the second edge region 12 is less than the thickness of the second dielectric layer 121 in the array region 10 or the first edge region 11, the second dielectric layer 121 may include a stacked first film layer 104 and a second film layer 106, with the first film layer 104 located in the first edge region 11 and the array region 10, and the second film layer 106 located in the second edge region 12, the first edge region 11, and the array region 10. In this way, during the removal of the second electrode plate located in the second edge region 12, the first film layer 104 can serve as a protective layer to protect the second electrode plate 113, preventing the etching process from causing excessive etching damage to the second electrode plate 113, thereby improving the performance of the second electrode plate 113.

[0050] When the thickness of the second dielectric layer 121 in the second edge region 12 is equal to the thickness of the second dielectric layer 121 in the array region 10 or the first edge region 11, the second dielectric layer 121 can be formed after the second electrode plate 113 is formed. In this way, the steps of forming the first film layer and etching the first film layer in the second region 12 can be reduced, thereby reducing the preparation cost of the semiconductor structure and improving the preparation efficiency of the semiconductor structure.

[0051] The first film layer 104 and the second film layer 106 also serve as electrical isolation layers between the second electrode plate 113 and the third electrode plate 122 , thereby reducing leakage current between the second electrode plate 113 and the third electrode plate 122 .

[0052] In some embodiments, the third electrode plate 122 is continuously located in the array region 10 and the second edge region 12 . The third electrode plate 122 serves as a lower electrode plate of the second capacitor structure 120 .

[0053] In some embodiments, the material of the third electrode plate 122 may include any one or more of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten.

[0054] In some embodiments, the third electrode plate 122 includes a first portion located in the second edge region 12 and a second portion located in the array region 10 , and a thickness T1 of the first portion is greater than or equal to a thickness T2 of the second portion.

[0055] In some embodiments, the surface of the third electrode plate 122 away from the substrate 100 is flush. Thus, a chemical planarization process can be used to etch the surface of the third electrode plate 122 away from the substrate 100, thereby removing regions of the third electrode plate 122 with surface defects, improving the performance of the third electrode plate 122, and thereby improving the performance of the second capacitor structure 120.

[0056] In some embodiments, the semiconductor structure includes: an isolation structure 109, which is continuously located in the first edge region 11, the array region 10, and the second edge region 12, and the isolation structure 109 covers the surfaces of the second dielectric layer 121 and the third electrode plate 122; a plurality of first contact plugs 131, which are located in the first edge region 11, and the plurality of first contact plugs 131 penetrate the isolation structure 109 and contact the second electrode plate 113; a plurality of second contact plugs 132, which are located in the second edge region 12, and the plurality of second contact plugs 132 penetrate the isolation structure 109, the third electrode plate 122, the second dielectric layer 121, and the first dielectric layer 112 and contact the first electrode plate 111.

[0057] In some embodiments, the isolation structure 109 is further located between the first contact plug 131 and the third electrode plate 122 , thereby achieving electrical insulation between the first contact plug 131 and the third electrode plate 122 .

[0058] In some embodiments, the material of the isolation structure 109 includes any one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0059] In some embodiments, the first contact plug 131 is used to connect to the second electrode plate 113 , that is, the first contact plug 131 is used to electrically connect the upper electrode plate of the first capacitor structure 110 and the upper electrode plate of the second capacitor structure 120 .

[0060] In some embodiments, the first contact plug 131 is located in the first edge area 11. Since the third electrode plate 122 is not located in the first edge area 11, and there is a first dielectric layer 112 between the first electrode plate 111 and the second electrode plate 113, the first contact plug 131 may not be connected to the first electrode plate 111 and the third electrode plate 122, but only electrically connected to the second electrode plate 113, thereby avoiding a short circuit between the electrode plates.

[0061] In addition, the isolation structure 109 is located between the first contact plug 131 and the third electrode plate 122. There is a distance between the first contact plug 131 and the third electrode plate 122, thereby ensuring a certain distance between the first contact plug 131 and the third electrode plate 122, and a certain distance between the second electrode plate 113 and the third electrode plate 122.

[0062] In some embodiments, the cross-section of the first contact plug 131 along the direction perpendicular to the substrate 100 is a trapezoidal structure, that is, the size of the first contact plug decreases in the direction approaching the substrate 100. In this way, the distance between the first contact plug 131 and the third electrode plate 122 can be increased, thereby reducing the risk of short circuit between the first contact plug 131 and the third electrode plate 122 and improving the yield of the semiconductor structure.

[0063] In some embodiments, the contact between the first contact plug 131 and the second electrode plate 113 may be between the bottom surface of the first contact plug 131 and the top surface of the second electrode plate 113, that is, the first contact plug 131 is not located within the second electrode plate 113. The contact between the first contact plug 131 and the first electrode plate 111 may be such that the first contact plug 131 penetrates a portion of the thickness of the first electrode plate 111 and contacts the first electrode plate 111. In this way, the contact between the first contact plug 131 and the first electrode plate 111 is closer, thereby reducing contact resistance and improving the connection performance between the first contact plug and the first electrode plate 111.

[0064] In some embodiments, the second contact plug 132 is located in the second edge area 12, electrically connected to the first electrode plate 111, and also electrically connected to the third electrode plate 122. The second contact plug 132 is used to connect the lower electrode plate of the second capacitor structure 120 and the lower electrode plate of the first capacitor structure 110. In this way, the first contact plug 131 electrically connects the upper electrode plates of the first capacitor structure 110 and the second capacitor structure 120, and the second contact plug 132 electrically connects the lower electrode plates of the first capacitor structure 110 and the second capacitor structure 120. The first capacitor structure 110 and the second capacitor structure 120 are connected in parallel, thereby increasing the capacitance of the semiconductor structure formed by the first capacitor structure 110 and the second capacitor structure 120.

[0065] In some embodiments, the second contact plug 132 is located in the second edge region 12, the second electrode plate 113 is not located in the second edge region, and the second dielectric layer 121 wraps the side of the second electrode plate 113. In this way, electrical insulation is achieved between the second contact plug 132 and the second electrode plate 113 to ensure that the first capacitor structure and the second capacitor structure are connected in parallel and to avoid a short circuit between the electrode plates.

[0066] In some embodiments, the contact between the first contact plug 131 and the first electrode plate 111 may be between the bottom surface of the first contact plug 131 and the top surface of the first electrode plate 111, that is, the first contact plug 131 is not located within the first electrode plate 111. The contact between the first contact plug 131 and the first electrode plate 111 may be that the first contact plug 131 penetrates a portion of the thickness of the first electrode plate 111 and contacts the first electrode plate 111. In this way, the contact between the first contact plug 131 and the first electrode plate 111 is closer, thereby reducing contact resistance and improving the connection performance between the first contact plug and the first electrode plate 111.

[0067] In some embodiments, the material of any one of the first contact plug 131 and the second contact plug 132 includes any one or more of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten.

[0068] In some embodiments, the second dielectric layer 121 is located between the second contact plug 132 and the second electrode plate 113, and the second contact plug 132 and the second electrode plate 113 are electrically insulated to ensure that the first capacitor structure and the second capacitor structure are connected in parallel and to avoid a short circuit between the electrode plates.

[0069] In some embodiments, the thickness of the second dielectric layer 121 between the second contact plug 132 and the second electrode plate 113 is greater than or equal to 5 nm. The thickness of the second dielectric layer 121 between the second contact plug 132 and the second electrode plate 113 may be 5.3 nm, 6.8 nm, 9.3 nm, 10.9 nm, 16.4 nm, 24.3 nm, or 38 nm. The thickness of the second dielectric layer 121 between the second contact plug 132 and the second electrode plate 113 being within any of the aforementioned ranges or values ​​can achieve electrical insulation between the second contact plug 132 and the second electrode plate 113, and a moderate spacing between the second electrode plate 113 and the third electrode plate 122, thereby preventing charge from moving between the second electrode plate 113 and the third electrode plate 122. Furthermore, the proportion of the second dielectric layer 121 can be reduced, thereby increasing the area of ​​the second electrode plate 113 and the third electrode plate 122, and thus increasing the capacitance area of ​​the second capacitor structure 120.

[0070] In some embodiments, the semiconductor structure further includes an insulating layer 102, which is located between the first electrode plate 111 and the substrate 100. The insulating layer 102 is used to ensure electrical insulation between the substrate 100 and the first electrode plate 111. The insulating layer 102 is made of silicon oxide.

[0071] The embodiment of the present disclosure provides a semiconductor structure, which includes a first electrode plate 111, a second electrode plate 113, a third electrode plate 122, a first dielectric layer 112 and a second dielectric layer 121. The first electrode plate 111, the first dielectric layer 112 and the second electrode plate 113 constitute a first capacitor structure 110, and the second electrode plate 113, the second dielectric layer 121 and the third electrode plate 122 constitute a second capacitor structure 120, that is, the second capacitor structure 120 and the first capacitor structure 110 share the second electrode plate 113. The first capacitor structure 110 is a deep trench capacitor structure, and the second capacitor structure 120 is a planar capacitor structure. The embodiment of the present disclosure effectively utilizes the area of ​​the top surface of the deep trench capacitor structure to form a planar capacitor structure, effectively increasing the capacitor area, realizing the construction of a multi-faceted capacitor, improving the deep trench capacitance value, and avoiding the situation where a single deep trench capacitor is difficult to meet higher capacitance requirements.

[0072] In addition, a second dielectric layer 121 is provided to cover the top surface of the second electrode plate 113, the side surface of the second electrode plate 113, and a portion of the surface of the first dielectric layer 112. The first contact plug 131 penetrates the third electrode plate 122 and is in electrical contact with the first electrode plate 111. The second contact plug 132 is in electrical contact with the second electrode plate 113. In this way, there is no need to etch the film layers and isolation structure of the second capacitor structure 120. The electrical contact between the first contact plug 131 and the first electrode plate 111 can be achieved in a single step, thereby reducing the number of mask plates and saving the preparation cost of the semiconductor structure preparation method.

[0073] In addition, the embodiment of the present disclosure reasonably arranges the positions and connection relationships of the first capacitor structure 110, the second capacitor structure 120, the first contact plug 131 and the second contact plug 132, thereby realizing two capacitor structures within a limited area, thereby increasing the capacitance of the semiconductor packaging structure, and realizing separate control of the two capacitor structures and the second capacitor structure 120 and the first capacitor structure 110 sharing the second electrode plate 113, thereby increasing the integration density of the semiconductor structure.

[0074] Accordingly, according to some embodiments of the present disclosure, the embodiments of the present disclosure also provide a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure provided by the above embodiments. The technical features that are the same as or corresponding to the above embodiments will not be elaborated here.

[0075] Figures 3 to 14This is a schematic diagram of the structure of the semiconductor structure corresponding to each step in the method for preparing the semiconductor structure provided in one embodiment of the present disclosure. Figure 4 for Figure 3 Schematic diagram of the cross-section structure along section A1-A2; Figure 7 for Figure 6 Schematic diagram of the cross-section structure along section A1-A2; Figure 11 for Figure 10 Schematic diagram of the cross-sectional structure along section A1-A2.

[0076] refer to Figure 3 and Figure 4 The method for preparing a semiconductor structure includes: providing a substrate 100, the substrate 100 having a first surface 22 and a second surface 21 relative to each other, and the substrate 100 includes an array area 10, and a plurality of grooves 101 extending from the first surface 22 to the second surface 21 are formed in the array area 10.

[0077] In some embodiments, substrate 100 includes a first edge region 11 and a second edge region 12, each adjacent to array region 10. Substrate 100 serves as an interposer. Substrate 100 may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. Substrate 100 may have a single-layer structure or a multi-layer structure.

[0078] In some embodiments, the method of forming the groove 101 can be: forming a first mask layer on the surface of the substrate 100, and then forming a lithographically patterned photoresist layer above the first mask layer; and transferring the pattern in the lithographically patterned photoresist layer through the first mask layer by using an anisotropic etching process such as a reactive ion etching process to form the groove 101.

[0079] In some embodiments, an anisotropic etching process may be performed to form the trenches 101. For example, a reactive ion etching process using a gas combination including HBr, NF3, O2, and SF6 may be used to form the trenches 101. The horizontal cross-sectional shape of each trench 101 may be a circle, an ellipse, a rectangle, a rounded rectangle, a ring having inner and outer peripheries of various shapes, or any two-dimensional shape defining a closed volume.

[0080] In some embodiments, the aspect ratio of the trench 101 is greater than or equal to 30. The aspect ratio of the trench 101 may be 30, 33, 34, 36.5, 38, 42, or 45. When the aspect ratio of the trench 101 is within any of the above ranges or values, the number of film layers of the first capacitor structure 110 may be limited, that is, only a small number of deep trench capacitor structures may be prepared in the trench, thereby limiting the capacitor area. At the same time, the lateral space accounts for a large proportion, and the possibility of establishing more deep trench capacitor structures in the lateral space is reduced, thereby limiting the capacitor area and capacitance of the semiconductor structure.

[0081] refer to Figure 5 The preparation method includes: forming an insulating layer 102 on the first surface 22 and extending into the trench 101. The insulating layer 102 is made of silicon oxide.

[0082] refer to Figures 5 to 11 The method for preparing a semiconductor structure includes: forming a first capacitor structure 110, the first capacitor structure 110 including a stacked first electrode plate 111, a first dielectric layer 112, and a second electrode plate 113, wherein the first electrode plate 111, the first dielectric layer 112, and the second electrode plate 113 are all on the first surface 22 and extend into the groove 101; forming a second capacitor structure 120, the second capacitor structure 120 including a second electrode plate 113, a second dielectric layer 121, and a third electrode plate 122, wherein the second dielectric layer 121 covers the top surface of the second electrode plate 113, the side surface of the second electrode plate 113, and a portion of the surface of the first dielectric layer 112, and the third electrode plate 122 is also located on a portion of the surface of the second dielectric layer 121.

[0083] In some embodiments, the first capacitor structure 110 is a deep trench capacitor structure, which has a higher power density than some other capacitor types used in semiconductor integrated circuits. The second capacitor structure 120 is a planar capacitor structure.

[0084] In some embodiments, the first capacitor structure 110 and the second capacitor structure 120 share the second electrode plate 113, that is, the second electrode plate 113 serves as the upper electrode plate of the first capacitor structure 110, and the second electrode plate 113 also serves as the upper electrode plate of the second capacitor structure 120. In this way, the preparation process of at least one layer of electrode plates and the spacer layer between the first capacitor structure 110 and the second capacitor structure 120 can be reduced, thereby reducing the process difficulty and process steps of the preparation method of the semiconductor structure. The preparation process of the spacer layer between the first capacitor structure 110 and the second capacitor structure 120 is reduced, that is, the area occupied by the spacer layer does not need to be considered in the setting of the semiconductor structure. On the contrary, the area of ​​the second electrode plate 113 can be increased, thereby increasing the capacitance area of ​​the first capacitor structure 110 and the second capacitor structure 120, and improving the capacitance performance of the semiconductor structure.

[0085] In some embodiments, reference Figures 5 to 11 A first electrode plate 111 is formed, located on the first surface 22 of the substrate and extending into the plurality of grooves 101. A first dielectric layer 121 is formed, conformally covering the surface of the first electrode plate 111. A second electrode plate 113 is formed, conformally covering the surface of the first dielectric layer 121. The second electrode plate 113 completely fills the plurality of grooves 101 and has a horizontal surface. A second dielectric layer 121 is formed, covering the surface of the second electrode plate 113. A third electrode plate 122 is formed, covering the surface of the second dielectric layer 121.

[0086] In some embodiments, the first electrode plate 111 is continuously located in the first edge region 11 , the array region 10 , and the second edge region 12 . The first electrode plate 111 serves as an upper electrode plate of the first capacitor structure 110 .

[0087] In some embodiments, the first dielectric layer 112 is continuously located in the first edge region 11 , the array region 10 , and the second edge region 12 .

[0088] In some embodiments, the second electrode plate 113 is continuously located in the first edge region 11 and the array region 10 . The second electrode plate 113 serves as the upper electrode plate of the first capacitor structure 110 and also serves as the upper electrode plate of the second capacitor structure 120 .

[0089] In some embodiments, the second dielectric layer 121 is continuously located in the first edge region 11 , the array region 10 , and the second edge region 12 , wherein the second dielectric layer 121 covers the surfaces of the second electrode plate 113 and the first dielectric layer 112 to wrap the second electrode plate 113 .

[0090] In some embodiments, the third electrode plate 122 is continuously located in the array region 10 and the second edge region 12 . The third electrode plate 122 serves as a lower electrode plate of the second capacitor structure 120 .

[0091] refer to Figure 5 A first electrode plate 111 , a first dielectric layer 112 , a first conductive film 103 and a first film layer 104 are sequentially stacked on the surface of the substrate 100 .

[0092] In some embodiments, the first conductive film 103 and the first film layer 104 are located in the first edge region 11 , the array region 10 , and the second edge region 12 .

[0093] In some embodiments, the first conductive film 103 fills the trench 101 and is located on the surface of the first dielectric layer 112 , and the first film layer 104 is located on the surface of the first conductive film 103 .

[0094] In some embodiments, the material of either the first electrode plate 111 or the first conductive film 103 may include any one or more of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten.

[0095] In some embodiments, the thickness of either the first electrode plate 111 or the first conductive film 103 may be in a range of 5 nm to 50 nm, such as in a range of 10 nm to 30 nm.

[0096] In some embodiments, the material of either the first dielectric layer 112 or the first film layer 104 may include any one or more of silicon oxide, silicon nitride, and a high dielectric constant material. The high dielectric constant material may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate.

[0097] In some embodiments, the thickness of either the first dielectric layer 112 or the first film layer 104 may be in a range from 2 nm to 30 nm, such as in a range from 10 nm to 20 nm.

[0098] In some embodiments, the first electrode plate 111 , the first dielectric layer 112 , the first conductive film 103 , and the first film layer 104 may be formed by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0099] refer to Figures 6 to 8 The first conductive film in the second edge area 12 is patterned to form a first groove 105, the bottom surface of the first groove 105 exposes the surface of the first dielectric layer 112, and the remaining first conductive film serves as the second electrode plate 113. The first electrode plate 111, the first dielectric layer and the second electrode plate 113 together constitute the first capacitor structure 110.

[0100] In some embodiments, reference Figure 6 as well as Figure 7 , patterning the first conductive film in the second edge region 12 and the first film layer 104 to form a first groove 105 .

[0101] In some embodiments, a second mask layer is formed, and the second mask layer is located on the surface of the first film layer. The second mask layer is located in the array area 10 and the first edge area 11 to expose the first conductive film and the first film layer in the second edge area; the exposed first conductive film and the first film layer are removed until the surface of the first dielectric layer 112 is exposed.

[0102] In some embodiments, removing the first conductive film and the first film layer may be performed by a wet etching process or a dry etching process.

[0103] refer to Figure 8 A second film layer 106 is formed on the surface of the first film layer 104. The second film layer 106 covers the surface of the first film layer 104 and the surface of the first dielectric layer 112. The first film layer 104 and the second film layer 106 serve as a second dielectric layer 121. The first film layer 104 can serve as a protective layer for protecting the second electrode plate 113, preventing the etching process from causing excessive etching damage to the second electrode plate 113, thereby improving the performance of the second electrode plate 113.

[0104] In some embodiments, the first groove 105 is located in the second edge area 12, and the area where the first groove 105 is located is the defined area of ​​the second edge area 12. By removing the first conductive film in the second edge area 12, that is, removing the second electrode plate in the second edge area 12, the second contact plug subsequently formed in the second edge area 12 does not need to consider the problem of short circuit of the second electrode plate, thereby reducing the difficulty of preparing the semiconductor structure.

[0105] In some embodiments, the orthographic projection of the first groove 105 on the substrate 100 is equal to the area of ​​the second edge region 12 , or the orthographic projection of the first groove 105 on the substrate 100 is smaller than the area of ​​the second edge region 12 .

[0106] In some embodiments, after forming the second electrode plate 113, a second dielectric layer 121 can be formed on the surface of the second electrode plate 113. In this way, the thickness of the second dielectric layer 121 in the second edge region 12 is equal to the thickness of the second dielectric layer 121 in the array region 10 or the first edge region 11. This can reduce the steps of forming the first film layer and etching the first film layer in the array region 10 or the first edge region 11, thereby reducing the preparation cost of the semiconductor structure and improving the preparation efficiency of the semiconductor structure.

[0107] In the process of etching the first groove, the first dielectric layer may also be etched to expose the top surface of the first electrode plate.

[0108] In some embodiments, reference Figure 9 A second conductive film 107 is formed on the surface of the second dielectric layer 121 .

[0109] In some embodiments, the material of the second conductive film 107 may include any one or more of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten.

[0110] refer to Figure 10 and Figure 11 The second conductive film in the first edge area 11 is patterned to form a second groove 108. The bottom surface of the second groove 108 exposes the surface of the second dielectric layer 121. The remaining second conductive film serves as the third electrode plate 122. The second electrode plate 113, the second dielectric layer 121 and the third electrode plate 122 together constitute the second capacitor structure 120.

[0111] In some embodiments, a third mask layer is formed, and the third mask layer is located on the surface of the second conductive film 107. The third mask layer is located in the array area 10 and the second edge area 12 to expose the second conductive film 107 in the first edge area; the exposed second conductive film 107 is removed until the surface of the second dielectric layer 121 is exposed.

[0112] In some embodiments, the removal of the second conductive film 107 may be performed by a wet etching process or a dry etching process.

[0113] In some embodiments, the third electrode plate 122 includes a first portion located in the second edge region 12 and a second portion located in the array region 10 , wherein a thickness T1 of the first portion is greater than or equal to a thickness T2 of the second portion.

[0114] In some embodiments, the distance between the first groove 105 and the second groove 108 is greater than or equal to 0. Thus, an isolation structure as an insulating material is provided between the first groove 105 and the second groove 108 to prevent an electrical short circuit between the first contact plug and the third electrode plate.

[0115] refer to Figure 12 , forming an isolation structure 109, which covers the second groove 108 and the third electrode plate 122. The material of the isolation structure 109 includes any one or more of silicon oxide, silicon oxynitride, silicon nitride or lanthanide oxide.

[0116] refer to Figure 13 The isolation structure 109 and the third electrode plate 122 are etched to expose the top surface of the second dielectric layer 121, thereby forming a third groove 125 in the first edge region 11 and a fourth groove 126 in the second edge region 12. In this way, the second dielectric layer 121 serves as an etch stop layer.

[0117] In some embodiments, a fourth mask layer having through holes is formed. The fourth mask layer is located on the surface of the isolation structure. The fourth mask layer is located in the first edge region 11, the array region 10, and the second edge region 12. The through holes are located in the first edge region 11 and the second edge region 12. The isolation structure 109 is etched along the through holes until the top surface of the second dielectric layer 121 located in the first edge region 11 and the top surface of the third electrode plate in the second edge region 12 are exposed. In the same etching process, the etching rate of the material of the second dielectric layer is different from the etching rate of the material of the isolation structure, and the etching rate of the third electrode plate is different from the etching rate of the isolation structure.

[0118] Etching is continued on the exposed top surface of the third electrode plate until the second dielectric layer in the second edge region is exposed, thereby forming a fourth groove 126. In the same etching process, the etching rate of the material of the second dielectric layer is different from the etching rate of the material of the third electrode plate, and the second dielectric layer serves as an etch stop layer.

[0119] refer to Figure 14 , the second dielectric layer 121 at the bottom of the third groove 125 is etched along the third groove 125 until the top surface of the second electrode plate 113 is exposed, forming a fifth groove 127, and the second dielectric layer 121 and the first dielectric layer 112 at the bottom of the fourth groove 126 are etched along the fourth groove 126 until the top surface of the first electrode plate 111 is exposed, forming a sixth groove 128.

[0120] In some embodiments, during the same etching process, the etching rate of the second electrode plate 113 is different from the etching rate of the second dielectric layer 121, thereby ensuring that etching damage to the second electrode plate 113 is not caused. During the same etching process, the etching rate of the first electrode plate 111 is different from the etching rate of the second dielectric layer 121. During the same etching process, the etching rate of the first electrode plate 111 is different from the etching rate of the first dielectric layer 112. This ensures that etching damage to the first electrode plate 111 is not caused.

[0121] The above-mentioned etching process can be a wet etching process or a dry etching process. Through multiple etching processes, a fifth groove 127 for accommodating the first contact plug and a sixth groove 128 for accommodating the second contact plug are formed, so that the morphology of the first contact plug and the second contact plug can be accurately controlled, thereby avoiding the short circuit problem between the electrode plates.

[0122] In some embodiments, in the same step, a fifth groove 127 for accommodating the first contact plug and a sixth groove 128 for accommodating the second contact plug are formed simultaneously, which is beneficial to improving the preparation efficiency of the semiconductor structure, while reducing the cleaning steps and waiting time between different steps, saving costs.

[0123] refer to Figures 1 to 2 The method for preparing the semiconductor structure includes: forming a plurality of first contact plugs 131 located in the first edge region 11, wherein the plurality of first contact plugs 131 penetrate the isolation structure 109 and contact the second electrode plate 113; forming a plurality of second contact plugs 132 located in the second edge region 12, wherein the plurality of second contact plugs 132 penetrate the isolation structure 109, the third electrode plate 122, the second dielectric layer 121, and the first dielectric layer 112 and contact the first electrode plate 111.

[0124] In some embodiments, multiple first contact plugs 131 and multiple second contact plugs 132 are formed in the same process step. The first contact plugs 131 are located in the fifth recess, and the second contact plugs 132 are located in the sixth recess. This reduces the number of masks and fabrication steps, thereby saving costs and improving the fabrication efficiency of the semiconductor structure.

[0125] In some embodiments, the isolation structure 109 is further located between the first contact plug 131 and the third electrode plate 122 , thereby achieving electrical insulation between the first contact plug 131 and the third electrode plate 122 .

[0126] In some embodiments, the first contact plug 131 is used to connect to the second electrode plate 113 , that is, the first contact plug 131 is used to electrically connect the upper electrode plate of the first capacitor structure 110 and the upper electrode plate of the second capacitor structure 120 .

[0127] In some embodiments, the first contact plug 131 is located in the first edge area 11. Since the third electrode plate 122 is not located in the first edge area 11, and there is a first dielectric layer 112 between the first electrode plate 111 and the second electrode plate 113, the first contact plug 131 may not be connected to the first electrode plate 111 and the third electrode plate 122, but only electrically connected to the second electrode plate 113, thereby avoiding a short circuit between the electrode plates.

[0128] In addition, the isolation structure 109 is located between the first contact plug 131 and the third electrode plate 122. There is a distance between the first contact plug 131 and the third electrode plate 122, thereby ensuring a certain distance between the first contact plug 131 and the third electrode plate 122, and a certain distance between the second electrode plate 113 and the third electrode plate 122.

[0129] In some embodiments, the cross-section of the first contact plug 131 along the direction perpendicular to the substrate 100 is a trapezoidal structure, that is, the size of the first contact plug decreases in the direction approaching the substrate 100. In this way, the distance between the first contact plug 131 and the third electrode plate 122 can be increased, thereby reducing the risk of short circuit between the first contact plug 131 and the third electrode plate 122 and improving the yield of the semiconductor structure.

[0130] In some embodiments, the second contact plug 132 is located in the second edge area 12, electrically connected to the first electrode plate 111, and also electrically connected to the third electrode plate 122. The second contact plug 132 is used to connect the lower electrode plate of the second capacitor structure 120 and the lower electrode plate of the first capacitor structure 110. In this way, the first contact plug 131 electrically connects the upper electrode plates of the first capacitor structure 110 and the second capacitor structure 120, and the second contact plug 132 electrically connects the lower electrode plates of the first capacitor structure 110 and the second capacitor structure 120. The first capacitor structure 110 and the second capacitor structure 120 are connected in parallel, thereby increasing the capacitance of the semiconductor structure formed by the first capacitor structure 110 and the second capacitor structure 120.

[0131] In some embodiments, the second contact plug 132 is located in the second edge region 12, the second electrode plate 113 is not located in the second edge region, and the second dielectric layer 121 wraps the side of the second electrode plate 113. In this way, electrical insulation is achieved between the second contact plug 132 and the second electrode plate 113 to ensure that the first capacitor structure and the second capacitor structure are connected in parallel and to avoid a short circuit between the electrode plates.

[0132] In some embodiments, the second dielectric layer 121 is located between the second contact plug 132 and the second electrode plate 113. The thickness of the second dielectric layer 113 located between the second contact plug 132 and the second electrode plate 113 is greater than or equal to 5 nm, and the thickness of the second dielectric layer 113 located between the first contact plug 131 and the second electrode plate 113 can be 5.3 nm, 6.8 nm, 9.3 nm, 10.9 nm, 16.4 nm, 24.3 nm, or 38 nm.

[0133] Accordingly, according to some embodiments of the present disclosure, another aspect of the present disclosure further provides a packaging structure, including the semiconductor structure provided by the above embodiments, and the same elements as the above embodiments are not further described here. Figure 16 A schematic diagram of a packaging structure provided in an embodiment of the present disclosure.

[0134] refer to Figure 16 The packaging structure includes: a circuit board 300; a packaging substrate 400, located on the surface of the circuit board 300, and the first surface of the packaging substrate 400 is electrically connected to the circuit board 300; a semiconductor structure 200 such as any of the above embodiments, located on the second surface of the packaging substrate 400, and the semiconductor structure 200 is electrically connected to the second surface of the packaging substrate 400.

[0135] In some embodiments, the packaging structure also includes: a central processing unit 500 (CPU) and a memory 600; wherein, the packaging substrate 400 is located on the surface of the circuit board 300, and the first surface of the packaging substrate 400 is connected to the circuit board 300 through the packaging solder balls 410; the second surface of the semiconductor structure is connected to the second surface of the packaging substrate 400 through the buckled bumps 210; the central processing unit 500 is located on the first surface of the semiconductor structure 200, and the first surface of the central processing unit 500 is connected to the first surface of the semiconductor structure 200 through the first micro bumps 510 (ubumps); the memory 600 is located on the second surface of the central processing unit 500, and the first surface of the memory 600 is connected to the second surface of the central processing unit 500 through the second micro bumps 610 (ubumps).

[0136] In some embodiments, the central processing unit 500 may include a basic module 501, a computing module 502, and a logic module 503. The basic module 501 has a plurality of vias 202 connected to the memory 600.

[0137] In some embodiments, the central processing unit 500 further includes a port physical layer 504 (Physical, abbreviated as PHY) for interfacing with external signals.

[0138] In some embodiments, the memory 600 includes a high-bandwidth memory, such as HBMDRAM (High Bandwidth Memory Dynamic Random Access Memory).

[0139] Flip-chip bumps 210 can include C4 Cu bumps, allowing direct flip-chip soldering (Flip Chip on Board) to complete chip-to-chip interconnection. This flip-chip method eliminates the need for many pre-package steps and costs. However, various circular or square micro-solder bumps must first be applied to corresponding points on the chip. If bumps are arranged throughout the entire chip surface, the flip-chip soldering method is called "Controlled Collapsed Chip Connection," or C4 for short.

[0140] In some embodiments, the packaging structure further includes a connecting wire 201, which is used to connect the conductive structure located in the via 202 and the solder joints and the solder joints to each other, wherein the solder joints include any one of the flip-up bumps 210, the first micro-bumps 510 and the second micro-bumps 610.

[0141] In the packaging structure in the above embodiments, the semiconductor structure 200 described in any one of the embodiments of the present disclosure is connected to chip structures such as the circuit board 300, the packaging substrate 400, the central processing unit 500 and the memory 600. The semiconductor structure 200 described in any one of the embodiments of the present disclosure serves as an interconnection structure connecting chips, which can improve the performance and yield of the packaging structure to enhance its overall performance.

[0142] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate having a first surface and a second surface opposite to each other, the substrate including an array region, and a plurality of grooves extending from the first surface to the second surface formed in the array region; a first electrode plate, located on the first surface of the substrate and extending into the plurality of grooves; a first dielectric layer, conformally covering the surface of the first electrode plate; a second electrode plate conformally covering the surface of the first dielectric layer, the second electrode plate completely filling the plurality of grooves, the second electrode plate further having a horizontal surface protruding from the upper portion of the grooves; a second dielectric layer covering a horizontal surface of the second electrode plate protruding above the groove; The third electrode plate covers the surface of the second dielectric layer.

2. The semiconductor structure according to claim 1, wherein: The substrate further includes a first edge region and a second edge region respectively adjacent to the array region, wherein The first electrode plate is continuously located in the first edge area, the array area, and the second edge area; The first dielectric layer is continuously located in the first edge region, the array region, and the second edge region; The second electrode plate is continuously located in the first edge area and the array area; The second dielectric layer is continuously located in the first edge region, the array region, and the second edge region, wherein the second dielectric layer covers the surface of the second electrode plate and the first dielectric layer to wrap the second electrode plate; The third electrode plate is continuously located in the array area and the second edge area.

3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further comprises: an isolation structure, continuously located in the first edge region, the array region, and the second edge region, the isolation structure covering the surface of the second dielectric layer and the third electrode plate; a plurality of first contact plugs located in the first edge region, the plurality of first contact plugs passing through the isolation structure and contacting the second electrode plate; A plurality of second contact plugs are located in the second edge region. The plurality of second contact plugs penetrate the isolation structure, the third electrode plate, the second dielectric layer, and the first dielectric layer, and contact the first electrode plate.

4. The semiconductor structure according to claim 2, wherein: The third electrode plate is flush with a surface away from the substrate and includes a first portion located in the second edge area and a second portion located in the array area. The thickness of the first portion is greater than or equal to the thickness of the second portion.

5. The semiconductor structure according to claim 2, wherein: The thickness of the second dielectric layer in the second edge region is less than or equal to the thickness of the second dielectric layer in the array region.

6. The semiconductor structure according to any one of claims 2 to 5, wherein: The second dielectric layer includes a stacked first film layer and a second film layer. The first film layer is located in the array region, and the second film layer is located in the first edge region, the second edge region, and the array region.

7. The semiconductor structure according to claim 1, wherein: The aspect ratio of the trench is greater than or equal to 30.

8. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate having a first surface and a second surface opposite to each other, the substrate including an array region, and a plurality of grooves extending from the first surface to the second surface formed in the array region; forming a first electrode plate located on the first surface of the substrate and extending into the plurality of grooves; forming a first dielectric layer to conformally cover the surface of the first electrode plate; forming a second electrode plate, conformally covering the surface of the first dielectric layer, and the second electrode plate completely filling the plurality of grooves, the second electrode plate further having a horizontal surface protruding from the upper portion of the grooves; forming a second dielectric layer to cover the horizontal surface of the second electrode plate protruding above the groove; A third electrode plate is formed to cover the surface of the second dielectric layer.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The substrate further includes a first edge region and a second edge region respectively adjacent to the array region, and the first electrode plate is continuously located in the first edge region, the array region, and the second edge region; The first dielectric layer is continuously located in the first edge region, the array region, and the second edge region; The process steps for forming the second electrode plate include: forming a first conductive film on the surface of the first dielectric layer, wherein the first conductive film is located in the first edge region, the array region, and the second edge region; patterning the first conductive film in the second edge region to form a first groove, wherein the bottom surface of the first groove is exposed to the surface of the first dielectric layer, and the remaining first conductive film serves as a second electrode plate; The process steps for forming the third electrode plate include: forming a stacked second dielectric layer and a second conductive film on a surface of the second electrode plate; Patterning a portion of the second conductive film in the first edge region to form a second groove, wherein the bottom surface of the second groove exposes the surface of the second dielectric layer, and the remaining second conductive film serves as a third electrode plate; The process steps for forming the second dielectric layer include: forming a first film layer on a surface of the first conductive film; patterning the first conductive film and the first film layer in the second edge region; A second film layer is formed on the surface of the first film layer, the second film layer covers the surface of the first film layer and the surface of the first dielectric layer, and the first film layer and the second film layer serve as a second dielectric layer.

10. The method for preparing a semiconductor structure according to claim 9, wherein: The method further includes: forming an isolation structure continuously located in the first edge region, the array region, and the second edge region, wherein the isolation structure covers the surface of the second dielectric layer and the third electrode plate; forming a plurality of first contact plugs located in the first edge region, wherein the plurality of first contact plugs penetrate the isolation structure and contact the second electrode plate; A plurality of second contact plugs are formed in the second edge region. The plurality of first contact plugs penetrate the isolation structure, the third electrode plate, the second dielectric layer, and the first dielectric layer and contact the first electrode plate.

11. The method for preparing a semiconductor structure according to claim 10, wherein: The plurality of first contact plugs and the plurality of second contact plugs are formed in the same process step.

12. A packaging structure, characterized in that: include: circuit boards; A packaging substrate is located on a surface of the circuit board, wherein a first surface of the packaging substrate is electrically connected to the circuit board; The semiconductor structure according to any one of claims 1 to 7, wherein the semiconductor structure is located on the second surface of the packaging substrate, and the semiconductor structure is electrically connected to the second surface of the packaging substrate.

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