Semiconductor device

Abstract

A semiconductor device includes a semiconductor base having a first main surface and a second main surface spaced apart in a first direction, the semiconductor base including an insulated gate bipolar transistor region including a first region in which a first sub-drift layer and a second sub-drift layer are provided, the first sub-drift layer being more proximate to the first main surface in the first direction than the second sub-drift layer; and a trench having a depth reaching a drift layer, the trench being a plurality of trenches, at least one of the plurality of trenches extending into the first sub-drift layer of the first region. Thus, when the semiconductor device is forwardly turned off, the first sub-drift layer and the second sub-drift layer in the first region can form a blocking junction which not only can mainly bear an electric field but also can assist in depleting carriers, so that a peak voltage can be reduced, and reverse withstand voltage and breakdown voltage resistance can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] In the prior art, during the initial forward conduction phase of a reverse-conducting insulated gate bipolar transistor (IGBT), the device undergoes a positive feedback process, known as voltage foldback, in which current continuously increases while resistance continuously decreases as the device transitions from a unipolar to a bipolar state. This phenomenon slows the turn-on speed of the device and, in severe cases, can prevent the device from turning on, compromising device reliability and performance.

[0003] In the related art, in order to eliminate the voltage foldback phenomenon in the reverse conducting insulated gate bipolar transistor, a common method is to increase the width of the P-type collector region. However, an excessively large P-type collector region will cause uneven current distribution inside the device, thereby reducing the device's voltage resistance. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device that can improve voltage resistance.

[0005] According to an embodiment of the present invention, a semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface being spaced apart in a first direction; a drift layer, the drift layer being arranged on the semiconductor substrate and located between the first main surface and the second main surface, the semiconductor substrate including an insulated gate bipolar transistor region and a fast recovery diode region, the insulated gate bipolar transistor region being circumferentially arranged outside the fast recovery diode region; the drift layer including a first drift layer and a second drift layer, the second drift layer being of a first conductivity type and located between the fast recovery diode region and the first main surface; a first drift layer located in the insulated gate bipolar transistor region and including a first sub-drift layer of a first conductivity type and a second sub-drift layer of a second conductivity type; the insulated gate bipolar transistor region includes a first region and a second region, the first region is adjacent to the fast recovery diode region, and the second region is away from the fast recovery diode region; the first sub-drift layer and the second sub-drift layer are arranged in the first region, and the first sub-drift layer is closer to the first main surface than the second sub-drift layer in the first direction; the first sub-drift layer and the second sub-drift layer are also arranged in the second region, In the second region, the second sub-drift layer is closer to the first main surface in the first direction than the first sub-drift layer; a base layer of the second conductivity type is arranged on the side of the drift layer facing the first main surface, and the surface of the base layer away from the drift layer constitutes a part of the first main surface; an emitter metal layer, the emitter metal layer is arranged on the first main surface; a groove, the depth direction of the groove penetrates the base layer from the first main surface and reaches the drift layer, the grooves are multiple, the multiple grooves are spaced apart in the second direction, and at least one of the multiple grooves extends into the first region In the first sub-drift layer; a collector layer of the second conductivity type and a cathode layer of the first conductivity type, the collector layer is arranged on the side of the first drift layer facing the second main surface, the side of the collector layer away from the drift layer constitutes at least a part of the second main surface, and the collector layer is located in the insulated gate bipolar transistor region; the cathode layer is arranged on the side of the second drift layer facing the second main surface, the side of the cathode layer away from the drift layer constitutes at least a part of the second main surface, and the cathode layer is located in the fast recovery diode region; a collector metal layer, the collector metal layer is arranged on the second main surface.

[0006] Therefore, by arranging a first sub-drift layer of the first conductivity type and a second sub-drift layer of the second conductivity type in the first region of the insulated gate bipolar transistor region, and the first sub-drift layer is closer to the first main surface than the second sub-drift layer, when the semiconductor device is forward-turned off, the first sub-drift layer and the second sub-drift layer in the first region can form a blocking junction, which can not only mainly bear the electric field but also assist in depleting carriers, thereby reducing the peak voltage and improving the reverse voltage resistance and breakdown voltage resistance.

[0007] In some examples of the present invention, a boundary between the first sub-drift layer and the second sub-drift layer in the first region and a boundary between the first sub-drift layer and the second sub-drift layer in the second region are flush with each other.

[0008] In some examples of the present invention, the depths of the first sub-drift layer and the second sub-drift layer in the first region in the first direction are equal and are both D1, and the depths of the first sub-drift layer and the second sub-drift layer in the second region in the first direction are equal and are both D2, and D1 and D2 satisfy the relationship: D1=D2.

[0009] In some examples of the present invention, the semiconductor device also includes a first dielectric isolation layer, which is arranged between the insulated gate bipolar transistor region and the fast recovery diode region, and the depth direction of the first dielectric isolation layer extends from the second main surface toward the first main surface. The first dielectric isolation layer passes through between the collector layer and the cathode layer and reaches the drift layer.

[0010] In some examples of the present invention, the first dielectric isolation layer is a silicon dioxide isolation layer.

[0011] In some examples of the present invention, one end of the first dielectric isolation layer facing the first main surface does not extend beyond the second sub-drift layer in the first region and the first sub-drift layer in the second region.

[0012] In some examples of the present invention, the semiconductor device also includes a second dielectric isolation layer, the collector metal layer includes a first collector metal layer and a second collector metal layer, the first collector metal layer is located in the insulated gate bipolar transistor region, the second collector metal layer is arranged in the fast recovery diode region, the first collector metal layer and the second collector metal layer are arranged at intervals, and the second dielectric isolation layer is arranged between the first collector metal layer and the second collector metal layer and corresponds to the first dielectric isolation layer.

[0013] In some examples of the present invention, the semiconductor device also includes a floating layer of a second conductive type, which is arranged in the second drift layer. The depth direction of the floating layer extends from the side of the second drift layer adjacent to the second main surface toward the first main surface, and the floating layer is in contact with the cathode layer.

[0014] In some examples of the present invention, there are multiple floating layers, and the multiple floating layers are spaced apart by the drift layer.

[0015] In some examples of the present invention, an end of the first dielectric isolation layer adjacent to the first main surface protrudes beyond an end of the floating layer adjacent to the first main surface.

[0016] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0018] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0020] Figure 3 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0021] Figure 4 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0022] Figure 5 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0023] Figure 6 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0024] Figure 7 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0025] Figure 8 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0026] Figure 9 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0027] Figure 10 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0028] Figure 11 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0029] Figure 12 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0030] Figure 13 FIG. 1 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Reference numerals:

[0032] 100. Semiconductor devices;

[0033] 1. Semiconductor substrate; 101. First main surface; 102. Second main surface; 103. Insulated gate bipolar transistor region; 1031. First region; 1032. Second region; 104. Fast recovery diode region;

[0034] 2. Drift layer; 201. First drift layer; 2011. First sub-drift layer; 2012. Second sub-drift layer; 202. Second drift layer;

[0035] 3. Base layer; 4. Emitter metal layer; 5. Groove;

[0036] 601, collector layer; 602, cathode layer;

[0037] 7. Collector metal layer; 701. First collector metal layer; 702. Second collector metal layer;

[0038] 8. First dielectric isolation layer; 9. Second dielectric isolation layer; 10. Floating layer; 11. Gate pad; 12. Emitter region; 13. Contact hole region; 14. Carrier storage layer;

[0039] 15. Gate; 1501. Gate oxide layer;

[0040] 16. Buffer layer. DETAILED DESCRIPTION

[0041] The embodiments of the present invention will be described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention will be described in detail below.

[0042] Reference below Figures 1-13A semiconductor device 100 according to an embodiment of the present invention is described. Semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is assumed to be N-type and the second conductivity type is assumed to be P-type. Similarly, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0043] Combine Figure 1 As shown, the semiconductor device 100 according to the present invention may mainly include: a semiconductor substrate 1, a drift layer 2, a base layer 3 of a second conductive type, an emitter metal layer 4, a trench 5, a collector layer 601, a cathode layer 602 and a collector metal layer 7, wherein the semiconductor substrate 1 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the first main surface 101 and the second main surface 102 are spaced apart in the first direction, which can provide a stable and reliable setting position for other structures in the semiconductor device 100.

[0044] In an embodiment of the present invention, a drift layer 2 is disposed within the semiconductor substrate 1 and between the first main surface 101 and the second main surface 102, thereby providing a transmission channel for current in the semiconductor device 100. The semiconductor device 100 includes an insulated gate bipolar transistor region 103 and a fast recovery diode region 104. The insulated gate bipolar transistor region 103 and the fast recovery diode region 104 are connected in reverse parallel within the semiconductor device 100, enabling the insulated gate bipolar transistor to have a reverse conduction function. The insulated gate bipolar transistor region 103 is circumferentially disposed outside the fast recovery diode region 104 and spaced apart from the fast recovery diode region 104. A transition region is located between the fast recovery diode region 104 and the insulated gate bipolar transistor region 103, thereby preventing the currents flowing through the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 from interfering with each other, thereby ensuring the normal operation of the reverse conducting insulated gate bipolar transistor.

[0045] Furthermore, the drift layer 2 includes a first drift layer 201 and a second drift layer 202. The second drift layer 202 is of the first conductivity type and is located in the fast recovery diode region 104. The first drift layer 201 is located in the insulated gate bipolar transistor region 103, thereby respectively forming the basic structure of the fast recovery diode region 104 and the basic structure of the insulated gate bipolar transistor region 103. In the insulated gate bipolar transistor region 103, the drift layer 2 is responsible for carrying the main current. Therefore, the distribution of the electric field has a significant impact on the performance of the semiconductor device 100.

[0046] Furthermore, the first drift layer 201 includes a first sub-drift layer 2011 of the first conductivity type and a second sub-drift layer 2012 of the second conductivity type, and the insulated gate bipolar transistor region 103 includes a first region 1031 and a second region 1032, the first region 1031 is adjacent to the fast recovery diode region 104, and the second region 1032 is far away from the fast recovery diode region 104.

[0047] Furthermore, a first sub-drift layer 2011 and a second sub-drift layer 2012 are provided in the first region 1031. The first sub-drift layer 2011 is closer to the first main surface 101 in the first direction than the second sub-drift layer 2012. In the embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. Thus, in the first region 1031 of the insulated gate bipolar transistor region 103 near the fast recovery diode region 104, the first sub-drift layer 2011 and the second sub-drift layer 2012 can form a blocking junction.

[0048] Furthermore, a first sub-drift layer 2011 and a second sub-drift layer 2012 are also provided in the second region 1032. In the second region 1032, the second sub-drift layer 2012 is closer to the first main surface 101 in the first direction than the first sub-drift layer 2011. Accordingly, in the second region 1032 of the insulated gate bipolar transistor region 103, which is away from the fast recovery diode region 104, the first sub-drift layer 2011 and the second sub-drift layer 2012 may also form a PN junction.

[0049] In an embodiment of the present invention, the base layer 3 is disposed on the side of the drift layer 2 facing the first main surface 101. The surface of the base layer 3 facing away from the drift layer 2 constitutes a portion of the first main surface 101. The emitter metal layer 4 is disposed on the first main surface 101, and the collector metal layer 7 is disposed on the second main surface 102. In this manner, the basic structure of the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 in the semiconductor device 100 is formed, ensuring the forward conduction characteristics of the insulated gate bipolar transistor region 103 and the reverse recovery characteristics of the fast recovery diode region 104.

[0050] Furthermore, an emitter region 12 and a contact hole region 13 are also provided in the base layer 3, wherein the emitter region 12 and the contact hole region 13 both constitute at least part of the first main surface 101, and the emitter region 12 is electrically connected to the emitter metal layer 4 so that the emitter region 12 and the emitter metal layer 4 have the same electric potential.

[0051] In the embodiment of the present invention, the depth direction of the groove 5 passes through the base layer 3 from the first main surface 101 and reaches the drift layer 2. There are multiple grooves 5, and the multiple grooves 5 are spaced apart in the second direction. At least one of the multiple grooves 5 extends into the first sub-drift layer 2011 of the first region 1031. This ensures that the electron flow channel in the insulated gate bipolar transistor region 103 is normally opened. It should be noted that the depth direction of the groove 5 in the embodiment of the present invention is Figure 1 The first direction in .

[0052] In an embodiment of the present invention, a trench 5 is provided in the insulated gate bipolar transistor region 103. The trench 5 in this region is an active trench, and an active gate is provided inside the trench. The active trench can extend the active gate of the insulated gate bipolar transistor region 103 from the first main surface 101 to the first drift layer 201. The active gate is electrically connected to the gate pad 11 of the semiconductor device 100, so that the active gate and the gate pad 11 can have the same electric potential.

[0053] In the active trench, the active gate is spaced apart from the inner wall of the active trench, an active gate insulating film is provided between the active gate and the active trench, and the active gate is arranged opposite to the emitter region 12, the base layer 3 and the first drift layer 201 through the active gate insulating film, so as to ensure the normal operation of the insulated gate bipolar transistor region 103.

[0054] In the semiconductor device 100 of the embodiment of the present invention, trenches 5 are provided in both the fast recovery diode region 104 and the transition region. The trenches 5 in this region are virtual trenches, and a virtual gate is provided inside the virtual trench. The virtual gate and the inner wall of the virtual trench are spaced apart, and a virtual gate insulating film is provided between the virtual gate and the virtual trench.

[0055] In an embodiment of the present invention, the collector layer 601 is disposed on the side of the first drift layer 201 facing the second main surface 102. The side of the collector layer 601 facing away from the drift layer 2 constitutes at least a portion of the second main surface 102. The collector layer 601 is located in the insulated gate bipolar transistor region 103. The cathode layer 602 is disposed on the side of the second drift layer 202 facing the second main surface 102. The side of the cathode layer 602 facing away from the drift layer 2 constitutes at least a portion of the second main surface 102. The cathode layer 602 is located in the fast recovery diode region 104. In this way, the basic structure of the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 can be formed.

[0056] According to an embodiment of the present invention, at the initial forward conduction stage of the reverse conducting insulated gate bipolar transistor, after the gate voltage opens the channel on the active gate side of the semiconductor device 100, carriers flow from the emitter region 12 of the first conductivity type along the first direction through the first region 1031, reach the side of the collector layer 601 close to the drift layer 2, and finally flow out from the cathode layer 602 in the fast recovery diode region 104. In this process, only electrons, one type of carrier, participate in the conduction. At this time, the reverse conducting insulated gate bipolar transistor is in a unipolar conduction state.

[0057] In the unipolar conduction state, a voltage drop will be generated along the carrier flow path. When this voltage drop is greater than the built-in potential of the PN junction formed by the collector layer 601 and the drift layer 2, the PN junction formed by the collector layer 601 of the second conductivity type and the first sub-drift layer 2011 of the first conductivity type in the drift layer 2 is turned on, and holes are injected from the collector layer 601 into the drift layer 2, and then flow out from the base layer 3 after passing through the drift layer 2. In this process, both electrons and holes participate in the conduction. At this time, the reverse conducting insulated gate bipolar transistor is in the bipolar conduction state.

[0058] During the transition between the unipolar conduction state and the bipolar conduction state of the reverse-conducting insulated gate bipolar transistor, a large amount of hole injection causes the reverse-conducting insulated gate bipolar transistor to produce a conductivity modulation effect, resulting in a decrease in the on-resistance of the semiconductor device 100. At this time, a negative resistance region exists in the current-voltage output characteristic curve of the semiconductor device 100, where the current increases and the voltage decreases. This phenomenon is called voltage foldback.

[0059] Furthermore, by setting a second sub-drift layer 2012 of the second conductive type in the second region 1032 of the insulated gate bipolar transistor region 103 near the first main surface 101, the area of ​​the effective drift region in the insulated gate bipolar transistor region 103 can be reduced, and more holes can be accumulated to attract the movement of electrons on the side of the collector layer 601 close to the drift layer 2, thereby making it easier to turn on the semiconductor device 100. As a result, the reverse conducting insulated gate bipolar transistor can be accelerated from the unipolar conduction state to the bipolar conduction state, thereby reducing or even eliminating the voltage foldback phenomenon.

[0060] Furthermore, when the semiconductor device 100 is forward-turned off, the blocking junction is reverse-biased, and the electric field is mainly borne by the blocking junction. At the same time, when turned off, the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 can assist in depleting carriers and reducing the peak electric field of the semiconductor device 100, thereby improving the reverse voltage resistance and breakdown voltage resistance of the semiconductor device 100.

[0061] Combine Figure 1As shown, when the semiconductor device 100 is subjected to a high voltage, the first drift sub-layer 2011 and the second drift sub-layer 2012 in the first region 1031 and the second region 1032 deplete each other, generating a lateral electric field. In an embodiment of the present invention, the boundary between the first drift sub-layer 2011 and the second drift sub-layer 2012 in the first region 1031 and the boundary between the first drift sub-layer 2011 and the second drift sub-layer 2012 in the second region 1032 are aligned. This arrangement ensures uniformity of the electric field in the IGBT region 103.

[0062] According to some embodiments of the present invention, Figure 1 As shown, the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 in the first direction are equal and are both D1, and the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 in the first direction are equal and are both D2, and D1 and D2 satisfy the relationship: D1=D2.

[0063] Specifically, under the condition that the boundary between the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 and the boundary between the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 are flush with each other, the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 in the first direction can be set to be equal, and the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 in the first direction can be set to be equal.

[0064] According to some other embodiments of the present invention, the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031 in the first direction may not be equal. Similarly, the depths of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 in the first direction may not be equal.

[0065] It should be noted that the blocking junction in the first region 1031 bears the main electric field, and the depth of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first direction can be specifically set according to the electric field distribution calculation, and it is still necessary to make the junction of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the second region 1032 flush with the junction of the first sub-drift layer 2011 and the second sub-drift layer 2012 in the first region 1031.

[0066] Furthermore, the size of the first region 1031 in the second direction and the size of the second region 1032 in the second direction can be specifically set based on the electric field distribution calculation to ensure that the active trench extends from the first main surface 101 to the first region 1031 in the first direction, so that the active trench is arranged opposite to the first sub-drift layer 2011 in the first region 1031 to ensure that the electron flow channel in the insulated gate bipolar transistor region is normally opened.

[0067] Combine Figure 1 As shown, the semiconductor device 100 further includes a first dielectric isolation layer 8, which is disposed between the insulated gate bipolar transistor region 103 and the fast recovery diode region 104. The depth direction of the first dielectric isolation layer 8 extends from the second main surface 102 toward the first main surface 101. The first dielectric isolation layer 8 passes through between the collector layer 601 and the cathode layer 602 and reaches the drift layer 2. It should be noted that the depth direction of the first dielectric isolation layer 8 in the embodiment of the present invention is Figure 1 The first direction in

[0068] Specifically, after the gate voltage opens the channel, the carriers reach the side of the collector layer 601 close to the drift layer 2 from the emitter region 12. At this time, the first dielectric isolation layer 8 can block the carriers on the side of the collector layer 601 close to the drift layer 2 in the first direction from flowing to the side of the cathode layer 602 close to the drift layer 2. This can increase the resistance of the collector layer 601 on the side close to the drift layer 2 in the first direction, thereby increasing the voltage drop on the carrier flow path on the side of the collector layer 601 on the side close to the drift layer 2 in the first direction, and thus accelerate the bipolar conduction rate of the insulated gate bipolar transistor region 103, so that the insulated gate bipolar transistor region 103 quickly enters the bipolar conduction state from the unipolar conduction state, thereby reducing or even eliminating the voltage foldback phenomenon.

[0069] According to an embodiment of the present invention, the first dielectric isolation layer 8 is a silicon dioxide isolation layer. Specifically, providing the first dielectric isolation layer 8 with a silicon dioxide isolation layer can effectively block carriers on the side of the collector layer 601 near the drift layer 2 from flowing from the insulated gate bipolar transistor region 103 to the fast recovery diode region 104. This can increase the resistance of the side of the collector layer 601 near the drift layer 2 in the insulated gate bipolar transistor region 103, thereby increasing the voltage drop along the carrier flow path. This can further enable the semiconductor device 100 to quickly transition from unipolar conduction to bipolar conduction, thereby reducing or even eliminating voltage foldback in the semiconductor device 100.

[0070] Combine Figure 1As shown, the end of the first dielectric isolation layer 8 facing the first main surface 101 does not extend beyond the second sub-drift layer 2012 in the first region 1031 and the first sub-drift layer 2011 in the second region 1032. This configuration prevents the first dielectric isolation layer 8 from extending too deeply into the drift layer 2 in the first direction. This, on the one hand, ensures that the first dielectric isolation layer 8 has a blocking effect on the movement of carriers from the IGBT region 103 to the fast recovery diode region 104, thereby accelerating the device's transition to bipolar conduction compared to a reverse-conducting IGBT. On the other hand, if the first dielectric isolation layer 8 extends too deeply into the drift layer 2, the carrier concentration in the fast recovery diode region 104 may be overly limited, thereby interfering with the reverse recovery characteristics of the device. This not only reduces voltage foldback during forward conduction in the IGBT region 103, but also ensures normal reverse recovery of the fast recovery diode region 104.

[0071] Combine Figure 1 As shown, the semiconductor device 100 also includes a second dielectric isolation layer 9, the collector metal layer 7 includes a first collector metal layer 701 and a second collector metal layer 702, the first collector metal layer 701 is located in the insulated gate bipolar transistor region 103, the second collector metal layer 702 is arranged in the fast recovery diode region 104, and the first collector metal layer 701 and the second collector metal layer 702 are arranged at intervals.

[0072] Specifically, the first collector metal layer 701 is located in the insulated gate bipolar transistor region 103 to form the basic structure of the insulated gate bipolar transistor region 103. The second collector metal layer 702 is located in the fast recovery diode region 104 to form the basic structure of the fast recovery diode region 104. The second dielectric isolation layer 9 is disposed between the first collector metal layer 701 and the second collector metal layer 702 and corresponds to the first dielectric isolation layer 8.

[0073] According to some embodiments of the present invention, the second dielectric isolation layer 9 may be a silicon dioxide isolation layer. In this embodiment, the second dielectric isolation layer 9 and the first dielectric isolation layer 8 may be integrally formed or separately formed during the production process of the semiconductor device 100. It should be noted that in this embodiment, the first collector metal layer 701 and the second collector metal layer 702 in the semiconductor device 100 have the same potential.

[0074] According to other embodiments of the present invention, the second dielectric isolation layer 9 may be air. In this embodiment, after the first dielectric isolation layer 8 is formed, it constitutes at least a portion of the second main surface 102. A collector metal is then deposited on the second main surface 102, wherein the first collector metal layer 701 of the insulated gate bipolar transistor region 103 and the second collector metal layer 702 of the fast recovery diode region 104 are spaced apart in the second direction, and the portion of the second main surface 102 formed by the first dielectric isolation layer 8 is exposed to the collector metal layer 7. It should be noted that in this embodiment, the first collector metal layer 701 and the second collector metal layer 702 in the semiconductor device 100 have the same potential.

[0075] According to further embodiments of the present invention, the second dielectric isolation layer 9 may be a collector metal. In this embodiment, after the first dielectric isolation layer 8 is formed, it forms at least a portion of the second main surface 102. A collector metal is then deposited on the second main surface 102, where the collector metal covers the second main surface 102. The second dielectric isolation layer 9 integrally connects the first collector metal layer 701 and the second collector metal layer 702. It should be noted that in this embodiment, the first collector metal layer 701 and the second collector metal layer 702 in the semiconductor device 100 have the same potential.

[0076] Combine Figure 1 As shown, the semiconductor device 100 further includes a floating layer 10 of the second conductivity type, which is disposed in the second drift layer 202. The depth direction of the floating layer 10 extends from the side of the second drift layer 202 adjacent to the second main surface 102 toward the first main surface 101, and the floating layer 10 is in contact with the cathode layer 602. It should be noted that the depth direction of the floating layer 10 in the embodiment of the present invention is Figure 1 The first direction in .

[0077] Specifically, when the semiconductor device 100 is forward-conducted, the floating layer 10 can provide an electron barrier to prevent electrons from flowing from the side of the collector layer 601 close to the drift layer 2 to the side of the cathode layer 602 close to the drift layer 2. This can concentrate the current on the collector layer 601, thereby increasing the resistance on the collector layer 601 and allowing the device to quickly enter bipolar conduction, thereby suppressing the voltage foldback phenomenon.

[0078] Furthermore, when the semiconductor device 100 reverse recovers, the floating layer 10 can also control the hole injection efficiency of the cathode layer 602 into the second drift layer 202, thereby improving the softness of the reverse conducting insulated gate bipolar transistor during the reverse recovery process and avoiding voltage overshoot during reverse recovery.

[0079] In an embodiment of the present invention, the doping concentration of the second conductive type floating layer 10 is low-concentration doping. This is because the doping concentration of the first conductive type second drift layer 202 in the fast recovery diode region 104 is also low-concentration doping. If the doping concentration of the floating layer 10 is too high, it will affect the opening of the fast recovery diode region 104.

[0080] Combine Figure 1 As shown, there are multiple floating layers 10, and the multiple floating layers 10 are spaced apart by the drift layer 2. In this way, the side of the cathode layer 602 facing the first main surface 101 can at least partially contact the second drift layer 202, so that there is a current gap in the fast recovery diode region 104. In this way, the cathode layer 602 can normally extract charge from the second drift layer 202 during the device shutdown process.

[0081] Combine Figure 1 As shown, one end of the first dielectric isolation layer 8 adjacent to the first main surface 101 protrudes beyond the end of the floating layer 10 adjacent to the first main surface 101. While the floating layer 10 is in contact with the cathode layer 602, a silicon dioxide isolation layer is provided between the fast recovery diode region 104 and the insulated gate bipolar transistor region 103. This prevents the floating layer 10 from contacting the cathode layer 602 and affecting the withstand voltage of the device.

[0082] The following combination Figure 2-13 A method for manufacturing the semiconductor device 100 according to an embodiment of the present invention will be described.

[0083] Combine Figure 2-13 As shown, a substrate for a semiconductor device 100 is provided, which includes a drift layer 2 of a first conductivity type. The substrate has a first main surface 101 and a second main surface 102 opposite to the first main surface 101. The first main surface 101 and the second main surface 102 are spaced apart in a first direction. The semiconductor device 100 is fabricated based on the substrate.

[0084] Furthermore, a groove 5 is etched on the substrate by a photolithography process, a gate oxide layer 1501 is first deposited in the groove 5 to cover the inner wall of the groove 5, and then a gate 15 metal is deposited in the groove 5. The gate 15 metal includes but is not limited to polysilicon.

[0085] Furthermore, ions of the second conductivity type are implanted into the drift layer 2 near the first main surface 101 to form a base layer 3. A carrier storage layer 14 is formed on a side of the drift layer 2 near the base layer 3.

[0086] Furthermore, ions of the first conductivity type are implanted on the base layer 3 to form an emitter region 12 . The emitter region 12 is located on at least one side of the trench 5 in the second direction and constitutes at least a portion of the first main surface 101 .

[0087] Furthermore, ions of the first conductive type are implanted on the base layer 3 to form a contact hole region 13 . The contact hole region 13 constitutes at least a portion of the first main surface 101 and is spaced apart from the trench 5 in the second direction.

[0088] Furthermore, a dielectric layer is deposited on the first main surface 101 of the substrate, and the dielectric layer is etched to form contact holes, a gate pad 11 and an emitter metal layer 4 at positions corresponding to the gate 15, the emitter region 12 and the contact hole region 13 on the dielectric layer, wherein the gate pad 11 is electrically connected to the active gate, and the emitter metal layer 4 is electrically connected to the emitter region 12.

[0089] Furthermore, etching is performed on the side of the substrate facing the second main surface 102 to form a trench between the insulated gate bipolar transistor region 103 and the fast recovery diode region 104 , and silicon dioxide is deposited in the trench to form a first dielectric isolation layer 8 .

[0090] Furthermore, ions of the second conductive type are implanted into the drift layer 2 corresponding to the IGBT region 103 and close to the second main surface 102 to form a buffer layer 16 on the side of the drift layer 2 close to the second main surface 102 in the IGBT region 103 .

[0091] Furthermore, ions of the second conductivity type are implanted into the first region 1031 of the insulated gate bipolar transistor region 103, near the fast recovery diode region 104, to form a second sub-drift layer 2012 in the first region 1031. Ions of the second conductivity type are then implanted into the first drift layer 201, away from the fast recovery diode region 104, to form a second sub-drift layer 2012 in the second region 1032. The second sub-drift layer 2012 in the first region 1031 forms a blocking junction with the first sub-drift layer 2011.

[0092] Furthermore, ions of the second conductivity type are implanted into the drift layer 2 in the fast recovery diode region 104 near the second main surface 102 to form a plurality of floating layers 10 that are spaced apart.

[0093] Furthermore, ions of the second conductivity type are implanted at a location on the second main surface 102 of the substrate corresponding to the insulated gate bipolar transistor region 103 to form a collector layer 601. The ion doping concentration of the collector layer 601 is higher than the ion doping concentration of the second drift sub-layer 2012. Ions of the first conductivity type are then implanted on the side of the floating layer 10 facing the second main surface 102 to form a cathode layer 602.

[0094] Furthermore, collector metal is deposited on the side of the second main surface 102 of the substrate away from the collector layer 601 to form a first collector metal layer 701 in the insulated gate bipolar transistor region 103 and a second collector metal layer 702 in the fast recovery diode region 104. Furthermore, silicon dioxide is deposited between the first collector metal layer 701 and the second collector metal layer 702 to form a second dielectric isolation layer 9. At this point, the second dielectric isolation layer 9 and the first dielectric isolation layer 8 form an integrated silicon dioxide isolation layer. At this point, the semiconductor device 100 according to the embodiment of the present invention is completed.

[0095] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0096] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0097] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate (1) having a first main surface (101) and a second main surface (102) opposite to the first main surface (101), wherein the first main surface (101) and the second main surface (102) are spaced apart in a first direction; A drift layer (2), the drift layer (2) being arranged on the semiconductor substrate (1) and located between the first main surface (101) and the second main surface (102), the semiconductor substrate (1) comprising an insulated gate bipolar transistor region (103) and a fast recovery diode region (104), the insulated gate bipolar transistor region (103) being circumferentially arranged outside the fast recovery diode region (104); The drift layer (2) comprises a first drift layer (201) and a second drift layer (202), the second drift layer (202) is of the first conductivity type and is located in the fast recovery diode region (104), the first drift layer (201) is located in the insulated gate bipolar transistor region (103) and comprises a first sub-drift layer (2011) of the first conductivity type and a second sub-drift layer (2012) of the second conductivity type, the insulated gate bipolar transistor region (103) comprises a first region (1031) and a second region (1032), the first region (1031) is adjacent to the fast recovery diode region (104), and the second region (1032) is away from the fast recovery diode region (104); The first sub-drift layer (2011) and the second sub-drift layer (2012) are provided in the first region (1031); the first sub-drift layer (2011) is closer to the first main surface (101) in a first direction than the second sub-drift layer (2012); The first sub-drift layer (2011) and the second sub-drift layer (2012) are also provided in the second region (1032); in the second region (1032), the second sub-drift layer (2012) is closer to the first main surface (101) in the first direction than the first sub-drift layer (2011); A base layer (3) of a second conductive type, the base layer (3) being arranged on a side of the drift layer (2) facing the first main surface (101), and a surface of the base layer (3) away from the drift layer (2) constituting a portion of the first main surface (101); an emitter metal layer (4), the emitter metal layer (4) being arranged on the first main surface (101); a groove (5), wherein the depth direction of the groove (5) penetrates the base layer (3) from the first main surface (101) and reaches the drift layer (2); the groove (5) is multiple, the multiple grooves (5) are spaced apart in the second direction, and at least one of the multiple grooves (5) extends into the first sub-drift layer (2011) of the first region (1031); a collector layer (601) of a second conductivity type and a cathode layer (602) of a first conductivity type, wherein the collector layer (601) is arranged on a side of the first drift layer (201) facing the second main surface (102), a side of the collector layer (601) away from the drift layer (2) constitutes at least a portion of the second main surface (102), and the collector layer (601) is located in the insulated gate bipolar transistor region (103); The cathode layer (602) is arranged on a side of the second drift layer (202) facing the second main surface (102), a side of the cathode layer (602) away from the drift layer (2) constitutes at least a portion of the second main surface (102), and the cathode layer (602) is located in the fast recovery diode region (104); A collector metal layer (7), the collector metal layer (7) being arranged on the second main surface (102).

2. The semiconductor device according to claim 1, wherein A boundary between the first sub-drift layer (2011) and the second sub-drift layer (2012) in the first region (1031) and a boundary between the first sub-drift layer (2011) and the second sub-drift layer (2012) in the second region (1032) are flush with each other.

3. The semiconductor device according to claim 2, wherein The depths of the first sub-drift layer (2011) and the second sub-drift layer (2012) in the first region (1031) in the first direction are equal and both are D1, and the depths of the first sub-drift layer (2011) and the second sub-drift layer (2012) in the second region (1032) in the first direction are equal and both are D2, and D1 and D2 satisfy the relationship: D1=D2.

4. The semiconductor device according to claim 1, wherein The invention also includes a first dielectric isolation layer (8), which is arranged between the insulated gate bipolar transistor region (103) and the fast recovery diode region (104), and the first dielectric isolation layer (8) extends from the second main surface (102) toward the first main surface (101) in a depth direction, and the first dielectric isolation layer (8) passes through between the collector layer (601) and the cathode layer (602) and reaches the drift layer (2).

5. The semiconductor device according to claim 4, wherein The first dielectric isolation layer (8) is a silicon dioxide isolation layer.

6. The semiconductor device according to claim 4, wherein One end of the first dielectric isolation layer (8) facing the first main surface (101) does not extend beyond the second sub-drift layer (2012) in the first region (1031) and the first sub-drift layer (2011) in the second region (1032).

7. The semiconductor device according to claim 4, wherein The invention also includes a second dielectric isolation layer (9), the collector metal layer (7) includes a first collector metal layer (701) and a second collector metal layer (702), the first collector metal layer (701) is located in the insulated gate bipolar transistor region (103), the second collector metal layer (702) is arranged in the fast recovery diode region (104), the first collector metal layer (701) and the second collector metal layer (702) are arranged at intervals, and the second dielectric isolation layer (9) is arranged between the first collector metal layer (701) and the second collector metal layer (702) and corresponds to the first dielectric isolation layer (8).

8. The semiconductor device according to claim 4, wherein The invention also includes a floating layer (10) of the second conductive type, wherein the floating layer (10) is arranged in the second drift layer (202), and the depth direction of the floating layer (10) extends from the side of the second drift layer (202) adjacent to the second main surface (102) toward the first main surface (101), and the floating layer (10) is in contact with the cathode layer (602).

9. The semiconductor device according to claim 8, wherein There are a plurality of floating layers (10), and the plurality of floating layers (10) are spaced apart by the drift layer (2).

10. The semiconductor device according to claim 8, wherein One end of the first dielectric isolation layer (8) adjacent to the first main surface (101) protrudes from one end of the floating layer (10) adjacent to the first main surface (101).

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