Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, which comprises a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure and a plurality of drain structures, wherein the plurality of source lines are located on the substrate, extend along a first direction and are arranged at intervals along a second direction; each source pad is located on a corresponding source line and extends along the second direction between adjacent source lines; the plurality of unit structures are arranged on the source pads along the first direction and the second direction and are connected to the source pads, and at least two unit structures which are staggered with each other in the first direction are located on the same source pad; the gate structure extends along the second direction and is connected to the unit structures located on the same source pad; and the plurality of drain structures are located above the corresponding source pads respectively, and each drain structure is connected to the unit structures connected to the corresponding source pad; and the application improves the electrical performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Semiconductor transistors (e.g., metal oxide semiconductor transistors (MOS transistors)) have been used in various applications, such as power supplies, power converters, and switches. Traditionally, MOS transistors utilize a planar structure. As semiconductor integrated circuit technology has evolved over time, MOS transistors have adopted a stacked structure to achieve transistor miniaturization. In a stacked structure design, several source lines are typically formed on a substrate, followed by a gate structure formed on the source lines. Several channel structures are formed within the gate structure, each of which is connected to the source line. A corresponding drain structure is formed on each channel structure, and each drain structure is connected to the source line via a channel structure. This results in limited driving capabilities for the semiconductor device, impacting its electrical performance. Summary of the Invention

[0003] The object of the present invention is to provide a semiconductor device and a method for preparing the same, so as to improve the electrical performance of the semiconductor device.

[0004] In order to achieve the above object, the present invention provides a semiconductor device comprising:

[0005] substrate;

[0006] a plurality of source lines located on the substrate, extending along a first direction and spaced apart from each other along a second direction;

[0007] a plurality of source pads, each of the source pads being located on a corresponding source line and extending along the second direction and being located between adjacent source lines;

[0008] a plurality of unit structures arranged along the first direction and the second direction on the source pad and connected to the source pad, wherein at least two of the unit structures that are offset from each other in the first direction are located on the same source pad;

[0009] a gate structure extending along the second direction and connecting the unit structures located on the same source pad;

[0010] A plurality of drain structures are respectively located above the corresponding source pads, and each of the drain structures is connected to the unit structure connected to the corresponding source pad.

[0011] Optionally, both ends of the source pad along the first direction are located on the source line, and both ends of the source pad along the second direction extend between adjacent source lines.

[0012] Optionally, the shape of the source pad includes a rhombus or a rectangle.

[0013] Optionally, a plurality of the source pads are arranged in an array, and two adjacent columns of the source pads are staggered along the second direction.

[0014] Optionally, the four unit structures are located on one source pad and are respectively located at four ends of the source pad.

[0015] Optionally, the gate structure includes a ring-shaped end.

[0016] Optionally, the gate structure includes a first portion and a second portion located on both sides of the unit structure along the first direction, and the first portion and the second portion are connected through the annular end portion.

[0017] Optionally, a gate dielectric layer and a barrier layer are provided between the gate structure and the unit structure, and a first isolation material layer is filled between several of the gate structures.

[0018] The present invention also provides a method for preparing a semiconductor device, comprising:

[0019] providing a substrate;

[0020] forming a plurality of source lines on the substrate, extending along a first direction and spaced apart from each other along a second direction;

[0021] forming a plurality of source pads, each of the source pads being located on a corresponding source line and extending along the second direction and being located between adjacent source lines;

[0022] forming a plurality of unit structures arranged along the first direction and the second direction on the source pad and connected to the source pad, wherein at least two of the unit structures offset from each other in the first direction are located on the same source pad;

[0023] forming a gate structure extending along the second direction and connecting the unit structures located on the same source pad; and

[0024] A plurality of drain structures are formed and located above the corresponding source pads, and each of the drain structures is connected to the unit structure connected to the corresponding source pad.

[0025] Optionally, the step of forming the unit structure includes:

[0026] forming a first sacrificial layer to at least cover the source pad;

[0027] Etching the first sacrificial layer to form a plurality of through holes, wherein the bottoms of the through holes expose the source pad;

[0028] forming a unit structure to fill the through hole;

[0029] The first sacrificial layer is removed by etching.

[0030] Optionally, the step of forming the gate structure includes:

[0031] forming a second sacrificial layer to at least cover the surface of the unit structure;

[0032] Etching and removing the second sacrificial layer on the top of the unit structure;

[0033] forming a first isolation material layer to fill between adjacent unit structures, with the top of the first isolation material layer flush with the top of the unit structure;

[0034] Etching the first isolation material layer to form a plurality of first openings penetrating the first isolation material layer;

[0035] removing the second sacrificial layer to form a second opening in the area where the second sacrificial layer is located;

[0036] forming a gate material layer to fill the first opening and the second opening;

[0037] The gate material layer is etched so that a top of the gate material layer is lower than a top of the unit structure, and the remaining gate material layer serves as the gate structure.

[0038] The semiconductor device and preparation method provided by the present invention include: a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure and a plurality of drain structures, wherein the plurality of source lines are located on the substrate, extend along a first direction and are arranged at intervals from each other along a second direction; each source pad is located on a corresponding source line and extends along the second direction and is located between adjacent source lines; a plurality of unit structures are arranged along the first direction and the second direction and are located on the source pad and connected to the source pad, and at least two unit structures that are staggered from each other in the first direction are located on the same source pad; the gate structure extends along the second direction and connects the unit structures located on the same source pad; a plurality of drain structures are respectively located above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad. In the present invention, a source pad is provided on the source line, the source pad extends along the second direction and is located between adjacent source lines, a plurality of unit structures are arranged along the first direction and the second direction and are located on the source pad and are connected to the source pad, and at least two unit structures that are offset from each other in the first direction are located on the same source pad, the gate structure is connected to the unit structures located on the same source pad, and each drain structure is connected to the unit structure connected to the corresponding source pad, so that each drain structure is connected to the corresponding source pad through multiple unit structures, which can increase the driving current of the semiconductor device and thus improve the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A top view of a semiconductor device provided in accordance with an embodiment of the present invention.

[0040] Figure 2 and Figure 3 A schematic cross-sectional view of a semiconductor device provided in accordance with an embodiment of the present invention.

[0041] Figures 4 to 45 Schematic diagram of corresponding steps of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0042] Wherein, the accompanying drawings are marked as follows:

[0043] 10-substrate; 20-source line; 20a-source pad; 31-second isolation material layer; 32-first isolation material layer; 33-third isolation material layer; 34-fourth isolation material layer; 41-isolation oxide layer; 42-protective layer; 43-gate dielectric layer; 50-etching stop layer; 61-first sacrificial layer; 62-through hole; 63-unit structure; 64-second sacrificial layer; 70-barrier layer; 71-first opening; 72-second opening; 80-gate material layer; 82-gate structure; 90-drain structure; 100-sidewall. DETAILED DESCRIPTION

[0044] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0045] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] Figure 1 A top view of the semiconductor device provided in this embodiment, Figure 2 and Figure 3 A schematic cross-sectional view of a semiconductor device provided in this embodiment, Figure 2 for Figure 1 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 3 for Figure 1 The cross-sectional diagram along the section line B1B2 is shown in the figure. Figure 1 In order to show the source line and gate structure, some structures are omitted and the drain structure is set to be transparent. Figures 1 to 3 This embodiment provides a semiconductor device including: a substrate 10, a plurality of source lines 20, a plurality of source pads 20a, a plurality of cell structures 63, a gate structure 82, and a plurality of drain structures 90. Substrate 10 may be, but is not limited to, a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate. In this embodiment, a dielectric layer (not shown) is further formed on substrate 10. Electrical connectors are formed in the dielectric layer, and the electrical connectors penetrate the dielectric layer to electrically connect to substrate 10 and source lines 20.

[0047] A plurality of source lines 20 are located on the substrate 10 (specifically, on the dielectric layer). The plurality of source lines 20 extend along a first direction D1 and are spaced apart from each other along a second direction D2. A second isolation material layer 31 is filled between adjacent source lines 20. In this embodiment, the source lines 20 may include a first source barrier layer, a source metal layer, a second source barrier layer, and a source semiconductor layer (not shown separately in the figure), stacked sequentially from bottom to top. The first source barrier layer and the second source barrier layer may each be made of TiN, the source metal layer may be made of W, and the source semiconductor layer may be made of polysilicon. The second isolation material layer 31 may be made of, but is not limited to, a low-k dielectric material, an oxide, a nitride, an oxynitride, and silicon oxycarbon nitride.

[0048] Each source pad 20a is located on the corresponding source line 20 and extends along the second direction D2 and is located between adjacent source lines 20. In this embodiment, the shape of the source pad 20a includes a rhombus or a rectangle ( Figure 1 The source pad in is blocked by the gate structure 82 and the drain structure 90. Figure 1 The source pad and the drain structure 90 have the same shape (both are diamond-shaped), but are not limited to this; both ends of the source pad 20a along the first direction D1 are located on the source line 20, and both ends of the source pad 20a along the second direction D2 extend between adjacent source lines 20. A number of source pads 20a are arranged in an array (specifically, a staggered array distribution), and two adjacent columns of source pads 20a are staggered along the second direction D2. In this embodiment, the source pad 20a is used for conductive connection, and the material of the source pad 20a may include polysilicon, but is not limited to this material. In this embodiment, an isolation oxide layer 41 is filled between the several source pads 20a, and the isolation oxide layer 41 is flush with the top of the source pad 20a.

[0049] Several unit structures 63 are arranged along the first direction D1 and the second direction D2 on the source pad 20a and connected to the source pad 20a, and at least two unit structures 63 that are offset from each other in the first direction D1 are located on the same source pad 20a. In this embodiment, four unit structures 63 are located on one source pad 20a, and the four unit structures 63 are respectively located at the four ends of the source pad 20a (two ends along the first direction D1 and two ends along the second direction D2, that is, at the four angles of the rhombus). Several unit structures 63 are also arranged in an array (specifically, a staggered array distribution), and two adjacent columns of unit structures 63 are staggered along the second direction D2. In this embodiment, the material of the unit structure 63 may include polysilicon (with doped ions), and may also include one or more combinations of metal silicide materials, ferroelectric materials, high-k dielectric materials, and indium gallium zinc oxide (IGZO), but is not limited to the above materials.

[0050] The gate structure 82 extends along the second direction D2 and connects to the unit structure 63 located on the same source pad 20a. In this embodiment, the gate structure 82 includes a ring-shaped end portion 82a ( Figure 1 The gate structure 82 includes a first portion 82b and a second portion 82c located on either side of the unit structure 63 along the first direction D1 (the left side of the unit structure 63 in the figure may be the first portion 82b, and the right side of the unit structure 63 may be the second portion 82c). The first portion 82b and the second portion 82c are connected by a ring-shaped end portion 82a. In this embodiment, the gate structure 82 may be a metal stack, such as TiN or W, but is not limited to these materials.

[0051] Furthermore, a gate dielectric layer 43 and a barrier layer 70 are disposed between the gate structure 82 and the cell structure 63. The gate dielectric layer 43 and the barrier layer 70 are sequentially disposed along the sidewalls of the cell structure 63, and a portion of the gate structure 82 is located on the gate dielectric layer 43 and the barrier layer 70. Furthermore, an etch-stop layer 50 is included, which covers the isolation oxide layer 41 and a portion of the source pad 20a. The gate dielectric layer 43 and the barrier layer 70 are located on the etch-stop layer 50, and a portion of the gate structure 82 is located on the etch-stop layer 50. In this embodiment, the material of the gate dielectric layer 43 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride; the barrier layer 70 may include titanium nitride; and the material of the etch-stop layer 50 may include silicon carbide, but is not limited to the above materials.

[0052] Furthermore, a first isolation material layer 32 and a third isolation material layer 33 are included. The first isolation material layer 32 is filled between adjacent gate structures 82. The top of the gate structure 82 is lower than the top of the cell structure 63. The second isolation material layer 33 is located on the gate structure 82, and the tops of the cell structure 63, the first isolation material layer 32, and the second isolation material layer 33 are flush. In this embodiment, the material of the first isolation material layer 32 and the third isolation material layer 33 may include one of a low-k dielectric material, an oxide, a nitride, an oxynitride, and a silicon oxycarbon nitride, but is not limited to the above materials.

[0053] Several drain structures 90 are respectively located above corresponding source pads 20a, and each drain structure 90 is connected to the unit structure 63 connected to the corresponding source pad 20a. In this embodiment, each drain structure 90 is connected to the corresponding source pad 20a through four unit structures 63. In this embodiment, the drain structure 90 includes a drain barrier layer and a drain metal layer (not shown) stacked sequentially from bottom to top. The material of the drain barrier layer may include TiN, and the material of the drain metal layer may include W, but is not limited to the above materials.

[0054] Furthermore, it also includes a side wall 100 and a fourth isolation material layer 34, the side wall 100 covers the side of the drain structure 90; the fourth isolation material layer 34 is filled between adjacent drain structures 90; the materials of the side wall 100 and the fourth isolation material layer 34 are different, the material of the side wall 100 may include silicon nitride, and the material of the fourth isolation material layer 34 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides and oxycarbon silicon nitride, but is not limited to the above materials.

[0055] In this embodiment, a source pad 20a is provided on the source line 20, the source pad 20a extends along the second direction D2 and is located between adjacent source lines 20, a plurality of unit structures 63 are arranged along the first direction D1 and the second direction D2 and are located on the source pad 20a and are connected to the source pad 20a, and at least two unit structures 63 that are staggered from each other in the first direction D1 are located on the same source pad 20a, the gate structure 82 is connected to the unit structures 63 located on the same source pad 20a, and each drain structure 90 is connected to the unit structure 63 connected to the corresponding source pad 20a, so that each drain structure 90 is connected to the corresponding source pad 20a through multiple unit structures 63, which can increase the driving current of the semiconductor device and thus improve the electrical performance of the semiconductor device.

[0056] This embodiment further provides a method for preparing a semiconductor device, which is used to prepare the above-mentioned semiconductor device, comprising:

[0057] Step S1: providing a substrate;

[0058] Step S2: forming a plurality of source lines on the substrate, extending along a first direction and spaced apart from each other along a second direction;

[0059] Step S3: forming a plurality of source pads, each of which is located on a corresponding source line and extends along the second direction between adjacent source lines;

[0060] Step S4: forming a plurality of unit structures, arranged along a first direction and a second direction on the source pad and connected to the source pad, wherein at least two unit structures offset from each other in the first direction are located on the same source pad;

[0061] Step S5: forming a gate structure extending along the second direction and connecting the unit structures located on the same source pad;

[0062] Step S6: forming a plurality of drain structures respectively located above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad.

[0063] Figures 4 to 45 Schematic diagram of the corresponding steps of the method for preparing the semiconductor device provided in this embodiment. Figures 4 to 45The method for manufacturing the semiconductor device provided in this embodiment is described in detail.

[0064] Please refer to Figures 4 to 6 , Figure 5 for Figure 4 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 6 for Figure 4 Schematic cross-section diagram along section line B1B2. Step S1 is performed: providing a substrate 10. Substrate 10 may be, but is not limited to, a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate. In this embodiment, a dielectric layer (not shown) is further formed on substrate 10. Electrical connectors are formed in the dielectric layer and extend through the dielectric layer to electrically connect to substrate 10 and source line 20.

[0065] Please refer to Figures 4 to 6 , perform step S2: form a plurality of source lines 20 on the substrate 10, wherein the plurality of source lines 20 extend along the first direction D1 and are spaced apart from each other along the second direction D2, and a second isolation material layer 31 is filled between adjacent source lines 20. The materials of the source lines 20 and the second isolation material layer 31 are as described above.

[0066] Please refer to Figures 4 to 6 , executing step S3: forming a plurality of source pads 20a, each source pad 20a being located on a corresponding source line 20 and extending along second direction D2 between adjacent source lines 20. Both ends of source pad 20a along first direction D1 are located on source line 20, and both ends of source pad 20a along second direction D2 extend between adjacent source lines 20. The plurality of source pads 20a are arranged in an array (specifically, a staggered array), with adjacent columns of source pads 20a staggered along second direction D2. The material of source pads 20a is as described above.

[0067] Executing step S4: the step of forming a unit structure includes:

[0068] Please refer to Figures 7 to 9 , Figure 8 for Figure 7 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 9 for Figure 7 The cross-sectional diagram along the section line B1B2 is shown in the figure. Figure 7Transparency is set for the first sacrificial layer 61, and some process layers are omitted. An isolation oxide layer 41 is formed to fill between the plurality of source pads 20a, with the tops of the isolation oxide layer 41 and the source pads 20a flush. An etch stop layer 50 is formed to cover the isolation oxide layer 41 and the source pads 20a. A first sacrificial layer 61 is formed to cover at least the source pads 20a. Specifically, due to the presence of the etch stop layer 50, the first sacrificial layer 61 covers the etch stop layer 50. The material of the first sacrificial layer 61 may include silicon nitride. The materials of the isolation oxide layer 41 and the etch stop layer 50 are as described above.

[0069] Please refer to Figures 10 to 12 , Figure 11 for Figure 10 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 12 for Figure 10 The first sacrificial layer 61 and the etch stop layer 50 are etched to form a plurality of through holes 62 , the bottoms of the through holes 62 exposing the source pad 20 a (exposing at least a portion of the top surface of the source pad 20 a ).

[0070] Please refer to Figures 13 to 15 , Figure 14 for Figure 13 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 15 for Figure 13 Schematic cross-sectional view along section line B1B2. A unit structure 63 is formed to fill the through hole 62, and several unit structures 63 are arranged along the first direction D1 and the second direction D2 on the source pad 20a and connected to the source pad 20a, and at least two unit structures 63 that are staggered with each other in the first direction D1 are located on the same source pad 20a. In this embodiment, four unit structures 63 are located on one source pad 20a, and the four unit structures 63 are respectively located at the four ends of the source pad 20a. Several unit structures 63 are also arranged in an array (specifically, a staggered array distribution), and two adjacent columns of unit structures 63 are staggered along the second direction D2; the material of the unit structure 63 is as described above.

[0071] For further information, please refer to Figures 16 to 18 , Figure 17 for Figure 16 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 18 for Figure 16 The cell structure 63 is etched so that the top of the cell structure 63 is lower than the top of the first sacrificial layer 61, and then a protective layer 42 is formed to cover the top of the cell structure 63 so that the protective layer 42 is flush with the top of the first sacrificial layer 61. The material of the protective layer 42 may include silicon oxide.

[0072] For further information, please refer to Figures 19 to 21 , Figure 20 for Figure 19 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 21 for Figure 19 The cross-sectional diagram along the section line B1B2 is shown in the figure. Figure 19 The first sacrificial layer 61 is removed by etching, exposing the sidewalls of the cell structure 63 and the surface of the etch stop layer 50 .

[0073] Executing step S5: the step of forming a gate structure includes:

[0074] Please refer to Figures 22 to 24 , Figure 23 for Figure 22 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 24 for Figure 22 The cross-sectional diagram along the section line B1B2 is shown in the figure. Figure 22 The second sacrificial layer 62 is transparent, and some process layers are omitted. The second sacrificial layer 62 is formed using a self-aligned process to at least cover the surface of the cell structure 63. Before forming the second sacrificial layer 62, a gate dielectric layer 43 and a barrier layer 70 are sequentially formed to cover the surface of the cell structure 63. The gate dielectric layer 43, barrier layer 70, and second sacrificial layer 62 extend to cover the surface of the etch stop layer 50 exposed by adjacent cell structures 63. The materials of the gate dielectric layer 43 and barrier layer 70 are as described above, and the material of the second sacrificial layer 62 may include silicon nitride.

[0075] Please refer to Figures 25 to 27 , Figure 26 for Figure 25 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 27 for Figure 25 The cross-sectional diagram along the section line B1B2 is shown in the figure. Figure 22 Some process layers are omitted. Portions of the gate dielectric layer 43, barrier layer 70, and second sacrificial layer 62 are etched to expose the etch stop layer 50 and the protective layer 42. After etching, the remaining gate dielectric layer 43, barrier layer 70, and second sacrificial layer 62 are disposed along the sidewalls of the cell structure 63.

[0076] Please refer to Figures 28 to 30 , Figure 29 for Figure 28 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 30 for Figure 28 A first isolation material layer 32 is formed to fill between adjacent unit structures 63. Due to the presence of the protective layer 42, the top of the first isolation material layer 32 is flush with the top of the protective layer 42. The material of the first isolation material layer 32 is as described above.

[0077] Please refer to Figures 31 to 33 , Figure 32 for Figure 31 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 33 for Figure 31 The cross-sectional diagram along the section line B1B2 is shown in the figure. Figure 31 The first isolation material layer 32 is etched to form a plurality of first openings 71 penetrating the first isolation material layer 32 . The first openings 71 are located on both sides of the second sacrificial layer 62 .

[0078] Please refer to Figures 34 to 36 , Figure 35 for Figure 34 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 36 for Figure 34 The cross-sectional diagram along the section line B1B2 is shown in the figure. Figure 31 The second sacrificial layer 62 is removed to form a second opening 72 in the area where the second sacrificial layer 62 is located. The first opening 71 and the second opening 72 are connected.

[0079] Please refer to Figures 37 to 39 , Figure 38 for Figure 37 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 39 for Figure 37 A gate material layer 80 is formed to fill the first opening 71 and the second opening 72 , and the top of the gate material layer 80 is flush with the top of the first isolation material layer 32 .

[0080] Please refer to Figures 40 to 42 , Figure 41 for Figure 40 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 42 for Figure 40 Schematic cross-section along section line B1B2. The gate material layer is etched until the top of the gate material layer is lower than the top of the cell structure 63. The remaining gate material layer serves as gate structure 82. Gate structure 82 extends along second direction D2 and connects to cell structure 63 located on the same source pad 20a. The material of gate structure 82 is as described above. Furthermore, a third isolation material layer 33 is formed to cover gate structure 82, first isolation oxide layer 32, and protective layer 42. The material of third isolation material layer 33 is as described above.

[0081] Please refer to Figures 43 to 45 , Figure 44 for Figure 43 The cross-sectional diagram along the section line A1A2 is shown in the figure. Figure 45 for Figure 43A cross-sectional view along section line B1B2 is shown in FIG. A portion of the third isolation material layer 33 , a portion of the first isolation oxide layer 32 , and the protective layer 42 are removed by etching to expose the top of the cell structure 63 . After etching, the third isolation material layer 33 , the first isolation oxide layer 32 , and the top of the cell structure 63 are flush.

[0082] Please refer to Figures 1 to 3 , execute step S6: form a plurality of drain structures 90 respectively located above the corresponding source pads 20a, and each drain structure 90 is connected to the unit structure 63 connected to the corresponding source pad 20a. In this embodiment, each drain structure 90 is connected to the corresponding source pad 20a through four unit structures 63, and the material of the drain structure 90 is as described above.

[0083] Furthermore, the process also includes forming a sidewall spacer 100 to cover the side surfaces of the drain structure 90 , and forming a fourth isolation material layer 34 to fill between adjacent drain structures 90 ; the materials of the sidewall spacer 100 and the fourth isolation material layer 34 are as described above.

[0084] In summary, the semiconductor device and the preparation method thereof provided by the present invention include: a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure and a plurality of drain structures, wherein the plurality of source lines are located on the substrate, extend along the first direction and are arranged at intervals from each other along the second direction; each source pad is located on the corresponding source line and extends along the second direction and is located between adjacent source lines; a plurality of unit structures are arranged along the first direction and the second direction and are located on the source pad and are connected to the source pad, and at least two unit structures that are staggered from each other in the first direction are located on the same source pad; the gate structure extends along the second direction and is connected to the unit structures located on the same source pad; a plurality of drain structures are respectively located above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad. In the present invention, a source pad is provided on the source line, the source pad extends along the second direction and is located between adjacent source lines, a plurality of unit structures are arranged along the first direction and the second direction and are located on the source pad and are connected to the source pad, and at least two unit structures that are offset from each other in the first direction are located on the same source pad, the gate structure is connected to the unit structures located on the same source pad, and each drain structure is connected to the unit structure connected to the corresponding source pad, so that each drain structure is connected to the corresponding source pad through multiple unit structures, which can increase the driving current of the semiconductor device and thus improve the electrical performance of the semiconductor device.

[0085] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; a plurality of source lines located on the substrate, extending along a first direction and spaced apart from each other along a second direction; a plurality of source pads, each of the source pads being located on a corresponding source line and extending along the second direction and being located between adjacent source lines; a plurality of unit structures arranged along the first direction and the second direction on the source pad and connected to the source pad, wherein at least two of the unit structures that are offset from each other in the first direction are located on the same source pad; a gate structure extending along the second direction and connecting the unit structures located on the same source pad; A plurality of drain structures are respectively located above the corresponding source pads, and each of the drain structures is connected to the unit structure connected to the corresponding source pad; The sidewalls cover the side surfaces of the drain structure.

2. The semiconductor device according to claim 1, wherein Both ends of the source pad along the first direction are located on the source line, and both ends of the source pad along the second direction extend between adjacent source lines.

3. The semiconductor device according to claim 2, wherein The source pad has a shape of a rhombus or a rectangle.

4. The semiconductor device according to claim 1, wherein The source pads are arranged in an array, and two adjacent rows of source pads are staggered along the second direction.

5. The semiconductor device according to claim 2, wherein The four unit structures are located on one source pad and are respectively located at four ends of the source pad.

6. The semiconductor device according to claim 1, wherein The gate structure includes a ring-shaped end portion.

7. The semiconductor device according to claim 6, wherein The gate structure includes a first portion and a second portion located on both sides of the unit structure along the first direction, and the first portion and the second portion are connected through the annular end portion.

8. The semiconductor device according to claim 1, wherein A gate dielectric layer and a barrier layer are provided between the gate structure and the unit structure, and a first isolation material layer is filled between a plurality of the gate structures.

9. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a plurality of source lines on the substrate, extending along a first direction and spaced apart from each other along a second direction; forming a plurality of source pads, each of the source pads being located on a corresponding source line and extending along the second direction and being located between adjacent source lines; forming a plurality of unit structures arranged along the first direction and the second direction on the source pad and connected to the source pad, wherein at least two of the unit structures offset from each other in the first direction are located on the same source pad; forming a gate structure extending along the second direction and connecting the unit structures located on the same source pad; and A plurality of drain structures are formed and located above the corresponding source pads, and each of the drain structures is connected to the unit structure connected to the corresponding source pad.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The steps of forming the unit structure include: forming a first sacrificial layer to at least cover the source pad; Etching the first sacrificial layer to form a plurality of through holes, wherein the bottoms of the through holes expose the source pad; forming a unit structure to fill the through hole; The first sacrificial layer is removed by etching.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: The steps of forming the gate structure include: forming a second sacrificial layer to at least cover the surface of the unit structure; Etching and removing the second sacrificial layer on the top of the unit structure; forming a first isolation material layer to fill between adjacent unit structures, with the top of the first isolation material layer flush with the top of the unit structure; Etching the first isolation material layer to form a plurality of first openings penetrating the first isolation material layer; removing the second sacrificial layer to form a second opening in the area where the second sacrificial layer is located; forming a gate material layer to fill the first opening and the second opening; The gate material layer is etched so that a top of the gate material layer is lower than a top of the unit structure, and the remaining gate material layer serves as the gate structure.

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