Storage unit, memory and preparation method thereof

Abstract

The present disclosure relates to a memory cell, a memory and a method for preparing the same. The memory cell includes a write transistor and a read transistor. The write transistor includes: a first gate, a first source, a first drain and a channel body located between the first source and the first drain; wherein the first gate is connected to a write word line, the first source is connected to a source line, and the first drain is connected to a write bit line. The read transistor includes: a second gate, a second source and a second drain; the second gate is connected to a read word line, the second drain is connected to a read bit line, and the second source is coupled to the channel body of the write transistor. The present disclosure can improve the sensing margin and data retention function of the memory cell, thereby improving the storage performance of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a storage unit, a memory and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of a number of memory cells arranged in an array. The memory cell may adopt a 1T1C architecture, for example, comprising a transistor and a capacitor.

[0003] At present, with the increasing demand for memory storage capacity, memory cells are beginning to be arranged in three-dimensional space. In addition, in order to overcome the scalability problem of DRAM using 1T1C architecture memory cells and the problem of complex process, the latest technology has proposed and studied the application of floating body effect in DRAM. For example, the memory cell can adopt a 1T0C (i.e., including one transistor and zero capacitors) architecture, and the mainstream transistor in the 1T0C architecture is a floating body transistor (FBC), which can be applied to 3D-DRAM.

[0004] However, floating-body transistors also have some problems, such as having a lower body potential and a lower sensing margin, which easily leads to a shorter read time after programming. Summary of the Invention

[0005] Based on this, the embodiments of the present disclosure provide a storage unit, a memory and a method for manufacturing the same, which are beneficial to improving the sensing margin and data retention function of the storage unit, thereby improving the storage performance of the memory.

[0006] In one aspect, embodiments of the present disclosure provide a memory cell comprising a write transistor and a read transistor. The write transistor comprises a first gate, a first source, a first drain, and a channel body located between the first source and the first drain; wherein the first gate is connected to a write word line, the first source is connected to a source line, and the first drain is connected to a write bit line. The read transistor comprises a second gate, a second source, and a second drain; the second gate is connected to a read word line, the second drain is connected to a read bit line, and the second source is coupled to the channel body of the write transistor.

[0007] According to some embodiments, the channel body includes: a first channel and a floating body. The first channel is provided in the same layer as the first source and the first drain. The floating body is located below the first channel and is integrally connected to the first channel. The first gate is located on a side of the first channel facing away from the floating body.

[0008] According to some embodiments, the write transistor further includes a first auxiliary latch layer located below the first source and the first drain, respectively, and located on a sidewall of the floating body.

[0009] According to some embodiments, the first auxiliary latch layer includes a silicon nitride layer.

[0010] According to some embodiments, the second source is located below the floating body. The write transistor further includes: a second auxiliary latch layer located below the first auxiliary latch layer and between the floating body and the second source.

[0011] According to some embodiments, the second auxiliary latching layer includes a silicon oxynitride layer.

[0012] According to some embodiments, the second source is located between the substrate and the floating body, and orthographic projections of the second source and the floating body on the substrate overlap.

[0013] According to some embodiments, a read transistor includes: a first semiconductor layer disposed on a substrate; wherein the second source and the second drain are respectively different regions of the first semiconductor layer; the first semiconductor layer also includes a second channel located between the second source and the second drain; and a second gate located on a side of the second channel facing away from the substrate.

[0014] According to some embodiments, the thickness of the second gate is the same as the thickness of the first gate.

[0015] According to some embodiments, a gap is formed between the second gate and a channel body of the write transistor, and a height of the channel body is less than or equal to a thickness of the second gate.

[0016] On the other hand, an embodiment of the present disclosure further provides a memory, comprising: a substrate and one or more storage units arranged on the substrate and as described in any of the above embodiments.

[0017] On the other hand, an embodiment of the present disclosure further provides a method for preparing a memory, comprising the following steps.

[0018] A substrate is provided, and a first semiconductor layer is formed on the substrate. The first semiconductor layer includes a second source and a second drain of a read transistor located in different regions, and a second channel located between the second source and the second drain.

[0019] A second gate of the read transistor is formed above the second channel.

[0020] A second semiconductor layer is formed above the second source electrode. The second semiconductor layer includes a first source electrode and a first drain electrode of the write transistor and a channel body located between the first source electrode and the first drain electrode.

[0021] A first gate of the write transistor is formed above the channel body.

[0022] According to some embodiments, before forming the second gate of the read transistor above the second channel, the method for manufacturing the memory further includes: forming a first auxiliary latch layer above the first semiconductor layer.

[0023] Correspondingly, the forming of the second gate of the read transistor above the second channel includes the following steps.

[0024] A first trench is formed in the first auxiliary latching layer above the second channel.

[0025] A second gate is formed filling the first trench.

[0026] According to some embodiments, the method for preparing the memory further includes the following steps.

[0027] Before forming the first auxiliary latch layer above the first semiconductor layer, a second auxiliary latch layer is formed on the upper surface of the first semiconductor layer; wherein the first auxiliary latch layer is formed on the upper surface of the second auxiliary latch layer.

[0028] A second trench is formed in the second auxiliary latch layer above the second channel.

[0029] A second gate oxide layer is formed to fill the second trench; wherein the second gate is formed on the upper surface of the second gate oxide layer.

[0030] According to some embodiments, forming the second semiconductor layer above the second source electrode includes the following steps.

[0031] A third trench parallel to the first trench is formed in the first auxiliary latching layer; a gap is formed between the third trench and the first trench.

[0032] The first auxiliary latching layer located above the second trench in the third trench is etched back to form a floating body receiving groove. The bottom surface of the floating body receiving groove exposes the upper surface of the second auxiliary latching layer.

[0033] A second semiconductor layer is formed to fill the floating body receiving groove and the third trench.

[0034] According to some embodiments, the method for preparing the memory further includes the following steps.

[0035] After forming a first gate of the write transistor above the channel body, ion implantation is performed on a first source and a first drain of the second semiconductor layer exposed at both sides of the first gate.

[0036] According to some embodiments, a material of the first semiconductor layer includes: a metal oxide semiconductor or polysilicon, and a material of the second semiconductor layer includes polysilicon.

[0037] According to some embodiments, the method for preparing the memory further includes the following steps.

[0038] A write word line connected to the first gate is formed.

[0039] A source line connected to the first source is formed.

[0040] A write bit line connected to the first drain is formed.

[0041] A read word line connected to the second gate is formed.

[0042] A read bit line connected to the second drain is formed.

[0043] The embodiments of the present disclosure may have / have at least the following advantages:

[0044] In an embodiment of the present disclosure, the memory cell adopts a 2T0C architecture based on the floating body effect, and the channel body in the write transistor is coupled to the second source of the read transistor, and the potential of the second source of the read transistor can be changed by the potential of the channel body in the write transistor. For example, the channel body in the write transistor includes a first channel and a floating body located below the first channel, and the floating body is integrally connected to the first channel, which can effectively accumulate carriers based on the floating body effect and have a higher carrier accumulation amount (that is, it can have a higher potential), thereby increasing the sensing margin of the memory cell. At the same time, the embodiment of the present disclosure can achieve data retention and further improve the data retention function of the memory cell by reasonably controlling the turn-on voltage of the read transistor. From the above, the embodiment of the present disclosure is conducive to effectively improving the storage performance of the memory.

[0045] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 is a schematic diagram of an equivalent circuit of a memory cell provided in some embodiments;

[0048] Figure 2 A schematic structural diagram of a storage unit provided in some embodiments;

[0049] Figure 3 is a schematic structural diagram of a write transistor provided in some embodiments;

[0050] Figure 4 A schematic diagram of current flow in a memory cell provided in some embodiments;

[0051] Figure 5 A schematic flow chart of a method for preparing a memory provided in some embodiments;

[0052] Figure 6 A schematic flow chart of another method for preparing a memory provided in some embodiments;

[0053] Figure 7 A schematic flow chart of another method for preparing a memory provided in some embodiments;

[0054] Figure 8 A schematic structural diagram of a structure obtained after forming a first semiconductor layer provided in some embodiments;

[0055] Figure 9 A schematic structural diagram of a structure obtained after forming a second auxiliary latch layer provided in some embodiments;

[0056] Figure 10 A schematic structural diagram of a structure obtained after forming a first auxiliary latch layer provided in some embodiments;

[0057] Figure 11 A schematic structural diagram of a structure obtained after forming a first trench and a second trench provided in some embodiments;

[0058] Figure 12 A schematic structural diagram of a structure obtained after forming a second gate provided in some embodiments;

[0059] Figure 13 A schematic structural diagram of a structure obtained after forming a third trench and a floating body receiving groove provided in some embodiments;

[0060] Figure 14 is a schematic structural diagram of a structure obtained after forming a second semiconductor layer provided in some embodiments;

[0061] Figure 15 A schematic structural diagram of another structure obtained after forming a second semiconductor layer provided in some embodiments;

[0062] Figure 16 A schematic structural diagram of the relative positional relationship between a floating body and a first channel in a second semiconductor layer provided in some embodiments;

[0063] Figure 17 A schematic structural diagram of a structure obtained after forming a first gate provided in some embodiments;

[0064] Figure 18 A schematic structural diagram of a structure obtained after forming a first source electrode and a first drain electrode provided in some embodiments;

[0065] Figure 19 is a schematic structural diagram of a structure obtained after forming a write word line, a source line, a write bit line, a read word line, and a read bit line, provided in some embodiments; and Figure 19 It is also a structural diagram of a memory provided in some embodiments.

[0066] Description of reference numerals:

[0067] Tw-write transistor, Tr-read transistor;

[0068] 11-first gate, 12-first source, 13-first drain, 14-channel body, 141-first channel, 142-floating body, 15-first gate oxide layer, 16-first auxiliary latch layer, 17-second auxiliary latch layer;

[0069] 21 - second gate, 22 - second source, 23 - second drain, 24 - second channel, 25 - second gate oxide layer;

[0070] G1-first groove, G2-second groove, G3-third groove, Gf-floating body receiving groove;

[0071] 3-base, 31-silicon substrate, 32-silicon oxide layer; L1-first semiconductor layer, L2-second semiconductor layer; 4-insulating layer;

[0072] WWL-write word line, WBL-write bit line, WSL-source line, RWL-read word line, RBL-read bit line. DETAILED DESCRIPTION

[0073] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0075] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0076] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0077] It should be understood that when describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The terms "coupled" and "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact; alternatively, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other.

[0078] Furthermore, while embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present disclosure.

[0079] The present disclosure provides a memory cell and memory that can utilize a 2TOC architecture to facilitate stacking and expansion of the memory cell and reduce manufacturing complexity. Furthermore, the memory cell and memory provided by the present disclosure can have a high sensing margin and data retention capability, thereby improving the memory's storage performance.

[0080] See also Figure 1 and Figure 2 Some embodiments of the present disclosure provide a memory cell comprising a write transistor Tw and a read transistor Tr.

[0081] For example, the write transistor Tw and the read transistor Tr may both be N-type transistors, or both be P-type transistors, or alternatively, one of the write transistor Tw and the read transistor Tr may be an N-type transistor and the other may be a P-type transistor.

[0082] In some embodiments, the write transistor Tw includes: a first gate 11, a first source 12, a first drain 13, and a channel body 14 located between the first source 12 and the first drain 13; wherein the first gate 13 is connected to the write word line WWL, the first source 12 is connected to the source line WSL, and the first drain 13 is connected to the write bit line WBL.

[0083] Here, the channel body 14 is a component of the write transistor Tw, which can write and store data. The channel body 14 is, for example, a semiconductor bulk structure that can generate a floating body effect in response to a control signal.

[0084] For example, please combine Figure 2 and Figure 3 It is understood that the channel body 14 includes a first channel 141 and a floating body 142. The first channel 141 is provided in the same layer as the first source 12 and the first drain 13. The floating body 142 is located below the first channel 141 and is integrally connected to the first channel 141. The first gate 11 is located on the side of the first channel 141 facing away from the floating body 142; that is, the first gate 11 is located above the first channel 141.

[0085] In some embodiments, the read transistor Tr includes a second gate 21, a second source 22, and a second drain 23. The second gate 21 is connected to the read word line RWL, the second drain 23 is connected to the read bit line RBL, and the second source 22 is coupled to the channel body 14 of the write transistor Tw.

[0086] Here, combined with Figure 1It can be understood that the second source 22 and the channel body 14 of the write transistor Tw are coupled, which means that the second source 22 and the channel body 14 of the write transistor Tw can interact with each other (for example, after the potential of the channel body 14 is changed, the potential of the second source 22 changes accordingly), and does not mean that the two are directly contacted and connected; that is, other layer structures need to be provided between the second source 22 and the channel body 14 of the write transistor Tw, such as the second auxiliary latch layer 17 or other insulating layer mentioned later.

[0087] In the embodiment of the present disclosure, the memory cell adopts a 2T0C architecture based on the floating body effect, and the channel body 14 in the write transistor Tw is coupled to the second source 22 of the read transistor Tr, and the potential of the second source 22 in the read transistor Tr can be changed by the potential of the channel body 14 in the write transistor Tw. In addition, the channel body 14 in the write transistor Tw includes a first channel 141 and a floating body 142 located below the first channel 141. The floating body 142 is integrally connected to the first channel 141, and can effectively accumulate carriers based on the floating body effect and have a higher carrier accumulation amount (that is, it can have a higher potential), thereby increasing the sensing margin of the memory cell. At the same time, the embodiment of the present disclosure can achieve data retention and further improve the data retention function of the memory cell by reasonably controlling the turn-on voltage of the read transistor Tr. From the above, the embodiment of the present disclosure is conducive to effectively improving the storage performance of the memory.

[0088] In addition, the storage unit and memory in the embodiments of the present disclosure can use a gate-induced drain leakage (GIDL) mechanism as the main storage mechanism (i.e., perform data writing) to ensure that the storage unit and memory can have lower power consumption and a larger sensing margin.

[0089] For example, during a data write operation, the voltages of the read word line RWL and the read bit line RBL are 0, and the read transistor Tr is inoperative. The write word line WWL provides a first gate voltage. Simultaneously, by controlling the voltages of the source line WSL and the write bit line WBL, carriers can be accumulated or not accumulated in the floating body 142 of the channel body 14, thereby implementing data writing.

[0090] It is understood that the type of carriers that can be accumulated in the floating body 142 is related to the type of semiconductor material used. For example, if the floating body 142 is formed of an N-type semiconductor material, the carriers that can be accumulated in the floating body 142 are holes. Figure 3 and Figure 4 In the figure, the floating body 142 is used as an example to illustrate the accumulation of holes. In addition, to match the different written data, for example, data "1" and data "0", the first gate voltage provided by the write word line WWL can be different, and the voltage provided by the write bit line WBL can also be different.

[0091] For example, when controlling the voltages of the read word line RWL and the read bit line RBL to perform a data read operation, if no carriers are accumulated in the floating body 142 of the write transistor Tw channel 14, the read transistor Tr reads no current or only a very small current, which is considered to be the read data "0". If carriers are accumulated in the floating body 142 of the write transistor Tw channel 14, the second source 22 of the read transistor Tr is equivalent to being forward biased, and the read transistor Tr reads a significant current change, which is considered to be the read data "1".

[0092] It should be added that, in some of the above embodiments, the first channel 141 in the channel body 14 is arranged in the same layer as the first source 12 and the first drain 13. Specifically, the first channel 141 and the first source 12 and the first drain 13 are different regions of the same semiconductor layer; that is, the first channel 141 and the first source 12 and the first drain 13 use the same semiconductor material and are formed in the same layer position (the layer position refers to the number of film layers along the film layer stacking direction, for example). In addition, the floating body 142 in the above-mentioned channel body 14 is located below the first channel 141 and is integrally connected to the first channel 141. Specifically, the floating body 142 and the first channel 141 are formed of the same semiconductor material, and the floating body 142 can be a protruding area downward from the layer where the first source 12 and the first drain 13 of the first channel 141 are located.

[0093] also, Figure 2 and Figure 3 Although a dashed line is used to demarcate the first channel 141 and the floating body 142 in the channel body 14, the location of the dashed line does not necessarily represent the boundary between the first channel 141 and the floating body 142. The actual boundary between the first channel 141 and the floating body 142 is determined by the actual working space boundary between the two during operation. This is not specifically limited in the present embodiment.

[0094] In some embodiments, please refer to Figure 2 and Figure 3 The first gate 11 is located on a side of the first channel 141 away from the floating body 142 ; the write transistor Tw further includes a first gate oxide layer 15 located between the first gate 11 and the first channel 141 .

[0095] By way of example, the first gate oxide layer 15 includes but is not limited to a silicon oxide layer.

[0096] In some embodiments, please refer to Figure 2 and Figure 3 The write transistor Tw further includes a first auxiliary latch layer 16 located below the first source 12 and the first drain 13 and on the sidewalls of the floating body 142 .

[0097] By way of example, the first auxiliary latching layer 16 includes, but is not limited to, a silicon nitride layer.

[0098] In the embodiment of the present disclosure, a first auxiliary latching layer 16 is formed below the first source 12 and the first drain 13 to cover the sidewalls of the floating body 142. The first auxiliary latching layer 16 can be used to effectively enhance the carrier latching capability of the floating body 142, thereby effectively improving the sensing margin and data retention capability of the storage unit.

[0099] In some embodiments, the second source 22 is located below the floating body 142 . The write transistor Tw further includes a second auxiliary latch layer 17 located below the first auxiliary latch layer 16 and between the floating body 142 and the second source 22 .

[0100] Illustratively, the second auxiliary latching layer 17 includes a silicon oxynitride layer.

[0101] Here, the second auxiliary latch layer 17 may be a silicon oxide layer that has been nitrided; that is, a silicon oxide layer is first formed above the second source 22 , and then the silicon oxide layer is nitrided to obtain the second auxiliary latch layer 17 .

[0102] As described above, the second auxiliary latch layer 17 provided in the embodiment of the present disclosure is located below the first auxiliary latch layer 16 and between the floating body 142 and the second source 22, which can further enhance the carrier latching capability of the floating body 142 while enhancing the coupling effect between the second source 22 of the read transistor Tr and the floating body 142.

[0103] In some examples, the thickness of the second auxiliary latching layer 17 is less than the thickness of the first auxiliary latching layer 16. For example, the thickness of the second auxiliary latching layer 17 is less than or equal to half the thickness of the first auxiliary latching layer 16. In the embodiment of the present disclosure, while ensuring that the floating body 142 can effectively latch carriers, the thickness of the second auxiliary latching layer 17 can be set as thin as possible to further enhance the coupling effect between the second source 22 of the read transistor Tr and the floating body 142.

[0104] In some embodiments, see Figure 3 and Figure 4 The second source electrode 22 is located between the substrate and the floating body 142. The orthographic projections of the second source electrode 22 and the floating body 142 on the substrate overlap.

[0105] Here, the substrate is located below the second source 22, that is, the side of the second source 22 facing away from the floating body 142. Figures 2 to 4 Although the substrate is not shown in the figure, it can be understood that the substrate serves as a carrier of the storage unit, and the storage unit provided in the above embodiment of the present disclosure can be directly prepared on the substrate.

[0106] In addition, the orthographic projections of the second source 22 and the floating body 142 on the substrate overlap, which can be specifically manifested as: the orthographic projection of the second source 22 on the substrate and the orthographic projection of the floating body 142 on the substrate partially overlap, or the orthographic projection of the floating body 142 on the substrate is located within the range of the orthographic projection of the second source 22 on the substrate.

[0107] In some embodiments, see Figure 2 and Figure 4 It is understood that the read transistor Tr includes a first semiconductor layer L1 disposed on a substrate; wherein the second source electrode 22 and the second drain electrode 23 are respectively different regions of the first semiconductor layer L1. The first semiconductor layer L1 also includes a second channel 24 located between the second source electrode 22 and the second drain electrode 23. The second gate 21 is located on the side of the second channel 24 facing away from the substrate.

[0108] It will be appreciated that in the disclosed embodiment, the channel body 14 of the write transistor Tw is coupled to the second source 22 of the read transistor Tr. Combined with the aforementioned structure of the write transistor Tw, the extension direction of the first semiconductor layer L1 in the read transistor Tr can intersect, for example, be orthogonal to, the extension direction of the second semiconductor layer (i.e., the semiconductor layer containing the first source 12, the first channel 141, and the second drain 13) in the write transistor Tw. This helps improve the space utilization of the memory cell.

[0109] In some embodiments, the material of the first semiconductor layer L1 includes metal oxide semiconductor or polysilicon, and the material of the second semiconductor layer includes polysilicon.

[0110] In some embodiments, the thickness of the second gate 21 is the same as that of the first gate 11. This makes it easy to determine the voltages corresponding to the read word line RWL and the write word line WWL, so as to properly control the turn-on operations of the write transistor Tw and the read transistor Tr.

[0111] In some embodiments, a gap is provided between the second gate 21 and the channel body 14 of the write transistor Tw. By properly setting the gap between the second gate 21 and the channel body 14 of the write transistor Tw, the disclosed embodiments can effectively reduce the parasitic capacitance between the second gate 21 and the channel body 14, thereby eliminating or preventing the adverse effects of the parasitic capacitance on the storage of the floating body 142 in the channel body 14.

[0112] In some embodiments, the height of the channel body 14 is less than or equal to the thickness of the second gate 21 .

[0113] In some embodiments, the first gate 11 , the second gate 21 , the write word line WWL, the source line WSL, the write bit line WBL, the read word line RWL, and the read bit line RBL may be formed of conductive materials, such as metal materials.

[0114] For example, the materials of the first gate 11, the second gate 21, the write word line WWL, the source line WSL, the write bit line WBL, the read word line RWL and the read bit line RBL can be one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.

[0115] In some embodiments, the write word line WWL, the source line WSL, the write bit line WBL, the read word line RWL, and the read bit line RBL may have a columnar structure and extend outward in a direction perpendicular to the substrate.

[0116] Some embodiments of the present disclosure further provide a memory, comprising: a substrate and one or more memory cells disposed on the substrate and as described in any of the above embodiments. The structure of the memory can be understood in conjunction with the structure obtained in the subsequent memory manufacturing method.

[0117] Furthermore, the memory provided by the embodiments of the present disclosure includes, but is not limited to, DRAM. Furthermore, the memory can be used, but is not limited to, to manufacture various types of storage devices, such as solid-state drives (SSDs), universal serial bus (USB) drives, memory cards, and the like.

[0118] The present disclosure also provides a method for preparing a memory device, for use in preparing the memory device and memory unit described in some of the aforementioned embodiments. This method also possesses the technical advantages of the aforementioned memory device and memory unit. Furthermore, the method provided by the present disclosure is simple and easy to implement, and it also helps improve the production efficiency and yield of the memory device.

[0119] See also Figure 5 , some embodiments of the present disclosure provide a method for preparing a memory, comprising the following steps.

[0120] S100 , providing a substrate, and forming a first semiconductor layer on the substrate. The first semiconductor layer includes: a second source and a second drain of a read transistor located in different regions, and a second channel located between the second source and the second drain.

[0121] S200 , forming a second gate of the read transistor above the second channel.

[0122] S300 , forming a second semiconductor layer above the second source electrode. The second semiconductor layer includes: a first source electrode and a first drain electrode of the write transistor, and a channel body located between the first source electrode and the first drain electrode.

[0123] S400 , forming a first gate of a write transistor above the channel body.

[0124] In some embodiments, see Figure 6 Before executing step S200 to form the second gate of the read transistor above the second channel, the method for preparing the memory further includes step S140.

[0125] S140 , forming a first auxiliary latch layer above the first semiconductor layer.

[0126] Accordingly, step S200 forms a second gate of the read transistor above the second channel, including the following steps.

[0127] S201 , forming a first trench in a first auxiliary latching layer above the second channel.

[0128] S202 , forming a second gate filling the first trench.

[0129] In some embodiments, see Figure 7 The memory preparation method further includes the following steps S110 to S130.

[0130] S110 , forming a second auxiliary latch layer on the upper surface of the first semiconductor layer.

[0131] S120 , forming a second trench in the second auxiliary latch layer above the second channel.

[0132] S130, forming a second gate oxide layer filling the second trench;

[0133] Accordingly, step S140 may be performed as follows: forming a first auxiliary latching layer on the upper surface of the second auxiliary latching layer.

[0134] Accordingly, step S200 may be performed as follows: forming a second gate on the upper surface of the second gate oxide layer.

[0135] In some embodiments, please refer to Figure 7 In step S300, a second semiconductor layer is formed above the second source electrode, including the following steps.

[0136] S301 , forming a third trench parallel to the first trench in the first auxiliary latching layer; a gap is formed between the third trench and the first trench.

[0137] S302: Carve back the first auxiliary latch layer located above the second source electrode in the third trench to form a floating body receiving groove. The bottom surface of the floating body receiving groove exposes the upper surface of the second auxiliary latch layer.

[0138] S303 , forming a second semiconductor layer filling the floating body receiving groove and the third trench.

[0139] In some embodiments, please refer to Figure 7 After performing step S400 to form a first gate of the write transistor above the channel body, the method for preparing the memory further includes step S500.

[0140] S500 , performing ion implantation on the first source and the first drain of the second semiconductor layer exposed at both sides of the first gate.

[0141] In some embodiments, please refer to Figure 7 The memory preparation method further includes the following steps S610 to S650.

[0142] S610 , forming a write word line connected to the first gate.

[0143] S620 , forming a source line connected to the first source.

[0144] S630 , forming a write bit line connected to the first drain.

[0145] S640 , forming a read word line connected to the second gate.

[0146] S650 , forming a read bit line connected to the second drain.

[0147] It is worth mentioning that in some of the above embodiments, the material of the first semiconductor layer includes metal oxide semiconductor or polysilicon, and the material of the second semiconductor layer includes polysilicon.

[0148] It should be understood that although the above Figures 5 to 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figures 5 to 7 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0149] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 8 to 19 Understand some embodiments of the present disclosure.

[0150] In step S100, refer to Figure 8A substrate 3 is provided, and a first semiconductor layer L1 is formed on the substrate 3. The first semiconductor layer L1 includes a second source 22 and a second drain 23 of a read transistor Tr located in different regions, and a second channel 24 located between the second source 22 and the second drain 23.

[0151] For example, the substrate 3 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof to form one or more layers. For example, the substrate 3 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. The disclosed embodiments do not limit the type, number of layers, etc. of the substrate 1.

[0152] In some examples, such as Figure 8 As shown in FIG, the base 3 includes a silicon substrate 31 and a silicon oxide layer 32 located on the upper surface of the silicon substrate 31. The first semiconductor layer L1 can be formed on the upper surface of the silicon oxide layer 32 to be insulated from the silicon substrate 31 by the silicon oxide layer 32.

[0153] In some examples, the first semiconductor layer L1 may be formed of polysilicon or metal oxide semiconductor materials, including but not limited to IGZO (Indium Gallium Zinc Oxide).

[0154] It should be added that, in some embodiments, to match the distribution positions of the storage units in the memory, the first semiconductor layer L1 is a semiconductor pattern layer, that is, the first semiconductor layer L1 is formed by a patterning process to be used for correspondingly preparing the second source 22, the second channel 24 and the second drain 23 in each storage unit.

[0155] In step S110, refer to Figure 9 , a second auxiliary latch layer 17 is formed on the upper surface of the first semiconductor layer L1.

[0156] By way of example, the second auxiliary latching layer 17 includes but is not limited to a silicon oxynitride layer.

[0157] For example, the second auxiliary latch layer 17 can be obtained by first depositing silicon oxide and then nitriding the silicon oxide.

[0158] For example, the second auxiliary latching layer 17 may also cover the entire upper surface of the first semiconductor layer L1 to reduce the number of processing times of the patterning process.

[0159] In step S140, refer to Figure 10 , forming a first auxiliary latching layer 16 above the first semiconductor layer L1 ; specifically, forming the first auxiliary latching layer 16 on the upper surface of the second auxiliary latching layer 17 .

[0160] By way of example, the first auxiliary latching layer 16 includes, but is not limited to, a silicon nitride layer.

[0161] For example, the first auxiliary latching layer 16 may also cover the entire upper surface of the second auxiliary latching layer 17 to reduce the number of processing times of the patterning process.

[0162] In step S120 and step S201, please refer to Figure 11 A second trench G2 is formed in the second auxiliary latching layer 17 above the second channel 24 , and a first trench G1 is formed in the first auxiliary latching layer 16 above the second channel 24 .

[0163] For example, the first trench G1 and the second trench G2 may be formed through one patterning process.

[0164] For example, the first trench G1 and the second trench G2 are connected and extend through the first auxiliary latching layer 16 and the second auxiliary latching layer 17 in a direction perpendicular to the substrate 3 (e.g., the Z direction). The bottom of the second trench G2 exposes the upper surface of the second channel 24. The first trench G1 and the second trench G2 can extend in the Y direction, for example.

[0165] In step S130, refer to Figure 12 , forming a second gate oxide layer 25 filling the second trench G2.

[0166] By way of example, the second gate oxide layer 25 includes but is not limited to a silicon oxide layer.

[0167] For example, the thickness of the second gate oxide layer 25 may be the same as the thickness of the second auxiliary latch layer 17 .

[0168] In step S202, please continue to refer to Figure 12 , forming the second gate 21 of the read transistor Tr above the second channel 24 , specifically, forming the second gate 21 filling the first trench G1 on the upper surface of the second gate oxide layer 25 .

[0169] For example, the material of the second gate 21 can be one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In Ti O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0170] In step S301, please refer to Figure 13A third trench G3 is formed in the first auxiliary latching layer 16 parallel to the first trench G1 . That is, the third trench G3 may extend along the Y direction, for example. Furthermore, a gap exists between the third trench G3 and the first trench G1 .

[0171] In step 302, please continue to refer to Figure 13 The first auxiliary latching layer 16 located above the second channel 24 in the third trench G3 is etched back to form a floating body receiving groove Gf. The bottom surface of the floating body receiving groove Gf exposes the upper surface of the second auxiliary latching layer 17.

[0172] In step 303, refer to Figure 14 , forming a second semiconductor layer L2 filling the floating body receiving groove Gf and the third trench G3.

[0173] Illustratively, the second semiconductor layer L2 includes but is not limited to a polysilicon layer.

[0174] It is understood that in other embodiments, see Figure 15 After forming the second gate 21, silicon nitride material can be further deposited to form a first auxiliary latch layer 16 that also covers the upper surface of the second gate 21, and then the aforementioned third trench G3 and floating body accommodating groove Gf are formed in the first auxiliary latch layer 16, and a second semiconductor layer L2 is formed to fill the third trench G3 and the floating body accommodating groove Gf.

[0175] In some of the above embodiments, the channel body 14 in the second semiconductor layer L2 includes a first channel 141 and a floating body 142. The first channel 141 is located at the same height as the first source 12 and the first drain 13, and the floating body 142 can be located below the first channel 141. The floating body 142 can be a protruding area downward from the layer where the first channel 141, the first source 12 and the first drain 13 are located (that is, the part filled in the floating body accommodating groove Gf).

[0176] It should be noted that, in some examples, the thickness of the second auxiliary latching layer 17 is less than the thickness of the first auxiliary latching layer 16. For example, the thickness of the second auxiliary latching layer 17 is less than or equal to half the thickness of the first auxiliary latching layer 16. In the disclosed embodiment, while ensuring that the floating body 142 can effectively latch carriers, the thickness of the second auxiliary latching layer 17 can be set as thin as possible to further enhance the coupling effect between the second source 22 of the read transistor Tr and the floating body 142.

[0177] In step S400, refer to Figure 17 , a first gate 11 of the write transistor Tw is formed above the channel body 14 .

[0178] For example, the material of the first gate 11 can be one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In Ti O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0179] In step S500, refer to Figure 18 , ion implantation is performed on the first source 22 and the first drain 23 of the second semiconductor layer L2 exposed on both sides of the first gate 11 .

[0180] For example, the first source 22 and the first drain 23 may be N-type doped polysilicon layers. The doping concentration of the N-type doping element in the first source 22 and the first drain 23 may be 1E20 / cm 3 ~1E21 / cm 3 N-type doping elements include, for example, Group V elements, such as phosphorus or arsenic.

[0181] In steps S610 to S650, please refer to Figure 19 , an insulating layer 4 can be formed to cover the exposed surfaces of the first gate 11 and the first auxiliary latch layer 16, and then through holes can be formed in the insulating layer 4 at positions corresponding to the first gate 11, the first source 12, the first drain 13, the second gate 21, and the second drain 23 to expose the surfaces of the corresponding layers. Finally, a conductive material can be filled in each through hole to obtain a write word line WWL connected to the first gate 11, a source line WSL connected to the first source 12, a write bit line WBL connected to the first drain 13, a read word line RWL connected to the second gate 21, and a read bit line RBL connected to the second drain 23.

[0182] For example, the write word line WWL, the source line WSL, the write bit line WBL, the read word line RWL, and the read bit line RBL can be formed of a metal material, such as tungsten or copper. Alternatively, the material of the write word line WWL, the source line WSL, the write bit line WBL, the read word line RWL, and the read bit line RBL can be one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), InTiO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0183] For example, the insulating layer 4 may be formed of oxide or nitride, such as silicon oxide or silicon nitride; or other insulating materials may be used.

[0184] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0185] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0186] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, and all such variations and improvements fall within the scope of protection of the present disclosure.

Claims

1. A storage unit, characterized in that: include: The write transistor is located on the substrate and includes: a first gate, a first source, a first drain, and a channel body located between the first source and the first drain; wherein the first gate is connected to a write word line, the first source is connected to a source line, and the first drain is connected to a write bit line; The read transistor is located on the substrate and includes: a second gate, a second source, a second drain, and a second channel body located between the second source and the second drain; the second gate is connected to the read word line, the second drain is connected to the read bit line, the second source is coupled to the channel body of the write transistor, and the second gate is located on a side of the second channel facing away from the substrate.

2. The storage unit according to claim 1, wherein The channel body comprises: a first channel, provided in the same layer as the first source and the first drain; a floating body, located below the first channel and integrally connected to the first channel; The first gate is located on a side of the first channel away from the floating body.

3. The storage unit according to claim 2, wherein: The write transistor further includes a first auxiliary latch layer located below the first source and the first drain, respectively, and located on a sidewall of the floating body.

4. The storage unit according to claim 3, wherein: The first auxiliary latching layer includes a silicon nitride layer.

5. The storage unit according to claim 3, wherein: The second source is located below the floating body; The write transistor further includes a second auxiliary latch layer located below the first auxiliary latch layer and between the floating body and the second source. The storage unit according to claim 5 , wherein: The second auxiliary latching layer includes a silicon oxynitride layer.

7. The storage unit according to claim 2, wherein: The second source is located between the substrate and the floating body; the orthographic projections of the second source and the floating body on the substrate overlap.

8. The storage unit according to claim 7, wherein: The read transistor includes: a first semiconductor layer disposed on the substrate; wherein, The second source electrode and the second drain electrode are respectively different regions of the first semiconductor layer; The first semiconductor layer further includes a second channel located between the second source electrode and the second drain electrode.

9. The storage unit according to claim 8, wherein: The thickness of the second gate is the same as that of the first gate.

10. The storage unit according to claim 8, wherein There is a gap between the second gate and the channel body of the write transistor; and a height of the channel body is less than or equal to a thickness of the second gate.

11. A memory, characterized in that: include: A substrate and one or more memory cells according to any one of claims 1 to 10, disposed on the substrate.

12. A method for preparing a memory, characterized in that: include: providing a substrate, and forming a first semiconductor layer on the substrate; The first semiconductor layer includes: a second source and a second drain of the read transistor located in different regions, and a second channel located between the second source and the second drain; forming a second gate of the read transistor above the second channel; forming a second semiconductor layer above the second source; the second semiconductor layer comprising: a first source and a first drain of a write transistor, and a channel body located between the first source and the first drain, wherein the second source is coupled to the channel body of the write transistor; A first gate of the write transistor is formed above the channel body.

13. The method for preparing a memory according to claim 12, wherein: The method further includes forming a first auxiliary latch layer on the first semiconductor layer before forming the second gate of the read transistor on the second channel; The step of forming a second gate of the read transistor above the second channel includes: forming a first trench in the first auxiliary latch layer above the second channel; The second gate is formed to fill the first trench.

14. The method for preparing a memory according to claim 13, wherein: Also includes: Before forming the first auxiliary latch layer above the first semiconductor layer, forming a second auxiliary latch layer on the upper surface of the first semiconductor layer; wherein the first auxiliary latch layer is formed on the upper surface of the second auxiliary latch layer; forming a second trench in the second auxiliary latch layer above the second channel; A second gate oxide layer is formed to fill the second trench; wherein the second gate is formed on the upper surface of the second gate oxide layer.

15. The method for preparing a memory according to claim 14, wherein: The forming of the second semiconductor layer above the second source electrode comprises: forming a third trench in parallel with the first trench in the first auxiliary latching layer; a gap is formed between the third trench and the first trench; Carving back the first auxiliary latching layer located above the second trench in the third trench to form a floating body receiving groove; the bottom surface of the floating body receiving groove exposes the upper surface of the second auxiliary latching layer; The second semiconductor layer is formed to fill the floating body receiving groove and the third trench.

16. The method for preparing a memory according to claim 12, wherein: Also includes: After forming the first gate of the write transistor above the channel body, ion implantation is performed on the first source and the first drain of the second semiconductor layer exposed at both sides of the first gate.

17. The method for preparing a memory according to claim 12, wherein: The material of the first semiconductor layer includes metal oxide semiconductor or polysilicon; the material of the second semiconductor layer includes polysilicon.

18. The method for preparing a memory according to any one of claims 12 to 17, wherein: Also includes: forming a write word line connected to the first gate; forming a source line connected to the first source; forming a write bit line connected to the first drain; forming a read word line connected to the second gate; A read bit line connected to the second drain is formed.

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