Organic light emitting diode display

Abstract

Disclosed is an organic light emitting diode display. The semiconductor device comprises a substrate, a semiconductor layer, a first insulating layer, a first conductor, a second insulating layer and a second conductor, wherein the semiconductor layer is positioned on the substrate and comprises a doped region and an undoped region; the first insulating layer covers the semiconductor layer; the first conductor is positioned on the first insulating layer; the third insulating layer covers the second conductor, the third conductor is located on the third insulating layer, the undoped region comprises a channel of the transistor, and the doped region comprises a first electrode and a second electrode of the transistor. A gate electrode of the driving transistor overlaps with a channel of the driving transistor and a part of a first electrode of a first fourth transistor arranged in the doped region, a previous scan line overlaps a second electrode of a first fourth transistor and a first electrode of a second fourth transistor arranged in the doped region and a channel of the first fourth transistor and a channel of the second fourth transistor arranged in the undoped region.

Description

[0001] This application is a divisional application of an invention patent application with an application date of June 6, 2019, application number 201910491292.6, and the name of the invention being “Organic Light Emitting Diode Display Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] Korean Patent Application No. 10-2018-0065631, filed on June 7, 2018 in the Korean Intellectual Property Office and entitled “ORGANIC LIGHT emitting diode display device”, is hereby incorporated by reference in its entirety. Technical Field

[0004] The present disclosure relates to organic light emitting diode displays. Background Art

[0005] A display device is a device that displays an image, and recently, an organic light emitting diode display has received attention. Since the organic light emitting diode display has a self-emission characteristic and does not require a separate light source, it is possible to reduce its thickness and weight, unlike a liquid crystal display device. In addition, the organic light emitting diode display has high quality characteristics such as low power consumption, high brightness, and high response speed. Summary of the invention

[0006] An organic light emitting diode display according to an exemplary embodiment may include: a substrate; a semiconductor layer, the semiconductor layer being located on the substrate; a first insulating layer, the first insulating layer covering the semiconductor layer; a first conductor, the first conductor being located on the first insulating layer; a second insulating layer, the second insulating layer covering the first conductor; a second conductor, the second conductor being located on the second insulating layer; a third insulating layer, the third insulating layer covering the second conductor; and a third conductor, the third conductor being located on the third insulating layer, wherein the semiconductor layer includes a doped region and an undoped region, the undoped region includes a channel of a driving transistor, a channel of a second transistor, a channel of a first fourth transistor, and a channel of a second fourth transistor, the doped region includes a first electrode and a second electrode of the driving transistor, a first electrode and a second electrode of the second transistor, a first electrode and a second electrode of the first fourth transistor, and a first electrode and a second electrode of the second fourth transistor, and the first conductor includes a driving transistor a gate electrode of a transistor, a scan line and a previous scan line, the third conductor includes a data line, the second transistor is electrically connected to the scan line and the data line, the second electrode of the second transistor is directly connected to the first electrode of the driving transistor, the first fourth transistor and the second fourth transistor are electrically connected to the previous scan line, the gate electrode of the driving transistor is directly connected to the first electrode of the first fourth transistor, the gate electrode of the driving transistor overlaps with a channel of the driving transistor and a portion of the first electrode of the first fourth transistor arranged in a doped region of the semiconductor layer in a plan view, and the previous scan line overlaps with the second electrode of the first fourth transistor arranged in the doped region of the semiconductor layer, the first electrode of the second fourth transistor arranged in the doped region of the semiconductor layer, the channel of the first fourth transistor arranged in an undoped region of the semiconductor layer, and the channel of the second fourth transistor arranged in the undoped region of the semiconductor layer in a plan view.

[0007] The second electrode of the first fourth transistor, the first electrode of the second fourth transistor, the channel of the first fourth transistor, and the channel of the second fourth transistor respectively have a straight line structure extending in one direction.

[0008] The previous scan line includes an extension region covering the second electrode of the first fourth transistor, the first electrode of the second fourth transistor, the channel of the first fourth transistor, and the channel of the second fourth transistor.

[0009] The semiconductor layer further includes a first extension, the first insulating layer includes a first opening exposing the first extension, and the gate electrode of the driving transistor is directly connected to the first extension through the first opening.

[0010] The second conductor includes a sustain line having an extended portion, and the gate electrode of the drive transistor forms a storage capacitor together with the extended portion of the sustain line overlapping the gate electrode of the drive transistor and a second insulating layer located between the gate electrode of the drive transistor and the extended portion of the sustain line.

[0011] A driving voltage is applied to the sustain line.

[0012] The third conductor further includes a driving voltage line including an extended portion, and the extended portion of the driving voltage line is directly connected to the sustaining line through an opening in the third insulating layer.

[0013] The organic light emitting diode display further includes a third transistor including a first third transistor and a second third transistor connected in series, wherein the extended portion of the driving voltage line covers at least a portion of a connection portion of the first third transistor and the second third transistor.

[0014] The connection portion is located in an undoped region of the semiconductor layer.

[0015] The semiconductor layer has a structure in which the semiconductor layer passes through the channel of the second third transistor and then bends to the left while extending upward, and then bends downward and passes through the channel of the first third transistor, and the scan line overlaps the channel of the second third transistor and the channel of the first third transistor.

[0016] The first extension of the semiconductor layer is arranged downstream of the channel passing through the first third transistor.

[0017] The semiconductor layer passes through the channel of the first third transistor and then bends to the left, and then sequentially meets the channel of the first fourth transistor and the channel of the second fourth transistor while bending upward again.

[0018] The first conductor further includes an initialization voltage line, the semiconductor layer further includes a second extension, the first insulating layer includes a second opening exposing the second extension, the initialization voltage line is directly connected to the second extension through the second opening, and the second extension is a part of the second electrode of the second fourth transistor.

[0019] The third conductor further includes a driving voltage line, and one pixel includes an organic light emitting element that emits light, a second transistor that receives a data voltage from the data line, and a driving transistor that applies current to the organic light emitting element.

[0020] The first conductor further includes a light emission control line, and the pixel further includes a fifth transistor and a sixth transistor connected to the light emission control line.

[0021] The pixel further includes: a first third transistor and a second third transistor connected in series; and a first fourth transistor and a second fourth transistor connected in series.

[0022] An organic light emitting diode display according to an exemplary embodiment may include a substrate, a semiconductor layer arranged on the substrate, a first insulating layer covering the semiconductor layer, a first conductor arranged on the first insulating layer, a second insulating layer covering the first conductor, a second conductor arranged on the second insulating layer, a third insulating layer covering the second conductor, and a third conductor arranged on the third insulating layer, wherein the semiconductor layer includes a doped region and an undoped region, and in the semiconductor layer overlapping the first conductor, the doped region is arranged between the undoped regions.

[0023] A channel of the (4-1)th transistor and a channel of the (4-2)th transistor may be respectively arranged in undoped regions arranged at opposite sides of a doped region, and an electrode of the (4-1)th transistor and an electrode of the (4-2)th transistor may be arranged in the doped region.

[0024] The first electrode of the (4-2)th transistor and the second electrode of the (4-1)th transistor may be disposed in the doping region.

[0025] The semiconductor layer including the undoped regions and the doped regions disposed between the undoped regions may have a straight line structure extending in one direction.

[0026] The first conductor may include a previous scan line, and the previous scan line may include an extension region covering the doped region and the undoped region.

[0027] The semiconductor layer may further include an extension, the first insulating layer may include an opening exposing the extension, and the first conductor may be directly connected to the extension through the opening.

[0028] The first conductor may be a gate electrode of a driving transistor.

[0029] The second conductor may include a sustain line having an extended portion, and the gate electrode of the driving transistor may form a storage capacitor together with the extended portion of the sustain line overlapping the gate electrode of the driving transistor and a second insulating layer arranged between the gate electrode of the driving transistor and the extended portion of the sustain line.

[0030] The sustain line may be applied with a driving voltage.

[0031] The third conductor may include a driving voltage line including an expansion portion, and the expansion portion of the driving voltage line may be directly connected to the sustain line through an opening formed in the third insulating layer.

[0032] The extended portion of the driving voltage line may cover at least a portion of a connection portion of the (3-1)th transistor and the (3-2)th transistor connected in series.

[0033] The connection portion may be disposed in the semiconductor layer and be undoped.

[0034] The first conductor may further include a scan line, the semiconductor layer may have a structure in which the semiconductor layer passes through the channel of the (3-2)th transistor and then bends to the left while extending upward, and then bends downward and passes through the channel of the (3-1)th transistor, and the scan line may overlap with the channel of the (3-2)th transistor and the channel of the (3-1)th transistor.

[0035] The extension of the semiconductor layer is arranged after passing through the channel of the (3-1)th transistor.

[0036] The semiconductor layer may pass through the channel of the (3-1)th transistor and then bend to the left, and may then sequentially meet the channel of the (4-1)th transistor and the channel of the (4-2)th transistor while bending upward again.

[0037] The semiconductor layer may further include a second extension, the first insulating layer may include an opening exposing the second extension, and the first conductor may be directly connected to the second extension through the opening.

[0038] The first conductor is an initialization voltage line.

[0039] The first conductor may include a scan line, a previous scan line and an initialization voltage line, the third conductor includes a data line and a driving voltage line, and one pixel includes an organic light emitting element that emits light, a second transistor connected to the scan line and the data line, and a driving transistor that applies current to the organic light emitting element.

[0040] The first conductor may further include a light emission control line, and the pixel may further include fifth and sixth transistors connected to the light emission control line.

[0041] The pixel may further include a (3-1)th transistor and a (3-2)th transistor connected in series and a (4-1)th transistor and a (4-2)th transistor connected in series.

[0042] A method for manufacturing an organic light emitting diode display according to an exemplary embodiment may include: forming a semiconductor layer on a substrate; forming a doping mask on the semiconductor layer and doping the semiconductor layer; removing the doping mask; forming a first insulating layer covering the semiconductor layer; forming a first conductor on the first insulating layer; doping the semiconductor layer by using the first conductor as a mask; forming a second insulating layer covering the first conductor; forming a second conductor on the second insulating layer; forming a third insulating layer covering the second conductor; forming a third conductor on the third insulating layer; forming a passivation layer covering the third conductor; and forming a pixel electrode on the passivation layer.

[0043] Forming the semiconductor layer on the substrate may include forming an amorphous silicon layer by using a first mask, and then crystallizing the amorphous silicon layer into a polycrystalline semiconductor.

[0044] Forming a doping mask on the semiconductor layer and doping the semiconductor layer may include forming the doping mask by using a second mask, and then doping the exposed semiconductor layer with impurities.

[0045] In removing the doping mask, the doping mask may be removed by using a stripper.

[0046] Forming the first insulating layer covering the semiconductor layer may include forming an opening at the first insulating layer by using a third mask.

[0047] In forming the first conductor on the first insulating layer, the first conductor may be formed by using a fourth mask.

[0048] The first conductor may include a scan line, a previous scan line, a light emitting control line, an initialization voltage line, and a gate electrode.

[0049] In forming the second conductor on the second insulating layer, the second conductor may be formed by using a fifth mask.

[0050] The second conductor may include a sustain line including an expansion portion serving as the first storage electrode.

[0051] Forming a third insulating layer covering the second conductor may include forming an opening at the third insulating layer by using a sixth mask.

[0052] The opening formed by the sixth mask may include an opening also formed in the first insulating layer, and the second insulating layer is disposed under the third insulating layer.

[0053] The openings in the first, second, and third insulating layers may expose a portion of the semiconductor layer, and the semiconductor layer may receive a data voltage or a driving voltage, or a driving current may be applied, through the exposed portion of the semiconductor layer.

[0054] The opening formed by the sixth mask may include an opening formed only in the third insulating layer, and the opening formed by the sixth mask may expose an expansion of the sustain line serving as the first storage electrode.

[0055] In forming the third conductor on the third insulating layer, the third conductor may be formed by using a seventh mask.

[0056] The third conductor may include a data line, a driving voltage line, and a data connection.

[0057] Forming a passivation layer covering the third conductor may include forming an opening at the passivation layer by using an eighth mask.

[0058] Forming the pixel electrode on the passivation layer may include forming the pixel electrode by using a ninth mask.

[0059] The manufacturing method may further include forming a partition wall surrounding the pixel electrode.

[0060] The manufacturing method may further include forming a buffer layer on the substrate before forming the semiconductor layer on the substrate.

[0061] The manufacturing method may further include forming a barrier layer on the substrate before forming the buffer layer on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0063] Figure 1 shows a layout diagram of an organic light emitting diode display according to an exemplary embodiment;

[0064] Figure 2 Shown along Figure 1 A cross-sectional view along line II-II;

[0065] Figures 3 to 16 Layout diagrams and cross-sectional views showing various stages in a method for manufacturing a pixel of an organic light emitting diode display according to an exemplary embodiment;

[0066] Fig.17 schematically illustrates a stacking relationship of pixels of an organic light emitting diode display according to an exemplary embodiment;

[0067] Fig.18 An enlarged view showing a fourth transistor of a pixel of an organic light emitting diode display according to an exemplary embodiment;

[0068] Fig.19 An equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment is shown;

[0069] Fig. 20 A timing diagram showing signals applied to a pixel of an organic light emitting diode display according to an exemplary embodiment;

[0070] Fig.21 A layout diagram of a pixel area in an organic light emitting diode display according to another exemplary embodiment is shown. DETAILED DESCRIPTION

[0071] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations to those skilled in the art.

[0072] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It will also be understood that when a layer or element is referred to as "on" another layer or substrate, the layer or element may be directly on another layer or substrate, or there may also be an intermediate layer. In addition, it should also be understood that when a layer is referred to as "between" two layers, the layer may be the only layer between the two layers, or there may also be one or more intermediate layers. On the contrary, when an element is referred to as "directly on" another element, there is no intermediate element. The wording "on" or "above" means being positioned on or below the object portion, and does not necessarily mean being positioned on the upper side of the object portion based on the direction of gravity. The same reference numerals always represent the same elements.

[0073] In addition, unless explicitly described to the contrary, the wording "comprise" and variations such as "comprises" or "comprising" will be understood to be intended to include the elements without excluding any other elements. Furthermore, in the present specification, the phrase "on a plane" means observing the target portion from the top, and the phrase "on a cross-section" means observing a cross-section formed by vertically cutting the target portion from the side.

[0074] In the following, reference will be made to Figure 1 and Figure 2 A pixel structure of an organic light emitting diode display according to an exemplary embodiment is described. Figure 1 is a layout diagram of an organic light emitting diode display according to an exemplary embodiment, and Figure 2 It is taken along line II-II Figure 1 Cross-sectional view of .

[0075] Reference Figure 1 , an organic light emitting diode (OLED) display according to an exemplary embodiment may include a scan line 151, a previous scan line 152, a light emission control line 153, and an initialization voltage line 157 extending substantially in a first direction X and transmitting a scan signal Sn, a previous scan signal Sn-1, a light emission control signal En, and an initialization voltage Vint, respectively. In addition, the OLED display includes a data line 171 and a driving voltage line 172 extending in a second direction Y intersecting the first direction X and transmitting a data voltage Dm and a driving voltage ELVDD, respectively.

[0076] Each pixel PX of the OLED display includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and an organic light emitting diode OLED (eg, Fig.19 ). Each of the third transistor T3 and the fourth transistor T4 includes a plurality of transistors that are connected and synchronously turned on by the same gate signal so that a signal input to the transistor on one side is output through the transistor on the other side, for example, the third transistor T3 has a structure including a first third transistor T3-1 and a second third transistor T3-2, and the fourth transistor T4 has a structure including a first fourth transistor T4-1 and a second fourth transistor T4-2. Hereinafter, such a connection structure will be referred to as a series connection structure.

[0077] exist Figure 1 and Figure 2 In the embodiment, the organic light emitting diode OLED is not shown, and the organic light emitting diode OLED is formed by a pixel electrode, an organic emission layer and a common electrode. The structure of the organic light emitting diode OLED is formed in Figure 1 and Figure 2 The connection relationship between the transistors (T1 to T7) that apply current to the organic light emitting diode OLED directly involves the area occupied by the pixel PX, and Figure 1 and Figure 2 This connection relationship is mainly shown.

[0078] In the present exemplary embodiment, in the OLED display, the semiconductor layer PS ( Figure 3) to form a plurality of transistors T1, T2, T3, T4, T5, T6 and T7, and the semiconductor layer PS is provided as a polycrystalline semiconductor. In addition, in the present exemplary embodiment, in addition to the channels of the plurality of transistors T1, T2, T3, T4, T5, T6 and T7 in the polycrystalline semiconductor, the polycrystalline semiconductor becomes a conductor by doping with P-type impurities so that the polycrystalline semiconductor has the properties of wiring. Therefore, there is no need to form an additional wiring layer. At the same time, according to an exemplary embodiment, the polycrystalline semiconductor may be doped with N-type impurities, and according to another exemplary embodiment, a semiconductor oxide may be used instead of the polycrystalline semiconductor.

[0079] The structure of the semiconductor layer PS according to the present exemplary embodiment may be Figure 3 As can be easily seen in the layout diagram of FIG. 1 and indicated by the hatched pattern portion, the semiconductor layer PS extends vertically with respect to the opposite side of the channel of the driving transistor T1 .

[0080] like Figure 1 As shown in , the first electrode S1 is arranged at the left side of the channel of the driving transistor T1 (i.e., along the first direction X), and the channel of the second transistor T2 is arranged in the semiconductor layer PS extending upward from the first electrode S1 (i.e., along the second direction Y). At the same time, the channel of the fifth transistor T5 is arranged in the semiconductor layer PS extending downward from the first electrode S1 (i.e., along the second direction Y). The second electrode D1 is arranged at the right side of the channel of the driving transistor T1 (i.e., along the first direction X), and the channel of the sixth transistor T6 is arranged in the semiconductor layer PS extending downward from the second electrode D1 (along the second direction Y).

[0081] The semiconductor layer PS of the pixel PX in the next stage is connected below the channel of the sixth transistor T6. The semiconductor layer PS extends upward from the second electrode D1 and bends several times, and the channel of the transistor T3-2, the channel of the transistor T3-1, the channel of the transistor T4-1, the channel of the transistor T4-2, and the channel of the seventh transistor T7 are arranged in sequence from the second electrode D1. More specifically, the semiconductor layer PS that has extended upward (i.e., along the second direction Y) from the second electrode D1 is bent to the left (i.e., along the first direction X) after passing through the channel of the transistor T3-2, and then bent downward (i.e., along the second direction Y) so that it passes through the channel of the transistor T3-1. After passing through the channel of the transistor T3-1, the semiconductor layer PS is bent to the left again (i.e., along the first direction X), and then bent upward (i.e., along the second direction Y) so that it meets the channel of the transistor T4-1 and the channel of the transistor T4-2 in sequence. After meeting the channel of transistor T4-1 and the channel of transistor T4-2 in sequence, the semiconductor layer PS passes through the channel of the seventh transistor T7, and then bends to the right again (i.e., along the first direction X), and then bends upward (i.e., along the second direction Y) so that it is connected to the semiconductor layer PS of the pixel PX of the previous level.

[0082] In addition, the semiconductor layer PS may include an extension for connecting to a wiring arranged in another layer. The semiconductor layer PS extending upward from the channel of the second transistor T2 includes an extension that is extended to receive the data voltage Dm. The semiconductor layer PS includes an extension that is extended to receive the driving voltage ELVDD at a portion that is bent downward from the channel of the fifth transistor T5 and then bent to the right. The semiconductor layer PS includes an extension that is extended to connect to the data connection member 73 and applies the driving current to the organic light emitting diode OLED through the pixel electrode arranged above it at a portion extending downward from the channel of the sixth transistor T6. In addition, the semiconductor layer PS according to the present exemplary embodiment also includes a first extension PSE arranged between the channel of the transistor T3-1 and the channel of the transistor T4-1, and the first extension PSE is a portion connected to the gate electrode G1. The semiconductor layer PS also includes a second extension PSE2 that extends to the left and then extends between the channel of the transistor T4-2 and the channel of the seventh transistor T7, and the second extension PSE2 is a portion that is extended to receive the initialization voltage Vint.

[0083] Some of this semiconductor layer PS is heavily doped with P-type impurities, and thus the heavily doped portion has the same properties as a conductor. For this purpose, some of the semiconductor layer PS needs to be covered, and the remaining portion is not covered, and thus becomes wiring by doping with P-type impurities.

[0084] Typically, a metal layer (e.g., a gate electrode) is formed on the semiconductor layer PS, and then the semiconductor layer PS may be doped while using the metal layer as a mask. However, an additional doping mask PBLK may be used to form all constituent elements in a narrower pixel region so that a doping structure different from that of the gate electrode may be formed. After doping by using the additional doping mask PBLK, the semiconductor layer PS may be additionally doped by using the metal layer as a mask.

[0085] exist Figure 1 In FIG. 1 , the semiconductor layer PS is marked with a hatched pattern, and the portion of the semiconductor layer PS that becomes a part of the wiring by doping is marked with a cross-hatched pattern. The structure of the doping mask PBLK is as shown in FIG. Figure 5 As shown in Figure 1 Only the semiconductor layer PS after doping is shown. In the present exemplary embodiment, a photosensitive material (eg, photoresist) is used as the doping mask PBLK, and the doping mask PBLK has a thickness sufficient to prevent P-type impurities from contacting the semiconductor layer PS. The doping mask PBLK is not Figure 1 , as it is removed after the doping process.

[0086] In the present exemplary embodiment, the semiconductor layer PS includes five portions that become wirings by being doped with P-type impurities. Figure 1 , first, a portion of the semiconductor layer PS disposed between the channel of the transistor T3-1 and the channel of the transistor T4-1 and including the first extension PSE is doped. Second, a portion of the semiconductor layer PS disposed between the channel of the transistor T4-1 and the channel of the transistor T4-2 is doped. Third, a portion of the semiconductor layer PS disposed between the channel of the transistor T4-2 and the channel of the seventh transistor T7 and then, for example, continuously extending to the left to include the second extension PSE2 is doped. Fourth, a portion of the semiconductor layer PS extending from the channel of the seventh transistor T7 to the pixel PX at the previous stage (i.e., along the second direction Y) is doped. Fifth, a portion of the semiconductor layer PS extending from the channel of the sixth transistor T6 to the pixel PX at the next stage is doped.

[0087] Reference Figure 2 , the first insulating layer 141 is disposed on the semiconductor layer PS to cover the semiconductor layer PS. The first opening 51 and the second opening 54 are formed in the first insulating layer 141. Figure 1 As shown in FIG. 5 , the first opening 51 and the second opening 54 expose the first expansion portion PSE and the second expansion portion PSE2 of the semiconductor layer PS, respectively.

[0088] A scan line 151 , a previous scan line 152 , a light emitting control line 153 , and an initialization voltage line 157 extending in the first direction X and transmitting a scan signal Sn, a previous scan signal Sn- 1 , a light emitting control signal En, and an initialization voltage Vint, respectively, are formed on the first insulating layer 141 .

[0089] First, the scan line 151 extends in the first direction X and overlaps with the channel of the second transistor T2, the channel of the transistor T3-1, and the channel of the transistor T3-2. In addition, the scan line 151 overlaps with the doped portion of the semiconductor layer PS between the channel of the transistor T3-1 and the channel of the transistor T4-1. In the present exemplary embodiment, the region overlapping with the channel of the second transistor T2 has a wide width. The transistor is formed in the undoped portion of the semiconductor layer PS overlapping with the scan line 151, so the second transistor T2, the transistor T3-1, and the transistor T3-2 are formed in the overlapping portion.

[0090] The previous scan line 152 extends in the first direction X and overlaps with the channel of the transistor T4-1, the channel of the transistor T4-2, and the channel of the seventh transistor T7. In addition, the previous scan line 152 overlaps with the doped portion of the semiconductor layer PS located between the channel of the transistor T4-1 and the channel of the transistor T4-2, and also overlaps with the doped portion of the semiconductor layer PS extending from the channel of the seventh transistor T7 to the pixel PX at the previous stage. In the present exemplary embodiment, the previous scan line 152 includes an extended area extended at a portion overlapping with the channel of the transistor T4-1 and the channel of the transistor T4-2, and bends downward while passing through the channel of the seventh transistor T7. The transistor is formed in a portion where the previous scan line 152 and the undoped portion of the semiconductor layer PS overlap each other, so the transistor T4-1, the transistor T4-2, and the seventh transistor T7 are respectively formed in the overlapping portion.

[0091] The light emission control line 153 also extends in the first direction X and overlaps with the channel of the fifth transistor T5 and the channel of the sixth transistor T6. The transistors are formed in the portion where the light emission control line 153 and the undoped portion of the semiconductor layer PS overlap each other, and thus the fifth transistor T5 and the sixth transistor T6 are respectively formed in the overlapping portion.

[0092] The initialization voltage line 157 also extends in the first direction X and overlaps only the doped portion of the semiconductor layer PS so that no transistor is formed. The initialization voltage line 157 of the present exemplary embodiment has a wide width at a portion of the second extension PSE2 of the semiconductor layer PS and is directly connected to the second extension PSE2 through the second opening 54. Accordingly, the initialization voltage Vint is applied to the semiconductor layer PS through the second extension PSE2.

[0093] At the same time, the gate electrode 155 of the driving transistor T1 is also formed on the first insulating layer 141. The gate electrode 155 has a quadrilateral structure and overlaps not only the channel of the driving transistor T1 but also the first extension PSE of the semiconductor layer PS. Since the transistor is formed in a portion where the gate electrode 155 and the undoped portion of the semiconductor layer PS overlap each other, the driving transistor T1 is formed in this portion. In addition, the gate electrode 155 overlaps the first extension PSE which is the doped portion of the semiconductor layer PS and is directly connected to the first extension PSE through the first opening 51. Accordingly, the voltage applied to the gate electrode 155 of the driving transistor T1 is affected by the operation of the transistor T3-1 and the transistor T4-1. In addition, the gate electrode 155 of the driving transistor T1 also serves as the second storage electrode of the storage capacitor Cst.

[0094] The gate electrode 155 of the driving transistor T1 may be formed of the same material as the scan line 151, the previous scan line 152, the light emission control line 153, and the initialization voltage line 157 and may be located on the same layer, for example, at the same height relative to the substrate 110. After the scan line 151, the previous scan line 152, the light emission control line 153, and the initialization voltage line 157 are formed, the semiconductor layer PS is additionally doped by using these metal layers as a mask. That is, the uncovered portion of the semiconductor layer PS is doped by the scan line 151, the previous scan line 152, the light emission control line 153, and the initialization voltage line 157, and then the uncovered portion of the semiconductor layer PS becomes a conductor so that the semiconductor has the property of wiring.

[0095] The gate electrode 155 , the scan line 151 , the previous scan line 152 , the light emission control line 153 , and the initialization voltage line 157 are covered by the second insulating layer 142 .

[0096] The sustain line 126 is disposed on the second insulating layer 142. The sustain line 126 extends in the first direction X and is aligned with the gate electrode 155 (eg, Figure 1) has an extended width in the second direction Y at the portion where the gate electrode 155 overlaps. The extended width of the sustain line 126 is formed to completely cover (e.g., completely overlap) the top surface of the gate electrode 155. The extended portion of the sustain line 126 overlaps with the gate electrode 155 on a plane, while the second insulating layer 142 is arranged between them, so that a storage capacitor Cst is formed. The extended portion of the sustain line 126 forms (e.g., defines) a first storage electrode of the storage capacitor Cst, and the gate electrode 155 forms (e.g., defines) a second storage electrode of the storage capacitor Cst. The extended portion of the sustain line 126 has a quadrilateral structure and has no open portion, so that the interior of the quadrilateral structure is filled with a metal material. Accordingly, even if the area where the pixel PX is formed is reduced, sufficient capacitance of the storage capacitor Cst can be ensured.

[0097] A third insulating layer 160 is formed on the sustain line 126. Four openings 62, 67, 68, and 69 are formed in the third insulating layer 160. The opening 62 is arranged above the channel of the second transistor T2 of the semiconductor layer PS, and exposes an extended portion that is expanded to receive the data voltage Dm. The opening 67 is arranged below the channel of the fifth transistor T5 of the semiconductor layer PS, and exposes an extended portion that is expanded to receive the driving voltage ELVDD. The opening 69 is arranged below the channel of the sixth transistor T6, and exposes an extended portion that is expanded to apply a driving current to the organic light emitting diode OLED. The opening 68 exposes a portion of the expanded portion of the sustain line 126. Accordingly, although the opening 68 is formed only in the third insulating layer 160, the openings 62, 67, and 69 are formed in the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160. The data line 171, the driving voltage line 172, and the data connection member 73 are formed on the third insulating layer 160.

[0098] The data line 171 extends in the second direction Y and may be partially bent. The data line 171 transmits the data voltage Dm to the first electrode S2 of the second transistor T2 through the opening 62 .

[0099] The driving voltage line 172 also extends in the second direction Y, and is partially bent and includes an extension having an extended width in the first direction X. The extension of the driving voltage line 172 is extended to cover a portion of the driving transistor T1, a portion of the transistors T3-1 and T3-2, and a portion of the transistors T4-1 and T4-2. The extension applies the driving voltage ELVDD to the sustain line 126 through the opening 68 at a portion overlapping with the extended portion of the sustain line 126. Accordingly, the driving voltage ELVDD is applied to the first storage electrode of the storage capacitor Cst. Since the opening 68 only needs to be formed at the portion where the driving voltage line 172 overlaps with the extended portion of the sustain line 126, the position of the opening 68 can be variously changed at the periphery of the shown position instead of being arranged in the shown position.

[0100] The extended portion of the driving voltage line 172 covers at least a portion of the connection portion of the transistors T3-1 and T3-2 connected in series. That is, the connection portion is a portion where the first electrode S3-1 of the transistor T3-1 is directly connected to the second electrode D3-2 of the transistor T3-2, and is arranged on the semiconductor layer PS. Since the extended portion of the driving voltage line 172 covers the connection portion of the transistors T3-1 and T3-2, the voltage of the connection portion can be stabilized. When the voltage of the connection portion of the transistors T3-1 and T3-2 is stabilized, the characteristics of the driving transistor T1 of each pixel PX can be stabilized. This is because the outputs of the transistors T3-1 and T3-2 are electrically connected to the gate electrode 155 of the driving transistor T1, and the data voltage Dm passes through the transistors T3-1 and T3-2 and is stored in the storage capacitor Cst. The extended portion of the driving voltage line 172 partially overlaps the transistors T4-1 and T4-2 and the driving transistor T1, and the overlapping area can be adjusted according to the features of the exemplary embodiment. In addition, the driving voltage line 172 applies the driving voltage ELVDD to the first electrode S5 of the fifth transistor T5 through the opening 67 , and has a width slightly widened at the periphery of the opening 67 .

[0101] The data connection member 73 is electrically connected to the expansion portion of the semiconductor layer PS disposed below the channel of the sixth transistor T6 through the opening 69. The data connection member 73 transmits the driving current to the organic light emitting diode OLED.

[0102] A passivation layer 180 covering the data line 171, the driving voltage line 172, and the data connection member 73 is formed on the data line 171, the driving voltage line 172, and the data connection member 73. An opening 81 exposing the data connection member 73 is formed in the passivation layer 180, and the organic light emitting diode OLED is arranged on the passivation layer 180. In addition, a partition wall separating the organic light emitting diode OLED is formed on the passivation layer 180. In addition, a spacer may be formed to maintain a predetermined gap with a layer additionally formed above.

[0103] The organic light emitting diode OLED includes a pixel electrode, an organic emission layer and a common electrode. The pixel electrode is connected to the data connection member 73 through the opening 81 .

[0104] An encapsulation layer is formed on the organic light emitting diode OLED, the partition wall and the spacer to protect the organic light emitting diode OLED from moisture and the like. The encapsulation layer may or may not contact the common electrode. The encapsulation layer may be a thin film encapsulation layer formed by stacking an inorganic layer and an organic layer, or may include a three-layer stacked layer of an inorganic layer, an organic layer and an inorganic layer. A covering layer and a functional layer may be arranged between the common electrode and the encapsulation layer.

[0105] As described above, when the semiconductor layer PS overlaps with the gate electrode 155, the scan line 151, the previous scan line 152, the light emitting control line 153, the data line 171 and the driving voltage line 172, seven transistors are formed. The seven transistors are as follows. The channel of each of the plurality of transistors T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6 and T7 overlaps with the gate electrode of each of the plurality of transistors T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6 and T7, and is arranged between the first electrode and the second electrode of each of the plurality of transistors T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6 and T7. The plurality of transistors T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6 and T7 may have substantially an equal stacked structure.

[0106] The driving transistor T1 includes a channel, a gate electrode 155, a first electrode S1, and a second electrode D1. The channel of the driving transistor T1 is arranged between the first electrode S1 and the second electrode D2, and overlaps with the gate electrode 155 on a plane. The channel is bent to increase the length of the channel in a limited area. As the channel length increases, the driving range of the gate voltage Vg applied to the gate electrode 155 of the driving transistor T1 increases, and the driving current increases constantly according to the gate voltage Vg. Accordingly, the magnitude of the gate voltage Vg can be changed so that the grayscale of the light emitted from the organic light emitting diode OLED can be more accurately controlled, and the display quality of the organic light emitting diode display can be improved. In addition, the channel extends in several directions, rather than in one direction, and thus can offset the influence caused by the directionality in the manufacturing process, thereby reducing process variations. Therefore, image degradation such as stain defects (for example, even if the same data voltage Dm is applied, brightness differences will appear depending on the pixel) that may occur due to changes in the characteristics of the driving transistor T1 caused by process variations can be prevented. Such a shape of the channel is not limited to the structure shown in the figure, and may have various structures such as Ω type, S type, etc.

[0107] The gate electrode 155 also serves as a second storage electrode of the storage capacitor Cst. That is, the storage capacitor Cst includes a first storage electrode and a second storage electrode overlapping each other, with a second insulating layer 142 arranged therebetween. The second storage electrode corresponds to the gate electrode 155 of the driving transistor T1, and the first storage electrode is an extended portion of the sustain line 126. Here, the second insulating layer 142 becomes a dielectric material, and the charge charged in the storage capacitor Cst and the voltage between the first storage electrode and the second storage electrode determine the capacitance. Since the driving voltage line 172 is connected to the first storage electrode through the opening 68, the charge corresponding to the difference between the driving voltage ELVDD and the gate voltage Vg of the gate electrode 155 is stored in the storage capacitor Cst. In addition, since the gate electrode 155 serves as the second storage electrode, the driving transistor T1 can have a sufficient size, and the storage capacitor Cst can have a sufficient capacitance even in a small-sized pixel because the driving transistor T1 and the storage capacitor Cst are arranged while overlapping each other.

[0108] The gate electrode of the second transistor T2 is an extended portion of the scan line 151. The first electrode S2 of the second transistor T2 is connected to the data line 171 through the opening 62, and therefore, the second electrode D2 is connected to the first electrode S1 of the driving transistor T1. The channel of the second transistor T2 is arranged between the first electrode S2 and the second electrode D2 in the semiconductor layer PS.

[0109] The third transistor T3 is formed by two transistors T3-1 and T3-2 that are adjacent to each other and connected in series. The third transistor T3 is connected in series to block the flow of leakage current. The structure in which the two transistors T3-1 and T3-2 are connected in series means that the two gate electrodes receive the same signal and are synchronously turned on by the same gate signal so that the signal input to one transistor is output through the other transistor. That is, the gate electrodes of the transistors T3-1 and T3-2 are arranged on the scan line 151, and the channel is formed in the semiconductor layer PS overlapping the gate electrodes of the transistors T3-1 and T3-2. The first electrode S3-2 of the transistor T3-2 is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the driving transistor T1, and the second electrode D3-1 of the transistor T3-1 is connected to the first electrode S4-1 of the transistor T4-1. In addition, the second electrode D3-1 of the transistor T3-1 is connected to the gate electrode 155 through the first opening 51. The first electrode S3-1 of the transistor T3-1 and the second electrode D3-2 of the transistor T3-2 are connected to each other.

[0110] The fourth transistor T4 is also formed by two transistors T4-1 and T4-2, and the two transistors T4-1 and T4-2 are connected in series. That is, the gate electrodes of the transistors T4-1 and T4-2 are arranged on the previous scan line 152, and the channel is formed in the semiconductor layer PS overlapping the gate electrodes of the transistors T4-1 and T4-2. The first electrode S4-1 of the transistor T4-1 is connected to the second electrode D3-1 of the transistor T3-1, the second electrode D4-2 of the transistor T4-2 is connected to the second electrode D7 of the seventh transistor T7, and the second electrode D4-1 of the transistor T4-1 is connected to the first electrode S4-2 of the transistor T4-2. As described above, the structure connected in series can prevent current leakage. The second electrode D4-2 of the transistor T4-2 is directly connected to the initialization voltage line 157 through the second opening 54. The first electrode S4-1 of the transistor T4-1 is connected to the gate electrode 155 through the first opening 51.

[0111] The gate electrode of the fifth transistor T5 is part of the light emission control line 153, and its channel is formed in the semiconductor layer PS overlapping the gate electrode of the fifth transistor T5. The driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the opening 67, and the second electrode D5 is connected to the first electrode S1 of the driving transistor T1.

[0112] The gate electrode of the sixth transistor T6 is part of the light emission control line 153, and its channel is formed in the semiconductor layer PS overlapping the gate electrode of the sixth transistor T6. The second electrode D6 of the sixth transistor T6 is connected to the data connection member 73 through the opening 69, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1.

[0113] The seventh transistor T7 is part of the previous scan line 152 and a channel is formed in the semiconductor layer PS overlapping the gate electrode of the seventh transistor T7. The first electrode S7 of the seventh transistor T7 is connected to the data connection member 73 through the opening 69, and the second electrode D7 is connected to the second electrode D4-2 of the transistor T4-2.

[0114] In the above, the first electrodes and the second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 have been described, and when one of the first electrode and the second electrode is a source region, the other corresponds to a drain region. In addition, according to an exemplary embodiment, the reference Figure 1 Describe the source and drain regions.

[0115] The semiconductor layer PS of the present exemplary embodiment is directly connected to the first conductor arranged thereon through the extensions PSE and PSE2 while overlapping the first conductor. Accordingly, the area of ​​the structure (including the opening) for electrical connection in each pixel PX can be reduced. In addition, since no additional connection wiring is required, the number of openings can be reduced and the area occupied by the openings can be reduced.

[0116] In each pixel PX of the present exemplary embodiment, a total of six openings 51, 54, 62, 67, 68, 69 are formed except for the opening 81 connected to the pixel electrode. Six openings are the minimum number in the pixel PX including seven transistors and one storage capacitor Cst, and accordingly, the area of ​​the pixel PX can be reduced and can be applied to a high-resolution organic light emitting diode display.

[0117] In addition, when forming a high-resolution pixel PX, the greater the number of structures connected by openings, the greater the possibility of failure, and thus the yield is reduced. That is, a total of one hundred and twenty (120) display devices are formed in one mother substrate, and the following Table 1 shows a comparison of the probability of failure between an exemplary embodiment in which one pixel PX has six openings and a comparative example in which one pixel PX has eight openings or ten openings when one display device has 1440×2880 pixels (QHD resolution).

[0118] (Table 1)

[0119]

[0120] Here, the defect rate is calculated with a probability of one in a million. That is, it can be determined that the defect rate can be reduced by about 25% by reducing only two openings of one pixel PX. Therefore, when forming a high-resolution pixel PX, it is preferable to use a pixel structure with a small number of openings in terms of reducing the area occupied by the pixel PX and the defect rate.

[0121] In the present exemplary embodiment, the doped semiconductor layer PS is formed below the previous scan line 152. Accordingly, the area occupied by the two transistors T4-1 and T4-2 is reduced.

[0122] Typically, a channel is formed in a portion where a wiring (e.g., a previous scan line) and a semiconductor layer overlap each other, and the width of the wiring exceeds a predetermined width. In this case, the wiring and the semiconductor layer need to overlap each other in two portions to form two channels, resulting in an increase in the area. In contrast, in the present exemplary embodiment, a doped region is formed under one wiring, and a channel is formed at opposite sides of the doped region, so that the area occupied by the two transistors can be reduced.

[0123] In addition, even if the doping mask PBLK is misaligned, the size of the channel of the fourth transistor T4 is not changed. That is, when the doping mask PBLK is vertically misaligned, the channel length of the transistor T4-1 may be changed (eg, Fig.18 L of T4-1 in ) and the channel length of transistor T4-2 (e.g., Fig.18 However, since the length of the fourth transistor T4 is the channel length of the transistor T4-1 (eg, Fig.18 The channel length of transistor T4-1 in FIG. Fig.18 The length of the fourth transistor T4 is therefore not changed.

[0124] In addition, the third transistor T3 and the fourth transistor T4 have a structure in which two transistors are connected in series, and accordingly, leakage current can be reduced.

[0125] In the following, reference will be made to Figures 3 to 16 as well as Figure 1 and Figure 2 A structure of a pixel PX of an organic light emitting diode display according to a manufacturing sequence is described. Figures 3 to 16 It shows that according to Figure 1 to Figure 2 Layout diagrams and cross-sectional views of various stages in a method for manufacturing a pixel PX of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0126] First, refer to Figure 3 to Figure 4 , the barrier layer 111 is arranged on the substrate 110, and the buffer layer 112 is arranged on the barrier layer 111. The semiconductor layer PS is arranged on the buffer layer 112. Figure 3 The shape of the semiconductor layer PS in a top view is shown in FIG. Figure 4 is along Figure 3 A cross-sectional view along line IV-IV.

[0127] The organic light emitting diode display according to the present exemplary embodiment may be a flexible display device using a plastic or polyimide (PI) substrate. According to an exemplary embodiment, the substrate 110 and the barrier layer 111 may be provided in plurality. For example, the barrier layer 111 may be arranged on the substrate 110, and then another substrate 110 and another barrier layer 111 may be arranged above the barrier layer 111. In another example, after repeating this unit structure of the substrate 110 and the barrier layer 111, the buffer layer 112 may be arranged on top of the unit structure. However, according to an exemplary embodiment, a glass substrate may be used, and in this case, the barrier layer 111 or the buffer layer 112 may be omitted. The barrier layer 111 and the buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, aluminum oxide, etc., or may include an organic insulating material such as polyimide, polyacrylic acid (with epoxy resin added), etc.

[0128] Reference Figure 3 and Figure 4 , a semiconductor layer PS is disposed on the buffer layer 112 , and the semiconductor layer PS includes channels, first electrodes, and second electrodes of a plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 . Figure 3 The structure of the semiconductor layer PS is shown in FIG.

[0129] The semiconductor layer PS is formed of a polycrystalline semiconductor, and may be formed by forming amorphous silicon and then crystallizing the amorphous silicon. According to example embodiments, the semiconductor layer PS may be formed of an oxide semiconductor.

[0130] The semiconductor layer PS has a vertically extending structure with respect to the opposite side of the channel of the driving transistor T1. For example, the semiconductor layer PS may have a Figure 1 The channel of the driving transistor T1 of the present exemplary embodiment bends downward while extending to the right, and then extends to the right again. However, the channel structure of the driving transistor T1 is not limited thereto, and may have various structures such as Ω type, S type, etc.

[0131] As previously referred Figure 1 As described, the first electrode S1 is arranged at the left side of the channel of the driving transistor T1, and the channel of the second transistor T2 is arranged in a portion of the semiconductor layer PS extending upward from the first electrode S1. At the same time, the channel of the fifth transistor T5 is arranged in a portion of the semiconductor layer PS extending downward from the first electrode S1. The second electrode D1 is arranged at the right side of the channel of the driving transistor T1, and the channel of the sixth transistor T6 is arranged in a portion of the semiconductor layer PS extending downward from the second electrode D1. The semiconductor layer PS of the pixel PX at the next level is connected below the channel of the sixth transistor T6. At the same time, the semiconductor layer PS extends upward from the second electrode D1 and bends several times, and the channels of the transistor T3-2, the transistor T3-1, the transistor T4-1, the transistor T4-2 and the seventh transistor T7 are arranged in sequence from the second electrode D1. More specifically, the semiconductor layer PS that has extended upward from the second electrode D1 bends to the left after passing through the channel of the transistor T3-2, and then bends downward so that it passes through the channel of the transistor T3-1. After passing through the channel of the transistor T3-1, the semiconductor layer PS bends to the left again and then bends upward so that it meets the channel of the transistor T4-1 and the channel of the transistor T4-2 in sequence. After meeting the channel of the transistor T4-1 and the channel of the transistor T4-2 in sequence, the semiconductor layer PS passes through the channel of the seventh transistor T7, and then bends to the right again, and then bends upward so that it is connected to the semiconductor layer PS of the pixel PX of the previous stage.

[0132] In addition, the semiconductor layer PS may include an extension for connecting to a wiring arranged in another layer. The semiconductor layer PS extending upward from the channel of the second transistor T2 includes an extension extended to receive the data voltage Dm. The semiconductor layer PS includes an extension extended to receive the driving voltage ELVDD at a portion bent downward from the channel of the fifth transistor T5 and then bent to the right. The semiconductor layer PS includes an extension extended to connect to the data connection 73 and apply a driving current to the organic light emitting diode OLED through a pixel electrode arranged thereon at a portion extending downward from the channel of the sixth transistor T6.

[0133] In addition, the semiconductor layer PS according to the present exemplary embodiment further includes a first extension portion PSE disposed between the channel of the transistor T3-1 and the channel of the transistor T4-1, and the first extension portion PSE is connected to the gate electrode G1 ( Fig.19 In addition, the semiconductor layer PS further includes a second expansion portion PSE2 extending leftward and then expanding between the channel of the transistor T4-2 and the channel of the seventh transistor T7, and the second expansion portion PSE2 is a portion expanded to receive the initialization voltage Vint.

[0134] The semiconductor layer PS having such a structure undergoes a wiring process through a doping process, such as Figure 5 and Figure 6 as shown in . Figure 5 is a top view of a pixel PX, and Figure 6 is along Figure 5 A cross-sectional view along line VI-VI.

[0135] exist Figure 5 , portions where the doping mask PBLK is not formed are marked with a hatched pattern, and the direction of the hatched pattern is perpendicular to the direction of the hatched pattern used to mark the semiconductor layer PS. The doping mask PBLK is arranged in portions where the corresponding hatched pattern is not drawn, and accordingly, the semiconductor layer PS arranged in these portions is not doped. Figure 5 The semiconductor layer PS in the portion marked with a hatched pattern in FIG. 1 is doped. In order to distinguish the doped semiconductor layer PS from the undoped semiconductor layer PS, Figure 5 , the semiconductor layer PS is shown marked with a cross-hatched pattern. In other words, the hatching pattern of the undoped semiconductor layer PS and the hatching pattern of the area exposed by the doping mask PBLK are oriented in different directions, so the overlapping portion of the semiconductor layer PS (to be doped) and the area exposed by the doping mask PBLK are cross-hatched. It should also be noted that in Figure 5 The boundary of the doping mask PBLK is shown by a thick solid line in FIG.

[0136] like Figure 6As shown in FIG. 1 , the doping mask PBLK is formed on an undoped portion of the semiconductor layer PS, and the P-type impurities are completely doped in the portion of the semiconductor layer PS exposed by the doping mask PBLK. In the present exemplary embodiment, a photosensitive material (e.g., a photoresist) is used as the doping mask PBLK, and is formed thick enough to prevent the P-type impurities from contacting the semiconductor layer PS. When doping is performed as described above, the semiconductor layer PS exposed to the region where the doping mask PBLK is not formed (i.e., the region having Figure 5 The region of the hatched pattern depicted with bold lines in FIG. 1 is doped and thus has the same characteristics as wiring. Figure 5 and Figure 6 In FIG. 1 , the semiconductor layer PS doped and turned to wiring is shown with a cross-hatched pattern.

[0137] Next, refer to Figure 7 and Figure 8 , the doping mask PBLK is removed, and, for example, a first insulating layer 141 is formed on the entire substrate 110 . Figure 7 is a top view of a pixel PX, and Figure 8 is along Figure 7 A cross-sectional view along line VIII-VIII.

[0138] In detail, a first insulating layer 141 covering the semiconductor layer PS and the buffer layer 112 is formed on the semiconductor layer PS and the buffer layer 112. The first insulating layer 141 may be formed of, for example, silicon nitride, silicon oxide, and aluminum oxide, and in the present exemplary embodiment, is formed of silicon oxide.

[0139] like Figure 7 and Figure 8 As shown in FIG. 1 , a first opening 51 and a second opening 54 are formed in (eg, through) the first insulating layer 141. The two openings 51 and 54 expose two extensions PSE and PSE2 of the semiconductor layer PS, respectively.

[0140] Now refer to Fig. 9 and Fig.10 A process for forming a first conductor is described. Fig. 9 is a top view of a pixel PX, and Fig.10 is along Fig. 9 A cross-sectional view of line XX.

[0141] The first conductor may be formed of various metals, for example, in the present exemplary embodiment, molybdenum (Mo) is used to form the first conductor. In another example, the first conductor may have a plurality of metal layers. The first conductor includes a scan line 151, a previous scan line 152, a light emitting control line 153, an initialization voltage line 157, and a gate electrode 155. After forming the first conductor, the semiconductor layer PS is additionally doped, and then P-type impurities are doped in the portion of the semiconductor layer PS exposed by the first conductor. After this additional doping process, the undoped portion of the semiconductor layer PS will be the channel of the transistor.

[0142] A scan line 151 , a previous scan line 152 , a light emitting control line 153 , and an initialization voltage line 157 extending in the first direction X and transmitting a scan signal Sn, a previous scan signal Sn- 1 , a light emitting control signal En, and an initialization voltage Vint, respectively, are formed on the first insulating layer 141 .

[0143] First, the scan line 151 extends in the first direction X and overlaps with the channel of the second transistor T2, the channel of the transistor T3-1, and the channel of the transistor T3-2. In addition, the scan line 151 overlaps with the doped portion of the semiconductor layer PS between the channel of the transistor T3-1 and the channel of the transistor T4-1. In the present exemplary embodiment, the region overlapping with the channel of the second transistor T2 has a wide width. The transistor is formed in the portion of the semiconductor layer PS that is not doped and overlaps with the scan line 151, so the second transistor T2, the transistor T3-1, and the transistor T3-2 are formed in the overlapping portion.

[0144] The previous scan line 152 extends in the first direction X, and overlaps with the channel of the transistor T4-1, the channel of the transistor T4-2, and the channel of the seventh transistor T7 while extending in the first direction X. In addition, the previous scan line 152 overlaps with the doped portion of the semiconductor layer PS between the channel of the transistor T4-1 and the channel of the transistor T4-2, and also overlaps with a portion of the semiconductor layer PS extending from the channel of the seventh transistor T7 to the pixel PX at the previous stage. In the present exemplary embodiment, the previous scan line 152 includes an extended region extended at a portion overlapping with the channel of the transistor T4-1 and the channel of the transistor T4-2, and bends downward while passing through the channel of the seventh transistor T7. The transistor is formed in a portion where the previous scan line 152 and the undoped portion of the semiconductor layer PS overlap each other, and thus the transistor T4-1, the transistor T4-2, and the seventh transistor T7 are respectively formed in the overlapping portion.

[0145] The light emission control line 153 also extends in the first direction X, and overlaps with the channel of the fifth transistor T5 and the channel of the sixth transistor T6 while extending in the first direction X. The transistors are formed in a portion where the light emission control line 153 and the undoped portion of the semiconductor layer PS overlap each other, and thus the fifth transistor T5 and the sixth transistor T6 are respectively formed in the overlapping portions.

[0146] The initialization voltage line 157 also extends in the first direction X and overlaps only the doped portion of the semiconductor layer PS so that no transistor is formed. The initialization voltage line 157 of the present exemplary embodiment has a wide width at a portion of the second extension PSE2 of the semiconductor layer PS and is directly connected to the second extension PSE2 through the second opening 54. Accordingly, the initialization voltage Vint is applied to the semiconductor layer PS through the second extension PSE2.

[0147] At the same time, the gate electrode 155 of the driving transistor T1 is also formed on the first insulating layer 141. The gate electrode 155 has a quadrilateral structure and overlaps not only the channel of the driving transistor T1 but also the first extension PSE of the semiconductor layer PS. Since the transistor is formed in a portion where the gate electrode 155 and the undoped portion of the semiconductor layer PS overlap each other, the driving transistor T1 is formed in this portion. In addition, the gate electrode 155 overlaps the first extension PSE which is the doped portion of the semiconductor layer PS and is directly connected to the first extension PSE through the first opening 51. Accordingly, the voltage applied to the gate electrode 155 of the driving transistor T1 is affected by the operation of the transistor T3-1 and the transistor T4-1. In addition, the gate electrode 155 of the driving transistor T1 also serves as the second storage electrode of the storage capacitor Cst.

[0148] Next, refer to Fig.11 and Fig.12 , a second insulating layer 142 covering the first conductor is arranged on the first conductor. Fig.11 is a top view of a pixel PX, and Fig.12 is along Fig.11 A cross-sectional view along line XII-XII.

[0149] In detail, the second insulating layer 142 may be formed of, for example, silicon nitride, silicon oxide, and aluminum oxide, and in the present exemplary embodiment, the second insulating layer 142 is formed of silicon oxide. Fig.11 and Fig.12 As shown in FIG. 1 , the second conductor is arranged on the second insulating layer 142. The second conductor may be formed of, for example, molybdenum (Mo). In addition, the second conductor may have a plurality of metal layers.

[0150] The second conductor includes a sustain line 126, and an extended portion of the sustain line 126 is used as a first storage electrode. The sustain line 126 extends in the first direction X and has an extended width at a portion overlapping with the gate electrode 155. The extended width of the sustain line 126 is formed to completely (e.g., completely) cover the gate electrode 155. The extended portion of the sustain line 126 overlaps the gate electrode 155 on a plane, while the second insulating layer 142 is arranged between them, so that a storage capacitor Cst is formed. The extended portion of the sustain line 126 forms a first storage electrode, and the gate electrode 155 forms a second storage electrode. The extended portion of the sustain line 126 has a quadrilateral structure and has no open portion, so that the inside of the quadrilateral structure is filled with a metal material. Accordingly, even if the area where the pixel PX is formed is reduced, sufficient capacitance of the storage capacitor Cst can be ensured.

[0151] Next, refer to Fig.13 and Fig.14 , a third insulating layer 160 covering the second conductor is formed on the second conductor. Fig.13 is a top view of a pixel PX, and Fig.14 is along Fig.13 A cross-sectional view of line XIV-XIV.

[0152] In detail, the third insulating layer 160 may be formed of, for example, silicon nitride, silicon oxide, and aluminum oxide, or may be formed of an organic insulating material. In the present exemplary embodiment, the third insulating layer 160 is formed of silicon nitride or silicon oxide. The third insulating layer 160 has four openings 62, 67, 68, and 69 formed therein.

[0153] The opening 62 is arranged above the channel of the second transistor T2 of the semiconductor layer PS, and exposes the extended portion expanded to receive the data voltage Dm. The opening 67 is arranged below the channel of the fifth transistor T5 of the semiconductor layer PS, and exposes the extended portion expanded to receive the driving voltage ELVDD. The opening 69 is arranged below the channel of the sixth transistor T6, and exposes the extended portion expanded to apply the driving current to the organic light emitting diode OLED. The opening 68 exposes a part of the extended portion of the sustain line 126. Accordingly, even if the opening 68 is formed only in the third insulating layer 160, the openings 62, 67, and 69 are also formed in the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160.

[0154] Next, refer to Fig.15 and Fig.16 , a third conductor is formed on the third insulating layer 160 . Fig.15 is a top view of a pixel PX, and Fig.16 is along Fig.15 Cross-sectional view along line II-II.

[0155] In detail, the third conductor may be formed of various metals and may include a plurality of metal layers. In the present exemplary embodiment, the third conductor has a three-layer structure of titanium (Ti), aluminum (Al) and titanium (Ti). The third conductor includes a data line 171, a driving voltage line 172 and a data connection member 73.

[0156] The data line 171 extends in the second direction Y and may be partially bent. The data line 171 transmits the data voltage Dm to the first electrode S2 of the second transistor T2 through the opening 62 .

[0157] The driving voltage line 172 extends in the second direction Y and includes an extension portion that is partially bent and has an extended width. The extension portion of the driving voltage line 172 is extended to cover a portion of the driving transistor T1, a portion of the transistors T3-1 and T3-2, and a portion of the transistors T4-1 and T4-2. The extension portion applies the driving voltage ELVDD to the sustaining line 126 through the opening 68 at a portion overlapping the extended portion of the sustaining line 126. Accordingly, the first storage electrode of the storage capacitor Cst is applied with the driving voltage ELVDD. The extension portion of the driving voltage line 172 covers at least a portion of the connecting portion of the transistors T3-1 and T3-2 connected in series. That is, the connecting portion is a portion where the first electrode S3-1 of the transistor T3-1 and the second electrode D3-2 of the transistor T3-2 are directly connected, and is arranged on the semiconductor layer PS. Since the extension portion of the driving voltage line 172 covers the connecting portion of the transistors T3-1 and T3-2, the voltage of the connecting portion can be stabilized. When the voltage of the connection part of the transistors T3-1 and T3-2 is stabilized, the characteristics of the driving transistor T1 of each pixel PX can be stabilized. This is because the outputs of the transistors T3-1 and T3-2 are electrically connected to the gate electrode 155 of the driving transistor T1, and the data voltage Dm passes through the transistors T3-1 and T3-2 and is stored in the storage capacitor Cst. The extended portion of the driving voltage line 172 partially overlaps the transistors T4-1 and T4-2 and the driving transistor T1, and the overlapping area can be adjusted according to the characteristics of the exemplary embodiment. In addition, the driving voltage line 172 applies the driving voltage ELVDD to the first electrode S5 of the fifth transistor T5 through the opening 67, and has a width slightly widened at the periphery of the opening 67.

[0158] The data connection member 73 is electrically connected to the expansion portion of the semiconductor layer PS disposed below the channel of the sixth transistor T6 through the opening 69. The data connection member 73 transmits the driving current to the organic light emitting diode OLED.

[0159] Return to reference Figure 1 and Figure 2A passivation layer 180 covering the third conductor is formed on the third conductor. The passivation layer 180 may be formed of an organic insulating material, and in the present exemplary embodiment, the passivation layer 180 is formed of polyimide (PI).

[0160] The pixel electrode is arranged on the passivation layer 180. The pixel electrode is connected to the data connection member 73 through the opening 81 formed in the passivation layer 180. The pixel electrode may be formed of a transparent conductive material or a metal and may include a plurality of layers. In the present exemplary embodiment, the passivation layer 180 has a double-layer structure of ITO and silver (Ag).

[0161] The partition wall and the spacer may be arranged on the passivation layer 180 and the pixel electrode. The partition wall has an opening portion overlapping the pixel electrode, and the organic emission layer is arranged in the opening portion. The common electrode is arranged on the organic emission layer and the partition wall. The pixel electrode, the organic emission layer and the common electrode form an organic light emitting diode OLED.

[0162] According to an exemplary embodiment, the pixel electrode may be an anode as a hole injection electrode, and the common electrode may be a cathode as an electron injection electrode. Conversely, the pixel electrode may be a cathode, and the common electrode may be an anode. Holes and electrons are injected into the organic emission layer from the pixel electrode and the common electrode, respectively, and excitons generated by coupling the injected holes and electrons drop from an excited state to a ground state to emit light.

[0163] The partition wall and the spacer may be formed of various organic materials, and in the present exemplary embodiment, they are formed of polyimide (PI). Since the partition wall and the spacer are formed of the same material, they can be formed together by using one mask, and in this case, a halftone mask can be used. Accordingly, when the spacer is formed with a halftone area, the number of masks can be reduced. However, when forming a high-resolution pixel PX, the partition wall and the spacer may not be formed together using a halftone mask. In this case, the partition wall and the spacer are formed separately by using a separate mask.

[0164] In the following, reference will be made to Fig.17 The number of masks used in this exemplary embodiment is described. Fig.17 is based on Figure 1 and Figure 2 Schematic diagram of a stacking relationship in a pixel PX of an organic light emitting diode display according to an exemplary embodiment.

[0165] exist Fig.17 , the order of layers is shown from bottom to top in the order in which they are formed, wherein the first (left) column indicates the type / name of the layer, the second column indicates the material corresponding to each layer, and the third column indicates the reference number corresponding to each layer in the specification. The numbers along the left side of the first column indicate the serial number of the mask used during manufacturing.

[0166] For details, refer to Figure 2 and Fig.17 , a barrier layer 111 and a buffer layer 112 are sequentially formed on the substrate 110. Fig.17 1, the buffer layer 112 is described first because when a glass substrate is used instead of a flexible substrate, the buffer layer 112 is formed only on the substrate 100, and the flexible substrate may be referred to as a substrate and a barrier layer in some cases. In the present exemplary embodiment, the buffer layer 112 may be formed of, for example, silicon oxide (SiOx) or silicon nitride (SiNx).

[0167] Next, a semiconductor layer PS is formed on the buffer layer 112. The semiconductor layer PS is formed by first forming an amorphous silicon layer and then crystallizing it into a polycrystalline semiconductor (p-Si). Then, a first mask is used to form a pattern of the semiconductor layer PS, for example, Fig.17 The number "1" in indicates the first mask.

[0168] Next, a doping mask PBLK is formed to dope the semiconductor layer PS. The doping mask PBLK may be formed of a photosensitive material such as a photoresist, and may have a thickness such that the introduction of impurities can be prevented during the doping process. The photoresist is completely (e.g., entirely) stacked, and then exposed by using a second mask, and a portion whose properties are changed by the exposure is removed or maintained, so that a doping mask PBLK is formed, for example, Fig.17 The number "2" in indicates the second mask. Next, P-type impurities are doped so that the exposed semiconductor layer PS has the same characteristics as the wiring. Subsequently, the doping mask PBLK is removed by using a stripper.

[0169] Next, the first insulating layer 141 is completely stacked. The first insulating layer 141 of the present exemplary embodiment is formed of, for example, silicon oxide (SiOx). Next, a photoresist pattern is formed by using a third mask to expose the positions where the openings 51 and 54 are formed in the first insulating layer 141, for example, Fig.17 The number “3” in denoted a third mask, and the openings 51 and 54 are formed by removing the exposed first insulating layer 141 .

[0170] Then, a first conductor is formed. The first conductor of the present exemplary embodiment is formed of molybdenum (Mo), and the molybdenum is completely stacked, and then a photoresist pattern is formed by using a fourth mask, for example, Fig.17 The number "4" in indicates the fourth mask. The molybdenum exposed by the photoresist pattern is removed so that the first conductor is completed. Accordingly, the scan line 151, the previous scan line 152, the light emitting control line 153, the initialization voltage line 157 and the gate electrode 155 are formed. After the first conductor is formed, the semiconductor layer PS exposed by the first conductor is additionally doped.

[0171] Next, the second insulating layer 142 is completely stacked. The second insulating layer 142 of the present exemplary embodiment is formed of silicon nitride (SiNx).

[0172] Next, a second conductor is formed. The second conductor of the present exemplary embodiment is also formed of molybdenum (Mo), and the molybdenum (Mo) is completely stacked, and then a photoresist pattern is formed thereon by using a fifth mask, for example, Fig.17 The number "5" in indicates a fifth mask. Molybdenum exposed by the photoresist pattern is removed so that the second conductor is completed. Accordingly, the sustain line 126 including a portion serving as an extension of the first storage electrode is formed.

[0173] Next, the third insulating layer 160 is completely stacked. The third insulating layer 160 of the present exemplary embodiment may be formed of silicon oxide (SiOx) or silicon nitride (SiNx). Then, a photoresist pattern exposing the positions of the openings 62, 67, 68, and 69 is formed by using a sixth mask, for example, Fig.17 The number "6" in indicates a sixth mask, and then the exposed third insulating layer 160 is removed so that openings 62, 67, 68, and 69 are formed. The openings 62, 67, and 69 are formed by removing the exposed third insulating layer 160 and the first and second insulating layers 141 and 142 disposed thereunder, but the opening 68 is formed by removing only the third insulating layer 160.

[0174] Next, a third conductor is formed. In the present exemplary embodiment, the third conductor has a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti). After the three layers of metal materials are sequentially stacked, a photoresist pattern is formed thereon by using a seventh mask, for example, Fig.17 The number "7" in refracted indicates the seventh mask. The third conductor is completed by removing the three layers of metal material exposed by the photoresist pattern. Accordingly, the data line 171, the driving voltage line 172 and the data connection member 73 are formed.

[0175] Next, the passivation layer 180 is completely formed, and in the present exemplary embodiment, polyimide (PI) is completely stacked. Next, the passivation layer 180 located at the position of the opening 81 is removed by using an eighth mask, for example, Fig.17 The number “8” in denoted an eighth mask, and the opening 81 is then formed and the data connection 73 is exposed.

[0176] Next, the pixel electrode PXL is formed. In the present exemplary embodiment, the pixel electrode PXL has a double-layer structure of ITO and silver (Ag). The double layer of ITO and silver (Ag) is completely stacked, and then a photoresist pattern is formed by using a ninth mask. The pixel electrode PXL is completed by removing the double layer exposed by the photoresist pattern. The pixel electrode PXL is directly connected to the data connection member 73 exposed by the opening 81 in the passivation layer 180.

[0177] Next, a partition wall PDL and a spacer SPC are formed. In the present exemplary embodiment, the partition wall PDL is first formed by using polyimide (PI). In the present exemplary embodiment, the polyimide (PI) is completely stacked, and then the partition wall PDL surrounding the pixel electrode PXL is completed by using a tenth mask. The partition wall PDL may separate the organic emission layer, and a common electrode may be formed on the organic emission layer and the partition wall PDL.

[0178] Next, a spacer SPC is formed. In the present exemplary embodiment, the spacer SPC is formed by using an additional mask (i.e., an eleventh mask) after forming the partition wall PDL, and the spacer SPC can be formed by stacking additional polyimide (PI). However, according to an exemplary embodiment, the partition wall PDL and the spacer SPC can be formed by using one mask, and in this case, a halftone mask can be used, and the spacer SPC can be formed by a halftone area in the halftone mask.

[0179] In the present exemplary embodiment, the partition wall PDL and the spacer SPC are formed by using separate masks, because if a halftone mask is used, the partition wall PDL and the spacer SPC cannot be formed together by using one mask due to the reduction of the pixel size in the high-resolution pixel PX. Therefore, two separate masks are used in the exemplary embodiment.

[0180] In the following, reference will be made to Fig.18 The structure of the fourth transistor T4 of the pixel PX according to the present exemplary embodiment is described in detail.

[0181] Fig.18 is based on Figure 1 to Figure 2 FIG. 1 is an enlarged view of a fourth transistor T4 of a pixel PX of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0182] Reference Fig.18, the doping mask PBLK is marked with a bold line. The hatched pattern portion shows an area exposed by the doping mask PBLK (i.e., exposed to P-type impurities). Therefore, the portion of the semiconductor layer PS arranged in the hatched pattern portion is doped (i.e., shown as cross-hatched), and the portion of the semiconductor layer PS located in the other portion (i.e., hatched pattern in a different direction relative to the exposed area of ​​the doping mask PBLK) is not doped.

[0183] In this structure, the entire width of the previous scan line 152 corresponding to the gate electrode of the fourth transistor T4 is not formed by one transistor, but is divided into two transistors T4-1 and T4-2 by the doped region (i.e., the cross-hatched region) arranged between them. Typically, the channel is formed in the portion where the wiring (e.g., the previous scan line 152) and the semiconductor layer PS overlap each other, and the width of the wiring needs to be greater than a predetermined width. Therefore, when the wiring and the semiconductor layer PS need to overlap in two parts to form two channels, the area increases. However, in this exemplary embodiment, the doped region is formed below a wiring, and the channel is formed at the opposite side of the doped region so that the area occupied by the two transistors can be reduced. In addition, the fourth transistor T4 is formed by two transistors T4-1 and T4-2 connected in series, and accordingly, the leakage current can be reduced.

[0184] In addition, even if the doping mask PBLK is not aligned, the size of the channel of the fourth transistor T4 does not change. That is, when the doping mask PBLK is vertically misaligned, the channel length of the transistor T4-1 (L of T4-1) and the channel length of the transistor T4-2 (L of T4-2) can be changed, but since the length of the fourth transistor T4 is the sum of the channel length of the transistor T4-1 (L of T4-1) and the channel length of the transistor T4-2 (L of T4-2), the length of the fourth transistor T4 will not be changed.

[0185] In the following, reference will be made to Fig.19 and Fig. 20 A circuit structure of an organic light emitting diode display and a signal application operation according to an exemplary embodiment are described.

[0186] Fig.19 An equivalent circuit diagram of a pixel PX of an organic light emitting diode display according to an exemplary embodiment is shown, and Fig. 20 A timing diagram of signals applied to a pixel PX of an organic light emitting diode display according to an exemplary embodiment is shown.

[0187] Reference Fig.19, a pixel PX of the organic light emitting diode display includes a plurality of transistors T1, T2, T3-1 and T3-2, T4-1 and T4-2, T5, T6 and T7, a storage capacitor Cst and an organic light emitting diode OLED connected to a plurality of signal lines 151, 152, 153, 157, 171, 172 and 741. In addition, the shapes and thicknesses of the lines are shown in different ways to show at what layer each wiring and element of the pixel PX is formed.

[0188] exist Fig.19 , the semiconductor layer PS is marked with a dotted line, the first conductor GAT1 is marked with a solid line, the second conductor GAT2 is marked with a thick solid line, and the third conductor DAT is marked with a dashed line. The first conductor GAT1 corresponds to a layer including signal lines 151, 152, 153, and 157, the second conductor GAT2 corresponds to a layer including the sustain line 126, and the third conductor DAT corresponds to a layer including signal lines 171, 172, and 741.

[0189] The portion marked with a thick solid line as a portion where the second conductor GAT2 is formed is a portion of the first storage electrode E1 of the storage capacitor Cst, and the portion marked with a dashed line as a portion where the third conductor DAT is formed is the data line 171, the driving voltage line 172, and the wiring connected to the organic light emitting diode OLED. The remaining portion is a portion for the semiconductor layer PS and the first conductor GAT1, and a portion including a gate electrode is formed as the first conductor GAT1, and a portion corresponding to a channel of the transistor, the first electrode, and the second electrode is formed as the semiconductor layer PS.

[0190] A plurality of transistors T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, and T7 include a driving transistor T1 and a switching transistor connected to a scan line 151, the switching transistor being a second transistor T2 and transistors T3-1 and T3-2. The remaining transistors in the plurality of transistors are transistors (hereinafter referred to as compensation transistors) provided for the operation of the organic light emitting diode OLED. The compensation transistors T4-1, T4-2, T5, T6, and T7 may include transistors T4-1 and T4-2, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0191] The plurality of signal lines 151, 152, 153, 157, 171, 172, and 741 may include a scan line 151, a previous scan line 152, a light emission control line 153, an initialization voltage line 157, a data line 171, a driving voltage line 172, and a common voltage line 741. A line transmitting a bypass signal GB applied to the gate electrode G7 of the seventh transistor T7 may be a part of the previous scan line 152 or may be electrically connected to the previous scan line 152.

[0192] The scan line 151 is connected to the gate driver and transmits the scan signal Sn to the switching transistor (i.e., the second transistor T2 and the transistors T3-1 and T3-2). The previous scan line 152 is connected to the gate driver and transmits the previous scan signal Sn-1 applied to the pixel PX at the previous stage to the transistors T4-1 and T4-2. The light emission control line 153 is connected to the light emission controller and transmits the light emission control signal En for controlling the light emission duration of the organic light emitting diode OLED to the fifth transistor T5 and the sixth transistor T6. The bypass signal GB is transmitted to the gate electrode G7 of the seventh transistor T7, and according to an exemplary embodiment, the same signal as the previous scan signal Sn-1 may be transmitted.

[0193] The data line 171 is a wiring that transmits a data voltage Dm generated by a data driver, and the brightness of the organic light emitting diode OLED (also referred to as an organic light emitting element) changes according to the data voltage Dm. The driving voltage line 172 applies a driving voltage ELVDD, the initialization voltage line 157 transmits an initialization voltage Vint that initializes the driving transistor T1, and the common voltage line 741 applies a common voltage ELVSS. The driving voltage line 172, the initialization voltage line 157, and the common voltage line 741 may be applied with constant voltages, respectively.

[0194] Hereinafter, a plurality of transistors will be described. First, the driving transistor T1 is a transistor that controls the intensity of the output current according to the applied data voltage Dm, and outputs the driving current I d Applied to the organic light emitting diode OLED, and thus the brightness of the organic light emitting diode OLED is controlled according to the data voltage Dm. For this purpose, the first electrode S1 of the driving transistor T1 is positioned to receive the driving voltage ELVDD, and thus is connected to the driving voltage line 172 via the fifth transistor T5. In addition, the first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2, and thus receives the data voltage Dm. The second electrode D1 (i.e., the electrode at the output side) is positioned to output current toward the organic light emitting diode OLED, and thus is connected to the anode of the organic light emitting diode OLED via the sixth transistor T6. At the same time, the gate electrode G1 is connected to one electrode of the storage capacitor Cst (i.e., the second storage electrode E2). Therefore, the voltage of the gate electrode G1 changes according to the voltage stored in the storage capacitor Cst, and accordingly, the driving current I output from the driving transistor T1 is changed. d .

[0195] The second transistor T2 is a transistor that receives the data voltage Dm into the pixel PX. The gate electrode G2 is connected to the scan line 151, and the first electrode S2 is connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1.

[0196] The third transistor T3 is a transistor that transfers the compensation voltage (i.e., Dm+Vth) that has been changed from the data voltage Dm while passing through the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst. The third transistor T3 includes a transistor T3-1 and a transistor T3-2 that are connected in series to each other. The gate electrodes G3-1 and G3-2 of the two transistors T3-1 and T3-2 are both connected to the scan line 151. The first electrode S3-2 of the transistor T3-2 is connected to the second electrode D1 of the driving transistor T1, and the second electrode D3-1 of the transistor T3-1 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. In addition, the first electrode S3-1 of the transistor T3-1 and the second electrode D3-2 of the transistor T3-2 are connected to each other in the connecting portion. When the third transistor T3 is described as a single transistor, the first electrode S3-2 of the transistor T3-2 becomes the first electrode of the third transistor T3, and the second electrode D3-1 of the transistor T3-1 becomes the second electrode of the third transistor T3. The third transistor T3 is turned on according to the scan signal Sn transmitted through the scan line 151, and thus the gate electrode G1 and the second electrode D1 of the driving transistor T1 are connected, and the second electrode D1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst are connected to each other.

[0197] The fourth transistor T4 initializes the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The fourth transistor T4 includes a transistor T4-1 and a transistor T4-2 connected in series to each other. The two gate electrodes G4-1 and G4-2 are connected to the previous scan line 152, and the second electrode D4-2 of the transistor T4-2 is connected to the initialization voltage line 157. The first electrode S4-1 of the transistor T4-1 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3-1 of the transistor T3-1. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the previous scan signal Sn-1 received through the previous scan line 152. Accordingly, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint may be a voltage having a low voltage value that can turn on the driving transistor T1.

[0198] The fifth transistor T5 transmits the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 is connected to the light emission control line 153, and the first electrode S5 is connected to the driving voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0199] The sixth transistor T6 converts the driving current I output from the driving transistor T1 into d The gate electrode G6 is connected to the light emitting control line 153, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the organic light emitting diode OLED.

[0200] The fifth transistor T5 and the sixth transistor T6 are synchronously turned on according to the light emitting control signal En transmitted through the light emitting control line 153, and when the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current I according to the voltage of the gate electrode G1 of the driving transistor T1 (that is, the voltage of the second storage electrode E2 of the storage capacitor Cst). d The output drive current I d The current Ioled is transmitted to the organic light emitting diode OLED through the sixth transistor T6. Therefore, the current Ioled flows to the organic light emitting diode OLED, so that the organic light emitting diode OLED emits light.

[0201] The seventh transistor T7 initializes the anode of the organic light emitting diode OLED. The gate electrode G7 is connected to the previous scan line 152, the first electrode S7 is connected to the anode of the organic light emitting diode OLED, and the second electrode D7 is connected to the initialization voltage line 157. When the seventh transistor T7 is turned on according to the bypass signal GB, the initialization voltage Vint is applied to the anode of the organic light emitting diode OLED, so that the organic light emitting diode OLED is initialized.

[0202] A first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and a second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. Accordingly, the second storage electrode E2 determines the voltage of the gate electrode G1 of the driving transistor T1, and receives the data voltage Dm through the second electrode D3 of the third transistor T3 or receives the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0203] In addition, Fig.19 In the exemplary embodiment, the connection portion of the third transistor T3 overlaps with the expansion portion of the driving voltage line 172, and thus the signal variation can be reduced and the output voltage of the pixel PX can be stabilized. At the same time, the anode of the organic light emitting diode OLED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7, and the cathode of the organic light emitting diode OLED is connected to the common voltage line 741 transmitting the common voltage ELVSS.

[0204] Fig.19 The pixel circuit of the exemplary embodiment includes seven transistors T1 to T7 and one capacitor Cst, but this is not restrictive. The number of transistors, the number of capacitors, and the connection between the transistors and the capacitors may be modified variously. According to the exemplary embodiment, the seventh transistor T7 may be omitted.

[0205] Although not shown, the organic light emitting diode display includes a display area displaying an image, and such pixels PX are aligned in various formats such as a matrix in the display area.

[0206] Now refer to Fig.19 and Fig. 20 An operation of a pixel PX of an organic light emitting diode display according to an exemplary embodiment is described.

[0207] During the initialization period, the low-level previous scan signal Sn-1 is supplied to the pixel PX through the previous scan line 152. Then, the fourth transistor T4 that has received the low-level previous scan signal Sn-1 is turned on, and thus the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst through the fourth transistor T4. Accordingly, the driving transistor T1 and the storage capacitor Cst are initialized. Since the voltage of the initialization voltage Vint is a low-level voltage, the driving transistor T1 can be turned on.

[0208] At the same time, during the initialization period, the bypass signal GB of the low level is applied to the seventh transistor T7. Therefore, the seventh transistor T7 is turned on, and the initialization voltage Vint is applied to the anode of the organic light emitting diode OLED through the seventh transistor T7. Accordingly, the anode of the organic light emitting diode OLED is also initialized.

[0209] Next, during the data writing period, a low-level scan signal Sn is supplied to the pixel PX through the scan line 151. The second transistor T2 and the third transistor T3 are turned on by the low-level scan signal Sn. When the second transistor T2 is turned on, the data voltage Dm is input to the first electrode S1 of the driving transistor T1 through the second transistor T2.

[0210] In addition, during the data write period, the third transistor T3 is turned on, and accordingly, the second electrode D1 of the driving transistor T1 is electrically connected to the gate electrode G1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G1 and the second electrode D1 of the driving transistor T1 are connected by a diode. In addition, since the gate electrode G1 of the driving transistor T1 is applied with a low level voltage (i.e., the initialization voltage Vint) during the initialization period, the driving transistor T1 is in a conducting state. Accordingly, the data voltage Dm input to the first electrode S1 of the driving transistor T1 is output to the second electrode D1 through the channel of the driving transistor T1, and is then stored in the second storage electrode E2 of the storage capacitor Cst through the third transistor T3.

[0211] In this case, the voltage applied to the second storage electrode E2 changes according to the threshold voltage Vth of the driving transistor T1, and when the data voltage Dm is applied to the first electrode S1 of the driving transistor T1 and the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1, the voltage output to the second electrode D1 may be (Vgs+Vth). Here, Vgs corresponds to the difference between the voltage at the gate electrode G1 of the driving transistor T1 and the voltage at the first electrode S1, and Vgs may have a value of (Dm-Vint). Therefore, the voltage output from the second electrode D1 and then stored in the second storage electrode E2 may be (Dm-Vint+Vth).

[0212] Next, during the light emission period, the light emission control signal En supplied from the light emission control line 153 has a low level value, and thus the fifth transistor T5 and the sixth transistor T6 are turned on. Accordingly, the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1, and the second electrode D1 of the driving transistor T1 is connected to the organic light emitting diode OLED. The driving transistor T1 generates a driving current I according to the voltage difference between the voltage of the gate electrode G1 and the voltage of the first electrode S1 (i.e., the driving voltage ELVDD). d The driving current I of the driving transistor T1 d May have a value proportional to the square of (Vgs-Vth). Here, Vgs is equal to the voltage difference at the opposite ends of the storage capacitor Cst, and Vgs has a value of (Vg-Vs), and thus Vgs has a value of (Dm-Vint+Vth-ELVDD). When the value of (Vgs-Vth) is obtained by subtracting Vth, the driving current I d has a value of (Dm-Vint-ELVDD). That is, the driving current I of the driving transistor T1 d A current having no relation to the threshold voltage Vth of the driving transistor T1 is output.

[0213] Therefore, although the driving transistor T1 of each pixel PX has a different threshold voltage Vth due to process variation, the driving transistor T1 may output a constant current, thereby solving the problem of non-uniformity in transistor characteristics.

[0214] In the above calculation, if the transistor is provided as a P-type transistor using a polycrystalline semiconductor, the value of Vth may be slightly greater than zero, or may have a negative value. In addition, the expression of + and - may be changed according to the direction of voltage calculation. However, what does not change is the drive current I which is the output current of the drive transistor T1. d It may have a value independent of the threshold voltage Vth. When the above-mentioned light emitting period is terminated, the initialization period starts again, and thus the same operation is repeated from the beginning.

[0215] Among the first and second electrodes of each of the plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 , one may become a source electrode and the other may become a drain electrode according to a direction in which a voltage or current is applied.

[0216] At the same time, according to an exemplary embodiment, when the seventh transistor T7 initializes the anode of the organic light emitting diode OLED during the initialization period, a small amount of current emitted under the condition that the driving transistor T1 is substantially non-conductive can be prevented from flowing to the organic light emitting diode OLED. In this case, a small amount of current is released to the terminal of the initialization voltage Vint through the seventh transistor T7 as a bypass current Ibp. Accordingly, the organic light emitting diode OLED does not emit unnecessary light, and thus can display black grayscale more vividly, and can improve contrast. In this case, the bypass signal GB may be a signal having a different timing from the previous scan signal Sn-1. According to an exemplary embodiment, the seventh transistor T7 may be omitted.

[0217] In the following, reference will be made to Fig.21 Description is structurally similar to Figure 1 and Figure 2 Exemplary embodiments of different exemplary embodiments. Fig.21 is a layout diagram of a pixel area in an organic light emitting diode display according to another exemplary embodiment.

[0218] and Figure 1 Different from the exemplary embodiments of Fig.21 In the exemplary embodiment of FIG. 1 , the position of the seventh transistor T7 is changed in the semiconductor layer PS. For this purpose, a Figure 1 The structure of the doping mask PBLK is different from the structure of the doping mask PBLK. In order to clearly show the doping mask PBLK, Figure 1 Different, in Fig.21 The doping mask PBLK is additionally shown in FIG. Even though it cannot be observed in the completed pixel PX because it is removed after doping, Fig.21 The doping mask PBLK is also shown to clearly show the Figure 1 difference.

[0219] exist Fig.21 In an exemplary embodiment, the doping mask PBLK is Figure 1 The doping mask PBLK shown in FIG. 1 is different, and thus the doping portion in the semiconductor layer PS is changed. Specifically, the doping position around the seventh transistor T7 is changed, and accordingly, as shown in FIG. Fig.21 As shown in FIG. 1 , the channel of the seventh transistor T7 is formed away from the channel of the transistor T4 - 2 .

[0220] That is, a channel cannot be formed in the doped portion of the semiconductor layer PS even if the doped portion overlaps the previous scan line 152 , and only the undoped portion of the semiconductor layer PS forms the channel of the seventh transistor T7 while overlapping the previous scan line 152 .

[0221] Reference Fig.21 , the channel of the transistor is formed in the region where the first conductor overlaps with the undoped layer of the semiconductor layer PS, and therefore when using Figure 1 or Fig.21 When the doping mask PBLK of the exemplary embodiment is different from the doping mask PBLK, the position of each transistor forming the pixel PX may be changed. This exemplary variation is not limited to Fig.21 , and may have various exemplary variations.

[0222] Fig.21 The exemplary embodiment also has Figure 1 The same effect as the exemplary embodiment of the present invention. That is, the number of contact holes formed in one pixel PX is reduced so that the size of the area occupied by the pixel PX can be reduced, and thus it can be applied to high-resolution pixels PX. In addition, even if the periphery of the fourth transistor T4 is doped with some of the areas where the gate electrode and the semiconductor layer PS overlap each other to form two transistors T4-1 and T4-2, the size of the pixel PX can be reduced by reducing the size of the area occupied by the pixel PX. In addition, even if the doping mask PBLK is not aligned, the size of the channel of the fourth transistor T4 will not change in this structure of the fourth transistor T4. In addition, the extensions PSE and PSE2 are added to the semiconductor layer PS, and the extensions PSE and PSE2 are directly connected while overlapping on the first conductor above it, so that the area occupied by the pixel PX can be reduced in size.

[0223] By way of summary and review, compared to a liquid crystal display, many constituent elements are included in one pixel of an organic light emitting diode display, and as the number of devices requiring high resolution increases, the size of the pixel becomes smaller, and thus, it becomes increasingly difficult to form all components of the pixel in a corresponding area.

[0224] On the contrary, the exemplary embodiment has been devoted to reducing the area occupied by the pixel even in a small-sized pixel area and forming all the constituent elements of each pixel. That is, according to the exemplary embodiment, the number of contact holes formed in one pixel can be reduced, thereby reducing the area occupied by the pixel. In addition, the number of openings formed in the pixel can be reduced, thereby reducing the inferior quality rate. At the same time, by forming a doped portion in the area where the gate electrode and the semiconductor layer overlap each other, the area occupied by the pixel can be reduced. In addition, an extension is added to the semiconductor layer, and the extension is arranged to overlap the conductor layer above it, thereby reducing the area occupied by the pixel.

[0225] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art as this application is submitted, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. Organic light-emitting diode display, include: substrate; a semiconductor layer, wherein the semiconductor layer is located on the substrate; a first insulating layer, wherein the first insulating layer covers the semiconductor layer; a first conductor, the first conductor being located on the first insulating layer; a second insulating layer, the second insulating layer covering the first conductor; a second conductor, the second conductor being located on the second insulating layer; a third insulating layer, the third insulating layer covering the second conductor; as well as a third conductor, the third conductor being located on the third insulating layer, Wherein, the semiconductor layer includes a doped region and an undoped region, The undoped region includes a channel of the driving transistor, a channel of the second transistor, a channel of the first fourth transistor, and a channel of the second fourth transistor, The doped region includes a first electrode and a second electrode of the driving transistor, a first electrode and a second electrode of the second transistor, a first electrode and a second electrode of the first fourth transistor, and a first electrode and a second electrode of the second fourth transistor, The first conductor includes a gate electrode of the driving transistor, a scan line, and a previous scan line, The third conductor includes a data line, The second transistor is electrically connected to the scan line and the data line, The second electrode of the second transistor is directly connected to the first electrode of the driving transistor, The first fourth transistor and the second fourth transistor are electrically connected to the previous scan line, The gate electrode of the driving transistor is directly connected to the first electrode of the first fourth transistor, The gate electrode of the driving transistor overlaps the channel of the driving transistor and a portion of the first electrode of the first fourth transistor arranged in the doping region of the semiconductor layer in a plan view, and In a plan view, the previous scan line overlaps with the second electrode of the first fourth transistor arranged in the doped region of the semiconductor layer, the first electrode of the second fourth transistor arranged in the doped region of the semiconductor layer, the channel of the first fourth transistor arranged in the undoped region of the semiconductor layer, and the channel of the second fourth transistor arranged in the undoped region of the semiconductor layer.

2. The organic light emitting diode display according to claim 1, in, The second electrode of the first fourth transistor, the first electrode of the second fourth transistor, the channel of the first fourth transistor, and the channel of the second fourth transistor respectively have a straight line structure extending in one direction.

3. The organic light emitting diode display according to claim 2, in, The previous scan line includes an extension region covering the second electrode of the first fourth transistor, the first electrode of the second fourth transistor, the channel of the first fourth transistor, and the channel of the second fourth transistor.

4. The organic light emitting diode display according to claim 1, in: The semiconductor layer further includes a first extension portion, The first insulating layer includes a first opening exposing the first extension portion, and The gate electrode of the driving transistor is directly connected to the first extension through the first opening.

5. The organic light emitting diode display according to claim 1, in: the second conductor comprising a sustaining wire having an extended portion, The gate electrode of the driving transistor forms a storage capacitor together with the extended portion of the sustain line overlapping the gate electrode of the driving transistor and the second insulating layer between the gate electrode of the driving transistor and the extended portion of the sustain line.

6. The organic light emitting diode display according to claim 5, in, A driving voltage is applied to the sustain line.

7. The organic light emitting diode display according to claim 6, in: The third conductor further includes a driving voltage line, wherein the driving voltage line includes an extension portion, The extended portion of the driving voltage line is directly connected to the sustain line through an opening in the third insulating layer.

8. The organic light emitting diode display according to claim 7, further comprising: include: a third transistor, the third transistor comprising a first third transistor and a second third transistor connected in series, The extended portion of the driving voltage line covers at least a portion of a connection portion between the first third transistor and the second third transistor.

9. The organic light emitting diode display according to claim 8, in, The connection portion is located in the undoped region of the semiconductor layer.

10. The organic light emitting diode display according to claim 8, in: The semiconductor layer has a structure in which the semiconductor layer passes through a channel of the second third transistor and then bends to the left while extending upward, and then bends downward and passes through a channel of the first third transistor, and The scan line overlaps the channel of the second third transistor and the channel of the first third transistor.

11. The organic light emitting diode display according to claim 10, in, The first extension of the semiconductor layer is arranged after passing through the channel of the first third transistor.

12. The organic light emitting diode display according to claim 11, in, The semiconductor layer passes through the channel of the first third transistor and then bends to the left, and then sequentially meets the channel of the first fourth transistor and the channel of the second fourth transistor while bending upward again.

13. The organic light emitting diode display according to claim 1, in: The first conductor also includes an initialization voltage line, The semiconductor layer further includes a second extension portion, The first insulating layer includes a second opening exposing the second extension portion, The initialization voltage line is directly connected to the second extension portion through the second opening, and the second extension portion is a portion of the second electrode of the second fourth transistor.

14. The organic light emitting diode display according to claim 1, in: The third conductor also includes a driving voltage line, A pixel consists of: an organic light emitting element that emits light, the second transistor, the second transistor receiving a data voltage from the data line, and The driving transistor applies current to the organic light emitting element.

15. The organic light emitting diode display according to claim 14, in: The first conductor also includes a light emitting control line, The pixel also includes a fifth transistor and a sixth transistor connected to the light emission control line.

16. The organic light emitting diode display according to claim 15, in: The pixel also includes: a first third transistor and a second third transistor connected in series; and The first fourth transistor and the second fourth transistor are connected in series.

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