SerDes monitoring device and method and system on chip

Abstract

The invention discloses a SerDes monitoring device and method and a system on chip, the device comprises a first selector, a first memory, an output module and multiple types of signal monitoring modules, and each type of signal monitoring module comprises an anomaly detection circuit. The first selector obtains multiple types of monitoring signals of the target channel from a physical layer interface of the SerDes bus based on the screening signal of the target channel, and transmits the ith type of monitoring signals to an anomaly detection circuit in the ith type of signal monitoring module, so that when the anomaly detection circuit judges that the ith type of monitoring signals are not matched with the ith type of reference information, the ith type of reference information is detected to be matched with the ith type of reference information; and storing the obtained abnormal information to a first memory and sending the abnormal information to an output module, and outputting an indication signal to a processor by the output module, so that the processor executes target processing in response to the indication signal. According to the device, an interactive observation means between the PHY of the SerDes bus and the controller can be increased, the positioning speed of SerDes problem points is improved, and the test cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a SerDes monitoring device and method, and a system on chip. Background Art

[0002] Serializer / Deserializer (SerDes) is a high-speed serial data interface with obvious advantages in efficiency and reliability. It is used in die-to-die connections to meet the high bandwidth and low latency requirements of die-to-die direct connections.

[0003] In the post-silicon verification stage, the means of observing the interaction between the physical layer (PHY) interface of the SerDes bus and the controller are relatively poor, and it is impossible to quickly locate SerDes problem points. A lot of time needs to be wasted using high-frequency oscilloscopes and protocol analyzers to capture signals and data packets for problem analysis. Summary of the invention

[0004] In order to solve the above problems, the present application provides a SerDes monitoring device and method, and a system on chip to increase the interactive observation means between the PHY and the controller of the SerDes bus, while improving the positioning speed of SerDes problem points and reducing testing costs.

[0005] In a first aspect, the present application provides a SerDes monitoring device, comprising: a first selector, a first memory, an output module, and multiple types of signal monitoring modules, the first selector comprising N output paths, one output path being connected to one type of signal monitoring module, and each signal monitoring module comprising an abnormality detection circuit, where N represents an integer greater than 0;

[0006] The first selector is used for, when receiving the screening signal of the target channel sent by the processor, obtaining multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the screening signal of the target channel, and transmitting the i-th type of monitoring signal to the abnormality detection circuit in the i-th type of signal monitoring module through the i-th output path among the N output paths, where i represents any value from 1 to N;

[0007] The abnormality detection circuit in the i-th type signal monitoring module is used to receive the i-th type monitoring signal, and when it is determined that the i-th type monitoring signal does not match the i-th type reference information, obtain abnormal information of the i-th type monitoring signal, store the abnormal information in the first memory, and send the abnormal information to the output module;

[0008] The output module is used to output an indication signal to the processor when receiving abnormal information, so that the processor performs target processing in response to the indication signal.

[0009] In the case of adopting the above technical solution, the first selector includes N output paths, and one output path is connected to a type of signal monitoring module, so the monitoring signal, the output path and the signal monitoring module correspond one to one. In this case, the i-th type of monitoring signal can be transmitted to the abnormality detection circuit included in the i-th type of signal monitoring module through the i-th output path, so as to use the abnormality detection circuit to determine whether the i-th type of monitoring signal matches the i-th type of reference information. If the i-th type of monitoring signal does not match the i-th type of reference information, it means that the i-th type of monitoring signal is abnormal, and the abnormal information of the i-th type of monitoring signal can be stored in the first memory, and the abnormal information is sent to the output module, so that the output module can output an indication signal to the processor when receiving the abnormal information, so that the processor responds to the indication signal to perform the target processing. It can be seen that in the technical solution disclosed in the present application, the output module can notify the processor in the form of an indication signal after obtaining the abnormal information, so that while the processor responds to the indication signal to perform the target processing, it can also quickly locate the SerDes problem point through the abnormal information stored in the first memory. Moreover, in the technical solution disclosed in the present application, the first selector includes N output paths, and one output path is connected to a type of signal monitoring module, so that the abnormality detection circuit included in each type of signal monitoring module can perform abnormality detection on the corresponding type of monitoring module, thereby ensuring that the SerDes monitoring device can comprehensively monitor different types of monitoring signals.

[0010] In addition, in the technical solution disclosed in the present application, the processor can send a filtering signal of the target channel to the first selector, so that after receiving the filtering signal of the target channel, the first selector can obtain multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the filtering channel of the target channel, and then send the multiple types of monitoring signals to the abnormality detection circuit included in different signal monitoring modules through N output paths, so as to use the abnormality detection circuit to determine whether this type of monitoring signal is abnormal. Therefore, the technical solution disclosed in the present application can perform abnormality detection on the monitoring signals of different channels, so that the SerDes monitoring device can be suitable for monitoring the monitoring signals of different channels, thereby effectively reducing the testing cost.

[0011] In a possible implementation, the i-th type signal monitoring module further includes a second selector, the abnormality detection circuit and the second selector are connected to the reset signal terminal, and the abnormality detection circuit is used to send abnormality information to the second selector.

[0012] The second selector is used to obtain a reset signal from the reset signal terminal and store the reset signal in the first memory when receiving a clear indication sent by the processor, otherwise, when abnormal information is obtained, store the abnormal information in the first memory. The clear indication is an indication signal sent by the processor in response to the indication signal.

[0013] In the technical solution disclosed in the present application, when the clear indication is an indication signal sent by the processor in response to the indication signal, if the second selector receives the clear indication, it means that the first memory has stored abnormal information. Therefore, a reset signal can be obtained from the reset signal terminal and the reset signal can be sent to the first memory. When the clear indication is not received, it means that the first memory does not store abnormal information. When the abnormal information is obtained, the abnormal information is stored in the first memory, thereby preventing the problem of difficulty in querying the abnormal information caused by the accumulation of redundant abnormal information, and providing convenience for locating SerDes problem points in the early stage of post-silicon verification.

[0014] In a possible implementation, the abnormality detection circuit in the i-th type signal monitoring module is further configured to determine the i-th type reference information based on the configuration indication when receiving the configuration indication sent by the processor.

[0015] In a possible implementation, the i-th signal monitoring module includes an abnormality detection circuit of M attributes, the i-th monitoring signal includes monitoring signals of multiple attributes, the i-th reference information includes reference signals of multiple attributes, and M represents an integer greater than 0;

[0016] The abnormality detection circuit of the jth attribute in the i-th type signal monitoring module is used to receive the monitoring signal of the jth attribute in the i-th type monitoring signal, and when it is determined that the monitoring signal of the jth attribute does not match the reference signal of the jth attribute in the i-th type reference information, obtain the abnormality information of the monitoring signal of the jth attribute, and store the abnormality information of the monitoring signal of the jth attribute in the first memory;

[0017] The reference signal of the jth attribute is a monitoring signal of an attribute in the i-th category monitoring signal. The reference signal of the jth attribute and the monitoring signal of the jth attribute have the same category but different attributes.

[0018] In a possible implementation, the first memory is used to receive a first read instruction sent by the processor, and send exception information to the processor in response to the first read instruction.

[0019] In the technical solution disclosed in the present application, the output module can output an indication signal to the processor when receiving abnormal information. Therefore, when the processor receives the indication signal, it indicates that there is a problem with the signal collected by the SerDes bus, and the abnormal information can be obtained from the first memory by sending a first read indication, thereby using the abnormal information to assist in locating the SerDes problem point.

[0020] In a possible implementation, the SerDes monitoring device disclosed in the present application further includes a first synchronizer. The second selector is used to send the abnormal information to the first synchronizer, and the first synchronizer is used to synchronize the abnormal information to the target clock domain and store the abnormal information synchronized to the target clock domain in the first memory.

[0021] When the processor is connected to the first memory through a bus module, the target clock domain is the clock domain of the bus module, which can avoid data transmission errors caused by inconsistent clock frequency and phase, and ensure that the processor can accurately and reliably read abnormal information from the first memory through the bus module.

[0022] In a possible implementation, the i-th type signal monitoring module further includes a signal identification circuit and a second memory, and i represents any one of some numerical values ​​from 1 to N.

[0023] The first selector is also used to transmit the i-th type of monitoring signal to the signal recognition circuit through the i-th output path;

[0024] The signal recognition circuit is used to obtain the i-th type of monitoring signal, and if the i-th type of monitoring signal changes, the i-th type of monitoring signal is stored in the second memory.

[0025] In the technical solution disclosed in the present application, when the signal identification circuit receives a change in the i-th monitoring signal, it indicates that the i-th monitoring signal contains valid information. Therefore, after storing the i-th monitoring signal in the second memory, the i-th monitoring signal stored in the second memory can be conveniently used to assist in SerDes problem location and analysis.

[0026] In one possible implementation, the signal identification circuit is also used to configure a target identifier for the i-th category monitoring signal when the i-th category monitoring signal changes, so that the i-th category monitoring signal carries the target identifier, and the target identifier is used to identify the change position of the i-th category monitoring signal.

[0027] In the technical solution disclosed in the present application, the location where changes occur in the i-th type of monitoring signal can be marked through the target identifier, which facilitates the subsequent identification of the change location of the i-th type of monitoring signal and assists in SerDes problem location and analysis.

[0028] In a possible implementation, the i-th type signal monitoring module further includes an edge detection circuit and a third selector;

[0029] The signal recognition circuit in the i-th type signal monitoring module is used to send the i-th type monitoring signal to the edge detection circuit and the third selector;

[0030] The edge detection circuit is used to send a write enable signal to the third selector when detecting that the i-th type monitoring signal carries a target identifier;

[0031] The third selector is used to store the i-th type monitoring signal in the second memory when receiving a write enable signal.

[0032] In the technical solution disclosed in the present application, when the edge detection circuit detects that the i-th type of monitoring signal carries a target identifier, it can control the third selector in the form of a write enable signal, so that the third selector can select the changed i-th type of monitoring signal to be stored in the second memory, thereby reducing the occupation of the second memory by useless information.

[0033] In a possible implementation, the second memory is used to receive a second read instruction sent by the processor, and send the i-th type of monitoring information to the processor in response to the second read instruction.

[0034] In the technical solution disclosed in the present application, the output module can output an indication signal to the processor when receiving abnormal information. Therefore, when the processor receives the indication signal, it indicates that there is a problem with the monitoring signal obtained from the physical layer interface of the SerDes bus, and the i-th type of monitoring information can be obtained from the second memory by sending a second read indication, thereby using the i-th type of monitoring information to assist in locating the SerDes problem point.

[0035] In a possible implementation, the SerDes monitoring device disclosed in the present application further includes a second synchronizer. The signal identification circuit is used to send the i-th type of monitoring signal to the second synchronizer, and the second synchronizer is used to synchronize the i-th type of monitoring signal to the target clock domain, and send the i-th type of monitoring signal synchronized to the target clock domain to the edge detection circuit and the third selector.

[0036] When the processor is connected to the second memory through a bus module, the target clock domain is the clock domain of the bus module, which can avoid data transmission errors caused by inconsistent clock frequency and phase, and ensure that the processor can accurately and reliably read abnormal information from the first memory through the bus module.

[0037] In a possible implementation, the i-th type signal monitoring module includes a signal recognition circuit of M attributes, the i-th type monitoring signal includes monitoring signals of multiple attributes, the i-th type reference information includes reference signals of multiple attributes, and M represents an integer greater than or equal to 2;

[0038] The i-th type signal monitoring module also includes a fourth selector, and the signal identification circuit of the j-th attribute in the i-th type signal monitoring module is used for the monitoring signal of the j-th attribute in the i-th type monitoring signal. If it is determined that the monitoring signal of the j-th attribute changes based on the reference information of the j-th attribute in the i-th type reference information, the monitoring signal of the j-th attribute is sent to the fourth selector, where j represents any value from 1 to M;

[0039] The fourth selector is used to obtain the monitoring signal of the jth attribute. If a screening signal of the target attribute sent by the processor is received, and if it is determined that the screening signal of the target attribute matches the monitoring signal of the jth attribute, the monitoring signal of the jth attribute is stored in the second memory.

[0040] Under the technical solution disclosed in the present application, after receiving the screening signal of the target attribute sent by the processor, the fourth selector can select the monitoring signal matching the target attribute from the monitoring signals sent by the multiple signal recognition circuits, and store it in the second memory. It can be seen that the SerDes monitoring device disclosed in the present application selects the monitoring signal of the required attribute in the monitoring signal of the same type according to the needs (such as SerDesIP), thereby ensuring that the SerDes monitoring device is suitable for different SerDesIPs.

[0041] In a second aspect, the present application further provides a SerDes monitoring method, which is applied to a SerDes monitoring device. The SerDes monitoring device includes: a first selector, a first memory, an output module, and multiple types of signal monitoring modules, the first selector includes N output paths, one output path is connected to one type of signal monitoring module, and each signal monitoring module includes an abnormality detection circuit, N represents an integer greater than 0, and the method includes:

[0042] When the first selector receives the screening signal of the target channel sent by the processor, it obtains multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the screening signal of the target channel, and transmits the i-th type of monitoring signal to the abnormality detection circuit in the i-th type of signal monitoring module through the i-th output path among the N output paths, where i represents any value from 1 to N;

[0043] The abnormality detection circuit in the i-th type signal monitoring module receives the i-th type monitoring signal, and when it is determined that the i-th type monitoring signal does not match the i-th type reference information, obtains abnormal information of the i-th type monitoring signal, stores the abnormal information in the first memory, and sends the abnormal information to the output module;

[0044] When receiving the abnormal information, the output module outputs an indication signal to the processor, so that the processor executes the target processing in response to the indication signal.

[0045] The beneficial effects of the SerDes monitoring method provided in the second aspect of the present application are the same as the beneficial effects of the SerDes monitoring device provided in the first aspect of the present application, and will not be repeated here.

[0046] The present application also provides a system on chip, including: a bus controller, a processor and a SerDes monitoring device, the bus controller is connected to the SerDes bus, the SerDes monitoring device includes a first selector, a first memory, an output module and multiple types of signal monitoring modules, the first selector includes N output paths, one output path is connected to one type of signal monitoring module, and each signal monitoring module includes an abnormality detection circuit, N represents an integer greater than 0;

[0047] The processor is used to send a screening signal of the target channel to the control end of the first selector. The first selector is used to obtain multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the screening signal of the target channel when receiving the screening signal of the target channel sent by the processor, and transmit the i-th type of monitoring signal to the abnormality detection circuit in the i-th type of signal monitoring module through the i-th output channel among the N output channels, where i represents any value from 1 to N;

[0048] The abnormality detection circuit in the i-th type signal monitoring module is used to receive the i-th type monitoring signal, and when it is determined that the i-th type monitoring signal does not match the i-th type reference information, obtain abnormal information of the i-th type monitoring signal, store the abnormal information in the first memory, and send the abnormal information to the output module;

[0049] The output module is used to output an indication signal to the processor when receiving abnormal information, and the processor is used to perform target processing in response to the indication signal.

[0050] The beneficial effects of the system on chip provided in the third aspect of the present application are the same as the beneficial effects of the SerDes monitoring device provided in the first aspect of the present application, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0052] Figure 1 A schematic diagram showing the structural framework of the system on chip disclosed in the embodiment of the present application is shown;

[0053] Figure 2 A schematic diagram of the structure of a SerDes monitoring device disclosed in an embodiment of the present application is shown;

[0054] Figure 3 A schematic diagram showing the abnormal information storage principle of the i-th type of monitoring signal disclosed in the embodiment of the present application is shown;

[0055] Figure 4 A structural schematic diagram of a signal monitoring module taking the i-th type signal monitoring module as an example in an embodiment of the present application is shown;

[0056] Figure 5 Another structural schematic diagram of a signal monitoring module in an embodiment of the present application is shown, taking the i-th type signal monitoring module as an example;

[0057] Figure 6 A schematic diagram of the monitoring principle of the rate signal disclosed in the embodiment of the present application is shown;

[0058] Figure 7 A schematic diagram showing the monitoring principle of the equalization signal disclosed in the present application is shown;

[0059] Figure 8 A schematic diagram of the format of messagebus transmission data disclosed in an embodiment of the present application is shown.

[0060] Fig. 9 A schematic diagram of the structure of a PIPE signal monitoring module disclosed in an embodiment of the present application is shown;

[0061] Fig.10 A schematic diagram showing the storage principle of the i-th type of monitoring signal disclosed in the embodiment of the present application is shown;

[0062] Fig.11 A schematic flow chart of the SerDes monitoring method disclosed in the present application is shown. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the present disclosure more obvious, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0064] In a die-to-die connection, a serializer / deserializer (SerDes) can be used as a high-speed data transmission interface to meet the high bandwidth and low latency requirements required for a die-to-die direct connection.

[0065] Currently, there are relatively few means of observing the interaction between the physical layer (Physical Layer, PHY) interface of the SerDes bus and the bus controller, which makes it impossible to quickly locate SerDes problem points. It takes a lot of time to use high-frequency oscilloscopes and protocol analyzers to capture signals and data packets for problem analysis.

[0066] In order to solve the above problems, an embodiment of the present application provides a system on chip to increase the means of interactive observation between the PHY and bus controller of the SerDes bus, while improving the positioning speed of SerDes problem points and reducing testing costs.

[0067] Figure 1 FIG. 1 shows a schematic diagram of the structural framework of the system on chip disclosed in the embodiment of the present application. Figure 1 As shown, the system on chip 100 of the embodiment of the present application may include: a bus controller 101, a SerDes monitoring device 102 and a processor 103. Here, the system on chip 100 may also include at least one chip, etc., which will not be described in detail here.

[0068] like Figure 1 As shown, the bus controller 101 is connected to the SerDes bus. Here, the SerDes bus has at least one PHY interface, and each PHY interface can be connected to the SerDes monitoring device 102. When the SerDes bus has multiple PHY interfaces, the SerDes monitoring device 102 can obtain multi-channel PHY interface signals output by the multiple PHY interfaces, and then selectively monitor the multi-channel PHY interface signals.

[0069] like Figure 1 As shown, the SerDes monitoring device 102 can be connected to the processor 103 via an Advanced Peripheral Bus (APB) bus. For example, the SerDes monitoring device 102 can be connected to the processor 103 via an APB4 bus, so that the processor 103 can complete various configurations of the SerDes monitoring device 102, receive the indication signal sent by the SerDes monitoring device 102, and qualitatively locate the interaction problem between the PHY interface of the SerDes bus and the controller.

[0070] like Figure 1 As shown, the above-mentioned bus controller 101, SerDes monitoring device 102 and processor 103 belong to the same system on chip, so that the bus controller 101, SerDes monitoring device 102 and processor 103 can be integrated in the same chip. In this case, there is no restriction on the number of chip pins in the chip package, and the SerDes monitoring device 102 can be connected to each PHY interface of the SerDes bus, so that the SerDes monitoring device 102 can be connected to all PHY interfaces of the SerDes bus, and then selectively monitor the multi-channel PHY interface signal output by any PHY interface. In this way, there is no need to spend a lot of time using high-frequency oscilloscopes and protocol analyzers to capture signals and data packets to analyze problems, thereby simplifying the means of locating SerDes problem points and reducing the difficulty of locating SerDes problem points.

[0071] Below Figure 2 Taking the structure of the SerDes monitoring device shown in FIG. 1 as an example, a monitoring method (i.e., an interactive observation method) for monitoring signals between a bus controller and a PHY interface of a SerDes interface is described. Figure 2 As shown, the SerDes monitoring device 200 disclosed in the embodiment of the present application includes a first selector 201 , a first memory 203 , an output module 204 and various types of signal monitoring modules 202 .

[0072] like Figure 2 As shown, the processor 103 is connected to the selection control end of the first selector 201 through the APB bus, and provides the screening signal of the target channel to the first selector 201. The input end of the first selector 201 is connected to at least one PHY interface of the SerDes bus, and is used to obtain multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the screening signal of the target channel when receiving the screening signal of the target channel sent by the processor 103.

[0073] If multiple PHYs of the SerDes bus are connected to the input end of the first selector, the screening signal of the target channel includes both the selection data of the PHY interface and the selection data of the channel type. Therefore, after receiving the screening signal of the target channel, the first selector 201 can determine multiple types of monitoring signals of a unique target channel based on the screening signal of the target channel.

[0074] Exemplarily, when the SerDes bus has four PHY interfaces, each PHY interface includes 16 differential signal lines (lanes). At this time, one lane is equivalent to one channel, so the first selector 201 can select the target PHY interface from the four PHY interfaces, and then select the multiple types of monitoring signals transmitted by one of the target 16 lanes as the multiple types of monitoring signals of the target channel.

[0075] like Figure 2 As shown, the first selector 201 includes N output paths, one output path is connected to one type of signal monitoring module 202, and N represents an integer greater than 0. When each type of signal monitoring module 202 includes an abnormality detection circuit, one output path is connected to the input end of the abnormality detection module in one type of signal monitoring module 202.

[0076] For the i-th type of monitoring signal among multiple types of monitoring signals, the first selector 201 is also used to transmit the i-th type of monitoring signal to the abnormality detection circuit in the i-th type of signal monitoring module through the i-th output channel among N output channels after acquiring multiple types of monitoring signals of the target channel, where i represents any value from 1 to N.

[0077] Exemplarily, in the technical solution disclosed in the embodiment of the present application, the multiple types of monitoring signals of the target channel may include physical layer interface signals (also known as PIPE signals), status signals, key clock signals, etc. It should be understood that the signal types included in the multiple types of monitoring signals here are only used as examples. In practice, depending on the different SerDes versions, more types of signals or fewer types of signals may be included.

[0078] Considering that the state controller and the PHY interface implement the interaction of control and status signals including but not limited to power management, data rate changes, transmitter margining, de-emphasis configuration, receiver detection, clock tolerance compensation, error detection (elastic buffer overflow and underflow, 8B / 10B encoding error), link equalization evaluation, etc., therefore, in the technical solution disclosed in the embodiment of the present application, the PIPE signal may include power status signals, rate signals, equalization signals, error monitoring signals, receiving end detection signals, message bus (messagebus) signals and other PIPE signals, and the equalization signal here may include equalization value signals and sending equalization value indication signals, etc.

[0079] The above-mentioned status signal may include the link status inside the physical coding sublayer (PCS), and may also be the status of various indication signals, such as a rate change indication signal, a transmission equalization indication signal, and the like.

[0080] When the multiple types of monitoring signals of the target channel include PIPE signals, status signals and key clock signals, the first selector 201 may include three output paths, namely, a PIPE signal output path, a status signal output path and a clock signal output path, and the signal monitoring module may include a PIPE signal monitoring module, a status signal monitoring module and a clock signal monitoring module.

[0081] In a specific implementation, the PIPE signal output path can transmit the PIPE signal of the target channel to the abnormality detection circuit in the PIPE signal monitoring module, the status signal output path can transmit the status signal of the target channel to the abnormality detection circuit in the status signal monitoring module, and the clock signal output path can transmit the key clock signal of the target channel to the abnormality detection circuit in the clock signal monitoring module.

[0082] like Figure 2As shown, in the technical solution disclosed in the present application, each signal monitoring module 202 is electrically connected to the input end of the first memory 203. For the i-th type signal monitoring module, the abnormality detection circuit in the i-th type signal monitoring module is used to receive the i-th type monitoring signal, and when it is determined that the i-th type monitoring signal does not match the i-th type reference information, the abnormal information of the i-th type monitoring signal is obtained, the abnormal information is stored in the first memory 203, and the abnormal information is sent to the output module 204. In this case, different signal monitoring modules 202 can share the first memory 203, so that the first memory 203 can store the abnormal information of the monitoring signal transmitted by different signal monitoring modules 202. In the technical solution disclosed in the embodiment of the present application, the method for determining the matching mode between the i-th type monitoring signal and the i-th type reference information is related to the type of the i-th type monitoring signal. In addition, the source of the i-th type reference information is varied, for example, it can be set by the processor 103, or it can be obtained from multiple types of monitoring signals of the target channel, and of course, the signal terminal of the i-th type reference information can be directly connected to the abnormality detection circuit in the i-th type signal monitoring module.

[0083] When the i-th type of reference information can be set by the processor 103, the processor 103 can be connected to the i-th type of signal monitoring module via the APB bus, so that the processor 103 can send a configuration instruction to the abnormality detection circuit included in the i-th type of signal monitoring module. In this case, the abnormality detection circuit included in the i-th type of signal monitoring module is also used to determine the i-th type of reference information based on the configuration instruction when receiving the configuration instruction sent by the processor 103.

[0084] When the i-th type signal monitoring module is a status signal monitoring module, the abnormality detection circuit in the status signal monitoring module can determine the jump timeout threshold using the configuration indication after receiving the configuration indication sent by the processor, and then detect whether the status signal changes within the jump timeout threshold (i.e., a jump occurs). If a change occurs, it means that the status signal jumps normally; otherwise, it means that the status signal jumps abnormally, and the jump abnormality information of the status signal can be stored in the first memory.

[0085] When the i-th type signal monitoring module is a clock signal monitoring module, the signal terminal of the reference clock is connected to the abnormality detection circuit in the clock signal monitoring module. After acquiring the key clock signal, the abnormality detection circuit in the clock signal monitoring module can time the key clock signal through the reference clock signal, and if it is detected that the error range of the clock signal to be measured is within the preset error range, the clock signal to be measured is considered to be stable, otherwise the clock is considered to be abnormal, and the abnormal information of the key clock signal is represented in a high level manner, and the abnormal information of the key clock signal is stored in the first memory.

[0086] When the i-th category monitoring signal includes monitoring signals of multiple attributes, the reference signal of the j-th attribute included in the i-th category monitoring signal may be a monitoring signal of one attribute in the i-th category monitoring signal, and the reference signal of the j-th attribute and the monitoring signal of the j-th attribute have the same category but different attributes.

[0087] Exemplarily, when the i-th type signal monitoring module is a PIPE signal monitoring module, for the PIPE signal, if the monitoring signal of the j-th attribute is a rate signal or a mean signal, when it is detected that the target channel is transmitting the rate signal or the mean signal, the power status signal can be used as the reference signal of the j-th attribute. If the power status is not the power status specified by the SerDes protocol, it means that the PIPE signal of the j-th attribute is abnormal. The abnormal information of the PIPE signal of the j-th attribute indicates that the PIPE signal of the j-th attribute is abnormal by raising the level.

[0088] like Figure 2 As shown, the output module 204 is used to output an indication signal to the processor 103 when receiving abnormal information, so that the processor 103 performs the target processing in response to the indication signal. The abnormal information here can be sent to the memory of the output module 204 by the abnormal detection circuit in any signal monitoring module.

[0089] Exemplarily, when the PIPE signal monitoring module, the status signal monitoring module and the clock signal monitoring module start working, if an abnormality occurs in the monitoring signal monitored by any signal monitoring module, abnormal information of the signal monitoring module will be generated, and finally all abnormal information will be summarized into an abnormal interrupt signal.

[0090] The above-mentioned abnormal interrupt signal includes pipe signal timing abnormal interrupt, pipe signal handshake timeout interrupt, state jump timeout interrupt or clock abnormal interrupt. Finally, the abnormal interrupt signal is transmitted to the processor in the form of an indication signal. After receiving the indication signal, the processor 103 can execute various possible target processing.

[0091] For example, Figure 1 and Figure 2 As shown, the processor 103 may restart the bus controller 101 to reset the bus controller 101, or may instruct the processor 103 to read the abnormal information from the first memory 203 and locate the SerDes problem point using the abnormal information.

[0092] For example, Figure 2As shown, the first memory 203 is used to receive the first read instruction sent by the processor 103, and in response to the first read instruction, send abnormal information to the processor 103. When the processor 103 receives the indication signal, it indicates that there is a problem with the signal collected by the Serdes bus, and the abnormal information can be obtained from the first memory 203 by sending the first read instruction, so as to use the abnormal information to assist in locating the SerDes problem point.

[0093] It can be seen that Figure 2 As shown, in the technical solution disclosed in the embodiment of the present application, the output module 204 can notify the processor 103 in the form of an indication signal after obtaining the abnormal information, so that while the processor 103 responds to the indication signal to perform the target processing, the SerDes problem point can also be quickly located through the abnormal information stored in the first memory 203. Moreover, in the technical solution disclosed in the embodiment of the present application, the first selector 201 includes N output paths, and one output path is connected to a type of signal monitoring module, so that the abnormal detection circuit included in each type of signal monitoring module can perform abnormal detection on the corresponding type of monitoring module, thereby ensuring that the SerDes monitoring device can comprehensively monitor different types of monitoring signals.

[0094] In addition, if Figure 2 As shown, the processor 103 can send a filtering signal of the target channel to the first selector 201, so that after receiving the filtering signal of the target channel, the first selector 201 can obtain multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the filtering channel of the target channel, and then send the multiple types of monitoring signals to the abnormality detection circuit included in different signal monitoring modules through N output paths, so as to use the abnormality detection circuit to determine whether this type of monitoring signal is abnormal. Therefore, the technical solution disclosed in the embodiment of the present application can perform abnormality detection on the monitoring signals of different channels, with high flexibility and low design complexity, and the SerDes monitoring device can be suitable for monitoring the monitoring signals of different channels, thereby effectively saving resources and reducing testing costs.

[0095] It should be noted that if Figure 2 As shown, in the technical solution disclosed in the embodiment of the present application, the first memory 203 can be a multi-bit register, which can actively record the abnormal information of various monitoring signals. If the processor 103 reads the abnormal information of the monitoring signal from the first memory 203, the abnormal information of the monitoring signal stored in the first memory 203 can be cleared to reduce the impact on the abnormal information of subsequent monitoring signals, and facilitate the early positioning of SerDes problem points in the post-silicon verification stage.

[0096] In addition, in the technical solution disclosed in the embodiment of the present application, different signal monitoring modules can be turned on by means of macro switches to realize function selection design to meet the requirements of different SerDes versions. Therefore, the SerDes monitoring device has strong applicability, and unnecessary functional modules can be disabled, which saves resources and reduces energy consumption.

[0097] For example, in the serdes_32G version, various data such as the minimum voltage value (Low Frequency, LF) and the maximum voltage value (Full Swing, FS) are transmitted through the messagebus. Therefore, a macro switch can be configured for the messagebus signal monitoring module to realize the function selection so that it can be configured to be closed when it is not needed. Of course, the processor can also selectively send enable signals to the PIPE signal monitoring module, the status monitoring module, and the clock anomaly monitoring module according to the actual version requirements.

[0098] In one possible implementation, when the i-th type of monitoring signal includes monitoring signals of multiple attributes, the i-th type of signal monitoring module includes anomaly detection circuits of M attributes, the i-th output path has multiple output sub-paths, and one output sub-path is connected to an anomaly detection circuit of one attribute.

[0099] Figure 3 FIG. 1 shows a schematic diagram of the abnormal information storage principle of the i-th type of monitoring signal disclosed in the embodiment of the present application. Figure 3 As shown, the abnormality detection circuit of M types of attributes may include an abnormality detection circuit 301A of the first type of attribute, an abnormality detection circuit 301B of the second type of attribute, ..., an abnormality detection circuit 301j of the jth type of attribute, ..., an abnormality detection circuit 301M of the Mth type of attribute, where j represents any value from 1 to M.

[0100] like Figure 3 As shown, in the technical solution disclosed in the embodiment of the present application, the abnormality detection circuit 301A of the first attribute, the abnormality detection circuit 301B of the second attribute, ..., the abnormality detection circuit 301j of the jth attribute, ..., and the abnormality detection circuit 301M of the Mth attribute are respectively connected to the first memory 203.

[0101] like Figure 3As shown, the first attribute abnormality detection circuit 301A in the i-th type signal monitoring module is used to receive the monitoring signal of the first attribute in the i-th type monitoring signal, and when it is determined that the monitoring signal of the first attribute does not match the reference signal of the first attribute in the i-th type reference information, obtain the abnormal information of the monitoring signal of the first attribute, and store the abnormal information of the monitoring signal of the first attribute in the first memory 203; the second attribute abnormality detection circuit 301B in the i-th type signal monitoring module is used to receive the monitoring signal of the second attribute in the i-th type monitoring signal, and when it is determined that the monitoring signal of the second attribute does not match the reference signal of the second attribute in the i-th type reference information, obtain the abnormal information of the monitoring signal of the second attribute, and store the abnormal information of the monitoring signal of the second attribute in the first memory 203; … …; The abnormality detection circuit 301j of the jth attribute in the i-th signal monitoring module is used for receiving the monitoring signal of the jth attribute in the i-th monitoring signal, and when it is determined that the monitoring signal of the j-th attribute does not match the reference signal of the j-th attribute in the i-th reference information, the abnormality information of the monitoring signal of the j-th attribute is obtained, and the abnormality information of the monitoring signal of the j-th attribute is stored in the first memory 203; …; The abnormality detection circuit 301M of the M-th attribute in the i-th signal monitoring module is used for receiving the monitoring signal of the M-th attribute in the i-th monitoring signal, and when it is determined that the monitoring signal of the M-th attribute does not match the reference signal of the M-th attribute in the i-th reference information, the abnormality information of the monitoring signal of the M-th attribute is obtained, and the abnormality information of the monitoring signal of the M-th attribute is stored in the first memory 203.

[0102] It can be seen that the abnormality detection circuits of multiple attributes can share the first memory 203. When the processor 103 sends a first read indication to the first memory 203, the first memory 203 can send the abnormal information of the monitoring signals of various attributes stored in the first memory 203 to the processor 103 when receiving the first read indication, for SerDes problem point analysis and location.

[0103] like Figure 2 and Figure 3 As shown, when the PIPE signal monitoring module includes an abnormality detection circuit 301A of a first attribute and an abnormality detection circuit 301B of a second attribute, the abnormality detection circuit 301A of the first attribute stores the abnormal information of the equalization signal in the first memory 203 when detecting that an abnormality occurs in the equalization signal, and sends the abnormal information of the equalization signal to the output module 204; the abnormality detection circuit of the second attribute stores the abnormal information of the rate signal in the first memory when detecting that an abnormality occurs in the rate signal, and sends the abnormal information of the rate signal to the output module 204.

[0104] like Figure 2and Figure 3 As shown, the above-mentioned output module 204 can send an indication signal to the processor 103 when detecting abnormal information of the rate signal or abnormal information of the equalization signal. The processor 103 can respond to the indication signal and obtain the abnormal information of the rate signal and the abnormal information of the equalization signal from the first memory 203, so as to analyze the SerDes problem point by using the abnormal information of the rate signal and the abnormal information of the equalization signal.

[0105] In an optional manner, when the i-th type of monitoring signal includes monitoring signals of multiple attributes, the number of output sub-paths included in the i-th output path can be equal to the number of attribute types of the monitoring signal. When the number of output sub-paths included in the i-th output path is equal to the number of attribute types of the monitoring signal, each output sub-path outputs a monitoring signal of a corresponding attribute in a one-to-one correspondence. For example, the j-th output sub-path included in the i-th output path outputs a monitoring signal of the j-th attribute in the i-th type of monitoring signal.

[0106] For the i-th type of monitoring signal, when the number of abnormality detection circuits is equal to the number of attribute types of the monitoring signal, the monitoring signal of one attribute, the abnormality detection circuit of one attribute, and the reference signal of one attribute correspond to each other. In this case, the i-th type signal monitoring module can perform abnormality detection on the monitoring signal of any attribute in the i-th type signal monitoring.

[0107] For the i-th category monitoring signal, when the number of anomaly detection circuits is less than the number of attribute types of the monitoring signal, a part of the monitoring signals included in the i-th category monitoring signal needs to be detected for anomaly by the anomaly detection circuit, and the other part of the monitoring signals does not need to be detected for anomaly by the anomaly detection circuit.

[0108] Exemplarily, for a PIPE signal, when the PIPE signal is a balanced signal, an abnormality detection circuit can be used to detect an abnormality of the balanced signal. For abnormal monitoring of the balanced signal, reference can be made to the above description. However, when the PIPE signal is a message bus signal, it is not necessary to detect an abnormality of the message bus signal.

[0109] In a possible implementation, in the technical solution disclosed in the embodiment of the present application, when abnormal information is detected, the redundancy problem of information stored in the first memory can be reduced by a reset signal.

[0110] Figure 4 A structural schematic diagram of a signal monitoring module in an embodiment of the present application is shown, taking the i-th type signal monitoring module as an example. Figure 4As shown, in the technical solution disclosed in the embodiment of the present application, the i-th type signal monitoring module 202j can include not only an abnormality detection circuit 2021A but also a second selector 2022A, and the abnormality detection circuit 2021A and the second selector 2022A are connected to the reset signal terminal, and the abnormality detection circuit 2021A is used to send abnormal information to the second selector 2022A.

[0111] like Figure 4 As shown, the processor 103 can be connected to the selection control terminal of the second selector 2022A through the APB bus, so that the second selector 2022A is used to indicate that the first memory 203 has stored abnormal information when receiving the clear instruction sent by the processor 103, and therefore, the reset signal can be obtained from the reset signal terminal and the reset signal can be stored in the first memory 203. The clear instruction here is an instruction signal sent by the processor 103 in response to the instruction signal.

[0112] like Figure 4 As shown, if the second selector 2022A does not receive the clear instruction, it means that the first memory 203 does not store the abnormal information. Then, when the second selector 2022A obtains the abnormal information, it stores the abnormal information in the first memory 203. When the abnormal information is obtained, the abnormal information is stored in the first memory 203, thereby preventing the problem of difficulty in querying the abnormal information caused by the accumulation of redundant abnormal information, and facilitating the early positioning of SerDes problem points in the post-silicon verification stage.

[0113] For example, as shown in the figure, for the equalization signal, when the processor receives the indication signal, the reset signal terminal can be controlled to input a low-level reset signal to the second selector 2022A, so that the second selector 2022A can store the reset signal of the location to the first memory 203, so that the processor 103 can query the abnormal information from the first memory 203 more quickly.

[0114] In order to accurately and reliably read the abnormal information, such as Figure 4 As shown, the i-th type signal monitoring module 202j disclosed in the embodiment of the present application may also include a first synchronizer 2023A. The output end of the second selector 2022A may be connected to the first memory 203 through the first synchronizer 2023A, so that the first selector 201 may be used to send the abnormal information to the first synchronizer 2023A, and the first synchronizer 2023A is used to synchronize the abnormal information to the target clock domain, and store the abnormal information synchronized to the target clock domain in the first memory 203.

[0115] For example, Figure 4As shown, when the processor 103 is connected to the output module 204 through the bus module, the target clock domain is the clock domain of the bus module, for example, the processor 103 is connected to the first memory 203 through the APB bus, and the target clock domain is the APB bus clock domain. This can avoid data transmission errors caused by inconsistent clock frequency and phase, and ensure that the processor 103 can accurately and reliably read abnormal information from the first memory 203 through the bus module.

[0116] It should be noted that in the technical solution disclosed in the embodiment of the present application, the first memory 203 can use a ring buffer to store the i-th type of monitoring signal. Here, the number of times the ring buffer stores the i-th type of monitoring signal can be adjusted by parameterizing the maximum number of monitoring times (the depth of the memory). For example, the maximum number of monitoring times can be set to 10 times. After recording the i-th type of monitoring signal that has changed ten times, when a new i-th type of monitoring signal arrives, the original data stored in the ring buffer can be replaced.

[0117] In one possible implementation, Figure 5 Another structural schematic diagram of a signal monitoring module in an embodiment of the present application is shown, taking the i-th type signal monitoring module as an example. Figure 5 As shown, the i-th type signal monitoring module 202i in the embodiment of the present application includes not only an abnormality detection circuit 2021A, but also a signal identification circuit 2021B and a second memory 2025B.

[0118] In the technical solution disclosed in the embodiment of the present application, i represents any one of the values ​​from 1 to N. That is, some of the signal monitoring modules do not include the signal identification circuit 2021B and the second memory 2025B, and another part of the signal monitoring modules may include the signal identification circuit 2021B and the second memory 2025B.

[0119] Exemplarily, the clock signal monitoring module may only include an abnormality detection circuit but not a signal recognition circuit, while the state signal monitoring module may include an abnormality detection circuit and a signal recognition circuit.

[0120] Exemplarily, when the PIPE signal monitoring module and the status signal monitoring module include an abnormality detection circuit, it means that for monitoring signals such as PIPE signals and status signals, it can decide whether to perform abnormality detection and signal recognition on the monitoring signals of such properties at the same time based on the signal properties. This does not mean that as long as the PIPE signal is monitored by the PIPE signal monitoring module, the PIPE signal must be subjected to abnormality detection and signal recognition at the same time. Similarly, it does not mean that as long as the status signal is monitored by the status signal monitoring module, it is not necessary to perform abnormality detection and signal recognition on the status signal at the same time.

[0121] like Figure 5 As shown, the i-th output path of the first selector 201 can be electrically connected to the input end of the i-th signal identification circuit 2021B, so that the first selector 201 is also used to transmit the i-th type of monitoring signal to the signal identification circuit 2021B through the i-th output path, so that the signal identification circuit 2021B is used to obtain the i-th type of monitoring signal, and if the i-th type of monitoring signal changes, the i-th type of monitoring signal is stored in the second memory 2025B. Here, the method for determining whether the i-th type of monitoring signal changes is related to the properties of the i-th type of monitoring signal.

[0122] like Figure 5 As shown, when the i-th monitoring signal changes, it indicates that the i-th monitoring signal contains valid information. Therefore, after storing the i-th monitoring signal in the second memory 2025B, the i-th monitoring signal stored in the second memory 2025B can be conveniently used to assist in SerDes problem location and analysis.

[0123] In an alternative approach, Figure 5 As shown, the processor 103 is also electrically connected to the second memory 2025B, so that the second memory 2025B is used to receive a second read instruction sent by the processor 103, and send the i-th type of monitoring information to the processor 103 in response to the second read instruction.

[0124] For example, Figure 5 As shown, when the output module 204 receives abnormal information, it can output an indication signal to the processor 103. Therefore, when the processor 103 receives the indication signal, it indicates that there is a problem with the monitoring signal obtained from the physical layer interface of the SerDes bus, and the i-th type of monitoring information can be obtained from the second memory 2025B by sending a second read indication, thereby using the i-th type of monitoring information to assist in locating the SerDes problem point.

[0125] In the technical solutions disclosed in the embodiments of the present application, the basic monitoring principles of the PIPE signal monitoring module are similar. The following takes the rate signal, the equalization signal and the message bus signal as examples and illustrates the monitoring principles of the PIPE signal monitoring module in combination with the accompanying drawings.

[0126] When the PIPE signal is a rate signal, the rate signal may include a rate value and a rate change indication signal. Figure 6 FIG. 2 shows a schematic diagram of the monitoring principle of the rate signal disclosed in the embodiment of the present application. Figure 6As shown, the signal recognition circuit can compare the current rate value of the rate signal with the sampling value of the rate signal when the rate change indication signal phystatus rises for the first time. If the current rate value of the rate signal is the same as the sampling value as a result of the comparison, it indicates that the rate signal has changed, and the rate signal can be saved in the second memory.

[0127] At the same time, the abnormality detection circuit can also determine whether the state value of the power state signal is the power state specified by the SerDes protocol. If the power state signal is not the power state signal specified by the SerDes protocol, then the abnormality information of the rate signal can be obtained.

[0128] The abnormality detection circuit can send the abnormal information of the rate signal to the first memory and the output module in a high-level manner. The first memory can store the abnormal information of the rate signal, and the output module can send an indication signal to the processor when receiving the abnormal information of the rate signal. The processor can respond to the indication signal, read the abnormal information of the rate signal from the first memory, read the changed rate value from the second memory, and then use the abnormal information of the rate signal and the changed rate value to analyze the SerDes problem point.

[0129] When the PIPE signal includes an equalization signal, the equalization signal includes an equalization value and a transmission equalization value indication signal. Figure 7 FIG. 2 shows a schematic diagram of the monitoring principle of the equalization signal disclosed in the present application. Figure 7 As shown, when the sending equalization value indication signal received by the signal identification circuit is pulled high, it indicates that the signal identification circuit is receiving the equalization value and the equalization value changes, and the equalization value can be stored in the second memory.

[0130] At the same time, the abnormality detection circuit can determine whether the status value of the power status signal is the power status specified by the SerDes protocol. If the power status signal is not the power status signal specified by the SerDes protocol, then the abnormal information of the equalization signal can be obtained, and the abnormal information of the equalization signal is reflected in a high manner.

[0131] The abnormality detection circuit can send the abnormal information of the equalization signal to the first memory and the output module in a high-level manner. The first memory can store the abnormal information of the equalization signal, and the output module can send an indication signal to the processor when receiving the abnormal information of the equalization signal. The processor can respond to the indication signal, read the abnormal information of the equalization signal from the first memory, read the changed equalization signal from the second memory, and then analyze the SerDes problem point using the abnormal information of the rate signal and the changed equalization value.

[0132] It should be noted that in the technical solution disclosed in the embodiment of the present application, when recording PIPE signals such as power status, equalization signal, and rate signal, the first memory can simultaneously record the link training state machine (Link Training and Status State Machine, LTSSM), so as to use LTSSM to reproduce the change process of monitoring signals such as power status and rate in the case of link jump, so as to facilitate the location of SerDes problem points.

[0133] When the PIPE signal includes the messagebus signal, the PIPE signal monitoring module mainly monitors the messagebus signal transmitted on M2P_Messagebus[7:0] and P2M_Messagebus[7:0]. The data format of the messagebus data included in the messagebus signal is as follows: Figure 8 shown.

[0134] Identify the messagebus data. When the 4-bit CMD value is identified, determine the cycle, address and data recorded in the messagebus data and store them in the form of {cmd, address, data}.

[0135] For example, when a 4-bit cmd is detected, it can be determined that the messagebus signal has changed, and then the type and number of cycles of the messagebus data are determined based on the detected 4-bit cmd value. For example, when the cmd value = 4'b0001, it means that three cycles of messagebus data need to be stored continuously. When the cmd value = 4'b0011, two cycles of messagebus data are stored continuously.

[0136] For example, when an abnormality occurs in the equalization signal and the rate signal, the first memory stores abnormal information such as the equalization signal and the rate signal. When the processor receives the indication signal, it can read the message bus data from the second memory, and then use the message bus data and the abnormal information such as the equalization signal and the rate signal read from the first memory to analyze the SerDes problem point.

[0137] In an optional manner, in the technical solution disclosed in the embodiment of the present application, the i-th type signal monitoring module is a state signal monitoring module, and the state signal may include the state of the rate change indication signal or the link signal inside the PCS. The following takes the state of the rate change indication signal or the link signal inside the PCS as an example to illustrate the monitoring principle of the state signal monitoring module.

[0138] like Figure 6As shown, when the status signal includes the status of the rate change indication signal, when the rate signal changes, the abnormality detection circuit can perform a timing operation on the rate change indication signal through the timing clock. When the status of the rate change indication signal does not change within the jump timeout threshold (i.e., the rate change indication signal is not pulled high within the jump timeout threshold), it indicates that the status of the rate change indication signal is abnormal, and a PIPE signal handshake timeout interrupt is generated.

[0139] When the abnormality detection circuit generates a PIPE signal timeout interrupt, the current rate value of the rate signal and the state jump condition signal of the rate change indication signal (that is, the state maintenance time of the rate change indication signal is equal to the timeout threshold and the rate value of the rate signal) can be recorded, and then based on the current rate value of the rate signal and the state jump condition signal of the rate change indication signal, the abnormal information of the rate signal is determined, and the abnormal information of the rate signal is stored in the first memory for the processor to read through the APB bus.

[0140] In an optional manner, in order to reduce the storage of invalid information in the second memory, in the technical solution disclosed in the embodiment of the present application, as Figure 5 As shown, the signal identification circuit 2021B is also used to configure a target identifier for the i-th monitoring signal when the i-th monitoring signal changes, so that the i-th monitoring signal carries the target identifier, and the target identifier is used to identify the change position of the i-th monitoring signal. Since the target identifier can mark the position where the change occurs in the i-th monitoring signal, it is convenient to subsequently identify the change position of the i-th monitoring signal, and assist in SerDes problem location and analysis.

[0141] In practical applications, the signal identification circuit 2021B can indicate that the i-th monitoring signal has changed in the form of {target identifier, monitoring value}, and indicate that the i-th monitoring signal has not changed in the form of {non-target identifier, monitoring value}. For example, the target identifier can be represented as 1, and the non-target identifier can be represented as 0.

[0142] For example, Figure 5 As shown, the i-th type signal monitoring module 202i may further include an edge detection circuit 2023B and a third selector 2024B. The output end of the signal identification circuit 2021B may be electrically connected to the input end of the edge detection circuit 2023B and the input end of the third selector 2024B, respectively, so that the signal identification circuit 2021B in the i-th type signal monitoring module 202i is used to send the i-th type monitoring signal to the edge detection circuit 2023B and the third selector 2024B.

[0143] like Figure 5As shown, the output end of the edge detection circuit 2023B can be electrically connected to the selection control end of the third selector 2024B, so that the third selector 2024B can be used to send a write enable signal to the third selector 2024B when it is detected that the i-th type monitoring signal carries a target identifier.

[0144] like Figure 5 As shown, the output end of the third selector 2024B can be electrically connected to the second memory 2025B, so that the third selector 2024B is used to store the i-th type monitoring signal in the second memory 2025B when receiving a write enable signal.

[0145] When a change in the i-th monitoring signal is represented in the form of {target identifier, monitoring value}, if the target identifier is represented as 1 and the non-target identifier is represented as 0, a rising edge detection can be performed on the i-th monitoring signal.

[0146] When the rising edge of the i-th monitoring signal is detected, it indicates that the i-th monitoring signal has changed, such as Figure 5 As shown, the third selector 2024B may be notified in the form of a write enable signal so that the third selector 2024B stores the i-th type monitoring signal in the second memory 2025B.

[0147] like Figure 5 As shown, when the rising edge of the i-th monitoring signal is not detected, the edge detection circuit 2023B will not send a write enable signal to the third selector 2024B, thereby ensuring that the third selector 2024B can store the changed monitoring value in the i-th monitoring signal to the second memory 2025B, thereby reducing the occupancy of the second memory 2025B by useless information.

[0148] like Figure 5 As shown, in order to accurately and reliably read the monitoring signal, in the technical solution disclosed in the embodiment of the present application, the i-th type signal monitoring module 202i may also include a second synchronizer 2022B.

[0149] like Figure 5 As shown, the signal identification circuit 2021B sends the exception information to the second synchronizer 2022B, and the second synchronizer 2022B is used to synchronize the exception information to the target clock domain, and store the exception information synchronized to the target clock domain into a signal sent to the edge detection circuit 2023B and the third selector 2024B.

[0150] like Figure 5As shown, when the processor 103 is connected to the second memory 2025B through the bus module, the target clock domain is the clock domain of the bus module, for example, the processor 103 is connected to the second memory 2025B through the APB bus, and the target clock domain is the APB bus clock domain. This can avoid data transmission errors caused by inconsistent clock frequency and phase, and ensure that the processor 103 can accurately and reliably read abnormal information from the first memory 203 through the bus module.

[0151] Exemplarily, when the status signal includes the link status inside the PCS, when it is detected that the link status inside the PCS has a state jump, it means that the link status inside the PCS has changed, and the current link status inside the PCS can be stored; when it is detected that the link status inside the PCS has not undergone a state jump within the state jump timeout threshold, it means that the link status jump inside the PCS has timed out, and the current link status inside the PCS where the state jump timeout occurs and the jump condition signal of the current link status can be recorded.

[0152] Among them, the state machine stores jump condition signals of multiple link states. When the state jump times out, the jump condition signal of the current link state can be obtained from the state machine according to the current link state in the pcs, but the idle state and the normal data transmission state can be excluded. Then, under the original clock domain of the state machine, the current link state in the pcs and the jump condition signal of the current link state are synchronized through the second synchronizer and finally stored in the second memory. The depth of the second memory can be defined using parameters, for example, 16, for the processor to read through the APB bus.

[0153] In an optional manner, in order to fully understand the monitoring principle of the signal monitoring module of the embodiment of the present application, Fig. 9 FIG. 2 shows a schematic diagram of the structure of a PIPE signal monitoring module disclosed in an embodiment of the present application. Fig. 9 As shown, the PIPE signal monitoring module 900 disclosed in the embodiment of the present application may include two parts, the first part is used to use the first memory 900A to store abnormal information of sending the equalization indication signal, and the second part is used to use the second memory 900B to store the changed equalization value.

[0154] The first part includes: a power detection subcircuit 901A, an abnormality detection circuit composed of a first AND gate 902A and a second AND gate 903A, a second selector MUX2 and a first synchronizer 904A; the second part includes: a signal recognition circuit composed of an identification configuration module 901B, a first trigger 902B, a fifth selector MUX5, a second synchronizer 903B, an edge detection circuit composed of a second trigger 904B and an XOR gate 905B, and a third selector MUX3.

[0155] After the processor sends an enable signal to the equalization signal monitoring submodule, when the fifth selector MUX5 detects that the sending equalization indication signal is pulled high, it can be considered that the identification configuration module 901B is transmitting the equalization value. In this case, the identification configuration module 901B can represent the current equalization value in the form of {non-target identification, equalization value}, and when the fifth selector MUX5 detects that the sending equalization indication signal is pulled high, the output can output the current moment's equalization value to the first trigger 902B, and the first trigger 902B reverses the non-target identification carried by the current equalization value, so that the current equalization value is represented in the form of {target identification, equalization value}.

[0156] The second synchronizer 903B can synchronize the current equalization value to the APB clock domain, and then use the edge detection circuit composed of the second trigger 904B and the XOR gate 905B to perform a rising edge detection on the current equalization value synchronized to the APB clock domain. When the rising edge is detected, the XOR gate 905B will send a write enable signal to the third selector MUX3, so that the third selector MUX3 will store the current equalization value in the form of {target identifier, equalization value} to the second memory 90B.

[0157] Exemplarily, the second trigger 904B is used to delay the current equilibrium value synchronized to the APB clock domain to obtain the current equilibrium value after the delay, and the current equilibrium value after the delay is sent to the XOR gate 905B. The XOR gate 905B performs an XOR operation on the current equilibrium value after the delay and the current equilibrium value before the delay.

[0158] When the XOR operation result is 1, it indicates that the current equilibrium value after the delay is different from the current equilibrium value before the delay. In this case, the edge detection circuit detects the rising edge, and when the third selector MUX3 receives the XOR operation result, the current equilibrium value is stored in the form of {target identifier, equilibrium value}.

[0159] When the result of the XOR operation is 0, it means that the current equilibrium value after the delay is the same as the current equilibrium value before the delay. In this case, the edge detection circuit does not detect the rising edge. When the third selector MUX3 receives the XOR operation result, the current equilibrium value synchronized to the APB clock domain will not be stored in the second memory 900B.

[0160] The identification configuration module 901B can invert the target identification carried by the equilibrium value to obtain the non-target identification. When the equilibrium value at the next moment arrives, the non-target identification can be used to identify the equilibrium value at the next moment.

[0161] When the fifth selector MUX5 does not detect that the sending equalization indication signal is pulled high, the output of the fifth selector MUX5 can output the equalization value of the previous moment to the first trigger 902B, and then send it to the input end of the fifth selector MUX5 through the first trigger 902B, without inverting the non-target identifier carried by the equalization value of the previous moment and sending it to the second synchronizer 903B and the identifier configuration module 901B.

[0162] At the same time, the power detection subcircuit 901A is used to determine whether the state value of the power state signal is the power state specified by the SerDes protocol. If the state value of the power state signal is not the preset power state, the power detection subcircuit 901A outputs a high level to the first AND gate 902A. The first AND gate 902A is used to receive the send equalization indication signal. When the send equalization indication signal is pulled high, if the power detection subcircuit 901A outputs a high level, the first AND gate 902A outputs a high level signal to the second AND gate 903A; after receiving the high level signal and the enable signal, the second AND gate 903A can output abnormal information of the high state to the second selector MUX2.

[0163] When the second selector MUX2 does not receive the clear instruction sent by the processor, it can directly send the abnormal information of the high state to the first synchronizer 904A, and synchronize to the clock domain of the APB bus through the first synchronizer 904A, and then store the abnormal information synchronized to the clock domain of the APB bus in the first memory 900A. When the second selector MUX2 receives the clear instruction sent by the processor, it can obtain the reset signal, transmit it to the first synchronizer 904A for synchronization, and then store it in the first memory 900A. At the same time, the reset signal can also be transmitted to the power detection subcircuit 901A to reset the power detection subcircuit 901A.

[0164] In an optional manner, when the i-th category monitoring signal includes monitoring signals of multiple attributes, the i-th category signal monitoring module includes signal identification circuits of M attributes, the i-th output path has multiple output sub-paths, one output sub-path is connected to a signal identification circuit of one attribute, and M represents an integer greater than or equal to 2.

[0165] When the i-th type of monitoring signal can include monitoring signals of M attributes, Fig.10 FIG. 1 shows a schematic diagram of the storage principle of the i-th type of monitoring signal disclosed in the embodiment of the present application. Fig.10 As shown, in the technical solution disclosed in the embodiment of the present application, the i-th signal monitoring module includes signal identification circuits of M types of attributes, namely, a signal identification circuit 1001A of the first type of attribute, a signal identification circuit 1001B of the second type of attribute, ..., a signal identification circuit 1001j of the j-th type of attribute, ..., a signal identification circuit 1001M of the M-th type of attribute.

[0166] Exemplarily, the number of the above-mentioned signal identification circuits may be equal to the number of attribute types of the monitoring signal, or may be less than the number of types of the monitoring signal. When the number of signal identification circuits is equal to the number of types of the monitoring signal, a monitoring signal of one attribute corresponds to a signal identification circuit of one attribute.

[0167] like Fig.10 As shown, the i-th type signal monitoring module also includes a fourth selector 1003, the selection control end of the fourth selector 1003 is electrically connected to the processor 1004, the output end of the signal identification circuit of M types of attributes is electrically connected to the input end of the fourth selector 1003, and the output end of the fourth selector 1003 is electrically connected to the second memory 1005. At this time, the signal identification circuit 1001j of the j-th attribute in the i-th type signal monitoring module is used to receive the monitoring signal of the j-th attribute in the i-th type monitoring signal, and if the monitoring signal of the j-th attribute changes, the monitoring signal of the j-th attribute is sent to the fourth selector 1003, and j represents any value from 1 to M.

[0168] like Fig.10 As shown, the fourth selector 1003 is used to obtain the monitoring signal of the jth attribute. If a screening signal of the target attribute sent by the processor is received, and when it is determined that the screening signal of the target attribute matches the monitoring signal of the jth attribute, the monitoring signal of the jth attribute is stored in the second memory 1005.

[0169] Exemplarily, when the i-th type signal monitoring module includes a third selector, the third selector includes selectors of M attributes, and a signal identification circuit of one attribute is electrically connected to the input end of the fourth selector through the selector of one attribute.

[0170] When the i-th type signal monitoring module includes signal recognition circuits of M attributes, signal recognition circuits of different attributes can share one edge detection circuit and a third selector, or a signal recognition circuit of one attribute corresponds to one edge detection circuit and a third selector. Fig.10 The edge detection circuit and the second synchronizer are omitted to highlight the double-layer selection storage logic in the monitoring signal storage process.

[0171] like Fig.10 As shown, the third selector includes selectors of M types of attributes, which are selector 1002A for the first type of attribute, selector 1002B for the second type of attribute, ..., selector 1002j for the jth type of attribute, ..., selector 1002M for the Mth type of attribute.

[0172] like Fig.10As shown, when the processor 1004 sends an enable signal to the signal recognition circuits of M types of attributes, the signal recognition circuit 1001A of the first type of attribute can send the detection signal of the changed first attribute to the fourth selector 1003 through the selector 1002A of the first attribute when it recognizes that the monitoring signal of the first attribute has changed; the signal recognition circuit 1001B of the second type of attribute can send the detection signal of the changed second attribute to the fourth selector 1003 through the selector 1002B of the second attribute when it recognizes that the monitoring signal of the second attribute has changed; ...; the signal recognition circuit 1001j of the jth attribute can send the detection signal of the changed jth attribute to the fourth selector 1003 through the selector 1002j of the jth attribute when it recognizes that the monitoring signal of the jth attribute has changed; ...; the signal recognition circuit 1001M of the Mth attribute can send the detection signal of the changed Mth attribute to the fourth selector 1003 through the selector 1002M of the Mth attribute when it recognizes that the monitoring signal of the Mth attribute has changed.

[0173] like Fig.10 As shown, the processor 1004 can send a screening signal of the target attribute to the fourth selector 1003 as needed (such as SerDes version), so that the fourth selector 1003 selects the monitoring signal of the required attribute from the same type of monitoring signals, thereby ensuring that the SerDes monitoring device is suitable for different SerDes versions.

[0174] Exemplarily, for message bus data, different types of data such as LF and FS may be included, and different types of data such as LF and FS may be stored in different locations of the second memory 1005 (i.e., different types of data such as LF and FS have different storage addresses in the second memory 1005). In this case, the LF signal recognition circuit may detect the LF data and send the LF data to the fourth selector 1003 through the LF selector; the FS signal recognition circuit may detect the FS data and send the FS data to the fourth selector 1003 through the FS selector.

[0175] like Fig.10As shown, when the fourth selector 1003 receives a filtering signal for LF data sent by the processor 1004, the filtering signal for LF data is used to store the LF data in the first storage position of the second memory 1005; when the fourth selector 1003 receives a filtering signal for FS data sent by the processor 1004, the filtering signal for FS data is used to store the FS data in the second storage position of the second memory 1005. Therefore, the fourth selector 1003 can use the filtering signal of the target attribute sent by the processor 1004 to select the storage address of the monitoring signal of the multiple attributes included in the i-th monitoring signal to determine the message bus data type that the i-th signal monitoring module needs to monitor.

[0176] It can be seen that in the technical solution disclosed in the embodiment of the present application, the attributes of the i-th type of monitoring signal that the second memory 1005 needs to store can be configured by the processor 1004, so that the fourth selector 1003 can filter the monitoring signals that the second memory 1005 needs to store from the received monitoring signals of various attributes. Therefore, in the technical solution disclosed in the embodiment of the present application, the monitoring signal screening can be performed through a two-layer selector to obtain the monitoring signal that the second memory 1005 needs to store.

[0177] The embodiment of the present application also discloses a SerDes monitoring method, which is applied to a SerDes monitoring device. The SerDes monitoring device includes: a first selector, a first memory, an output module, and multiple types of signal monitoring modules, the first selector includes N output paths, one output path is connected to one type of signal monitoring module, and each signal monitoring module includes an abnormality detection circuit, where N represents an integer greater than 0.

[0178] Fig.11 FIG. 2 shows a flow chart of the SerDes monitoring method disclosed in the present application. Fig.11 As shown, the SerDes monitoring method disclosed in the present application may include:

[0179] Step 1101: When the first selector receives the filtering signal of the target channel sent by the processor, it obtains multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the filtering signal of the target channel, and transmits the i-th type of monitoring signal to the abnormality detection circuit in the i-th type of signal monitoring module through the i-th output channel among N output channels, where i represents any value from 1 to N.

[0180] Step 1102: The abnormality detection circuit in the i-th signal monitoring module receives the i-th monitoring signal, and when it is determined that the i-th monitoring signal does not match the i-th reference information, obtains abnormal information of the i-th monitoring signal, stores the abnormal information in the first memory, and sends the abnormal information to the output module.

[0181] Step 1103: When the output module receives the abnormal information, it outputs an indication signal to the processor, so that the processor performs the target processing in response to the indication signal. For example, the processor can control the bus controller to restart or reset in response to the indication signal, and of course, it can also send a first read indication to the first memory, so that after receiving the first read indication, the first memory can send all abnormal information stored in the first memory to the processor for SerDes problem point analysis and location.

[0182] In an optional manner, when the i-th type of reference information can be set by the processor, the SerDes monitoring method disclosed in the present application may further include:

[0183] The abnormality detection circuit included in the i-th type signal monitoring module is also used to determine the i-th type reference information based on the configuration instruction when receiving the configuration instruction sent by the processor.

[0184] For example, the i-th type of reference information is a change duration threshold, and the abnormality detection circuit can detect whether the i-th type of monitoring signal changes within the change duration threshold. If it changes, it means that the i-th type of monitoring signal is normal. If it does not change, it means that the i-th type of monitoring signal is abnormal, and the abnormal information of the i-th type of monitoring signal is stored in the first memory.

[0185] In a possible implementation, the i-th type signal monitoring module further includes a second selector, which stores the abnormal information in the first memory, including:

[0186] When the second selector receives the clear instruction sent by the processor, it obtains the reset signal from the reset signal terminal and stores the reset signal in the first memory. Otherwise, when the abnormal information is obtained, it stores the abnormal information in the first memory.

[0187] In a possible implementation, the SerDes monitoring device disclosed in the embodiment of the present application further includes a first synchronizer 2023A. Storing the abnormal information in the first memory includes:

[0188] The first selector sends the exception information to the first synchronizer, the first synchronizer synchronizes the exception information to the target clock domain, and stores the exception information synchronized to the target clock domain to the first memory. When the processor is connected to the first memory through a bus module, the target clock domain is the clock domain of the bus module.

[0189] In a possible implementation, in the technical solution disclosed in the embodiment of the present application, the i-th type signal monitoring module further includes a signal identification circuit and a second memory. In this case, the SerDes monitoring method disclosed in the embodiment of the present application further includes:

[0190] The signal recognition circuit obtains the i-th monitoring signal, and if the i-th monitoring signal changes, the i-th monitoring signal is stored in the second memory. In this case, the processor can send a second read instruction to the second memory, and the second memory sends the i-th monitoring signal to the processor when receiving the second read instruction.

[0191] In a possible implementation, the SerDes monitoring method disclosed in the embodiment of the present application further includes:

[0192] When the signal recognition circuit detects a change in the i-th monitoring signal, it configures a target identifier for the i-th monitoring signal so that the i-th monitoring signal carries the target identifier, and the target identifier is used to identify the change position of the i-th monitoring signal.

[0193] In a possible implementation, in the technical solution disclosed in the embodiment of the present application, the i-th type signal monitoring module may further include an edge detection circuit and a third selector. Storing the i-th type monitoring signal in the second memory may include:

[0194] The signal recognition circuit in the i-th type signal monitoring module sends the i-th type monitoring signal to the edge detection circuit and the third selector;

[0195] The edge detection circuit sends a write enable signal to the third selector when detecting that the i-th type monitoring signal carries a target identifier;

[0196] The third selector stores the i-th type monitoring signal in the second memory when receiving the write enable signal.

[0197] In a possible implementation, in the technical solution disclosed in the embodiment of the present application, the i-th type signal monitoring module may further include a second synchronizer. In this case, storing the i-th type monitoring signal in the second memory may include:

[0198] The signal identification circuit sends the i-th type of monitoring signal to the second synchronizer, the second synchronizer synchronizes the i-th type of monitoring signal to the target clock domain, and sends the i-th type of monitoring signal synchronized to the target clock domain to the edge detection circuit and the third selector. When the processor is connected to the second memory through the bus module, the target clock domain is the clock domain of the bus module.

[0199] In one possible implementation, in the technical solution disclosed in the embodiment of the present application, the i-th signal monitoring module includes signal identification circuits of M attributes, the i-th monitoring signal includes monitoring signals of multiple attributes, the i-th reference information includes reference signals of multiple attributes, a monitoring signal of one attribute and a reference signal of one attribute correspond to a signal identification circuit of one attribute, and M represents an integer greater than or equal to 2.

[0200] In the technical solution disclosed in the embodiment of the present application, the i-th signal monitoring module also includes a fourth selector. In this case, the signal recognition circuit obtains the i-th monitoring signal, which may include: the signal recognition circuit of the j-th attribute in the i-th signal monitoring module receives the monitoring signal of the j-th attribute in the i-th monitoring signal.

[0201] If the i-th type of monitoring signal changes, storing the i-th type of monitoring signal in the second memory may include:

[0202] If the signal recognition circuit determines that the monitoring signal of the j-th attribute changes, the monitoring signal of the j-th attribute is sent to the fourth selector, where j represents any value from 1 to M;

[0203] The fourth selector obtains the monitoring signal of the jth attribute. If the fourth selector receives the screening signal of the target attribute sent by the processor, and determines that the screening signal of the target attribute matches the monitoring signal of the jth attribute, the fourth selector stores the monitoring signal of the jth attribute in the second memory.

[0204] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0205] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0206] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0207] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0208] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0209] Additionally, as used herein, "or" used in a list of items beginning with "at least one" indicates a separate list, so that, for example, a list of "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not mean that the example described is preferred or better than other examples.

[0210] It should also be noted that in the system and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0211] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0212] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A SerDes monitoring device, characterized in that: include: A first selector, a first memory, an output module, and multiple types of signal monitoring modules, wherein the first selector includes N output paths, one output path is connected to one type of signal monitoring module, and each of the signal monitoring modules includes an abnormality detection circuit, wherein N represents an integer greater than 0; The first selector is used for, when receiving the screening signal of the target channel sent by the processor, obtaining multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the screening signal of the target channel, and transmitting the i-th type of monitoring signal to the abnormality detection circuit in the i-th type of signal monitoring module through the i-th output path of the N output paths, where i represents any value from 1 to N; The abnormality detection circuit in the i-th type signal monitoring module is used to receive the i-th type monitoring signal, and when it is determined that the i-th type monitoring signal does not match the i-th type reference information, obtain abnormal information of the i-th type monitoring signal, store the abnormal information in the first memory, and send the abnormal information to the output module; The output module is used to output an indication signal to the processor when receiving the abnormal information, so that the processor performs target processing in response to the indication signal.

2. The SerDes monitoring device according to claim 1, characterized in that: The i-th type signal monitoring module further includes a second selector, the abnormality detection circuit and the second selector are connected to a reset signal terminal, and the abnormality detection circuit is used to send the abnormality information to the second selector; The second selector is used to obtain a reset signal from the reset signal terminal and store the reset signal in the first memory when receiving a clear indication sent by the processor; otherwise, when the exception information is obtained, store the exception information in the first memory.

3. The SerDes monitoring device according to claim 1, characterized in that: The abnormality detection circuit in the i-th type signal monitoring module is further used to determine the i-th type reference information based on the configuration indication when receiving the configuration indication sent by the processor.

4. The SerDes monitoring device according to claim 1, characterized in that: The i-th signal monitoring module includes an abnormality detection circuit of M attributes, the i-th monitoring signal includes monitoring signals of multiple attributes, the i-th reference information includes reference signals of multiple attributes, and M represents an integer greater than 0; The abnormality detection circuit of the jth attribute in the i-th type signal monitoring module is used to receive the monitoring signal of the jth attribute in the i-th type monitoring signal, and when it is determined that the monitoring signal of the jth attribute does not match the reference signal of the jth attribute in the i-th type reference information, obtain the abnormality information of the monitoring signal of the jth attribute, and store the abnormality information of the monitoring signal of the jth attribute in the first memory; The reference signal of the j-th attribute is a monitoring signal of an attribute in the i-th type of monitoring signal. The reference signal of the j-th attribute and the monitoring signal of the j-th attribute have the same category but different attributes.

5. The SerDes monitoring device according to any one of claims 1 to 4, characterized in that: The i-th type signal monitoring module further includes a signal identification circuit and a second memory, wherein i represents any one of some numerical values ​​from 1 to N; The first selector is further used to transmit the i-th type of monitoring signal to the signal identification circuit through the i-th output path; The signal identification circuit is used to obtain the i-th type of monitoring signal, and if it is detected that the i-th type of monitoring signal changes, the i-th type of monitoring signal is stored in the second memory.

6. The SerDes monitoring device according to claim 5, characterized in that: The signal identification circuit is also used to configure a target identifier for the i-th category monitoring signal when the i-th category monitoring signal changes, so that the i-th category monitoring signal carries the target identifier, and the target identifier is used to identify the change position of the i-th category monitoring signal.

7. The SerDes monitoring device according to claim 6, characterized in that: The i-th type signal monitoring module also includes an edge detection circuit and a third selector; The signal identification circuit in the i-th type signal monitoring module is used to send the i-th type monitoring signal to the edge detection circuit and the third selector; The edge detection circuit is used for sending a write enable signal to the third selector when detecting that the i-th type monitoring signal carries the target identifier; The third selector is used for storing the i-th type monitoring signal in the second memory when receiving the write enable signal.

8. The SerDes monitoring device according to claim 5, characterized in that: The i-th type signal monitoring module includes a signal recognition circuit of M attributes, the i-th type monitoring signal includes monitoring signals of multiple attributes, the i-th type reference information includes reference signals of multiple attributes, and M represents an integer greater than or equal to 2; The i-th type signal monitoring module also includes a fourth selector, and the signal identification circuit of the j-th attribute in the i-th type signal monitoring module is used to receive the monitoring signal of the j-th attribute in the i-th type monitoring signal, and if the monitoring signal of the j-th attribute changes, the monitoring signal of the j-th attribute is sent to the fourth selector, where j represents any value from 1 to M; The fourth selector is used to obtain the monitoring signal of the j-th attribute. If a screening signal of the target attribute sent by the processor is received, and if it is determined that the screening signal of the target attribute matches the monitoring signal of the j-th attribute, the monitoring signal of the j-th attribute is stored in the second memory.

9. A SerDes monitoring method, characterized in that: The invention is applied to a SerDes monitoring device, the SerDes monitoring device comprising: a first selector, a first memory, an output module and multiple types of signal monitoring modules, the first selector comprising N output paths, one output path being connected to one type of signal monitoring module, and each of the signal monitoring modules comprising an abnormality detection circuit, wherein N represents an integer greater than 0, and the method comprises: When the first selector receives the screening signal of the target channel sent by the processor, it obtains multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the screening signal of the target channel, and transmits the i-th type of monitoring signal to the abnormality detection circuit in the i-th type of signal monitoring module through the i-th output path of the N output paths, where i represents any value from 1 to N; The abnormality detection circuit in the i-th signal monitoring module receives the i-th monitoring signal, and when it is determined that the i-th monitoring signal does not match the i-th reference information, obtains abnormal information of the i-th monitoring signal, stores the abnormal information in the first memory, and sends the abnormal information to the output module; When receiving the abnormal information, the output module outputs an indication signal to the processor, so that the processor executes a target process in response to the indication signal.

10. A system on chip, characterized in that: include: A bus controller, a processor and a SerDes monitoring device, wherein the bus controller is connected to a SerDes bus, the SerDes monitoring device comprises a first selector, a first memory, an output module and multiple types of signal monitoring modules, the first selector comprises N output paths, one output path is connected to one type of signal monitoring module, and each of the signal monitoring modules comprises an abnormality detection circuit, wherein N represents an integer greater than 0; The processor is used to send a screening signal of the target channel to the control end of the first selector, and the first selector is used to obtain multiple types of monitoring signals of the target channel from the physical layer interface of the SerDes bus based on the screening signal of the target channel when receiving the screening signal of the target channel sent by the processor, and transmit the i-th type of monitoring signal to the abnormality detection circuit in the i-th type of signal monitoring module through the i-th output path of the N output paths, where i represents any value from 1 to N; The abnormality detection circuit in the i-th type signal monitoring module is used to receive the i-th type monitoring signal, and when it is determined that the i-th type monitoring signal does not match the i-th type reference information, obtain abnormal information of the i-th type monitoring signal, store the abnormal information in the first memory, and send the abnormal information to the output module; The output module is used to output an indication signal to the processor when receiving the abnormal information, and the processor is used to execute the target processing in response to the indication signal.

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