FPGA-based lightning signal GNSS synchronous high-speed data acquisition system

Abstract

The present invention relates to a lightning detection and collection system. It comprises a high-speed A / D conversion module, a GNSS timing unit, a data processing unit, a DDR data storage unit, an ARM processing unit, a file storage unit, and a data return unit. The high-speed A / D conversion module converts the lightning detection analog signal into a digital signal; the GNSS timing unit outputs a high-precision sampling reference clock to ensure the absolute time of the detected lightning signal. The data processing unit realizes analog-to-digital conversion control, lightning detection data acquisition, timestamp acquisition, pre-trigger and trigger control, peak acquisition, and output control. The FPGA logic gate circuit temporarily stores the processed data in the DDR data storage unit using DMA, and notifies the ARM processing unit to process the data; after receiving the notification of data collection, the ARM processing unit extracts the corresponding data from the DDR data storage unit cache and stores it in the file storage unit, and the extracted peak data and corresponding time information are returned to the data processing center through the data return unit.

Description

Technical Field

[0001] The invention relates to the technical field of atmospheric electricity and space electric field detection, and in particular to a lightning detection and collection system. Background Art

[0002] Lightning is one of the important phenomena in atmospheric electromagnetic activities and is of great significance to fields such as meteorology, atmospheric electricity and space science. The study of lightning depends on the acquisition of lightning signals. By measuring the changes in lightning electromagnetic fields, the characteristics of electromagnetic field changes at each stage of lightning can be obtained; time-synchronized distributed lightning signal high-speed acquisition provides essential detection data for lightning radiation source positioning and is a basic detection technology for obtaining lightning discharge characteristics, but the existing means still have great deficiencies in integration and reliability.

[0003] The core of the lightning detection system is the acquisition and storage of lightning signals. Currently, lightning detection mostly uses high-speed data acquisition cards in conjunction with industrial computers and BDS / GPS synchronous clocks to achieve lightning detection functions. Each component is a discrete component connected by cables, slots, etc. Due to the different lengths of the connection, there may be differences in signal transmission delays, and there are also great defects in signal anti-interference. There is an urgent need for a detection device with highly integrated functional components. Summary of the invention

[0004] The purpose of the present invention is to provide a lightning signal GNSS synchronous high-speed data acquisition system based on FPGA, which is composed of core devices and peripheral units composed of programmable gate array FPGA and embedded ARM processor, including high-speed A / D conversion module, GNSS timing unit, data processing unit, DDR data storage unit, ARM processing unit, file storage unit, and data return unit. The FPGA logic gate circuit is programmed to form a data processing unit 3, which realizes analog-to-digital conversion control, lightning detection data acquisition, timestamp acquisition, pre-trigger and trigger control, wave peak acquisition, and output control. The FPGA logic gate circuit filters the detection signal, oversamples, calculates the signal amplitude through Hilbert transformation, and triggers the peak value extraction function, and temporarily stores the processed data in the DDR data storage unit using DMA, and notifies the ARM processing unit to process the data; the ARM processing unit embedded operating system extracts the corresponding data from the DDR data storage unit cache and stores it in the file storage unit after receiving the notification of data acquisition, and the extracted peak data and corresponding time information are returned to the data processing center through the data return unit.

[0005] The technical solution adopted by the present invention to solve the technical problem is: a lightning signal GNSS synchronous high-speed data acquisition system based on FPGA, which is composed of core devices and peripheral units composed of FPGA logic gate circuits and embedded ARM processors, including a high-speed A / D conversion module 1, a GNSS timing unit 2, a data processing unit 3, a DDR data storage unit 4, an ARM processing unit 5, a file storage unit 6, and a data return unit 7. The high-speed A / D conversion module 1 converts the analog signal output by the lightning detection sensor into a digital signal; the GNSS timing unit 2 outputs a high-precision clock frequency as a sampling reference clock of the high-speed A / D conversion module 1 to ensure the accuracy of the signal conversion time, and the output high-precision full second clock signal 1PPS and NMEA0183 data with time information cooperate with the sampling reference clock to obtain the absolute time of the detected lightning electric signal. The FPGA logic gate circuit is programmed to form a data processing unit 3 to realize analog-to-digital conversion control, lightning detection data acquisition, timestamp acquisition, pre-trigger and trigger control, peak acquisition, and output control. The FPGA logic gate circuit filters the detection signal, oversamples, calculates the signal amplitude through Hilbert transform, and triggers the peak value extraction function. The processed data is temporarily stored in the DDR data storage unit 4 using DMA, and the ARM processing unit 5 is notified to process the data. The embedded operating system of the ARM processing unit 5 extracts the corresponding data from the cache of the DDR data storage unit 4 and stores it in the file storage unit 6 after receiving the notification of data collection. The extracted peak data and the corresponding time information are transmitted back to the data processing center through the data transmission unit 7.

[0006] The high-speed A / D conversion module 1 is composed of a limiter, an anti-aliasing filter, and a high-speed analog-to-digital conversion chip. The limiter is connected to the signal input end to limit the input signal voltage between the positive and negative power supply voltages to avoid damage to the back-end devices due to transient large signals such as lightning; the limiter output analog signal is connected to the anti-aliasing filter, and the filter cutoff frequency corresponding to the 80MS / s sampling rate is set to 30MHz; the anti-aliasing filter can suppress signals higher than the upper frequency limit corresponding to the Nyquist theorem to prevent frequency aliasing; the high-speed analog-to-digital conversion chip quantizes the analog signal into a digital signal under the drive of the sampling reference clock.

[0007] The GNSS timing unit 2 is composed of a BDS / GPS receiver and a highly stable constant temperature crystal oscillator (OCXO). The second pulse signal output by the BDS / GPS receiver is used as a sampling reference signal. The frequency offset of the output of the highly stable constant temperature crystal oscillator (OCXO) is measured, and the frequency loop of the highly stable constant temperature crystal oscillator (OCXO) is calibrated and compensated. The highly stable constant temperature crystal oscillator (OCXO) outputs a high-precision clock signal and a second signal. The time in the NMEA0183 protocol of the acquired clock signal plus 1s is used as the reference time t for the start of acquisition. start And wait for the system second pulse signal as the start time of collection.

[0008] The data processing unit 3 is composed of a digital-to-analog conversion control module, a pre-trigger and trigger control module, a timestamp acquisition module, a peak acquisition module, an output control module, and a data output module. The digital-to-analog conversion control module configures the high-speed A / D conversion module 1, and the pre-trigger and trigger control module generates a trigger signal and implements pre-triggering, and outputs the digital signal as waveform data; the timestamp acquisition module obtains time data by receiving the 1PPS and NMEA0183 signals of the GNSS timing unit 2 and combining them with the trigger signal; the peak acquisition module obtains the value and position of the maximum value point in the waveform data and outputs it as peak data, and the output control module outputs the waveform data, time data, and peak data in a scheduled order, and transmits them to the DDR data storage unit 4 through the data transmission module.

[0009] The DDR data storage unit 4 is a peripheral device of the FPGA, which is used for caching lightning data from the FPGA logic gate circuit to the ARM processing unit 5. The lightning waveform data, peak data, and time data output by the data processing unit 3 are transmitted to the DDR data storage unit 4 for temporary storage, and then all data are read out from the DDR data storage unit 4 and written into the file storage unit 6 through the ARM processing unit 5, thereby compensating for the speed difference between lightning signal collection and file writing.

[0010] The ARM processing unit 5 is an embedded module of the FPGA, including a DMA transmission control module, a file storage module, and a data output module. The DMA transmission control module is used to transmit FPGA data to the DDR data storage unit 4, and the file storage module is used to store lightning data in the file storage unit 6. The data return module UART serial port is connected to the data return unit 7 to realize data return.

[0011] The file storage unit 6 is a peripheral device of the FPGA and a local storage device of the high-speed data acquisition system. Each data packet in the DDR data storage unit 4 is read by the ARM processing unit 5 and stored in the storage device as an independent file. The timestamp is corrected by calculating the average clock cycle length, and the channel name, timestamp, peak size, and peak position are used as the file name, and the waveform data is written into the file in binary form.

[0012] The data return unit 7 is a peripheral device of the FPGA. The file is written into the total volume through the file storage module of the ARM processing unit 5, and is transmitted to the router through the data return module using the URAT interface with the TCP / IP protocol, and then transmitted to the data processing center through the Internet.

[0013] The beneficial effects of the present invention are: utilizing the internal programmable logic resources of FPGA to realize the real-time digital filtering function of lightning detection data, obtaining the electromagnetic radiation signal within the antenna bandwidth of the lightning detection sensor, and realizing the real-time waveform recognition and peak extraction of lightning signals and the output of results in the FPGA real-time data processing unit. Compared with the prior art, it can achieve higher accuracy and resolution to detect lightning signals, reduce the error caused by the jitter of the clock module timing of the BDS / GPS receiver, and the oversampling technology can further improve the effective resolution of the data. The system also integrates data extreme value information extraction and data network return, providing a powerful tool for efficient detection of lightning, helping to gain a deeper understanding of the physical process of lightning discharge, and can be used for a wide range of lightning monitoring and research applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the system of the present invention. DETAILED DESCRIPTION

[0015] The lightning signal GNSS synchronous high-speed data acquisition system based on FPGA of the present invention is implemented by combining software and hardware, taking FPGA as hardware and embedded processor as software, so that hardware and software are designed as an organic whole to achieve the best combination of hardware and software. FPGA is a chip whose internal structure can be changed by programming. Its full name is Field Programmable Gate Array, which is a digital integrated circuit. Its internal hardware resources include configurable basic logic units and configurable hardware connections. The internal structure of FPGA can be changed and configured by software means to realize specific design functions. The design and development process of FPGA involves programming using hardware description language, and then compiling, synthesizing, and layout and routing through EDA tools, and finally converting it into a burnable file, which is loaded into the FPGA device, thereby changing its internal connection and completing the realization of the required functions.

[0016] The system consists of core devices and peripheral units composed of FPGA logic gate circuits and embedded ARM processors, including high-speed A / D conversion module 1, GNSS timing unit 2, data processing unit 3, DDR data storage unit 4, ARM processing unit 5, file storage unit 6, and data return unit 7. The high-speed A / D conversion module 1 converts the analog signal output by the lightning detection sensor into a digital signal; the GNSS timing unit 2 outputs a high-precision clock frequency as the sampling reference clock of the high-speed A / D conversion module 1 to ensure the accuracy of the signal conversion time, and the output high-precision full-second clock signal 1PPS and NMEA0183 data with time information are used in conjunction with the sampling reference clock to obtain the absolute time of the detected lightning signal. The FPGA logic gate circuit is programmed to form the data processing unit 3 to realize analog-to-digital conversion control, lightning detection data acquisition, timestamp acquisition, pre-trigger and trigger control, peak acquisition, and output control. The FPGA logic gate circuit filters the detection signal, oversamples, calculates the signal amplitude through Hilbert transform, and triggers the peak value extraction function, and uses DMA to temporarily store the processed data in the DDR data storage unit 4, and notifies the ARM processing unit 5 to process the data. The embedded operating system of the ARM processing unit 5 extracts the corresponding data from the cache of the DDR data storage unit 4 and stores it in the file storage unit 6 after receiving the notification of data collection. The extracted peak data and the corresponding time information are transmitted back to the data processing center through the data transmission unit 7. Figure 1 .

[0017] The high-speed A / D conversion module 1 is composed of a limiter, an anti-aliasing filter, and a high-speed analog-to-digital conversion chip, which realizes the effective processing and conversion of analog signals, aiming to ensure the accuracy and efficiency of data acquisition. The limiter is connected to the signal input terminal to limit the input signal voltage between the positive and negative power supply voltages to avoid damage to the back-end devices due to transient large signals such as lightning. The limiter output analog signal is connected to the anti-aliasing filter, and the filter cutoff frequency corresponding to the 80MS / s sampling rate is set to 30MHz. The anti-aliasing filter can suppress signals higher than the upper frequency limit corresponding to the Nyquist theorem to prevent frequency aliasing. Driven by the sampling reference clock, the high-speed analog-to-digital conversion chip quantizes the analog signal into a digital signal.

[0018] GNSS timing unit 2 consists of a BDS / GPS receiver and a high-stable oven-controlled crystal oscillator (OCXO). The second pulse signal output by the BDS / GPS receiver is used as the sampling reference signal to measure the output frequency offset of the high-stable oven-controlled crystal oscillator (OCXO), and calibrate and compensate the frequency loop of the high-stable oven-controlled crystal oscillator (OCXO). The high-stable oven-controlled crystal oscillator (OCXO) outputs a high-precision clock signal and a second signal.

[0019] Accurate clock acquisition: After the system is powered on, the high-stable oven-controlled crystal oscillator (OCXO) outputs a 10MHz reference clock to the FPGA. The FPGA uses the PLL phase-locked loop function to multiply the frequency by 16 to output a 160MHz signal as the system working clock. The frequency accuracy of the 160MHz signal output by the PLL phase-locked output is consistent with the accuracy of the 10MHz signal output by the crystal oscillator. The clock module of the BDS / GPS receiver receives satellite signals. After obtaining stable positioning and time information, the second signal output by the clock module of the BDS / GPS receiver is used as the reference signal to measure the 160MHz signal phase-locked by the onboard high-stable oven-controlled crystal oscillator (OCXO). In order to improve the resolution of the measurement frequency and reduce the influence of the second pulse signal of the clock module of the BDS / GPS receiver on the atmospheric transmission jitter error, multiple second pulse signals are used as references to measure the accurate frequency of the signal. After receiving the second pulse of the clock module of the BDS / GPS receiver, the FPGA starts counting the 160MHz signal and stops counting after receiving the 1000th second pulse. The count value 1000 / 16 can be used to calculate the actual frequency of the high-stable oven-controlled crystal oscillator. The difference between the actual frequency of the high-stable constant temperature crystal oscillator and the theoretical 10MHz frequency is calculated. According to the crystal oscillator voltage control gain, the output control signal is adjusted to correct the crystal oscillator frequency. The crystal oscillator adjustment signal is controlled by Kalman filtering.

[0020] The frequency of the high-stable oven-controlled crystal oscillator (OCXO) is locked at 10MHz. The system uses the high-stable oven-controlled crystal oscillator (OCXO) PLL phase-locked multiplication to obtain a 160MHz clock signal, which is divided by 2 and used as the sampling clock.

[0021] Accurate second signal acquisition: The clock signal received by the clock module of the BDS / GPS receiver is the same source as the atomic clock on the satellite, which ensures that the long-term stability of the signal is sufficiently guaranteed. The satellite signal transmission path is affected by the atmosphere, which causes the time signal to have a large jitter (greater than 25ns) in a short time. In order to reduce the impact of the second signal jitter of the clock module of the BDS / GPS receiver, the following steps are taken: 1) Ensure that the high-stable constant temperature crystal oscillator works stably with an accuracy better than 2ppm. The clock module of the BDS / GPS receiver continuously outputs position and time signals. 2) Take the second pulse signal t0 output by the clock module of the BDS / GPS receiver at the current moment as the reference second pulse signal, count with the system 160MHz clock, and output the system second pulse signal every 160MHz. 3) Measure the time difference between the system second pulse signal and the second pulse signal of the clock module of the BDS / GPS receiver, and count 1000 time differences to obtain the average value of the time difference. 4) According to the average value of the second pulse time difference, correct the reference second pulse signal and output the system second pulse signal. 5) Repeat steps 2), 3), and 4. The system pulse-per-second signal is based on the pulse-per-second signal of the clock module of 1000 BDS / GPS receivers and a calibrated high-stability constant-temperature crystal oscillator. The accuracy and jitter are better than the pulse-per-second signal output by the clock module of the BDS / GPS receiver.

[0022] The data processing unit 3 of the present invention is composed of a digital-to-analog conversion control module, a pre-trigger and trigger control module, a timestamp acquisition module, a peak acquisition module, an output control module, and a data output module. The high-speed A / D conversion module 1 adopts the AD9627 high-speed analog-to-digital conversion chip, but the AD9627 chip cannot be used directly, and the digital-to-analog conversion control module is required to configure the high-speed A / D conversion module 1, and the high-speed analog-to-digital conversion chip is configured through the SPI interface to convert and output digital signals through Xilinx primitives. Both timestamp acquisition and peak information acquisition require trigger signals. The present invention generates trigger signals and realizes pre-trigger functions through pre-trigger and trigger control modules. The system adopts voltage triggering, and the input digital signal is continuously compared with the threshold voltage. When the threshold voltage is exceeded, the trigger signal changes from 0 to 1 and is output. The trigger signal changes back to a low level after counting 4096 digital signal clock cycles, generates a trigger signal, and outputs the digital signal as waveform data. The pre-trigger function not only saves the data after the trigger when the trigger signal arrives, but also saves the data for a period of time before the trigger. It is necessary to implement cache in FPGA and realize pre-triggering through read-write synchronous FIFO.

[0023] The timestamp acquisition module obtains time data by receiving the 1PPS and NMEA0183 signals from the GNSS timing unit 2 and combining them with the trigger signal. The timestamp acquisition module first obtains the time information in the NMEA0183 protocol output by the BDS / GPS receiver, and adds 1s to the time as the reference time for the start of the acquisition. start And wait for the system second pulse signal as the start time of acquisition, t start Save in Unix timestamp format. After the acquisition starts, a 32-bit counter counter1 is used to count the system second pulses, and a 32-bit counter counter2 is used to count the ADC sampling clock. When the external signal reaches the trigger moment, the values ​​in counter1 and counter2 are saved, and the time corresponding to the trigger moment is t start + counter1+counter2 / 80000000, the integer part is the Unix timestamp, and the decimal part is the precise time after the corresponding second, with a resolution of 1.25ns.

[0024] The peak acquisition module is used to find the peak of the lightning signal in real time and record the voltage value and position of the peak. After the rising edge of the trigger signal arrives, a set of continuous digital signal data is calculated in real time to find the maximum and minimum values, and the one with the largest absolute value is taken as the peak, and the voltage value of the peak and its position in the continuous data are output. When the rising edge of the trigger signal arrives, the counter starts counting by using the reference clock, and stores the digital signal data at this moment into the maximum value register and the minimum value register respectively, and stores the counter value at this moment into the maximum value position register and the minimum value position register. The digital signal data is continuously compared with the maximum value register and the minimum value register data. If the digital signal data is greater than the maximum value register data, the digital signal data at this moment is sent to the maximum value register and this register is used for the next comparison, and the counter value at this moment is sent to the maximum value position register. If it is not greater than the register value, it remains unchanged. Similarly, if the digital signal data is less than the minimum value register data, the digital signal data at this moment is sent to the minimum value register and this register is used for the next comparison, and the counter value at this moment is sent to the minimum value position register. If it is not less than the register value, it remains unchanged. When a set of continuous data comparison is completed, the maximum value, minimum value and corresponding position are all obtained. Since the digital signal data is represented by offset binary, the voltage from the minimum negative value to the maximum positive value is monotonically increasing in binary. If the highest bit is 1, the actual voltage is greater than 0, and if the highest bit is 0, the actual voltage is less than 0. Therefore, it is only necessary to compare the inverse code of the maximum value with the minimum value. The larger one is the point where the actual voltage is absolutely maximum, that is, the peak, and its position is the peak position. The peak and peak position can be obtained in two clock cycles after a set of continuous data transmission is completed. The value and position of the maximum value point in the waveform data are obtained in the peak acquisition module and output as peak data to the output control module.

[0025] The output control module outputs the waveform data, time data and peak data in a scheduled order, and transmits them to the DDR data storage unit 4 for storage through the data transmission module. After data processing, the lightning signal is output from the FPGA as 16-bit data at a speed of 80MHZ, and the data volume is 160MB / s. The maximum rate of writing data to the file storage unit 6 through the FATFS file system is 1MB / s, and the file creation time must also be considered. Therefore, the lightning signal acquisition speed is much faster than the file writing speed, and using DDR as a cache can effectively solve this problem. The DDR data storage unit 4 is an FPGA peripheral device, which is used for the cache of lightning data from the FPGA logic gate circuit to the ARM processing unit 5. The lightning waveform data, peak data, and time data output by the data processing unit 3 are transmitted to the DDR data storage unit 4 for temporary storage, and then all data are read from the DDR data storage unit 4 and written into the file storage unit 6 through the ARM processing unit 5, making up for the speed difference between lightning signal acquisition and file writing.

[0026] The ARM processing unit 5 is an embedded module of the FPGA. The AXI DMA SG mode transmission control module design is implemented in the ARM processor through the C language. The lightning waveform data, peak data, and time data in the data processing unit 3 are transmitted to the DDR data storage unit 4 through the S2MM receiving channel. It includes a DMA transmission control module, a file storage module, and a data output module. The DMA transmission control module controls the data transmission between memories or the data exchange process between external devices and memories, which allows data writing and data reading to be executed concurrently and synchronously. The functions of the DMA transmission control module are address and descriptor configuration and data transmission process control. The DMA transmission control module is used to realize the transmission of FPGA data to the DDR data storage unit 4. The functions of the file storage module are file name determination and file creation. The lightning data is stored in the file storage unit 6 through the file storage module. The functions of the data output module are UARTemio interface and AT command configuration. The data output module UART serial port is connected to the data return unit 7 to realize data return.

[0027] The file storage unit 6 is a peripheral device of the FPGA and a local storage device of the high-speed data acquisition system. Each data packet in the DDR data storage unit 4 is read by the ARM processing unit 5 and stored in the storage device as an independent file. The timestamp is corrected by calculating the average clock cycle length, and the channel name, timestamp, peak size, and peak position are used as the file name, and the waveform data is written to the file in binary form. The system operation status is monitored by the total amount of file writes, and the remaining space of the storage device is calculated. The file storage unit 6 is preferably a solid state hard disk, or an SD memory card, or a peripheral storage device can be connected via a USB interface.

[0028] The data return unit 7 is a peripheral device of the FPGA. The file is written into the total amount through the file storage module of the ARM processing unit 5. The data return module adopts a UART serial port connection to transmit the data to the router through the data return unit 7 via the TCP / IP protocol, and then transmits it to the data processing center via the Internet.

[0029] The description and drawings of this application are only a specific implementation method and are not restrictive. Under the guidance of this application, technicians in this field can make many forms without departing from the scope of protection of the purpose of this application and the claims, all of which are within the scope of protection of this application.

Claims

1. A lightning signal GNSS synchronous high-speed data acquisition system based on FPGA, characterized by: The acquisition system is composed of core devices and peripheral units consisting of FPGA logic gate circuits and embedded ARM processors, including a high-speed A / D conversion module (1), a GNSS timing unit (2), a data processing unit (3), a DDR data storage unit (4), an ARM processing unit (5), a file storage unit (6), and a data return unit (7); The high-speed A / D conversion module (1) converts the analog signal output by the lightning detection sensor into a digital signal; the GNSS timing unit (2) outputs a high-precision clock frequency as a sampling reference clock of the high-speed A / D conversion module (1) to ensure the accuracy of the signal conversion time, and the output high-precision full-second clock signal 1PPS and NMEA0183 data with time information are used in conjunction with the sampling reference clock to obtain the absolute time of the detected lightning signal; The FPGA logic gate circuit is programmed to form a data processing unit (3), and the data processing unit (3) is composed of a digital-to-analog conversion control module, a pre-trigger and trigger control module, a timestamp acquisition module, a wave peak acquisition module, an output control module, and a data output module. The digital-to-analog conversion control module configures the high-speed A / D conversion module (1) to realize analog-to-digital conversion control, lightning detection data acquisition, timestamp acquisition, pre-trigger and trigger control, wave peak acquisition, and output control; the pre-trigger and trigger control module generates a trigger signal and realizes pre-triggering, and outputs the digital signal as waveform data; the timestamp acquisition module receives the 1PPS and NMEA0183 signals of the GNSS timing unit (2) and obtains time data after combining the trigger signal; in the wave peak acquisition module, the 1PPS and NMEA0183 signals of the GNSS timing unit (2) are received and combined with the trigger signal. The module obtains the value and position of the maximum value point in the waveform data and outputs it as peak data. The output control module outputs the waveform data, time data and peak data in a sequence and transmits them to a DDR data storage unit (4) through a data transmission module. The DDR data storage unit (4) is an FPGA peripheral device and is used for caching lightning data from the FPGA logic gate circuit to the ARM processing unit (5). The lightning waveform data, peak data and time data output by the data processing unit (3) are transmitted to the DDR data storage unit (4) for temporary storage. Then, all data are read from the DDR data storage unit (4) and written into the file storage unit (6) through the ARM processing unit (5), thereby compensating for the speed difference between lightning signal acquisition and file writing. The FPGA logic gate circuit filters the detection signal, oversamples it, calculates the signal amplitude through Hilbert transform, triggers the peak value extraction function, and temporarily stores the processed data in the DDR data storage unit (4) through DMA, and notifies the ARM processing unit (5) to process the data; the ARM processing unit (5) embedded operating system extracts the corresponding data from the cache of the DDR data storage unit (4) and stores it in the file storage unit (6) after receiving the notification of the collected data, and the extracted peak value data and corresponding time information are transmitted back to the data processing center through the data transmission unit (7).

2. The FPGA-based lightning signal GNSS synchronous high-speed data acquisition system according to claim 1 is characterized in that: The high-speed A / D conversion module (1) is composed of a limiter, an anti-aliasing filter, and a high-speed analog-to-digital conversion chip. The limiter is connected to the signal input terminal to limit the input signal voltage between the positive and negative power supply voltages to prevent the back-end devices from being damaged by large transient lightning signals. The limiter output analog signal is connected to the anti-aliasing filter, and the filter cutoff frequency corresponding to the 80MS / s sampling rate is set to 30MHz. The anti-aliasing filter can suppress signals higher than the upper frequency limit corresponding to the Nyquist theorem to prevent frequency aliasing. The high-speed analog-to-digital conversion chip quantizes the analog signal into a digital signal under the drive of a sampling reference clock.

3. The FPGA-based lightning signal GNSS synchronous high-speed data acquisition system according to claim 1 is characterized in that: The GNSS timing unit (2) is composed of a BDS / GPS receiver and a high-stable constant temperature crystal oscillator (OCXO). The second pulse signal output by the BDS / GPS receiver is used as a sampling reference signal. The frequency offset of the output of the high-stable constant temperature crystal oscillator (OCXO) is measured, and the frequency loop of the high-stable constant temperature crystal oscillator (OCXO) is calibrated and compensated. The high-stable constant temperature crystal oscillator (OCXO) outputs a high-precision clock signal and a second signal. The time in the NMEA0183 protocol of the acquired clock signal plus 1 second is used as the reference time t for the start of acquisition. start And wait for the system second pulse signal as the start time of collection.

4. The FPGA-based lightning signal GNSS synchronous high-speed data acquisition system according to claim 1 is characterized in that: The ARM processing unit (5) is an embedded module of the FPGA, including a DMA transmission control module, a file storage module, and a data output module. The DMA transmission control module is used to transmit FPGA data to the DDR data storage unit (4), the file storage module is used to store lightning data in the file storage unit (6), and the data return module is connected to the data return unit (7) through a UART serial port to realize data return.

5. The FPGA-based lightning signal GNSS synchronous high-speed data acquisition system according to claim 1 is characterized in that: The file storage unit (6) is a peripheral device of the FPGA and a local storage device of the high-speed data acquisition system. Each data packet in the DDR data storage unit (4) is read by the ARM processing unit (5) and stored in the storage device as an independent file. The timestamp is corrected by calculating the average clock cycle length, and the channel name, timestamp, peak size, and peak position are used as the file name, and the waveform data is written into the file in the form of binary numbers.

6. The FPGA-based lightning signal GNSS synchronous high-speed data acquisition system according to claim 1 is characterized by: The data return unit (7) is a peripheral device of the FPGA. The file is written into the total volume through the file storage module of the ARM processing unit (5), and is transmitted to the router through the data return module using the URAT interface with the TCP / IP protocol, and then transmitted to the data processing center through the Internet.

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