A Universal M-LVDS Bus Protocol Design Method

Abstract

The present invention discloses a universal M-LVDS bus protocol design method, which belongs to the technical field of backplane bus of electronic products of aerospace measurement and control systems. The backplane high-speed bus is an M-LVDS bus, and a master node and several slave nodes are provided on the bus; the master node sends a master clock and command signal, which are sent to the slave node via the bus; the slave node sends a slave clock and data signal, which are sent to the master node via the bus. The bus uses time-division multiplexing, and the communication cycle is the subframe cycle of the aerospace measurement and control system. The physical layer data protocol and the link layer protocol are established to ensure orderly data transmission and reception on the bus; in each communication cycle, the master node sends the command signal according to the timing, and the slave node uploads the data signal according to the received command signal. Through the application of the present invention, reliable information transmission between multiple boards in the integrated electronic equipment of the aerospace measurement and control system is achieved.

Description

Technical Field

[0001] The invention relates to a universal M-LVDS bus protocol design method, belonging to the technical field of backplane buses of electronic products in aerospace measurement and control systems. Background Art

[0002] The integrated electronics products for aerospace measurement and control systems consist of an integrated module combined with various acquisition and editing modules. These modules collect diverse parameters in real time, at high speeds, and with high precision. The collected data is then aggregated to the integrated module for framing. Therefore, communication between the multiple boards within the product requires the design and implementation of a reliable bus protocol that can handle high-capacity, high-speed data transmission.

[0003] Existing high-speed backplane buses are implemented in two ways: parallel and serial. Serial buses offer advantages such as simple design, strong anti-interference capabilities, and low cost. The widely used CAN bus uses a multi-master architecture to support free communication between multiple nodes. However, the CAN bus has a theoretical maximum communication rate of only 1Mbps, and a single message frame only transmits 8 bytes of valid data, making it unsuitable for high-capacity, high-speed data transmission scenarios.

[0004] Chinese patent CN101459675B proposes a real-time, multiplexed, synchronous, high-speed serial bus protocol. The serial bus's transmission signals include a control signal, a clock signal, and a data signal. A single node is pre-designated as the sole master node on the bus. The master node issues a control signal to control each node's data transmission in turn. The transmission order and data length for each node are pre-set. The bus protocol proposed in this application places high demands on the master node's stability and lacks reliability design. The master node lacks the ability to monitor and control information from any slave node in real time, and each node can only transmit data according to a pre-assigned data length. This protocol fails to meet the design requirements for high speed and reliability, and lacks adaptability. Summary of the Invention

[0005] The technical problem solved by the present invention is to overcome the shortcomings of the existing technology and propose a universal M-LVDS bus protocol design method. Based on the M-LVDS interface, a high-speed and reliable one-master-multiple-slave bus physical layer and link layer communication protocol is designed to achieve reliable information transmission between multiple boards.

[0006] The technical solution of the present invention is:

[0007] A general M-LVDS bus protocol design method:

[0008] The backplane high-speed bus is an M-LVDS bus, which has a master node and several slave nodes. The master node sends a master clock and command signal, which are sent to the slave nodes via the bus. The slave nodes send a slave clock and data signal, which are sent to the master node via the bus. The command signals include synchronization commands, data acquisition commands, control commands, and self-test parameter acquisition commands.

[0009] The bus uses time-division multiplexing, with the communication cycle being the subframe cycle of the aerospace measurement and control system. Physical layer data protocols and link layer protocols are established to ensure orderly data transmission and reception on the bus. In each communication cycle, the master node sends command signals in sequence, and the slave node uploads data signals based on the received command signals.

[0010] Furthermore, in each communication cycle, the master node sends a command signal according to the timing sequence, and the specific timing sequence is:

[0011] First, the master node sends a synchronization instruction to all slave nodes;

[0012] Secondly, the master node sends a data fetch instruction to the slave node;

[0013] The control instructions and self-test parameter instructions are optional instructions and are not instructions that must be sent in each sequence. If the master node wants to send a control instruction or a self-test parameter instruction, it must send the control instruction or the self-test parameter instruction after the master node has sent all data acquisition instructions and received all data reported by the corresponding slave nodes. At the same time, the control instruction has a higher priority than the self-test parameter instruction. If both the control instruction and the self-test parameter instruction are to be sent, the control instruction is sent first and then the self-test parameter instruction is sent.

[0014] Furthermore, if data acquisition instructions are to be sent to multiple slave nodes, the slave nodes are sorted and sent in sequence, and the data acquisition instruction is sent to the next slave node after receiving the data reported by the current slave node; if any slave node exits abnormally, the slave node is skipped without affecting the normal communication of other nodes on the bus.

[0015] Furthermore, the physical layer data protocol established is:

[0016] For synchronization instructions: the master node sends a synchronization instruction to each slave node once in each communication cycle. After receiving the synchronization instruction, each slave node synchronizes its local sampling clock with the master node clock.

[0017] For data access instructions: the master node sends a data access instruction to the slave node. The instruction contains the address of the slave node that needs to access data. The corresponding slave node uses a response data reporting method and sends data according to the data length required by the master node within 1μs.

[0018] For control instructions: the master node sends a control instruction to the slave node. The instruction contains the address identifier and control data of the slave node to be controlled, and the corresponding slave node performs the corresponding action;

[0019] For self-test parameter instructions: the master node sends a self-test parameter instruction to the slave node. The instruction contains the address identifier of the slave node that needs to report the self-test parameters. The corresponding slave node adopts a response data reporting method and sends data in the specified format within 1μs.

[0020] Furthermore, if the slave node reports data acquisition or self-test parameter data and the actual number of data bytes of the slave node is less than the valid data length, the slave node fills the remaining part of the valid data with 0x77; when the master node receives and parses the data reported by the slave node and finds that it does not conform to the standard format, the master node fills the channel corresponding to the valid data of the slave node with 0xDD.

[0021] Furthermore, according to usage requirements, the data length field of the transmission frame is modified, that is, the data length field in the master node data acquisition instruction is adaptively modified to enable the slave node to transmit data according to the new transmission frame length.

[0022] Furthermore, the established link layer data protocol is:

[0023] For a master node or a slave node, when acting as a transmitter, the signal is sent on the rising edge of the local clock, and the receiver latches the signal on the falling edge of the transmitter clock;

[0024] When the slave node is powered on or not sending clock and data, the bus remains in a high-impedance state;

[0025] After receiving the data acquisition instruction or the self-test parameter acquisition instruction, the slave node sends the clock and data within 1μs: the slave node sends n cycles of clock signal before sending data, and continues to send m cycles of clock signal after sending data. During the above-mentioned clock signal transmission process, the slave node data output is 0;

[0026] The master clock output by the master node is a continuous clock, and the slave clock output by the slave node is an intermittent clock. The frequency difference between the slave clock and the master clock shall not exceed ±5%.

[0027] Furthermore, the backplane high-speed bus is an M-LVDS bus, which has a master node and several slave nodes. The circuit and electrical interface are configured as follows:

[0028] The master node and the slave node are respectively equipped with a control module, and each control module is equipped with two M-LVDS interface chips, which are connected to the M-LVDS bus together. The bus adopts serial differential signal transmission;

[0029] The master node control module sends the master clock and command signals, which are converted into M-LVDS differential signals by an M-LVDS interface chip and sent to each slave node through the bus. Another M-LVDS interface chip connected to the master node control module receives the slave clock and data signals sent by the slave node control module on the bus, and sends them to the master node control module after signal conversion.

[0030] An M-LVDS interface chip connected to the slave node control module receives the master clock and command signals sent by the master node control module on the bus, and sends them to the slave node control module after signal conversion; the slave node control module sends the slave clock and data signals, which are converted into M-LVDS differential signals by another M-LVDS interface chip and sent to the master node through the bus.

[0031] Furthermore, two master nodes and two M-LVDS buses are set up, and each master node is connected to each slave node via a bus; each slave node de-redundantly responds to the instructions of the two master nodes and outputs two channels of information for mutual backup; specifically:

[0032] For synchronization instructions: the two master nodes send synchronization instructions to each slave node through their respective buses. Each slave node adopts the principle of first come first served, that is, the slave node responds to the synchronization instruction received first, performs local clock synchronization, and blocks the synchronization instructions on the other bus at the same time;

[0033] For data fetch instructions or self-test data instructions: the two master nodes send data fetch instructions or self-test data instructions to the slave nodes through their respective buses, and the corresponding slave nodes independently respond to the instructions of the two master nodes through two buses and report the data to each master node;

[0034] For control instructions: the two master nodes send control instructions to the slave nodes through their respective buses, and the corresponding slave nodes receive the control instructions sent by the two master nodes through two buses respectively, and perform corresponding actions according to the definition of the instruction content.

[0035] Furthermore, the two master nodes are synchronized through the synchronization instructions of the bus. The specific implementation method is: when the master node of the first bus sends a synchronization instruction to each slave node in each communication cycle, it also sends a synchronization instruction to the master node of the second bus. The master node of the second bus responds to the received synchronization instruction and synchronizes with the master node of the first bus.

[0036] The advantages of the present invention compared with the prior art are:

[0037] (1) The present invention proposes a universal M-LVDS bus protocol, which supports high-speed serial communication based on the backplane of the M-LVDS standard interface. By modifying the data length field in the master node configurable file, it adapts to the needs of transmitting different amounts of data on the bus, enabling data transmission products of aerospace measurement and control systems to have a transmission rate of hundreds of Mbps.

[0038] (2) In the bus protocol designed by the present invention, the master node has the authority to schedule any slave node on the bus. The health status of any slave node can be obtained by the master node sending a self-test instruction at any time. In other words, the master node can determine in real time whether the communication function of each slave node is healthy. At the same time, the failure or abnormal exit of any slave node will not affect the normal communication of other nodes on the bus, and the bus has the ability to transmit stably and reliably.

[0039] (3) In the bus protocol designed by the present invention, slave nodes can output two paths of information that back up each other through a dual-redundancy strategy, ensuring the reliability of slave node data transmission. Simultaneously, a dual-master node redundancy strategy can be set up for nodes A / B to ensure reliable backup transmission of the master node. This dual-master / slave node redundancy strategy effectively ensures the high reliability of data transmission on the M-LVDS bus interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0041] Figure 1 Schematic diagram of bus signal flow based on M-LVDS interface of the present invention;

[0042] Figure 2 This is a bus timing diagram based on the M-LVDS interface of the present invention;

[0043] Figure 3 This is a schematic diagram of the hardware connection of the dual-redundant M-LVDS interface of the present invention. DETAILED DESCRIPTION

[0044] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] like Figure 1As shown in the figure, the backplane high-speed bus uses an interface chip that supports the M-LVDS (multi-point low voltage differential signal) interface to build the peripheral hardware circuit. The bus uses serial differential signal transmission. The interface chip is connected to the logic device FPGA, and the FPGA completes the high-speed bus link layer communication protocol control.

[0046] The present invention proposes a universal M-LVDS bus protocol design method, which designs bus circuits and electrical interfaces, timing requirements, data transmission and reception requirements, communication protocol requirements, and dual M-LVDS bus scheduling methods, thereby realizing reliable information transmission between multiple boards in the integrated electronic equipment of aerospace measurement and control systems.

[0047] (1) Bus circuit and electrical interface

[0048] The backplane high-speed bus uses an interface chip that supports the M-LVDS standard interface to build peripheral hardware circuits. The M-LVDS bus signal flow diagram is as follows: Figure 1 As shown, the backplane signal definition is shown in Figure 2 The M-LVDS bus complies with the ANSI / TIA / EIA-899 standard, and the interface level standard is the M-LVDS level standard.

[0049] The master and slave nodes are interconnected via the backplane bus and M-LVDS interface chip. The master node transmits master clock and command signals, which are converted into M-LVDS differential signals by the M-LVDS interface chip and sent via the backplane to each slave node. The slave node then undergoes signal conversion via the M-LVDS interface chip and sends them to its control circuit. The slave node also transmits slave clock and data signals, which are converted into M-LVDS differential signals by the M-LVDS interface chip and sent via the backplane to the master node. The master node then undergoes signal conversion via the M-LVDS interface chip and sends them to its control circuit, which then controls the link layer communication protocol.

[0050] Table 1M-LVDS bus backplane signal definition table

[0051] Serial number Signal Definition Signal Description 1 M-LVDS0+ Master->Slave Clock+ 2 M-LVDS0- Master->Slave Clock- 3 M-LVDS1+ Master->Slave Instructions+ 4 M-LVDS1- Master->Slave Instructions- 5 M-LVDS2+ Slave->Master Clock+ 6 M-LVDS2- Slave->Master Clock- 7 M-LVDS3+ From->Master Data+ 8 M-LVDS3- From -> Master Data -

[0052] (2) Bus timing

[0053] like Figure 1 As shown, the bus transmits four signals, namely synchronization instructions, data acquisition instructions and data reporting (represented by n), control instructions / data (represented by m), and self-test parameter acquisition instructions (represented by x), in a time-division multiplexing manner.

[0054] 1) The working sequence of each cycle (subframe cycle) of the master node is:

[0055] a. The master node first sends a synchronization command, which is a mandatory command. After receiving and parsing the synchronization command, each slave node on the bus completes the time synchronization of each subframe cycle. That is, the acquisition time zero of the slave node in each subframe cycle starts at the moment of receiving the synchronization command;

[0056] b. The master node sends a data fetch instruction 1, which is a mandatory instruction. Instruction 1 contains the address identifier of slave node 1. After receiving the fetch instruction, slave node 1 sends all data in the current subframe period to the M-LVDS bus according to the communication protocol requirements for the master node to read.

[0057] Note: The example in this article assumes that the address in the data access instruction 1 is identified as slave node 1, that is, the data from slave node 1 is retrieved.

[0058] c. The master node receives and analyzes all the data reported by slave node 1 in this subframe period. And so on. When the master node needs to obtain data from multiple slave nodes, it repeats steps b and c above.

[0059] d. The master node sends a control instruction / data, which is an optional instruction and is sequenced after the master node has sent all the data acquisition instructions. When the master node needs to control the slave node at certain moments in the full frame or in a subframe period, the master node sends a control instruction / data. The instruction contains the address identifier and control data of the slave node to be controlled. The slave node performs the corresponding action according to the content of the received instruction / data without replying to the master node. If the master node needs to control multiple slave nodes, repeat the steps in item d. Note that the master node has no requirements for the order in which multiple control instructions / data are sent, which is based on the specific application.

[0060] e. The master node sends a self-test parameter acquisition instruction, which is an optional instruction and is sequenced after the master node has sent all control instructions / data (if any). When the master node needs to obtain the self-test data of a slave node at certain moments in the full frame or in a subframe period, the master node sends a self-test parameter acquisition instruction. The instruction contains the address identifier of the slave node from which the self-test parameters need to be acquired. After the slave node receives and parses the self-test parameter acquisition instruction for this node, it sends the self-test parameter data of this node to the M-LVDS bus (consistent with the data reporting protocol corresponding to the acquisition instruction) according to the communication protocol requirements for the master node to read;

[0061] Note: The formats of the data fetch instruction n and the self-test parameter fetch instruction x can be consistent. The data fetch instruction and the self-test parameter fetch instruction for the same slave node can be distinguished by different address identifiers.

[0062] (3) Bus physical layer data protocol (example)

[0063] a. Synchronous instructions

[0064] Synchronous command, master node → slave node, sent once per subframe period, the command format is shown in Table 2:

[0065] Table 2 Physical layer data protocol synchronization instruction format

[0066]

[0067]

[0068] After receiving the synchronization instruction from the master node, the slave node synchronizes the local sampling clock with the master node clock and determines the meaning of the identification code according to the identification code definition.

[0069] b. Acquisition (including self-test parameters) instructions and data (including self-test parameters) reporting

[0070] Data reporting (including self-test parameters) adopts the response data reporting method. The master node first sends the data acquisition instruction, and the slave node reports the data of this module.

[0071] Data fetch instruction, master node → slave node, instruction format see Table 3 and Table 4:

[0072] Table 3 Physical layer data protocol data acquisition instruction format

[0073] Serial number Field Name Length (Byte) Content (HEX) 1 Frame header 1 7E 2 Slave node ID 1 See Table 4 3 Valid data length 1 The number of "valid data" bytes required to be returned from the node 4 Frame tail 1 7E

[0074] Table 4 Physical layer data protocol slave node identification definition table

[0075] Serial number Slave node name Slave node data identifier (HEX) Slave node self-test identifier (HEX) 1 Slave Node 1 1F 2F 2 Slave Node 2 2E 3E 3 Slave Node 3 3D 4D 4 Slave Node 4 4C 5C 5 Slave Node 5 5B 6B 6 Slave Node 6 6A 7A 7 Slave Node 7 79 89 8 Slave Node 8 88 98 9 Slave Node 9 97 A7 10 Slave Node 10 A6 B6 11 Slave node 11 B5 C5

[0076] Data reporting (including self-test parameters), slave node → master node, data reporting format is shown in Table 5:

[0077] Table 5 Physical layer data protocol data reporting format

[0078] Serial number Field Name Length (Byte) Content (HEX) 1 Frame header 1 7E 2 Valid data length 1 Number of bytes of "valid data" 3 Valid data Defined according to specific application requirements Defined according to specific application requirements 4 Frame tail 1 7E

[0079] After receiving the data fetch instruction from this module, the slave node sends data in the specified format within 1μs. If the actual number of bytes of data from the slave node is less than the valid data length, the slave node fills the remaining portion of the valid data with 0x77. If the master node parses the data reported by the slave node and finds that it does not conform to the specified format, the master node fills the channel corresponding to the valid data of the slave node with 0xDD.

[0080] c. Control instructions / data

[0081] Control instructions / data, master node → slave node, control instructions / data format is shown in Table 6.

[0082] Table 6 Physical layer data protocol control command / data format

[0083] Serial number Field Name Length (Byte) Content (HEX) 1 Frame header 1 7E 2 Control instruction / data identification 1 BB 3 Slave node ID 1 See Table 4 4 Command / data length 1 Number of bytes of instruction / data content 5 Command / data content Defined according to specific application requirements Defined according to specific application requirements 6 Frame tail 1 7E

[0084] After receiving the control instruction / data from the master node, the slave node executes the corresponding action according to the instruction / data content definition.

[0085] (4) Bus link layer protocol

[0086] To ensure orderly data transmission and reception on the bus, the link layer protocol requires the following:

[0087] a. The transmitter sends instructions / data on the rising edge of the transmitter clock, and the receiver latches instructions / data on the falling edge of the transmitter clock.

[0088] b. Each slave node outputs clock and data in a time-sharing manner. When the slave node is powered on and not sending clock and data, the bus remains in a high-impedance state and the bus interface chip is disabled from sending.

[0089] c. After receiving a data fetch command or a self-test parameter fetch command, the slave node sends clock and data signals within 1 μs. When sending, the slave node sends eight clock cycles before sending data and another eight clock cycles after sending data. The slave node's data output is 0 for 16 clock cycles before and after the data is sent.

[0090] d. The master node output clock is a continuous clock, and the slave node output clock is an intermittent clock. The frequency difference between the slave node output clock and the master node output clock shall not exceed ±5%.

[0091] The eM-LVDS bus link layer communication protocol uses the following translation process: When the transmitter is sending data (excluding the frame header and frame footer identifier 0x7E), if it encounters five consecutive "1s", it automatically inserts a "0" after them; when the receiver is receiving data (excluding the frame header and frame footer identifier 0x7E), if it receives five consecutive "1s", it automatically deletes the following "0" to restore the original data.

[0092] (5) Bus communication cycle

[0093] Taking the full-frame / sub-frame communication cycle commonly used in aerospace measurement and control systems as an example, the M-LVDS bus communication cycle is the system sub-frame cycle, such as 20 / 60ms and 25 / 64ms.

[0094] (6) Protocol configurability

[0095] The transmission frame length and slave node scheduling sequence are configurable. Based on usage requirements, only the data length field in the transmission frame protocol is modified. This adaptively modifies the data length field in the master node's fetch instruction, allowing slave nodes to transmit data according to the new transmission frame length. The slave node scheduling sequence is also specified in the configuration file. The abnormal exit of any slave node will not affect the normal communication of other nodes on the bus, ensuring high stability and reliability.

[0096] (7) Dual redundant communication strategy

[0097] like Figure 3 As shown, two groups of M-LVDS standard interface circuits are designed in the hardware to support dual redundant data transmission.

[0098] The software supports dual redundancy strategy. The master node has the authority to dispatch any slave node on the bus. The slave node has the ability to deduplicate the instructions of the two master nodes and respond promptly. The slave node outputs two channels of information to back up each other, ensuring high reliability of communication.

[0099] In the dual M-LVDS bus communication scheduling mode, the requirements for the above instructions are as follows:

[0100] a. Synchronous instructions

[0101] The two master nodes of the dual M-LVDS bus send synchronization instructions to each slave node (excluding the master node of the other M-LVDS bus) through their respective M-LVDS buses. Each slave node adopts the "first come, first served" principle, that is, the slave node responds to the synchronization instruction received first and performs local clock synchronization, while shielding the synchronization instruction on the other M-LVDS bus in this subframe period.

[0102] The following methods can be used to synchronize the two master nodes of a dual M-LVDS bus, with a clock synchronization error of no more than 100ns:

[0103] The two master nodes are synchronized through the synchronization instructions of the M-LVDS bus. The specific implementation method is: when the master node of the first M-LVDS bus sends a synchronization instruction to each slave node in each subframe period, it also sends a synchronization instruction to the master node of the second M-LVDS bus. The master node of the second M-LVDS bus responds to the received synchronization instruction and synchronizes with the master node of the first M-LVDS bus.

[0104] b. Acquisition (including self-test parameters) instructions and data (including self-test parameters) reporting

[0105] The two master nodes of the dual M-LVDS bus send data access instructions to each slave node (excluding the master node of the other M-LVDS bus) through their respective M-LVDS buses. Each slave node independently responds to the data access instructions of the two master nodes through two buses and reports the data in the corresponding cache of the slave node (one corresponding cache area is established for each of the two M-LVDS buses, and the data in the two cache areas are the same) to the corresponding master node.

[0106] c. Control instructions / data

[0107] The two master nodes of the dual M-LVDS bus send control instructions / data to each slave node (excluding the master node of the other M-LVDS bus) through their respective M-LVDS buses. Each slave node receives the control instructions / data sent by the two master nodes through two buses and performs corresponding actions according to the content definition of the instructions / data.

[0108] The above-described embodiments are only preferred specific implementations of the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A general M-LVDS bus protocol design method, characterized in that: The backplane high-speed bus is an M-LVDS bus, which has a master node and several slave nodes. The master node sends a master clock and command signal, which are sent to the slave nodes via the bus. The slave nodes send a slave clock and data signal, which are sent to the master node via the bus. The command signals include synchronization commands, data acquisition commands, control commands, and self-test parameter acquisition commands. The bus uses time-division multiplexing, with the communication cycle being the subframe cycle of the aerospace measurement and control system. Physical layer data protocols and link layer protocols are established to ensure orderly data transmission and reception on the bus. In each communication cycle, the master node sends command signals in sequence, and the slave node uploads data signals based on the received command signals. Set up two master nodes and two M-LVDS buses. Each master node is connected to each slave node through a bus. Each slave node removes redundancy and responds promptly to the instructions of the two master nodes. The slave nodes output two channels of information for mutual backup. Specifically: For synchronization instructions: the two master nodes send synchronization instructions to each slave node through their respective buses. Each slave node adopts the principle of first come first served, that is, the slave node responds to the synchronization instruction received first, performs local clock synchronization, and blocks the synchronization instructions on the other bus at the same time; For data fetch instructions or self-test data instructions: the two master nodes send data fetch instructions or self-test data instructions to the slave nodes through their respective buses, and the corresponding slave nodes independently respond to the instructions of the two master nodes through two buses and report the data to each master node; For control instructions: the two master nodes send control instructions to the slave nodes through their respective buses, and the corresponding slave nodes receive the control instructions sent by the two master nodes through two buses respectively, and perform corresponding actions according to the definition of the instruction content.

2. The universal M-LVDS bus protocol design method according to claim 1, characterized in that: In each communication cycle, the master node sends the command signal according to the timing. The specific timing is: First, the master node sends a synchronization instruction to all slave nodes; Secondly, the master node sends a data fetch instruction to the slave node; The control instruction and the self-test parameter acquisition instruction are optional instructions and are not instructions that must be sent in each timing sequence. If the master node wants to send a control instruction or a self-test parameter acquisition instruction, it must send the control instruction or the self-test parameter acquisition instruction after the master node has sent all data acquisition instructions and received all data reported by each corresponding slave node. At the same time, the control instruction has a higher priority than the self-test parameter acquisition instruction. If both the control instruction and the self-test parameter acquisition instruction are to be sent, the control instruction is sent first and then the self-test parameter acquisition instruction is sent.

3. The universal M-LVDS bus protocol design method according to claim 2, characterized in that: If you want to send data access instructions to multiple slave nodes, sort the slave nodes and send them in sequence. After receiving the data reported by the current slave node, send the data access instruction to the next slave node. If any slave node exits abnormally, the slave node will be skipped without affecting the normal communication of other nodes on the bus.

4. The universal M-LVDS bus protocol design method according to claim 1, wherein: The physical layer data protocol established is: For synchronization instructions: the master node sends a synchronization instruction to each slave node once in each communication cycle. After receiving the synchronization instruction, each slave node synchronizes its local sampling clock with the master node clock. For data access instructions: the master node sends a data access instruction to the slave node. The instruction contains the address of the slave node that needs to access data. The corresponding slave node uses a response data reporting method and sends data according to the data length required by the master node within 1μs. For control instructions: the master node sends a control instruction to the slave node. The instruction contains the address identifier and control data of the slave node to be controlled, and the corresponding slave node performs the corresponding action; For the self-test parameter acquisition instruction: the master node sends a self-test parameter acquisition instruction to the slave node. The instruction contains the address identifier of the slave node that needs to report the self-test parameters. The corresponding slave node adopts a response data reporting method and sends data in the specified format within 1μs.

5. The universal M-LVDS bus protocol design method according to claim 4, characterized in that: If the slave node reports data acquisition or self-test parameter data and the actual number of data bytes of the slave node is less than the valid data length, the slave node fills the remaining part of the valid data with 0x77; when the master node receives and parses the data reported by the slave node and finds that it does not conform to the specification format, the master node fills the channel corresponding to the valid data of the slave node with 0xDD.

6. The universal M-LVDS bus protocol design method according to claim 4, characterized in that: According to the usage requirements, the data length field of the transmission frame is modified, that is, the data length field in the master node's data acquisition instruction is adaptively modified to enable the slave node to transmit data according to the new transmission frame length.

7. The universal M-LVDS bus protocol design method according to claim 1, wherein: The established link layer data protocol is: For a master node or a slave node, when acting as a transmitter, the signal is sent on the rising edge of the local clock, and the receiver latches the signal on the falling edge of the transmitter clock; When the slave node is powered on or not sending clock and data, the bus remains in a high-impedance state; After receiving the data acquisition instruction or the self-test parameter acquisition instruction, the slave node sends the clock and data within 1μs: the slave node sends n cycles of clock signal before sending data, and continues to send m cycles of clock signal after sending data. During the above-mentioned clock signal transmission process, the slave node data output is 0; The master clock output by the master node is a continuous clock, and the slave clock output by the slave node is an intermittent clock. The frequency difference between the slave clock and the master clock shall not exceed ±5%.

8. The universal M-LVDS bus protocol design method according to claim 1, wherein: The backplane high-speed bus is an M-LVDS bus, which has a master node and several slave nodes. The circuit and electrical interface settings are as follows: The master node and the slave node are respectively equipped with a control module, and each control module is equipped with two M-LVDS interface chips, which are connected to the M-LVDS bus together. The bus adopts serial differential signal transmission; The master node control module sends the master clock and command signals, which are converted into M-LVDS differential signals by an M-LVDS interface chip and sent to each slave node through the bus. Another M-LVDS interface chip connected to the master node control module receives the slave clock and data signals sent by the slave node control module on the bus, and sends them to the master node control module after signal conversion. An M-LVDS interface chip connected to the slave node control module receives the master clock and command signals sent by the master node control module on the bus, and sends them to the slave node control module after signal conversion; the slave node control module sends the slave clock and data signals, which are converted into M-LVDS differential signals by another M-LVDS interface chip and sent to the master node through the bus.

9. The universal M-LVDS bus protocol design method according to claim 1, wherein: The two master nodes are synchronized through the bus synchronization instructions. The specific implementation method is: when the master node of the first bus sends a synchronization instruction to each slave node in each communication cycle, it also sends a synchronization instruction to the master node of the second bus. The master node of the second bus responds to the received synchronization instruction and synchronizes with the master node of the first bus.

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