Nanosecond synchronous communication method and device, electronic equipment and storage medium

Abstract

The invention provides a nanosecond synchronous communication method and device, electronic equipment and a storage medium. A synchronous communication framework of an upper computer, a synchronous control module and a lower computer which are connected in sequence is provided; controlling the synchronous control module to communicate with the upper computer through a high-speed bus, and acquiring synchronous queue information corresponding to the upper computer; the synchronous control module generates a synchronous state code, converts the synchronous state code into high-speed serial data, and sends the high-speed serial data to the lower computer by adopting a high-speed bus; and after synchronization of the lower computer is completed, the synchronization control module generates a synchronization completion status code and returns the synchronization completion status code to the upper computer through the high-speed bus. According to the invention, the high-speed transceiving function of the synchronization state code can be realized, the synchronization delay and synchronization jitter of the synchronization signal can be effectively reduced, meanwhile, the interference signal from the outside can be effectively inhibited, and the stability and reliability of the signal can be maintained in the transmission process.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a nanosecond-level synchronous communication method, device, electronic device and storage medium. Background Art

[0002] At present, the hardware implementation of the synchronous bus uses the RS485 interface. The RS485 protocol is a half-duplex communication protocol. When the RS485 transceiver TX_EN is enabled, the RS485 interface acts as a transmitting device. When TX_EN is not enabled, the RS485 acts as a receiving device. After RX_EN is enabled, RX_DATA can receive data. The three-wire SPI method consists of three groups of RS485 transceivers. Three groups of differential RS485 signals are transmitted through a DB9 interface, which is used as a synchronous hardware interface to transmit synchronous signals through a serial cable.

[0003] The purpose of the hardware synchronization system is to serve as an important bridge for the coordinated work between the various subsystems of the whole machine. The two important indicators of synchronization jitter and synchronization delay determine the yield and accuracy of the equipment. High-efficiency, low-latency, and low-jitter hardware have become particularly important. However, the synchronization delay of the existing hardware solution ranges from 100ns to 5000ns. Since the transmission takes a lot of time, and the hardware transceiver also has a certain delay, in addition to the delay caused by the line length, the transceiver will also bring a certain delay. At the same time, because the transmission bandwidth of the physical line is relatively low, the transmission efficiency is slow. Due to the reasons of the transceiver and the hardware transmission cable, the transmission jitter is relatively large. The synchronization system has relatively high requirements for delay and jitter. The existing solution can only be compensated by software, resulting in the consumption of software resources. At the same time, since the transmission requires clock, receiving data, and sending data, three physical connection lines are required, which takes up a lot of space and consumes a lot of resources. Summary of the invention

[0004] The embodiments of the present disclosure at least provide a nanosecond-level synchronous communication method, device, electronic device and storage medium, which can realize the high-speed sending and receiving function of the synchronous status code, effectively reduce the synchronization delay and synchronization jitter of the synchronization signal, and at the same time, effectively suppress interference signals from the outside world to maintain the stability and reliability of the signal during the transmission process.

[0005] The present disclosure provides a nanosecond-level synchronous communication method, including:

[0006] Provide a synchronous communication architecture of a host computer, a synchronous control module and a slave computer connected in sequence;

[0007] Control the synchronization control module to communicate with the host computer through a high-speed bus to obtain synchronization queue information corresponding to the host computer;

[0008] The synchronization control module generates a synchronization status code, converts the synchronization status code into high-speed serial data, and sends the data to the lower computer via a high-speed bus;

[0009] After the synchronization of the lower computer is completed, the synchronization control module generates a synchronization completion status code and returns it to the upper computer through the high-speed bus.

[0010] In an optional implementation, the synchronization control module uses an FPGA chip.

[0011] In an optional implementation manner, a coaxial connector is used between the synchronization control module and the lower computer as an interface for synchronization signal transmission;

[0012] A coaxial cable is used between the synchronization control module and the lower computer as a bus for synchronization signal transmission.

[0013] In an optional implementation, the synchronization control module adopts a multi-core VPX architecture.

[0014] In an optional implementation, the lower computer includes multiple VPX chassis.

[0015] In an optional implementation manner, the synchronization status code is converted into high-speed serial data and sent to the lower computer using a high-speed bus, specifically including:

[0016] Controlling the serial-to-parallel converter in the FPGA chip to convert the parallel 8-bit wide synchronization state code into the high-speed serial data;

[0017] Control the GT interface resources in the FPGA chip to send the high-speed serial data.

[0018] In an optional implementation, the synchronization control module communicates with the host computer using a high-speed bus PCIEX4.

[0019] The present disclosure also provides a nanosecond-level synchronous communication device, including:

[0020] An architecture module, used to provide a synchronous communication architecture of a host computer, a synchronous control module and a slave computer connected in sequence;

[0021] A synchronization queue information acquisition module, used to control the synchronization control module to communicate with the host computer through a high-speed bus to obtain the synchronization queue information corresponding to the host computer;

[0022] A status code conversion module, used for generating a synchronization status code from the synchronization control module, converting the synchronization status code into high-speed serial data, and sending the data to the lower computer using a high-speed bus;

[0023] The status code returning module is used to generate a synchronization completion status code by the synchronization control module after the synchronization of the lower computer is completed, and return it to the upper computer through a high-speed bus.

[0024] An embodiment of the present disclosure also provides an electronic device, including: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the above-mentioned nanosecond-level synchronous communication method or steps in any possible implementation of the above-mentioned nanosecond-level synchronous communication method are performed.

[0025] The embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned nanosecond-level synchronous communication method or the steps in any possible implementation of the above-mentioned nanosecond-level synchronous communication method are executed.

[0026] The embodiments of the present disclosure also provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the above-mentioned nanosecond-level synchronous communication method, or the steps in any possible implementation of the above-mentioned nanosecond-level synchronous communication method.

[0027] A nanosecond-level synchronous communication method, device, electronic device and storage medium provided by the embodiment of the present disclosure provide a synchronous communication architecture of a host computer, a synchronous control module and a lower computer connected in sequence; the synchronous control module is controlled to communicate with the host computer through a high-speed bus to obtain the synchronous queue information corresponding to the host computer; the synchronous control module generates a synchronous status code, and converts the synchronous status code into high-speed serial data, and sends it to the lower computer using a high-speed bus; after the synchronization of the lower computer is completed, the synchronous control module generates a synchronous completion status code, and returns it to the host computer through a high-speed bus. The high-speed sending and receiving function of the synchronous status code can be realized, and the synchronization delay and synchronization jitter of the synchronization signal can be effectively reduced. At the same time, the interference signal from the outside can be effectively suppressed, and the stability and reliability of the signal can be maintained during the transmission process.

[0028] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0030] Figure 1 A flow chart of a nanosecond-level synchronous communication method provided by an embodiment of the present disclosure is shown;

[0031] Figure 2 A schematic diagram of the structure of a synchronous communication architecture provided by an embodiment of the present disclosure is shown;

[0032] Figure 3 A schematic diagram of a nanosecond-level synchronous communication device provided by an embodiment of the present disclosure is shown;

[0033] Figure 4 A schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0035] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0036] The term "and / or" herein only describes an association relationship, indicating that three relationships may exist. For example, A and / or B may represent the following three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set consisting of A, B, and C.

[0037] Research has found that the synchronization delay of existing hardware solutions ranges from 100ns to 5000ns. Since transmission takes a lot of time and the hardware transceiver also has a certain delay, in addition to the delay caused by the line length, the transceiver will also cause a certain delay. At the same time, the transmission bandwidth of the physical line is relatively low, resulting in slow transmission efficiency. Due to the reasons of the transceiver and the hardware transmission cable, the transmission jitter is relatively large. The synchronization system has relatively high requirements for delay and jitter. The existing solution can only be compensated by software, resulting in the consumption of software resources. At the same time, since the transmission requires clock, receiving data, and sending data, three physical connection lines are required, which takes up a lot of space and consumes a lot of resources.

[0038] Based on the above research, the present disclosure provides a nanosecond synchronous communication method, device, electronic device and storage medium, providing a synchronous communication architecture of a host computer, a synchronous control module and a lower computer connected in sequence; controlling the synchronous control module to communicate with the host computer through a high-speed bus to obtain the synchronous queue information corresponding to the host computer; the synchronous control module generates a synchronous status code, and converts the synchronous status code into high-speed serial data, and sends it to the lower computer using a high-speed bus; after the synchronization of the lower computer is completed, the synchronous control module generates a synchronous completion status code, and returns it to the host computer through a high-speed bus. The high-speed transceiver function of the synchronous status code can be realized, effectively reducing the synchronization delay and synchronization jitter of the synchronization signal, and at the same time, effectively suppressing interference signals from the outside world, and maintaining the stability and reliability of the signal during the transmission process.

[0039] To facilitate understanding of the present embodiment, a nanosecond-level synchronous communication method disclosed in the embodiment of the present disclosure is first introduced in detail. The execution subject of the nanosecond-level synchronous communication method provided in the embodiment of the present disclosure is generally a computer device with certain computing capabilities, and the computer device includes, for example: a terminal device or a server or other processing device, and the terminal device can be a user equipment (User Equipment, UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. In some possible implementations, the nanosecond-level synchronous communication method can be implemented by a processor calling a computer-readable instruction stored in a memory.

[0040] See also Figure 1 FIG. 1 is a flowchart of a nanosecond-level synchronous communication method provided by an embodiment of the present disclosure, wherein the method includes steps S101 to S104, wherein:

[0041] S101, providing a synchronous communication architecture of a host computer, a synchronous control module and a slave computer connected in sequence.

[0042] In a specific implementation, a host computer, a synchronization control module and a lower computer are provided which are hardware-connected in sequence. The synchronization control module adopts a multi-core VPX architecture, and the lower computer includes multiple VPX chassis. The number of cores of the synchronization control module is the same as the number of VPX chassis of the lower computer. The synchronization control module adopts an FPGA chip, and the synchronization control module and the host computer communicate using a high-speed bus PCIEX4.

[0043] Among them, the host computer can be a PC.

[0044] As a possible implementation method, the structure of the synchronous communication architecture of the host computer, the synchronous control module and the slave computer can be seen in Figure 2 As shown, Figure 2 A schematic diagram of the structure of a synchronous communication architecture provided in an embodiment of the present disclosure.

[0045] Specifically, the synchronization control module can adopt the hardware structure of the synchronization hardware main control card, which is located in the motion control chassis. The motion control chassis adopts a 6U VPX architecture and communicates with the single-board computing board through the high-speed bus PCIE X4 to obtain the synchronization queue information of the host computer.

[0046] S102, controlling the synchronization control module to communicate with the host computer via a high-speed bus to obtain synchronization queue information corresponding to the host computer.

[0047] In a specific implementation, the SQ in the host computer sends the synchronization queue to the SD in the synchronization control module, and the synchronization control module communicates with the host computer using the high-speed bus PCIE X4.

[0048] Here, PCIE X4 can reach a maximum bandwidth of 40Gbps, which can realize low-latency information transmission from the single-board computer to the synchronization control card, use interrupt mode for queue information feedback, and provide timely and effective feedback on queue operation results.

[0049] S103, the synchronization control module generates a synchronization status code, converts the synchronization status code into high-speed serial data, and sends it to the lower computer via a high-speed bus.

[0050] In a specific implementation, in the synchronization control module, after SD receives the synchronization queue sent by SQ in the host computer, PPC sends a synchronization status code to the corresponding queue.

[0051] As a possible implementation, the process of converting the synchronization status code into high-speed serial data can be implemented by the following steps 1-2:

[0052] Step 1: Control the serial-to-parallel converter in the FPGA chip to convert the parallel 8-bit wide synchronization state code into the high-speed serial data.

[0053] Step 2: Control the GT interface resources in the FPGA chip to send the high-speed serial data.

[0054] In the specific implementation, the synchronization control module adopts a highly integrated, high-performance FPGA chip with a maximum operating frequency of up to 500Mhz. It can perform high-speed queue caching and queue queuing, and has more hardware resources, such as DSP, BRAM, etc.

[0055] Furthermore, a coaxial connector is used as an interface for synchronization signal transmission between the synchronization control module and the lower computer; and a coaxial cable is used as a bus for synchronization signal transmission between the synchronization control module and the lower computer.

[0056] Here, the synchronization cable uses a high-speed coaxial cable, which can reach a transmission rate of up to 20Gbps and a maximum transmission distance of 185 meters. The use of coaxial cable can greatly reduce the delay caused by the cable, improve the synchronization control accuracy and speed synchronization error.

[0057] Among them, one of the main advantages of coaxial cable is its low loss characteristic. Due to its structure and material selection, low-loss coaxial cable can effectively reduce signal loss. In addition, the special shielding structure of coaxial cable can effectively suppress interference signals from the outside world. These characteristics of coaxial cable enable the stability and reliability of the signal to be maintained during transmission, which is very friendly to synchronization systems that require stable and reliable signals, low latency, and low jitter.

[0058] Here, the 8-bit synchronization state code is converted into high-speed serial data through a serial-to-parallel converter and then sent through a high-speed synchronization bus, which can effectively reduce the synchronization delay and synchronization jitter of the synchronization signal.

[0059] As a possible implementation, the synchronous bus interface is implemented using a BNC interface, which is a type of coaxial cable connector.

[0060] Here, since there is no unique coaxial cable connector standard in the industry, other coaxial cable connectors such as SMA, TNC, etc. can also replace the BNC interface as an alternative solution in the embodiments of the present application.

[0061] S104: After the synchronization of the lower computer is completed, the synchronization control module generates a synchronization completion status code and returns it to the upper computer through a high-speed bus.

[0062] A nanosecond-level synchronous communication method provided by the embodiment of the present disclosure provides a synchronous communication architecture of a host computer, a synchronous control module, and a lower computer connected in sequence; the synchronous control module is controlled to communicate with the host computer through a high-speed bus to obtain the synchronous queue information corresponding to the host computer; the synchronous control module generates a synchronous status code, and converts the synchronous status code into high-speed serial data, and sends it to the lower computer using a high-speed bus; after the synchronization of the lower computer is completed, the synchronous control module generates a synchronous completion status code, and returns it to the host computer through a high-speed bus. The high-speed sending and receiving function of the synchronous status code can be realized, and the synchronization delay and synchronization jitter of the synchronization signal can be effectively reduced. At the same time, the interference signal from the outside can be effectively suppressed, and the stability and reliability of the signal can be maintained during the transmission process.

[0063] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0064] Based on the same inventive concept, a nanosecond-level synchronous communication device corresponding to the nanosecond-level synchronous communication method is also provided in the embodiment of the present disclosure. Since the principle of solving the problem by the device in the embodiment of the present disclosure is similar to the above-mentioned nanosecond-level synchronous communication method in the embodiment of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0065] See also Figure 3 , Figure 3 Schematic diagram of a nanosecond-level synchronous communication device provided by an embodiment of the present disclosure. Figure 3 As shown in , the nanosecond synchronous communication device 300 provided by the embodiment of the present disclosure includes:

[0066] The architecture module 310 is used to provide a synchronous communication architecture for a host computer, a synchronous control module and a slave computer that are connected in sequence.

[0067] The synchronization queue information acquisition module 320 is used to control the synchronization control module to communicate with the host computer through a high-speed bus to obtain the synchronization queue information corresponding to the host computer.

[0068] The state code conversion module 330 is used to generate a synchronization state code from the synchronization control module, convert the synchronization state code into high-speed serial data, and send it to the lower computer using a high-speed bus.

[0069] The status code returning module 340 is used to generate a synchronization completion status code by the synchronization control module after the synchronization of the lower computer is completed, and return it to the upper computer through the high-speed bus.

[0070] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference may be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.

[0071] A nanosecond-level synchronous communication device provided by the embodiment of the present disclosure provides a synchronous communication architecture of a host computer, a synchronous control module and a lower computer connected in sequence; the synchronous control module is controlled to communicate with the host computer through a high-speed bus to obtain the synchronous queue information corresponding to the host computer; the synchronous control module generates a synchronous status code, and converts the synchronous status code into high-speed serial data, and sends it to the lower computer using a high-speed bus; after the synchronization of the lower computer is completed, the synchronous control module generates a synchronous completion status code, and returns it to the host computer through a high-speed bus. The high-speed sending and receiving function of the synchronous status code can be realized, and the synchronization delay and synchronization jitter of the synchronization signal can be effectively reduced. At the same time, the interference signal from the outside can be effectively suppressed, and the stability and reliability of the signal can be maintained during the transmission process.

[0072] Corresponds to Figure 1The nanosecond-level synchronous communication method in the present disclosure also provides an electronic device 400, such as Figure 4 FIG. 4 is a schematic diagram of the structure of an electronic device 400 provided in an embodiment of the present disclosure, including:

[0073] Processor 41, memory 42, and bus 43; memory 42 is used to store execution instructions, including memory 421 and external memory 422; memory 421 here is also called internal memory, which is used to temporarily store operation data in processor 41 and data exchanged with external memory 422 such as hard disk. Processor 41 exchanges data with external memory 422 through memory 421. When the electronic device 400 is running, the processor 41 communicates with the memory 42 through bus 43, so that the processor 41 executes Figure 1 The steps of the nanosecond-level synchronous communication method.

[0074] The embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the nanosecond-level synchronous communication method described in the above method embodiment are executed. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0075] The present disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, the steps of the nanosecond synchronous communication method described in the above method embodiment can be executed. For details, please refer to the above method embodiment, which will not be repeated here.

[0076] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0077] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0078] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0079] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0080] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0081] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A nanosecond level synchronous communication method, characterized in that: include: Provide a synchronous communication architecture of a host computer, a synchronous control module and a slave computer connected in sequence; Control the synchronization control module to communicate with the host computer through a high-speed bus to obtain synchronization queue information corresponding to the host computer; The synchronization control module generates a synchronization status code, converts the synchronization status code into high-speed serial data, and sends the data to the lower computer using a high-speed bus; After the synchronization of the lower computer is completed, the synchronization control module generates a synchronization completion status code and returns it to the upper computer through the high-speed bus.

2. The method according to claim 1, characterized in that: The synchronous control module adopts FPGA chip.

3. The method according to claim 1, characterized in that: A coaxial connector is used between the synchronization control module and the lower computer as an interface for synchronization signal transmission; A coaxial cable is used between the synchronization control module and the lower computer as a bus for synchronization signal transmission.

4. The method according to claim 1, characterized in that: The synchronization control module adopts a multi-core VPX architecture.

5. The method according to claim 1, characterized in that: The lower computer includes a plurality of VPX chassis.

6. The method according to claim 2, characterized in that The synchronous state code is converted into high-speed serial data, and sent to the lower computer using a high-speed bus, specifically including: Controlling the serial-to-parallel converter in the FPGA chip to convert the parallel 8-bit wide synchronization state code into the high-speed serial data; Control the GT interface resources in the FPGA chip to send the high-speed serial data.

7. The method according to claim 1, characterized in that: The synchronization control module communicates with the host computer using a high-speed bus PCIE X4.

8. A nanosecond synchronous communication device, characterized in that: include: An architecture module, used to provide a synchronous communication architecture of a host computer, a synchronous control module and a slave computer connected in sequence; A synchronization queue information acquisition module, used to control the synchronization control module to communicate with the host computer through a high-speed bus to obtain the synchronization queue information corresponding to the host computer; A status code conversion module, used for generating a synchronization status code from the synchronization control module, converting the synchronization status code into high-speed serial data, and sending the data to the lower computer using a high-speed bus; The status code returning module is used to generate a synchronization completion status code by the synchronization control module after the synchronization of the lower computer is completed, and return it to the upper computer through a high-speed bus.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the nanosecond synchronous communication method as described in any one of claims 1 to 7 are performed.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the nanosecond synchronous communication method according to any one of claims 1 to 7 are executed.

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