Trimming method and device for establishing time margin, electronic equipment and storage medium

Abstract

The invention provides a trimming method and device for an establishment time margin, electronic equipment and a storage medium, and the method comprises the steps: carrying out the one-step repair and one-step adjustment of the establishment time margin, each step is based on different types of time sequence paths, firstly collecting all time sequence paths of establishment time violations, repairing the establishment time violations, and carrying out the one-step repair and one-step adjustment of the establishment time margin; according to the method, the function correctness of the digital circuit is ensured, then a time sequence path with overlarge setting time margin is collected, the setting time margin is adjusted, the setting time is prevented from being repaired excessively, and meanwhile the power consumption and the area of the digital circuit are reduced. According to the method, each step of trimming of each category is specifically and detailedly stipulated, a code trimming process is formed, automatic trimming can be conveniently achieved through the storage device and the processor, and the repairing efficiency is effectively improved. In the trimming method, the trimming degree of each step of scheme is small, the possibility of repeated trimming can be reduced, and the trimming accuracy and stability are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a method and device for establishing a time margin, an electronic device, and a storage medium. Background Art

[0002] When designing integrated circuits, the chip is required to have good timing closure. The timing closure of the chip includes two parts: setup time convergence and hold time convergence. If the setup time does not meet the requirements, it will affect the function of the circuit or cause the circuit's operating frequency to fail to meet the design requirements. Therefore, repairing setup time violations is crucial for digital chip design. In addition, the power consumption and area of ​​the integrated circuit are key indicators in circuit design. Therefore, when repairing setup time violations, the power consumption and area of ​​the integrated circuit need to be considered.

[0003] As the scale of integrated circuit design increases, chip timing convergence becomes increasingly difficult. Current setup time violation repair solutions include: inserting buffers on the clock path using useful deviations, or replacing the logic cell size on the data path with a larger size, or replacing the logic cell threshold voltage on the data path with a lower threshold voltage. The timing repair effects of the three repair solutions are limited, and they will increase the power consumption or area of ​​the chip. In a more optimized solution, two or three of the three repair solutions are combined, which improves the repair effect to a certain extent, but still cannot solve the drawbacks of increased power consumption and area. And when to use which repair solution requires the designer to judge by himself. Usually, there are repeated attempts and continuous re-acquisition of simulation results through simulation software to verify whether the repair is successful, and the repair efficiency is low.

[0004] In addition, existing repair schemes may introduce the problem of excessive repair of setup time violations after repairing the setup time violations, making the setup time margin too large. Although the functional correctness of the circuit is guaranteed, it brings waste of power consumption and area. Summary of the invention

[0005] In order to overcome the above shortcomings, embodiments of the present invention provide a method and device for establishing a time margin, an electronic device, and a storage medium.

[0006] The technical solution adopted in the embodiment of the present invention is as follows:

[0007] According to a first aspect of an embodiment of the present invention, a method for adjusting a setup time margin is provided, comprising:

[0008] S1: Extract the time margin S of all timing paths in the digital circuit, S = T + Δ - (T co +T data )-T su, where T is the clock period of the digital circuit, and Δ is the deviation between the clock source reaching the clock input terminals of the two registers, that is, the time T for the clock source to reach the clock terminal of the second register. clk2 minus the time T to reach the first register clock terminal clk1 , T co 、T data are the maximum propagation delay and maximum logic delay of the timing path, T su is the setup time of the timing path;

[0009] S2: The time margin S is less than the qualified threshold S min The timing path is repaired to increase its timing margin to the qualified threshold S min In the above, the time margin S0 before repair and the time repair degree ΔS are used to determine whether the time margin of the timing path after repair reaches S min above;

[0010] S3: After repair, calculate the power consumption and area of ​​the digital circuit. If the power consumption is greater than the required power consumption value P of the digital circuit, max Or the area is greater than the required area value A max , then for the time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin to reduce the power consumption of the digital circuit to P max Below, reduce the area of ​​digital circuit to A max In the following, the power consumption of the digital circuit after adjustment is determined to be reduced to P by using the time margin S0', power consumption P0', area A0' and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA' before adjustment. max Below, whether the area is reduced to A max Below, does the timing path's time margin drop to S max The following and in S min above;

[0011] Among them, for the time margin S is less than the qualified threshold S min The timing paths are repaired, including:

[0012] Repair solution a is: add a buffer between the clock source and the second register clock end in the clock path of the digital circuit timing path, increase T clk2 , thereby increasing the deviation Δ between the clock source reaching the clock input terminals of the two registers and increasing the setup time margin S;

[0013] Repair solution b is: In the data path of the digital circuit timing path, increasing the size of the logic element by one level can make the element's driving ability stronger and the element delay smaller, thereby reducing T data, increase the setup time margin S;

[0014] Repair solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T data , increase the setup time margin S;

[0015] Among them, for the time margin S greater than the surplus threshold S max The timing path is adjusted, including:

[0016] Adjustment scheme a' is: in the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock end to reduce T clk2 , thereby reducing Δ, reducing the setup time margin S, and improving power consumption and area;

[0017] Adjustment scheme b' is: in the data path of the digital circuit timing path, the size of the logic element is reduced by one level, thereby increasing T data , reduce the setup time margin S, improve power consumption and area;

[0018] Adjustment scheme c' is: in the data path of the digital circuit timing path, the threshold voltage of the logic element is increased by one level, thereby increasing T data , reduce the setup time margin S, and improve power consumption and area.

[0019] According to a second aspect of an embodiment of the present invention, there is provided a device for adjusting a time margin, comprising:

[0020] Extraction module, used to extract the time margin S of all timing paths in the digital circuit, S = T + Δ - (T co +T data )-T su , where T is the clock period of the digital circuit, and Δ is the deviation between the clock source reaching the clock input terminals of the two registers, that is, the time T for the clock source to reach the clock terminal of the second register. clk2 minus the time T to reach the first register clock terminal clk1 , T co 、T data are the maximum propagation delay and maximum logic delay of the timing path, T su is the setup time of the timing path;

[0021] The repair module is used to repair the time margin S less than the qualified threshold S min The timing path is repaired to increase its timing margin to the qualified threshold S min In the above, the time margin S0 before repair and the time repair degree ΔS are used to determine whether the time margin of the timing path after repair reaches S minabove;

[0022] The adjustment module is used to calculate the power consumption and area of ​​the digital circuit after repair. If the power consumption is greater than the power consumption requirement value P of the digital circuit, max Or the area is greater than the required area value A max , then for the time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin to reduce the power consumption of the digital circuit to P max Below, reduce the area of ​​digital circuit to A max In the following, the power consumption of the digital circuit after adjustment is determined to be reduced to P by using the time margin S0', power consumption P0', area A0' and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA' before adjustment. max Below, whether the area is reduced to A max Below, does the timing path's time margin drop to S max The following and in S min above;

[0023] Among them, for the time margin S is less than the qualified threshold S min The timing paths are repaired, including:

[0024] Repair solution a is: add a buffer between the clock source and the second register clock end in the clock path of the digital circuit timing path, increase T clk2 , thereby increasing the deviation Δ between the clock source reaching the clock input terminals of the two registers and increasing the setup time margin S;

[0025] Repair solution b is: In the data path of the digital circuit timing path, increasing the size of the logic element by one level can make the element's driving ability stronger and the element delay smaller, thereby reducing T data , increase the setup time margin S;

[0026] Repair solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T data , increase the setup time margin S;

[0027] Among them, for the time margin S greater than the surplus threshold S max The timing path is adjusted, including:

[0028] Adjustment scheme a' is: in the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock end to reduce T clk2 , thereby reducing Δ, reducing the setup time margin S, and improving power consumption and area;

[0029] Adjustment scheme b' is: in the data path of the digital circuit timing path, the size of the logic element is reduced by one level, thereby increasing T data , reduce the setup time margin S, improve power consumption and area;

[0030] Adjustment scheme c' is: in the data path of the digital circuit timing path, the threshold voltage of the logic element is increased by one level, thereby increasing T data , reduce the setup time margin S, and improve power consumption and area.

[0031] According to a third aspect of an embodiment of the present invention, there is provided an electronic device, including:

[0032] one or more processors;

[0033] A memory for storing one or more programs;

[0034] When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in the first aspect.

[0035] According to a fourth aspect of an embodiment of the present invention, there is provided a computer-readable storage medium on which computer instructions are stored. When the instructions are executed by a processor, the steps of the method described in the first aspect are implemented.

[0036] The beneficial effects of the embodiments of the present invention are as follows:

[0037] 1. The timing paths are divided into two categories according to the setup time margin for repair and adjustment. First, the illegal timing paths whose setup time margin is less than the qualified threshold are repaired. After the repair is completed, the timing paths with excessive setup time margin are adjusted. On the basis of ensuring the correctness of the digital circuit function, excessive setup time margin repair is prevented, and power consumption and area optimization are achieved.

[0038] 2. Before the adjustment begins, the adjustment degree of each adjustment plan is digitized by querying the process library or routine testing. During the adjustment process, it is possible to quickly determine whether the time margin, power consumption and area meet the requirements through addition and subtraction operations, and stop the adjustment at any time based on the judgment results, avoiding the need to use simulation software to re-simulate the time margin, power consumption or area of ​​the digital circuit for each adjustment step, which greatly saves the adjustment time, improves the adjustment efficiency, and enhances the predictability and controllability of the adjustment process.

[0039] 3. Specific and detailed regulations are made for each step of the repair and adjustment plan to form a codable adjustment process, which facilitates automated adjustment through storage devices and processors, saving time and labor costs.

[0040] 4. The degree of adjustment for each step of the adjustment method is set to be small and easy to implement, which can effectively avoid excessive adjustment of the settling time, reduce the possibility of repeated adjustment, and improve the accuracy and stability of the adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a flow chart of a setup time margin adjustment method provided by an embodiment of the present invention.

[0042] Figure 2 A schematic diagram of the relationship between the timing path topology structure and various signals provided by an embodiment of the present invention.

[0043] Figure 3 A schematic diagram of a flow chart of repairing a setup time violation path provided by an embodiment of the present invention.

[0044] Figure 4 A schematic diagram of a specific repair solution for establishing a time violation path provided by an embodiment of the present invention.

[0045] Figure 5 A schematic diagram of a flow chart of adjusting a path with excessive setup time margin provided by an embodiment of the present invention.

[0046] Figure 6 A schematic diagram of a specific adjustment solution for a path with excessive setup time margin provided by an embodiment of the present invention.

[0047] Figure 7 A block diagram of a setup time margin adjustment device provided by an embodiment of the present invention.

[0048] Figure 8 A schematic diagram of an electronic device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] In the present invention, before adjustment, it is necessary to obtain the time repair degree of the three repair schemes, as well as the time adjustment degree, power consumption adjustment degree and area adjustment degree of the three adjustment schemes. Among them, the power consumption and area of ​​the buffer on the clock path, logic elements of different sizes and logic elements of different threshold voltages can be obtained by querying the process library parameters, thereby obtaining the power consumption adjustment degree and area adjustment degree of the three adjustment schemes.

[0051] As for the degree of time adjustment, a test is required to obtain the delay of the buffer, logic elements of different sizes and logic elements of different threshold voltages under the working clock of the digital circuit, so as to obtain the establishment time adjustment degree of the three adjustment schemes. This test can be easily implemented through conventional technical means.

[0052] The following is a detailed description of a method for adjusting the time margin provided by an embodiment of the present invention, referring to Figure 1 , the method comprises the following steps:

[0053] S1: Extract the time margin S of all timing paths in the digital circuit;

[0054] Specifically, the tool for extracting the time margin of all timing paths in the digital circuit includes but is not limited to: PrimeTime, Design Compiler, etc.

[0055] like Figure 2 The calculation formula for the setup time margin is S = T + Δ - (T co +T data )-T su , where T is the clock period of the digital circuit, and Δ is the deviation between the clock source reaching the clock input terminals of the two registers, that is, the time T for the clock source to reach the clock terminal of the second register. clk2 minus the time T to reach the first register clock terminal clk1 , T co 、T data are the maximum propagation delay and maximum logic delay of the timing path, T su is the setup time of the timing path. To ensure the correct function of the digital circuit, the setup time margin S needs to be greater than the qualified threshold S min .

[0056] S2: The time margin S is less than the qualified threshold S min The timing path is repaired to increase its timing margin to the qualified threshold S min In the above, the time margin S0 before repair and the time repair degree ΔS are used to determine whether the time margin of the timing path after repair reaches S min above;

[0057] Specifically, when the time margin S is less than the qualified threshold S min There are three repair solutions for repairing the timing path, as follows:

[0058] Repair solution a is: add a buffer between the clock source and the second register clock end in the clock path of the digital circuit timing path, increase T clk2, thereby increasing the deviation Δ between the clock source reaching the clock input terminals of the two registers and increasing the setup time margin S; the time repair degree ΔS of this repair scheme is ΔS a , but adding buffers will increase the power consumption and area of ​​the chip.

[0059] Repair solution b is: In the data path of the digital circuit timing path, increasing the size of the logic element by one level can make the element's driving ability stronger and the element delay smaller, thereby reducing T data , increase the setup time margin S; the time repair degree ΔS of this repair scheme is ΔS b , but increasing the size of logic elements will increase the power consumption and area of ​​the chip.

[0060] Repair solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T data , increase the setup time margin S; the time repair degree ΔS of this repair scheme is ΔS c , but reducing the threshold voltage of logic elements will increase the power consumption and area of ​​the chip.

[0061] S3: After repair, calculate the power consumption and area of ​​the digital circuit. If the power consumption is greater than the required power consumption value P of the digital circuit, max Or the area is greater than the required area value A max , then for the time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin to reduce the power consumption of the digital circuit to P max Below, reduce the area of ​​digital circuit to A max In the following, the power consumption of the digital circuit after adjustment is determined to be reduced to P by using the time margin S0', power consumption P0', area A0' and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA' before adjustment. max Below, whether the area is reduced to A max Below, does the timing path's time margin drop to S max The following and in S min above;

[0062] Specifically, all three repair schemes have disadvantages that are unfavorable to chip power consumption and area. Therefore, after completing the repair of the setup time violation, it is necessary to use power analysis tools and area analysis tools to calculate the power consumption and area of ​​the digital circuit. Then, on the basis of ensuring the correct function of the digital circuit, adjust the setup time margin S to make it less than the surplus margin S. max , preventing excessive setup time repair and reducing the power consumption and area of ​​the digital circuit to meet the required requirements.

[0063] The analysis tools for calculating the power consumption and area of ​​digital circuits include but are not limited to: Innovus, ICCompiler, PowerArtist, etc.

[0064] For the time margin S greater than the surplus threshold S max The timing path adjustment includes the following three adjustment schemes, as follows:

[0065] Adjustment scheme a' is: in the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock end to reduce T clk2 , thereby reducing Δ, reducing the setup time margin S, and improving power consumption and area; the time adjustment degree ΔS' of this adjustment scheme is -ΔS' a , the power consumption adjustment degree ΔP' is -ΔP' a , the area adjustment degree ΔA' is -ΔA' a .

[0066] Adjustment scheme b' is: in the data path of the digital circuit timing path, the size of the logic element is reduced by one level, thereby increasing T data , reduce the setup time margin S, improve power consumption and area; the time adjustment degree ΔS' of this adjustment scheme is -ΔS' b , the power consumption adjustment degree ΔP' is -ΔP' b , the area adjustment degree ΔA' is -ΔA' b .

[0067] The size levels of the logic elements are divided into small size, standard size, large size and maximum size; the area of ​​the small size is 0.5 to 0.8 times the area of ​​the standard size, the area of ​​the large size is 2 to 3 times the area of ​​the standard size, and the area of ​​the maximum size is 3 to 5 times the area of ​​the standard size.

[0068] Adjustment scheme c' is: in the data path of the digital circuit timing path, the threshold voltage of the logic element is increased by one level, thereby increasing T data , reduce the setup time margin S, improve power consumption and area; the time adjustment degree ΔS' of this adjustment scheme is -ΔS' c , the power consumption adjustment degree ΔP' is -ΔP' c , the area adjustment degree ΔA' is -ΔA' c .

[0069] The threshold voltage levels of the logic element are divided into ultra-low threshold voltage, low threshold voltage, standard threshold voltage, and high threshold voltage. The ultra-low threshold voltage is 0.5 to 0.7 times the standard voltage, the low threshold voltage is 0.7 to 0.9 times the standard voltage, and the high threshold voltage is 1.1 to 1.5 times the standard voltage.

[0070] In S3, if the time margin S of all timing paths is less than the surplus threshold S max , and the power consumption or area still cannot meet the requirements, then reduce the surplus threshold S max , and then continue the adjustment steps to make the power consumption and area meet the requirements.

[0071] In one embodiment, the surplus threshold S max Reduce one clock cycle to form a new surplus threshold S max , and then continue the adjustment steps to make the power consumption and area meet the requirements.

[0072] It is worth noting that in the adjustment of the setup time margin, each path that needs to be adjusted is cycled in the order of scheme a, b, c or a', b', c' until the time margin S or power consumption and area meet the required requirements. When adjusting the path with excessive setup time margin, if the time margin S of all timing paths is less than the surplus threshold S max , and the power consumption or area still cannot meet the requirements, then reduce the surplus threshold S max , reducing one clock cycle T, forming a new surplus threshold S max , and then continue to cycle according to the scheme a', b', c' in order to make the power consumption and area meet the requirements.

[0073] It can be seen from the above embodiments that before the adjustment begins, the present application digitally processes the adjustment degree of each step of the adjustment scheme by querying the process library or conventional testing, so that during the adjustment process, it is possible to quickly judge whether the time margin, power consumption and area meet the requirements directly through addition and subtraction operations, and stop the adjustment at any time according to the judgment result, avoiding the need to re-simulate the time margin, power consumption or area of ​​the digital circuit through simulation software for each adjustment step, which greatly saves the adjustment time, improves the adjustment efficiency, and enhances the predictability and controllability of the adjustment process.

[0074] By configuring the qualified threshold S min and the surplus threshold S max In this application, the timing paths are divided into two categories according to the size of the time margin for repair and adjustment. First, the time margin S is less than the qualified threshold S min The violation path is repaired to ensure the functional correctness of the digital circuit, and then the time margin S is greater than the surplus threshold S max The path is adjusted to avoid power consumption and area waste caused by excessive repair, thereby optimizing power consumption and area.

[0075] In addition, the present application provides detailed provisions for each step of the adjustment scheme, forming a coded adjustment process, which is convenient for realizing automatic adjustment through storage devices and processors, saving time and labor costs. Moreover, the adjustment degree of each step of the scheme in the adjustment method is small, which can effectively avoid excessive adjustment of the establishment time, reduce the possibility of repeated adjustment, and improve the accuracy and stability of the adjustment.

[0076] Embodiment 1:

[0077] See also Figure 3 , Figure 3 FIG. 1 is a flow chart of repairing a time violation path according to an embodiment of the present application, wherein firstly, a qualified threshold S of the time margin is configured. min , determine the time repair degree ΔS of each repair scheme, and then extract the setup time margin S of all timing paths in the digital circuit.

[0078] Collection time margin S<S min The setup time violation path S1~S n , and then S1~S n Repair, the specific repair plan is as follows Figure 4 Taking the S1 path as an example, the initial time margin S of the S1 path is 01 <S min , repair schemes a, b, and c are performed on the S1 path loop. First, a buffer is added between the clock source and the second register clock end in the clock path of the S1 path to establish a time margin repair of S 01 +ΔS a <S min Then, in the data path of path S1, the size of logic element U1 is increased by one level, and the setup time margin is fixed to S 01 +ΔS a +ΔS b <S min Then, in the data path of path S1, the threshold voltage of logic element U1 is reduced by one level, and the setup time margin is restored to S 01 +ΔS a +ΔS b +ΔS c <S min .

[0079] At this time, the first round of repair of S1 path has been completed, but the setup time of S1 is still in violation, so the next round of repair begins. A buffer is added between the clock source and the second register clock end, the size of the logic element U2 is increased by one level, and the threshold voltage of the logic element U2 is reduced by one level. The second round of repair of S1 is completed. If the setup time margin S of S1 is 01 +2ΔS a +2ΔSb +2ΔS c >S min , then the setup time violation repair of path S1 is completed, and the next violation path S2 is repaired to make its setup time margin>S min , and so on to repair all the setup time violation paths S1 to S n .

[0080] All illegal paths S1~S n After the repair is completed, use the digital circuit power consumption and area analysis tool to calculate the power consumption and area of ​​the digital circuit. If the power consumption and area meet the required requirements, the timing repair is completed.

[0081] Embodiment 2:

[0082] See also Figure 5 , Figure 5 FIG. 1 is a flow chart of adjusting and establishing a time margin excessive path according to an embodiment of the present application, wherein firstly, a qualified threshold value S of the time margin is configured. min and the surplus threshold S max , determine the time adjustment degree ΔS', power adjustment degree ΔP' and area adjustment degree ΔA' of each adjustment scheme, and determine the power consumption requirement value P of the digital circuit max and area requirement A max , and then extract the setup time margin S of all timing paths in the digital circuit.

[0083] After repairing the setup time violation path according to the setup time violation repair solution in Example 1 of the present application, use the digital circuit power consumption and area analysis tool to calculate the power consumption and area of ​​the digital circuit. If the power consumption is greater than P max or area greater than A max , then the collection setup time margin S>S max The setup time margin of path S1'~S is too large n ', and then S1'~S n 'Make adjustments, the specific adjustment plan is as follows Figure 6 As shown. Taking the S1' path as an example, the initial time margin S of the S1' path 01 '>S max , adjust the S1' path loop by schemes a', b', and c'. First, in the clock path of the S1' path, remove a buffer between the clock source and the second register clock end, and adjust the setup time margin to S 01 '-ΔS' a >S max , the power consumption of the digital circuit is adjusted to P0'-ΔP' a >P max , the digital circuit area is adjusted to A0'-ΔA' a >Amax Then, in the data path of the S1' path, the size of the logic element U1 is reduced by one level, and the setup time margin is adjusted to S 01 '-ΔS' a -ΔS' b >S max , the power consumption of the digital circuit is adjusted to P0'-ΔP' a -ΔP' b >P max , the digital circuit area is A0'-ΔA' a -ΔA' b >A max Then, in the data path of the S1' path, the threshold voltage of the logic element U1 is increased by one level, and the setup time margin is adjusted to S 01 '-ΔS' a -ΔS' b -ΔS' c >S max , the power consumption of the digital circuit is adjusted to P0'-ΔP' a -ΔP' b -ΔP' c >P max , the digital circuit area is A0'-ΔA' a -ΔA' b -ΔA' c >A max .

[0084] At this point, the first round of adjustments to the S1' path has been completed, but the power consumption and area of ​​the digital circuit still do not meet the requirements, so the next round of adjustments to the S1' path begins until the setup time margin of the S1' path is less than S max And > S min , complete the setup time margin adjustment of the S1' path, and start adjusting the S2' path to make its setup time margin < S max And > S min , and so on, adjust all the paths S1' to S1' with excessive setup time margins. n '.

[0085] In the above process, when the power consumption of the digital circuit is less than P max And the area is smaller than A max When the adjustment process ends immediately, if all the setup time margins are too large, the paths S1' to S n 'The adjusted setup time margin is <S max And > S min , but the power consumption and area of ​​the digital circuit still do not meet the required requirements, then the surplus threshold S max Reduce one clock cycle to form a new surplus threshold, and repeat the above process until the power consumption and area of ​​the digital circuit meet the required requirements.

[0086] Corresponding to the above-mentioned embodiment of the method for adjusting the setup time margin, the present application also provides an embodiment of the device for adjusting the setup time margin.

[0087] Figure 7 FIG. 1 is a block diagram of a device for adjusting a setup time margin according to an exemplary embodiment. Figure 7 , the device comprises:

[0088] Extraction module 1, used to extract the time margin S of all timing paths in the digital circuit, S = T + Δ - (T co +T data )-T su , where T is the clock period of the digital circuit, and Δ is the deviation between the clock source reaching the clock input terminals of the two registers, that is, the time T for the clock source to reach the clock terminal of the second register. clk2 minus the time T to reach the first register clock terminal clk1 , T co 、T data are the maximum propagation delay and maximum logic delay of the timing path, T su is the setup time of the timing path;

[0089] Repair module 2, for the time margin S is less than the qualified threshold S min The timing path is repaired to increase its timing margin to the qualified threshold S min In the above, the time margin S0 before repair and the time repair degree ΔS are used to determine whether the time margin of the timing path after repair reaches S min above;

[0090] Adjustment module 3 is used to calculate the power consumption and area of ​​the digital circuit after repair. If the power consumption is greater than the power consumption requirement value P of the digital circuit, max Or the area is greater than the required area value A max , then for the time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin to reduce the power consumption of the digital circuit to P max Below, reduce the area of ​​digital circuit to A max In the following, the power consumption of the digital circuit after adjustment is determined to be reduced to P by using the time margin S0', power consumption P0', area A0' and the time adjustment degree ΔS', power consumption adjustment degree ΔP', and area adjustment degree ΔA' before adjustment. max Below, whether the area is reduced to A max Below, does the timing path's time margin drop to S max The following and in S min above;

[0091] Among them, for the time margin S is less than the qualified threshold S min The timing paths are repaired, including:

[0092] Repair solution a is: add a buffer between the clock source and the second register clock end in the clock path of the digital circuit timing path, increase T clk2 , thereby increasing the deviation Δ between the clock source reaching the clock input terminals of the two registers and increasing the setup time margin S;

[0093] Repair solution b is: In the data path of the digital circuit timing path, increasing the size of the logic element by one level can make the element's driving ability stronger and the element delay smaller, thereby reducing T data , increase the setup time margin S;

[0094] Repair solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T data , increase the setup time margin S;

[0095] Among them, for the time margin S greater than the surplus threshold S max The timing path is adjusted, including:

[0096] Adjustment scheme a' is: in the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock end to reduce T clk2 , thereby reducing Δ, reducing the setup time margin S, and improving power consumption and area;

[0097] Adjustment scheme b' is: in the data path of the digital circuit timing path, the size of the logic element is reduced by one level, thereby increasing T data , reduce the setup time margin S, improve power consumption and area;

[0098] Adjustment scheme c' is: in the data path of the digital circuit timing path, the threshold voltage of the logic element is increased by one level, thereby increasing T data , reduce the setup time margin S, and improve power consumption and area.

[0099] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0100] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present application scheme. A person of ordinary skill in the art can understand and implement it without paying any creative work.

[0101] Accordingly, the present application also provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the above-mentioned method for adjusting the establishment time margin. Figure 8 As shown, a hardware structure diagram of a device having data processing capability in which a time margin adjustment device provided by an embodiment of the present invention is located, except Figure 8 In addition to the processor, memory, DMA controller, disk, and non-volatile memory shown, any device with data processing capabilities in which the apparatus in the embodiment is located may also include other hardware, which will not be described in detail, generally based on the actual functions of the device with data processing capabilities.

[0102] Accordingly, the present application also provides a computer-readable storage medium on which computer instructions are stored, and when the instructions are executed by a processor, the method for adjusting the setup time margin as described above is implemented. The computer-readable storage medium can be an internal storage unit of any device with data processing capabilities described in any of the aforementioned embodiments, such as a hard disk or a memory. The computer-readable storage medium can also be an external storage device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), an SD card, a flash card (Flash Card), etc. equipped on the device. Furthermore, the computer-readable storage medium can also include both an internal storage unit and an external storage device of any device with data processing capabilities. The computer-readable storage medium is used to store the computer program and other programs and data required by any device with data processing capabilities, and can also be used to temporarily store data that has been output or is to be output.

[0103] Those skilled in the art will readily appreciate other embodiments of the present application after considering the description and practicing the contents disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The description and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims.

[0104] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for establishing a time margin adjustment, It is characterized in that include: S1: Extract the time margin S of all timing paths in the digital circuit, S = T + Δ - (T co +T data )-T su , where T is the clock period of the digital circuit, and Δ is the deviation between the clock source reaching the clock input terminals of the two registers, that is, the time T for the clock source to reach the clock terminal of the second register. clk2 minus the time T to reach the first register clock terminal clk1 , T co 、T data are the maximum propagation delay and maximum logic delay of the timing path, T su is the setup time of the timing path; S2: The time margin S is less than the qualified threshold S min The timing path is repaired to increase its timing margin to the qualified threshold S min Above, where the time margin S before repair is 0 and the time repair degree ΔS, to determine whether the time margin of the timing path after repair reaches S min above; S3: After repair, calculate the power consumption and area of ​​the digital circuit. If the power consumption is greater than the required power consumption value P of the digital circuit, max Or the area is greater than the required area value A max , then for the time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin to reduce the power consumption of the digital circuit to P max Below, reduce the area of ​​digital circuit to A max The following is the time margin S before adjustment. 0 ', power consumption P 0 ', Area A 0 ' and time adjustment degree ΔS', power adjustment degree ΔP', area adjustment degree ΔA', to determine whether the power consumption of the digital circuit after adjustment is reduced to P max Below, whether the area is reduced to A max Below, does the timing path's time margin drop to S max The following and in S min above; Among them, for the time margin S is less than the qualified threshold S min The timing path is repaired, including: Repair solution a is: add a buffer between the clock source and the second register clock end in the clock path of the digital circuit timing path, increase T clk2 , thereby increasing the deviation Δ between the clock source reaching the clock input terminals of the two registers and increasing the setup time margin S; Repair solution b is: In the data path of the digital circuit timing path, increasing the size of the logic element by one level can make the element's driving ability stronger and the element delay smaller, thereby reducing T data , increase the setup time margin S; Repair solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T data , increase the setup time margin S; Among them, for the time margin S greater than the surplus threshold S max The timing path is adjusted, including: Adjustment scheme a' is: in the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock end to reduce T clk2 , thereby reducing Δ, reducing the setup time margin S, and improving power consumption and area; Adjustment scheme b' is: in the data path of the digital circuit timing path, the size of the logic element is reduced by one level, thereby increasing T data , reduce the setup time margin S, improve power consumption and area; Adjustment scheme c' is: in the data path of the digital circuit timing path, the threshold voltage of the logic element is increased by one level, thereby increasing T data , reduce the setup time margin S, and improve power consumption and area.

2. The adjustment method according to claim 1, It is characterized in that The tool for extracting the time margin of all timing paths in the digital circuit is selected from PrimeTime and Design Compiler.

3. The adjustment method according to claim 1, It is characterized in that The size levels of the logic elements are divided into small size, standard size, large size and maximum size; the area of ​​the small size is 0.5 to 0.8 times the area of ​​the standard size, the area of ​​the large size is 2 to 3 times the area of ​​the standard size, and the area of ​​the maximum size is 3 to 5 times the area of ​​the standard size.

4. The adjustment method according to claim 1, It is characterized in that The threshold voltage levels of the logic element are divided into ultra-low threshold voltage, low threshold voltage, standard threshold voltage, and high threshold voltage. The ultra-low threshold voltage is 0.5 to 0.7 times the standard voltage, the low threshold voltage is 0.7 to 0.9 times the standard voltage, and the high threshold voltage is 1.1 to 1.5 times the standard voltage.

5. The adjustment method according to claim 1, It is characterized in that In S3, if the time margin S of all timing paths is less than the surplus threshold S max , and the power consumption or area still cannot meet the requirements, then reduce the surplus threshold S max , and then continue the adjustment steps to make the power consumption and area meet the requirements.

6. The adjustment method according to claim 5, It is characterized in that For the surplus threshold S max Reduce one clock cycle to form a new surplus threshold S max , and then continue the adjustment steps to make the power consumption and area meet the requirements.

7. The adjustment method according to claim 1, It is characterized in that The analysis tool for calculating the power consumption and area of ​​the digital circuit is selected from Innovus, IC Compiler, and PowerArtist.

8. A time margin adjustment device, It is characterized in that include: Extraction module, used to extract the time margin S of all timing paths in the digital circuit, S = T + Δ - (T co +T data )-T su , where T is the clock period of the digital circuit, and Δ is the deviation between the clock source reaching the clock input terminals of the two registers, that is, the time T for the clock source to reach the clock terminal of the second register. clk2 minus the time T to reach the first register clock terminal clk1 , T co 、T data are the maximum propagation delay and maximum logic delay of the timing path, T su is the setup time of the timing path; The repair module is used to repair the time margin S less than the qualified threshold S min The timing path is repaired to increase its timing margin to the qualified threshold S min Above, where the time margin S before repair is 0 and the time repair degree ΔS, to determine whether the time margin of the timing path after repair reaches S min above; The adjustment module is used to calculate the power consumption and area of ​​the digital circuit after repair. If the power consumption is greater than the power consumption requirement value P of the digital circuit, max Or the area is greater than the required area value A max , then for the time margin S greater than the surplus threshold S max The timing path is adjusted to reduce its time margin to reduce the power consumption of the digital circuit to P max Below, reduce the area of ​​digital circuit to A max The following is the time margin S before adjustment. 0 ', power consumption P 0 ', Area A 0 ' and time adjustment degree ΔS', power adjustment degree ΔP', area adjustment degree ΔA', to determine whether the power consumption of the digital circuit after adjustment is reduced to P max Below, whether the area is reduced to A max Below, does the timing path's time margin drop to S max The following and in S min above; Among them, for the time margin S is less than the qualified threshold S min The timing path is repaired, including: Repair solution a is: add a buffer between the clock source and the second register clock end in the clock path of the digital circuit timing path, increase T clk2 , thereby increasing the deviation Δ between the clock source reaching the clock input terminals of the two registers and increasing the setup time margin S; Repair solution b is: In the data path of the digital circuit timing path, increasing the size of the logic element by one level can make the element's driving ability stronger and the element delay smaller, thereby reducing T data , increase the setup time margin S; Repair solution c is: In the data path of the digital circuit timing path, reducing the threshold voltage of the logic element by one level can reduce the element delay, thereby reducing T data , increase the setup time margin S; Among them, for the time margin S greater than the surplus threshold S max The timing path is adjusted, including: Adjustment scheme a' is: in the clock path of the digital circuit timing path, remove a buffer between the clock source and the second register clock end to reduce T clk2 , thereby reducing Δ, reducing the setup time margin S, and improving power consumption and area; Adjustment scheme b' is: in the data path of the digital circuit timing path, the size of the logic element is reduced by one level, thereby increasing T data , reduce the setup time margin S, improve power consumption and area; Adjustment scheme c' is: in the data path of the digital circuit timing path, the threshold voltage of the logic element is increased by one level, thereby increasing T data , reduce the setup time margin S, and improve power consumption and area.

9. An electronic device, It is characterized in that include: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer instructions stored thereon, It is characterized in that When the instruction is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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