Production process of chip superfine circuit

Abstract

The invention provides a production process of a chip superfine circuit, relates to the field of intelligent chip production, and adopts an image processing and analysis technology based on deep learning to perform feature extraction and significant feature optimization of a circuit pattern microscopic image and a circuit pattern design image. And automatically generating a defect detection result based on comparison between a semantic interaction matching coefficient between the optimized microscopic image and the optimized design image feature and a preset threshold value. Therefore, tiny defects which are difficult to find by a traditional method can be identified, and the detection sensitivity and accuracy are improved. And meanwhile, the system can adapt to different types of defects and different batches of wafers, and the flexibility and the automation level of the detection system are improved.

Description

Technical Field

[0001] The present application relates to the field of smart chip production, and more specifically, to a production process for ultra-fine circuits of a chip. Background Art

[0002] With the advancement of science and technology, electronic products are developing in the direction of smaller, faster and smarter, which not only promotes higher requirements for chip performance and functional density, but also promotes the development of ultra-fine line chip technology. Ultra-fine line technology enables chips to achieve higher circuit density and more efficient energy efficiency while maintaining a smaller size, which is essential for modern electronic devices such as smartphones, wearable devices and IoT terminals. Therefore, defect detection has become a key link in ensuring chip quality and reliability.

[0003] However, although the traditional simple automatic optical inspection (AOI) can improve the inspection speed, it is difficult to cope with complex and changeable defect types because it relies on preset templates and rules. Especially in the case of ultra-fine lines, subtle defects are often difficult to accurately identify. In addition, since the detection algorithm of the AOI system is usually based on threshold settings, this fixed threshold method is not flexible enough when processing different batches or different types of wafers, and it is difficult to adapt to diverse inspection needs. Specifically, in the manufacturing process of ultra-fine lines, any slight deviation may lead to serious quality problems. Due to its inherent limitations, the traditional AOI system is difficult to meet the requirements of modern chip manufacturing for high precision and high reliability.

[0004] Therefore, an optimized production process for ultra-fine circuits on chips is desired. Summary of the invention

[0005] In order to solve the above technical problems, the present application is proposed. The embodiment of the present application provides a production process for ultra-fine circuits of a chip, which uses image processing and analysis technology based on deep learning to extract features and optimize significant features of circuit pattern microscopic images and circuit pattern design images, thereby automatically generating defect detection results based on the comparison between the semantic interaction matching coefficient between the optimized microscopic image and the optimized design image features and a preset threshold. In this way, tiny defects that are difficult to detect with traditional methods can be identified, thereby improving the sensitivity and accuracy of detection. At the same time, it can adapt to different types of defects and different batches of wafers, thereby improving the flexibility and automation level of the detection system.

[0006] According to one aspect of the present application, a production process for ultra-fine circuits of a chip is provided, which includes: Provide silicon wafers; Placing the silicon wafer in a high temperature furnace for oxidation treatment to form a layer of silicon dioxide film on the surface of the silicon wafer to obtain an oxidized silicon wafer; Coating a layer of photoresist on the silicon oxide wafer, projecting a designed circuit pattern onto the photoresist using a photolithography machine, and performing exposure treatment with ultraviolet rays to obtain a circuit pattern; Performing defect detection based on a microscopic image on the circuit pattern to obtain a defect detection result; In response to the defect detection result indicating that there is no defect, etching the silicon oxide wafer having the circuit pattern to remove the exposed silicon layer and form the desired ultra-fine circuit; Based on circuit design requirements, impurity atoms are introduced into specific regions to change the electrical properties of the specific regions, and interconnection lines are made to obtain a chip; Performing an electrical performance test on the chip to obtain a test result; In response to the test result indicating that there is no defect, the chip is packaged.

[0007] In combination with the first aspect of the present application, in a chip ultrafine circuit production process of the first aspect of the present application, the circuit pattern is subjected to microscopic image-based defect detection to obtain a defect detection result, including: collecting a microscopic image of the circuit pattern; extracting a design image of the circuit pattern from a database; inputting the microscopic image of the circuit pattern and the design image of the circuit pattern into a circuit pattern feature extractor respectively to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map; inputting the circuit pattern microscopic feature map and the circuit pattern design feature map into a feature gating enhancement module guided by grid energy significance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map; inputting the circuit pattern microscopic optimization feature map and the circuit pattern design optimization feature map into a sequence matching network based on energy-intensive interactive distribution to obtain a sequence-to-sequence semantic matching coefficient; and generating the defect detection result based on the sequence-to-sequence semantic matching coefficient.

[0008] Compared with the prior art, the production process of ultra-fine circuits in chips provided by the present application uses image processing and analysis technology based on deep learning to extract features and optimize significant features of circuit pattern microscopic images and circuit pattern design images, thereby automatically generating defect detection results based on the comparison between the semantic interaction matching coefficient between the optimized microscopic image and the optimized design image features and a preset threshold. In this way, tiny defects that are difficult to detect with traditional methods can be identified, and the sensitivity and accuracy of detection are improved. At the same time, it can adapt to different types of defects and different batches of wafers, improving the flexibility and automation level of the detection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 The present invention is a flowchart of a process for producing ultra-fine circuits on a chip according to an embodiment of the present application.

[0010] Figure 2 The present invention is a flow chart of performing microscopic image-based defect detection on the circuit pattern to obtain defect detection results in a production process of chip ultrafine circuits according to an embodiment of the present application.

[0011] Figure 3 The present invention is a schematic diagram of data flow for performing microscopic image-based defect detection on the circuit pattern in the production process of the chip ultrafine circuit according to the embodiment of the present application to obtain the defect detection result.

[0012] Figure 4 In the production process of chip ultrafine circuits according to an embodiment of the present application, the circuit pattern microscopic feature map and the circuit pattern design feature map are input into a feature gating enhancement module guided by grid energy significance to obtain a flow chart of a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map.

[0013] Figure 5 A flowchart of inputting the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map into a sequence matching network based on energy-intensive interactive distribution to obtain a sequence semantic matching coefficient in the production process of chip ultra-fine circuits according to an embodiment of the present application. DETAILED DESCRIPTION

[0014] Below, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described here.

[0015] Technological progress is leading electronic products to be thinner, more efficient and more intelligent. This trend not only sets higher standards for chip performance and functional integration, but also creates demand for ultra-fine circuit technology. This technology enables chips to achieve higher circuit density and better energy efficiency while maintaining a smaller size, which is crucial for modern electronic devices such as smartphones, smart wearable devices and IoT devices. In this context, defect detection has become a core step to ensure chip quality and reliability.

[0016] However, although traditional automatic optical inspection (AOI) technology has played a role in improving inspection speed, its inspection method based on preset templates and rules is powerless when faced with complex and diverse defect types, especially in the production of ultra-fine lines, where tiny defects are often difficult to accurately identify. In addition, the inspection algorithm of the AOI system usually relies on fixed thresholds. This rigid method lacks flexibility when processing different batches or different types of wafers, and it is difficult to adapt to changing inspection needs. In the ultra-fine line manufacturing process, even small deviations can cause serious quality problems. Therefore, due to its inherent limitations, traditional AOI systems are difficult to meet the strict requirements of modern chip manufacturing for high precision and high reliability.

[0017] Based on this, the present application proposes an optimized production process for chip ultra-fine circuits. Figure 1 FIG. 1 is a flow chart of a process for producing ultra-fine circuits on a chip according to an embodiment of the present application. Figure 1 As shown, according to the production process of chip ultrafine circuits provided in the embodiment of the present application, the process includes: S110, providing a silicon wafer; S120, placing the silicon wafer in a high-temperature furnace for oxidation treatment to form a layer of silicon dioxide film on the surface of the silicon wafer to obtain a silicon oxide wafer; S130, coating a layer of photoresist on the silicon oxide wafer, and using a photolithography machine to project the designed circuit pattern onto the photoresist, and exposing it to ultraviolet light to obtain a circuit pattern; S140, performing defect detection on the circuit pattern based on a microscopic image to obtain a defect detection result; S150, in response to the defect detection result being that there is no defect, etching the silicon oxide wafer with the circuit pattern to remove the exposed silicon layer and form the required ultrafine circuit; S160, based on the circuit design requirements, introducing impurity atoms in a specific area to change the electrical properties of the specific area, and making interconnection lines to obtain a chip; performing an electrical performance test on the chip to obtain a test result; S170, in response to the test result being that there is no defect, packaging the chip.

[0018] In the production process of ultra-fine circuits of chips, first of all, it is necessary to prepare silicon wafers. Silicon wafers are the basic materials for chip manufacturing. They have good semiconductor properties and are widely used in integrated circuit manufacturing. Then the silicon wafer needs to be placed in a high-temperature furnace to react silicon with oxygen to grow a layer of silicon dioxide film on the surface of the silicon wafer. The generated silicon dioxide film has good insulation properties and chemical stability, which can prevent impurities from diffusing into the silicon wafer, and can provide a suitable surface for the construction of circuit patterns. Then a layer of photoresist is coated on the silicon oxide wafer. Photoresist is a light-sensitive material that can form a circuit pattern in the subsequent exposure process. As a key equipment in chip manufacturing, the photolithography machine can accurately project the pre-designed circuit pattern onto the photoresist, and then expose it through ultraviolet light to cause the photoresist in the exposed area to undergo chemical changes, thereby obtaining a circuit pattern on the silicon oxide wafer. During the chip manufacturing process, any tiny defect may cause the chip performance to degrade or even fail. Then, it is necessary to perform defect detection based on microscopic images on the circuit pattern to promptly discover defects in the circuit pattern, such as line breakage and short circuit. After determining that the circuit pattern has no defects, the silicon oxide wafer with the circuit pattern is etched. The etching process selectively removes the exposed silicon layer. Through precise etching, ultra-fine lines with very small sizes can be formed. These lines are the key structures for the chip to realize various functions (such as signal transmission, logical operations, etc.). Then, according to the circuit design requirements of the chip, impurity atoms (such as boron, phosphorus, etc.) are introduced into specific areas. This doping process can change the electrical properties of silicon, such as forming P-type or N-type semiconductor areas, thereby constructing various transistors, diodes and other devices, and making interconnection lines to connect the various devices, so that the chip can work normally according to the designed circuit function. Then, the manufactured chip is subjected to electrical performance testing to check whether the various electrical parameters of the chip (such as current, voltage, resistance, etc.) meet the design requirements to determine whether the chip can work normally. When the electrical performance test results of the chip show no defects, the final packaging operation is required. Packaging can protect the chip from the influence of the external environment (such as physical impact, chemical corrosion, etc.), and at the same time provide the chip with an interface to connect to the external circuit, so that the chip can be easily integrated into various electronic devices.

[0019] Accordingly, in performing microscopic image-based defect detection on the circuit pattern to obtain defect detection results, the microscopic image of the circuit pattern is collected, and the design image of the circuit pattern is extracted from the database, and image processing and analysis technology based on deep learning is used to extract features of the microscopic image and the design image and optimize significant features, thereby automatically generating the defect detection results based on the comparison between the semantic interaction matching coefficient between the optimized microscopic image and the optimized design image features and a preset threshold. In this way, tiny defects that are difficult to detect with traditional methods can be identified, and the sensitivity and accuracy of detection are improved. At the same time, it can adapt to different types of defects and different batches of wafers, improving the flexibility and automation level of the detection system.

[0020] Figure 2 The present invention is a flow chart of performing microscopic image-based defect detection on the circuit pattern to obtain defect detection results in a production process of chip ultrafine circuits according to an embodiment of the present application. Figure 3 The present invention is a schematic diagram of data flow for performing microscopic image-based defect detection on the circuit pattern in the production process of the chip ultrafine circuit according to the embodiment of the present application to obtain the defect detection result. Figure 2 and Figure 3 As shown, the circuit pattern is subjected to microscopic image-based defect detection to obtain a defect detection result, including: S141, collecting a microscopic image of the circuit pattern; S142, extracting a design image of the circuit pattern from a database; S143, inputting the microscopic image of the circuit pattern and the design image of the circuit pattern into a circuit pattern feature extractor respectively to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map; S144, inputting the circuit pattern microscopic feature map and the circuit pattern design feature map into a feature gating enhancement module guided by grid energy significance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map; S145, inputting the circuit pattern microscopic optimization feature map and the circuit pattern design optimization feature map into an inter-sequence matching network based on energy-dense interactive distribution to obtain an inter-sequence semantic matching coefficient; S146, generating the defect detection result based on the inter-sequence semantic matching coefficient.

[0021] In step S141 and step S142, a microscopic image of the circuit pattern is collected, and a design image of the circuit pattern is extracted from a database. It should be understood that the microscopic image of the circuit pattern usually contains the microscopic structure and features of the wafer surface, such as line width, spacing, edge clarity, pattern integrity, etc., which can reveal physical defects on the wafer, such as broken wires, bridges, depressions, particles, protrusions, etc. The design image of the circuit pattern usually contains detailed layout information of all microscopic circuit elements on the chip. It is a reference standard in the defect detection process and is used to compare with the microscopic image to identify deviations and defects in the actual manufacturing process.

[0022] In step S143, the microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into the circuit pattern feature extractor to obtain the circuit pattern microscopic feature map and the circuit pattern design feature map. Specifically, in an embodiment of the present application, the microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into the circuit pattern feature extractor to obtain the circuit pattern microscopic feature map and the circuit pattern design feature map, including: the microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into the circuit pattern feature extractor based on the hole convolution neural network model to obtain the circuit pattern microscopic feature map and the circuit pattern design feature map. It should be understood that the microscopic image of the circuit pattern contains the microscopic structure and features of the wafer surface, and the design map of the circuit pattern contains the detailed layout information of all microscopic circuit elements on the chip. Considering that the hole convolution encoding method in the hole convolution neural network model can expand the receptive field by introducing intervals in the convolution kernel without increasing the amount of calculation and the number of parameters, thereby capturing a wider range of contextual information of the input data, which is conducive to improving the accuracy of defect detection. Based on this, in the technical solution of the present application, the microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into a circuit pattern feature extractor based on a hole convolutional neural network model to respectively capture and extract the microscopic detail features and design layout information in the circuit pattern, and obtain a circuit pattern microscopic feature map and a circuit pattern design feature map.

[0023] In step S144, the circuit pattern microscopic feature map and the circuit pattern design feature map are input into a feature gating enhancement module guided by grid energy significance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map. Accordingly, considering that both the circuit pattern microscopic feature map and the circuit pattern design feature map contain key and significant circuit pattern features, that is, different regions have different importance, such as in a circuit pattern, some connection points may be more important than other regions because they are key channels for electronic signal transmission. For example, key connection points and sensitive element regions may be more important than other regions. In order to enhance and highlight the contrast of key features in the circuit pattern microscopic feature map and the circuit pattern design feature map, thereby improving the accuracy of defect detection, in the technical solution of the present application, the circuit pattern microscopic feature map and the circuit pattern design feature map are input into a feature gating enhancement module guided by grid energy significance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map. In particular, the feature gating enhancement module guided by grid energy significance defines a grid to define the area of ​​interest and simulates the attention mechanism based on energy significance, so as to enhance the expressiveness of the feature map and improve the overall performance of the model. This method introduces attention focus in the feature extraction process, so that the model can more accurately capture the key information in the image, thereby improving the accuracy of recognition or classification.

[0024] Here, the circuit pattern microscopic feature map is used for detailed description. First, the circuit pattern microscopic feature map is grid-divided to divide a whole large feature map into multiple smaller local areas to obtain a set of circuit pattern microscopic local feature maps, which helps to analyze and extract the local features in each small area in more detail. Then, the energy significance description factor of each local feature map is calculated to obtain a set of circuit pattern microscopic local energy significance description factors. Specifically, the energy significance description factor is obtained based on the statistical features of the maximum value, minimum value, mean and variance of each local feature map to quantify the importance of each local area to the entire image domain, so as to better identify and focus on those areas that are most likely to contain key information, providing a basis for subsequent data analysis. Subsequently, each energy significance description factor is input into a local feature adaptive selector based on a gating function to obtain a set of circuit pattern microscopic local significant modulation weights corresponding to the circuit pattern microscopic local feature map. It should be understood that the gating mechanism can be regarded as an information filter, which can determine which information is important and which can be ignored according to the energy significance description factor of each local feature, so as to dynamically adjust according to different input data. This means that the model can adaptively optimize different input images, so that the model can focus more on the key circuit parts in the microscopic image. Furthermore, the microscopic local significant modulation weight of each circuit pattern is used as a weight to weight each circuit pattern microscopic local feature map so that the model pays more attention to certain local areas with significant energy in the feature map, such as those that may contain defects or key features, and suppresses those unimportant parts. In particular, the essence of the weighted enhancement step is attention application, because the model's attention is directed to the most important part of the image, which helps to improve the model's sensitivity to small but important details in the image. Afterwards, each weighted feature is feature aggregated in accordance with the grid division method to obtain the circuit pattern microscopic local significant guided enhancement feature map. Finally, in order to achieve uniform distribution of features, a feature dispersion module based on a dilated convolutional layer is used to process the local significant guided enhancement feature map to obtain a circuit pattern micro-optimization feature map, so as to reduce the discontinuity of feature expression at the boundary caused by grid division. That is, through the expansion characteristics of the dilated convolution, the features at the edge of the grid can be effectively smoothed and fused, thereby achieving a more consistent feature expression in the entire feature map to eliminate the boundary effect introduced by grid division.

[0025] Specifically, Figure 4 In the production process of the chip ultrafine circuit according to the embodiment of the present application, the circuit pattern microscopic feature map and the circuit pattern design feature map are input into the feature gating enhancement module based on grid energy significance guidance to obtain the circuit pattern microscopic optimization feature map and the circuit pattern design optimization feature map. Figure 4 As shown, the circuit pattern microscopic feature map and the circuit pattern design feature map are input into a feature gating enhancement module based on grid energy significance guidance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map, including: S1441, gridding the circuit pattern microscopic feature map to obtain a set of circuit pattern microscopic local feature maps; S1442, calculating the energy significance description factor of each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps to obtain a set of circuit pattern microscopic local energy significance description factors; S1443, inputting the set of circuit pattern microscopic local energy significance description factors into a local feature adaptive selector based on a gating function to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map. A set of circuit pattern microscopic local significant modulation weights; S1444, taking each circuit pattern microscopic local significant modulation weight in the set of circuit pattern microscopic local significant modulation weights as a weight, weighting each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps respectively to obtain a set of circuit pattern microscopic local enhanced feature maps; S1445, performing feature aggregation on the set of circuit pattern microscopic local enhanced feature maps in accordance with the grid division method to obtain a circuit pattern microscopic local significant guided enhanced feature map; S1446, inputting the circuit pattern microscopic local significant guided enhanced feature map into a feature dispersion module based on a hole convolution layer to obtain the circuit pattern microscopic optimized feature map.

[0026] More specifically, in an embodiment of the present application, the energy significance description factor of each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps is calculated to obtain a set of circuit pattern microscopic local energy significance description factors, including: extracting the maximum value and the minimum value of the circuit pattern microscopic local feature map respectively to obtain the circuit pattern microscopic local feature maximum value and the circuit pattern microscopic local feature minimum value; calculating the difference between the circuit pattern microscopic local feature maximum value and the circuit pattern microscopic local feature minimum value to obtain the circuit pattern microscopic local feature difference value; calculating the global mean and variance of the circuit pattern microscopic local feature map respectively to obtain the circuit pattern microscopic local feature mean value and the circuit pattern microscopic local feature variance; adding the value obtained by multiplying the circuit pattern microscopic local feature variance by a constant two and the circuit pattern microscopic local feature mean value to a hyperparameter to obtain a circuit pattern microscopic local feature statistical modulation value; dividing the circuit pattern microscopic local feature difference value by the circuit pattern microscopic local feature statistical modulation value to obtain the circuit pattern microscopic local energy significance description factor corresponding to the circuit pattern microscopic local feature map.

[0027] More specifically, in an embodiment of the present application, the set of circuit pattern microscopic local energy significance description factors is input into a local feature adaptive selector based on a gating function to obtain a set of circuit pattern microscopic local significance modulation weights, including: calculating an exponential function with a natural constant e as the base and the negative of each circuit pattern microscopic local energy significance description factor in the set of circuit pattern microscopic local energy significance description factors as the exponent to obtain a set of circuit pattern microscopic local energy significance description exponential factors; calculating the reciprocal of the sum of each circuit pattern microscopic local energy significance description exponential factor in the set of circuit pattern microscopic local energy significance description exponential factors and a constant one to obtain a set of normalized circuit pattern microscopic local energy significance description factors; and inputting each normalized circuit pattern microscopic local energy significance description factor in the set of normalized circuit pattern microscopic local energy significance description factors into a gating function for masking processing to obtain the set of circuit pattern microscopic local significance modulation weights.

[0028] In the embodiment of the present application, specifically, the circuit pattern microscopic feature map and the circuit pattern design feature map are input into a feature gating enhancement module based on grid energy significance guidance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map, including: inputting the circuit pattern microscopic feature map into a feature gating enhancement module based on grid energy significance guidance, and processing it with the following significant gating enhancement formula to obtain the circuit pattern microscopic optimization feature map; wherein the significant gating enhancement formula is: in, is the circuit pattern microscopic feature diagram, is the meshing operation, are respectively the microscopic local feature maps of each circuit pattern in the set of microscopic local feature maps of the circuit pattern, is the first in the set of microscopic local feature maps of the circuit pattern A microscopic local feature map of the circuit pattern, and Extract the maximum and minimum values ​​in the feature map respectively. and They are The mean and variance of is a hyperparameter, Indicates The circuit pattern microscopic local energy significance description factor corresponding to the circuit pattern microscopic local feature map, For masking, It is The circuit pattern microscopic local significant modulation weight corresponding to the circuit pattern microscopic local feature map, θ is the predetermined threshold, To perform feature aggregation operations on each weighted feature map, The circuit pattern has a microscopically significant local guide enhancement feature map, is the dilated convolution operation, is the circuit pattern microscopic optimization feature map. Similarly, the encoding method of the design image of the circuit pattern is also shown in the above formula.

[0029] In step S145, the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map are input into a sequence matching network based on energy-intensive interactive distribution to obtain a sequence semantic matching coefficient. It should be understood that in order to evaluate the semantic matching similarity between the microscopic image and the design image in a more fine-grained manner, thereby detecting possible defects or deviations and improving the accuracy of defect detection, in the technical solution of the present application, the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map are input into a sequence matching network based on energy-intensive interactive distribution to obtain a sequence semantic matching coefficient. In detail, the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map are first expanded to obtain a sequence of circuit pattern micro-optimization feature vectors and a sequence of circuit pattern design optimization feature vectors, providing a basis for subsequent local regions. Then, feature selection is performed on the sequence of vectors obtained after expansion to select the features most relevant to the target variable, eliminate irrelevant or redundant features, and obtain a sequence of selected feature vectors. Next, the energy synergistic response value between the selected feature vector pairs is calculated to quantify the interaction and synergistic effect between the feature vectors. That is, here, by capturing the local fine-grained semantic association interaction between microscopic features and design features, the semantic association matching relationship between local regions is more carefully characterized to obtain the circuit pattern microscopic-pattern design optimization feature collaborative energy fine-grained global distribution matrix. Subsequently, the global distribution matrix is ​​subjected to hole convolution encoding to capture the semantic association interaction relationship in a wider range, and the semantic association between the whole is characterized to obtain the circuit pattern microscopic-pattern design optimization feature collaborative energy fine-grained global distribution feature matrix. Finally, the global distribution feature matrix is ​​input into the inter-sequence matching degree measurement network to calculate the semantic similarity matching between the two sequences to obtain the final inter-sequence semantic matching coefficient.

[0030] Specifically, Figure 5 A flowchart of inputting the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map into a sequence matching network based on energy-intensive interactive distribution to obtain a sequence semantic matching coefficient in the production process of the chip ultra-fine circuit according to the embodiment of the present application. Figure 5As shown, the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map are input into a sequence matching network based on energy-intensive interactive distribution to obtain a sequence semantic matching coefficient, including: S1451, the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map are expanded to obtain a sequence of circuit pattern micro-optimization feature vectors and a sequence of circuit pattern design optimization feature vectors; S1452, feature selection is performed on the sequence of circuit pattern micro-optimization feature vectors and the sequence of circuit pattern design optimization feature vectors to obtain a sequence of selected circuit pattern micro-optimization feature vectors and a sequence of selected circuit pattern design optimization feature vectors; S1453, the selected circuit pattern micro-optimization feature vectors are calculated. The energy synergy response value between any pair of selected circuit pattern micro-optimization feature vectors and selected circuit pattern design optimization feature vectors in the sequence of feature vectors and the sequence of selected circuit pattern design optimization feature vectors is used to obtain a circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution matrix; S1454, the circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution matrix is ​​subjected to dilated convolution encoding to obtain a circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution feature matrix; S1455, the circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution feature matrix is ​​input into a sequence matching degree measurement network to obtain the sequence semantic matching coefficient.

[0031] More specifically, in an embodiment of the present application, feature selection is performed on the sequence of the circuit pattern micro-optimization feature vectors and the sequence of the circuit pattern design optimization feature vectors to obtain a sequence of selected circuit pattern micro-optimization feature vectors and a sequence of selected circuit pattern design optimization feature vectors, including: using a first importance metric function to calculate the circuit pattern micro-optimization importance factor of each circuit pattern micro-optimization feature vector in the sequence of the circuit pattern micro-optimization feature vectors; based on a comparison between each of the circuit pattern micro-optimization importance factors and a first preset threshold, feature selection is performed on the sequence of the circuit pattern micro-optimization feature vectors to obtain the sequence of selected circuit pattern micro-optimization feature vectors; using a second importance metric function to calculate the circuit pattern design optimization importance factor of each circuit pattern design optimization feature vector in the sequence of the circuit pattern design optimization feature vectors; based on a comparison between each of the circuit pattern design optimization importance factors and a second preset threshold, feature selection is performed on the sequence of the circuit pattern design optimization feature vectors to obtain the sequence of selected circuit pattern design optimization feature vectors.

[0032] In the embodiment of the present application, specifically, using the first importance metric function to calculate the circuit pattern micro-optimization importance factor of each circuit pattern micro-optimization feature vector in the sequence of the circuit pattern micro-optimization feature vectors includes: using the first importance metric function to calculate the circuit pattern micro-optimization importance factor of each circuit pattern micro-optimization feature vector in the sequence of the circuit pattern micro-optimization feature vectors using the following formula; wherein the calculation formula is:

[0033] in, are respectively each circuit pattern micro-optimization feature vector in the sequence of circuit pattern micro-optimization feature vectors, is the circuit pattern micro weight matrix, is the circuit pattern microscopic bias vector, represents the tanh function, is the weight coefficient vector, The importance factor is optimized for each circuit pattern microstructure.

[0034] More specifically, in an embodiment of the present application, the energy synergistic response value between any pair of selected circuit pattern micro-optimization feature vectors and selected circuit pattern design optimization feature vectors in the sequence of the selected circuit pattern micro-optimization feature vectors and the sequence of the selected circuit pattern design optimization feature vectors is calculated to obtain a circuit pattern micro-pattern design optimization feature synergistic energy fine-grained global distribution matrix, including: calculating the position-by-position division between the selected circuit pattern micro-optimization feature vector and the selected circuit pattern design optimization feature vector to obtain a selected circuit pattern micro-design local area matching feature vector; extracting the maximum value of the selected circuit pattern micro-design local area matching feature vector to obtain a selected circuit pattern micro-design local area matching feature maximum value; respectively calculating the mean and variance of the selected circuit pattern micro-design local area matching feature vector to obtain a selected circuit pattern micro-design local area matching feature mean and a selected circuit pattern micro-design local area matching feature variance; and adding the selected circuit pattern micro-design local area matching feature variance and deviation to obtain a selected circuit pattern micro-design local area matching feature mean. The value obtained by adding the offset items is multiplied by four to obtain the first energy synergistic response value of the selected circuit pattern microscopic-designed local area matching feature; the square of the difference between the maximum value of the selected circuit pattern microscopic-designed local area matching feature and the mean value of the selected circuit pattern microscopic-designed local area matching feature is calculated to obtain the selected circuit pattern microscopic-designed local area feature difference value; the modulated selected circuit pattern microscopic-designed local area matching feature variance obtained by multiplying the selected circuit pattern microscopic-designed local area matching feature variance by two is added to the value obtained by multiplying the bias item by two and the selected circuit pattern microscopic-designed local area feature difference value to obtain the second energy synergistic response value of the selected circuit pattern microscopic-designed local area matching feature; the first energy synergistic response value of the selected circuit pattern microscopic-designed local area matching feature is divided by the second energy synergistic response value of the selected circuit pattern microscopic-designed local area matching feature to obtain the energy synergistic response value between the selected circuit pattern microscopic optimization feature vector and the selected circuit pattern design optimization feature vector.

[0035] In the embodiment of the present application, specifically, the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map are input into a sequence matching network based on energy-intensive interactive distribution to obtain a sequence semantic matching coefficient, including: expanding the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map to obtain a sequence of circuit pattern micro-optimization feature vectors and a sequence of circuit pattern design optimization feature vectors; inputting the sequence of circuit pattern micro-optimization feature vectors and the sequence of circuit pattern design optimization feature vectors into a sequence matching network based on energy-intensive interactive distribution, and processing them with the following sequence matching formula to obtain the sequence semantic matching coefficient; wherein the sequence matching formula is: in, and are respectively a sequence of the circuit pattern micro-optimization feature vectors and a sequence of the circuit pattern design optimization feature vectors, To perform feature selection, and are respectively a sequence of the selected circuit pattern micro-optimization feature vectors and a sequence of the selected circuit pattern design optimization feature vectors, and The first and second sequences of the selected circuit pattern micro-optimization feature vectors and the selected circuit pattern design optimization feature vectors are respectively represented by The circuit pattern micro-optimization feature vector after the selection and the The circuit pattern design optimization feature vector after selection, It means to calculate the energy synergy response value between two vectors. The circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution matrix is The eigenvalues ​​at the positions, To extract the maximum value of a vector, For the The circuit pattern micro-optimization feature vector after the selection and the The selected circuit pattern micro-design local area matching feature vector between the selected circuit pattern design optimization feature vectors, and They are The mean and variance of is the bias term, E is the circuit pattern micro-pattern design optimization feature synergistic energy fine-grained global distribution matrix, is the dilated convolutional coding, is the circuit pattern microscopic-pattern design optimization feature synergistic energy fine-grained global distribution feature matrix, is the matching degree measurement operation between sequences, is the semantic matching coefficient between the sequences.

[0036] In step S146, the defect detection result is generated based on the semantic matching coefficient between the sequences. Specifically, in an embodiment of the present application, the defect detection result is generated based on the semantic matching coefficient between the sequences, including: generating the defect detection result based on the comparison between the semantic matching coefficient between the sequences and a preset threshold. That is, the defect detection result is automatically generated by comparing the semantic interaction matching coefficient obtained by performing sequence semantic matching using the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map with a preset threshold. In this way, tiny defects that are difficult to detect with traditional methods can be identified, thereby improving the sensitivity and accuracy of detection. At the same time, it can adapt to different types of defects and different batches of wafers, thereby improving the flexibility and automation level of the detection system.

[0037] In a preferred example, since the circuit pattern microscopic optimization feature map and the circuit pattern design optimization feature map respectively represent the local spatial enhanced image semantic features of the microscopic image and the design image of the circuit pattern based on the energy significance of the image semantic feature grid distribution, when the circuit pattern microscopic optimization feature map and the circuit pattern design optimization feature map are input into the sequence matching network based on the energy dense interactive distribution, there will also be image semantic feature aggregation matching offset caused by the inconsistency of the local spatial image semantic distribution energy dense interactive matching distribution based on the difference in the semantic distribution of the source images, thereby affecting the accuracy of the semantic matching coefficient between sequences.

[0038] Therefore, when the circuit pattern micro-optimization feature graph and the circuit pattern design optimization feature graph are input into an inter-sequence matching network based on energy-intensive interactive distribution to obtain an inter-sequence semantic matching coefficient, the present application jointly optimizes the circuit pattern micro-optimization feature graph and the circuit pattern design optimization feature graph, including the steps of: respectively expanding the circuit pattern micro-optimization feature graph and the circuit pattern design optimization feature graph into a circuit pattern micro-optimization feature vector and a circuit pattern design optimization feature vector; cascading the circuit pattern micro-optimization feature vector and the circuit pattern design optimization feature vector into a circuit pattern micro-design optimization feature vector; subtracting the 0 norm of the circuit pattern micro-design optimization feature vector from the length of the circuit pattern micro-design optimization feature vector to obtain a circuit pattern micro-design optimization isolated representation value; calculating the logarithm of the square of the circuit pattern micro-design optimization isolated representation value and the sum of the circuit pattern micro-design optimization isolated representation value with base 2 to obtain a circuit pattern micro-design optimization information order value; calculating the circuit pattern micro-design optimization information order value with each eigenvalue of the circuit pattern micro-design optimization feature vector as the base, the circuit pattern micro-design optimization feature vector. The difference between the circuit pattern microscopic-design optimization isolated representation value and one is an exponential power function, and is point-multiplied with the circuit pattern microscopic-design optimization information order value to obtain the circuit pattern microscopic-design optimization guide vector; the circuit pattern microscopic-design optimization feature vector is point-multiplied with the difference between the circuit pattern microscopic-design optimization isolated representation value and one, and then point-multiplied with the reciprocal of the circuit pattern microscopic-design optimization isolated representation value to obtain the circuit pattern microscopic-design optimization field constraint vector; the circuit pattern microscopic-design optimization field constraint vector is calculated with the natural constant e as the base. Each eigenvalue of the quantity is an exponential function of the exponent to obtain a circuit pattern microscopic-design optimization field bias vector; the circuit pattern microscopic-design optimization pilot vector and the circuit pattern microscopic-design optimization field bias vector are dot-added to obtain an optimized circuit pattern microscopic-design optimization feature vector; the optimized circuit pattern microscopic-design optimization feature vector is split into an optimized circuit pattern microscopic optimization feature vector and an optimized circuit pattern design optimization feature vector, and restored to an optimized circuit pattern microscopic optimization feature graph and an optimized circuit pattern design optimization feature graph.

[0039] The optimization process of the circuit pattern micro-design optimization feature vector is expressed as:

[0040] in, optimizing a feature vector for the circuit pattern micro-design, represents the length of the circuit pattern micro-design optimization feature vector, represents the zero norm of the vector, n represents the isolated representation value of the circuit pattern micro-design optimization, It means point multiplication by position. To calculate the power function with each eigenvalue of the circuit pattern micro-design optimization eigenvector as the base, the difference of the circuit pattern micro-design optimization isolated representation value minus one is the exponent, represents the logarithm with base 2, Indicates adding by position point. represents the natural exponential function, represents the optimized circuit pattern micro-design optimized feature vector.

[0041] Thus, for the high-dimensional feature manifold of the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map, the eigenvalue of the feature set is used as the vector field representation of the aggregation dimension, and the superposition value of the vector field of the circuit pattern micro-design optimization feature vector at the isolated zero position is used as the order information to fix the local position of the eigenvalue of its feature set, and add the bias of the reversibility of the feature regression distribution field of the circuit pattern micro-design optimization feature vector as a reward to achieve the mapping target tracking of the regression distribution of the circuit pattern micro-design optimization feature vector for the eigenvalue position, so that the feature set of the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map perceives the mapping migration to the aggregate distribution, thereby improving the accuracy of the semantic matching coefficient between the sequences by improving the image semantic feature matching mapping comprehensibility of the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map. In this way, it is possible to identify tiny defects that are difficult to find by traditional methods, and improve the sensitivity and accuracy of detection. At the same time, it can adapt to different types of defects and different batches of wafers, and improve the flexibility and automation level of the detection system.

[0042] In summary, the production process of chip ultrafine circuits based on the embodiment of the present application is explained, which uses image processing and analysis technology based on deep learning to extract features and optimize significant features of circuit pattern microscopic images and circuit pattern design images, thereby automatically generating defect detection results based on the comparison between the semantic interaction matching coefficient between the optimized microscopic image and the optimized design image features and the preset threshold. In this way, tiny defects that are difficult to find with traditional methods can be identified, and the sensitivity and accuracy of detection are improved. At the same time, it can adapt to different types of defects and different batches of wafers, improving the flexibility and automation level of the detection system.

[0043] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details of the above application are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present application to the use of the above specific details to be implemented.

Claims

1. A production process for ultra-fine circuits on a chip, characterized in that: include: Provide silicon wafers; Placing the silicon wafer in a high temperature furnace for oxidation treatment to form a layer of silicon dioxide film on the surface of the silicon wafer to obtain an oxidized silicon wafer; Coating a layer of photoresist on the silicon oxide wafer, projecting a designed circuit pattern onto the photoresist using a photolithography machine, and performing exposure treatment with ultraviolet rays to obtain a circuit pattern; Performing defect detection based on a microscopic image on the circuit pattern to obtain a defect detection result; In response to the defect detection result indicating that there is no defect, etching the silicon oxide wafer having the circuit pattern to remove the exposed silicon layer and form the desired ultra-fine circuit; Based on circuit design requirements, impurity atoms are introduced into specific regions to change the electrical properties of the specific regions, and interconnection lines are made to obtain a chip; Performing an electrical performance test on the chip to obtain a test result; In response to the test result indicating that there is no defect, the chip is packaged.

2. The process for producing ultra-fine circuits on a chip according to claim 1, characterized in that: Performing microscopic image-based defect detection on the circuit pattern to obtain a defect detection result, comprising: collecting a microscopic image of the circuit pattern; extracting a design image of the circuit pattern from a database; Inputting the microscopic image of the circuit pattern and the design image of the circuit pattern into a circuit pattern feature extractor to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map respectively; Inputting the circuit pattern microscopic feature map and the circuit pattern design feature map into a feature gating enhancement module based on grid energy significance guidance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map; Inputting the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map into an inter-sequence matching network based on energy-intensive interaction distribution to obtain an inter-sequence semantic matching coefficient; The defect detection result is generated based on the semantic matching coefficient between the sequences.

3. The process for producing ultra-fine circuits on a chip according to claim 2, characterized in that: The microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into a circuit pattern feature extractor to obtain a circuit pattern microscopic feature map and a circuit pattern design feature map, including: the microscopic image of the circuit pattern and the design image of the circuit pattern are respectively input into a circuit pattern feature extractor based on a hole convolutional neural network model to obtain the circuit pattern microscopic feature map and the circuit pattern design feature map.

4. The process for producing ultra-fine circuits on a chip according to claim 3, characterized in that: Inputting the circuit pattern microscopic feature map and the circuit pattern design feature map into a feature gating enhancement module based on grid energy significance guidance to obtain a circuit pattern microscopic optimization feature map and a circuit pattern design optimization feature map, including: Performing grid division on the circuit pattern microscopic feature map to obtain a set of circuit pattern microscopic local feature maps; Calculating the energy significance description factor of each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps to obtain a set of circuit pattern microscopic local energy significance description factors; Inputting the set of circuit pattern microscopic local energy significance description factors into a local feature adaptive selector based on a gating function to obtain a set of circuit pattern microscopic local significance modulation weights; Using each circuit pattern microscopic local significant modulation weight in the set of circuit pattern microscopic local significant modulation weights as a weight, weighting each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps to obtain a set of circuit pattern microscopic local enhanced feature maps; Performing feature aggregation on the set of the circuit pattern microscopic local enhancement feature maps according to the grid division method to obtain the circuit pattern microscopic local significant guidance enhancement feature map; The circuit pattern microscopic local significant guided enhanced feature map is input into a feature dispersion module based on a hole convolution layer to obtain the circuit pattern microscopic optimized feature map.

5. The process for producing ultra-fine circuits on a chip according to claim 4, characterized in that: Calculating the energy significance description factor of each circuit pattern microscopic local feature map in the set of circuit pattern microscopic local feature maps to obtain a set of circuit pattern microscopic local energy significance description factors, including: Respectively extracting the maximum value and the minimum value of the circuit pattern microscopic local feature map to obtain the circuit pattern microscopic local feature maximum value and the circuit pattern microscopic local feature minimum value; Calculating the difference between the maximum value of the microscopic local feature of the circuit pattern and the minimum value of the microscopic local feature of the circuit pattern to obtain a difference value of the microscopic local feature of the circuit pattern; Respectively calculating the global mean and variance of the circuit pattern microscopic local feature map to obtain the circuit pattern microscopic local feature mean and the circuit pattern microscopic local feature variance; The value obtained by multiplying the variance of the microscopic local feature of the circuit pattern by a constant of two and the mean value of the microscopic local feature of the circuit pattern are added to the hyperparameter to obtain a statistical modulation value of the microscopic local feature of the circuit pattern; The circuit pattern microscopic local feature difference value is divided by the circuit pattern microscopic local feature statistical modulation value to obtain a circuit pattern microscopic local energy significance description factor corresponding to the circuit pattern microscopic local feature map.

6. The process for producing ultra-fine circuits on a chip according to claim 5, characterized in that: The set of circuit pattern microscopic local energy significance description factors is input into a local feature adaptive selector based on a gating function to obtain a set of circuit pattern microscopic local significance modulation weights, including: Calculating an exponential function with the natural constant e as the base and the negative number of each circuit pattern microscopic local energy significance description factor in the set of circuit pattern microscopic local energy significance description factors as the exponent to obtain a set of circuit pattern microscopic local energy significance description exponential factors; Calculating the reciprocal of the sum of each circuit pattern microscopic local energy significance description index factor in the set of circuit pattern microscopic local energy significance description index factors and a constant of one to obtain a set of normalized circuit pattern microscopic local energy significance description factors; Each normalized circuit pattern microscopic local energy significance description factor in the set of normalized circuit pattern microscopic local energy significance description factors is input into a gating function for masking processing to obtain a set of circuit pattern microscopic local significance modulation weights.

7. The process for producing ultra-fine circuits on a chip according to claim 6, characterized in that: Inputting the circuit pattern micro-optimization feature map and the circuit pattern design optimization feature map into an inter-sequence matching network based on energy-intensive interaction distribution to obtain an inter-sequence semantic matching coefficient, including: Expanding the circuit pattern microscopic optimization feature map and the circuit pattern design optimization feature map to obtain a sequence of circuit pattern microscopic optimization feature vectors and a sequence of circuit pattern design optimization feature vectors; Performing feature selection on the sequence of circuit pattern micro-optimization feature vectors and the sequence of circuit pattern design optimization feature vectors to obtain a sequence of selected circuit pattern micro-optimization feature vectors and a sequence of selected circuit pattern design optimization feature vectors; Calculating the energy synergy response value between any pair of selected circuit pattern micro-optimization feature vectors and selected circuit pattern design optimization feature vectors in the sequence of selected circuit pattern micro-optimization feature vectors and the sequence of selected circuit pattern design optimization feature vectors to obtain a circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution matrix; Performing dilated convolution coding on the circuit pattern microscopic-pattern design optimization feature collaborative energy fine-grained global distribution matrix to obtain a circuit pattern microscopic-pattern design optimization feature collaborative energy fine-grained global distribution feature matrix; The circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution feature matrix is ​​input into the sequence matching degree measurement network to obtain the sequence semantic matching coefficient.

8. The process for producing ultra-fine circuits on a chip according to claim 7, characterized in that: Performing feature selection on the sequence of circuit pattern micro-optimization feature vectors and the sequence of circuit pattern design optimization feature vectors to obtain a sequence of selected circuit pattern micro-optimization feature vectors and a sequence of selected circuit pattern design optimization feature vectors, comprising: Calculating the circuit pattern micro-optimization importance factor of each circuit pattern micro-optimization feature vector in the sequence of circuit pattern micro-optimization feature vectors using a first importance metric function; Based on the comparison between each of the circuit pattern micro-optimization importance factors and a first preset threshold, feature selection is performed on the sequence of circuit pattern micro-optimization feature vectors to obtain the sequence of selected circuit pattern micro-optimization feature vectors; calculating a circuit pattern design optimization importance factor of each circuit pattern design optimization feature vector in the sequence of circuit pattern design optimization feature vectors using a second importance metric function; Based on the comparison between each of the circuit pattern design optimization importance factors and a second preset threshold, feature selection is performed on the sequence of circuit pattern design optimization feature vectors to obtain the sequence of selected circuit pattern design optimization feature vectors.

9. The process for producing ultra-fine circuits on a chip according to claim 8, characterized in that: Calculating the energy synergy response value between any pair of selected circuit pattern micro-optimization feature vectors and selected circuit pattern design optimization feature vectors in the sequence of the selected circuit pattern micro-optimization feature vectors and the sequence of the selected circuit pattern design optimization feature vectors to obtain a circuit pattern micro-pattern design optimization feature synergy energy fine-grained global distribution matrix, including: Calculating the position-by-position division between the selected circuit pattern microscopic optimization feature vector and the selected circuit pattern design optimization feature vector to obtain a selected circuit pattern microscopic-design local area matching feature vector; Extracting the maximum value of the selected circuit pattern microscopic-designed local area matching feature vector to obtain the selected circuit pattern microscopic-designed local area matching feature maximum value; Respectively calculating the mean and variance of the selected circuit pattern microscopic-designed local area matching feature vector to obtain the selected circuit pattern microscopic-designed local area matching feature mean and the selected circuit pattern microscopic-designed local area matching feature variance; The value obtained by adding the selected circuit pattern microscopic-designed local area matching feature variance and the bias term is multiplied by four to obtain the selected circuit pattern microscopic-designed local area matching feature first energy synergy response value; Calculating the square of the difference between the maximum value of the selected circuit pattern microscopic-designed local area matching feature and the mean value of the selected circuit pattern microscopic-designed local area matching feature to obtain a selected circuit pattern microscopic-designed local area feature difference value; The second energy synergy response value of the selected circuit pattern microscopic-designed local area matching feature is obtained by adding the modulated selected circuit pattern microscopic-designed local area matching feature variance obtained by multiplying the selected circuit pattern microscopic-designed local area matching feature variance by two, the value obtained by multiplying the bias term by two, and the selected circuit pattern microscopic-designed local area feature difference value; The energy synergy response value between the selected circuit pattern microscopic-designed local area matching feature vector and the selected circuit pattern design optimized feature vector is obtained by dividing the first energy synergy response value of the selected circuit pattern microscopic-designed local area matching feature vector by the second energy synergy response value of the selected circuit pattern microscopic-designed local area matching feature vector.

10. The process for producing ultra-fine circuits on a chip according to claim 9, characterized in that: Generating the defect detection result based on the semantic matching coefficient between sequences includes: generating the defect detection result based on a comparison between the semantic matching coefficient between sequences and a preset threshold.

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