Integrated semiconductor device and packaging method

Abstract

The present application belongs to the field of semiconductor technology, and discloses an integrated semiconductor device and a packaging method, wherein the integrated semiconductor device includes a half-bridge module, including two bridge arm structures connected to each other and spaced along a first direction, each bridge arm structure including a substrate, a cooling structure and a plurality of semiconductor chips, the plurality of semiconductor chips are arranged on the first surface of the substrate, and the cooling structure covers the second surface of the substrate; a packaging structure connected between the two bridge arm structures and covering the first surface; a connecting terminal, the two bridge arm structures are conductively connected through the connecting terminal, and the connecting terminal extends from one side of the packaging structure and is conductively connected to an external circuit; the first surface and the second surface are respectively located on both sides of the substrate in the first direction, the first surfaces of the two substrates are arranged close to each other, and the second surfaces of the two substrates are arranged far from each other. The integrated semiconductor device and packaging method of the present application can increase the overall heat dissipation area of ​​the integrated semiconductor device and improve the overall power density.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to an integrated semiconductor device and a packaging method. Background Art

[0002] In the semiconductor field, integrated semiconductor devices need to be applied in different scenarios, so the parameter requirements for integrated semiconductor devices also increase. Among them, high-power integrated semiconductor devices will generate high power and power consumption during operation, resulting in serious heating problems.

[0003] At present, a heat sink is usually added to the surface of the power module to cool the chip and circuit structure inside the integrated semiconductor device. However, when the integrated semiconductor device is a half-bridge module, it usually includes two quarter bridge arm structures. When the two bridge arm structures are integrated into a module of a fixed area, the chip and circuit are relatively concentrated, resulting in a smaller heat dissipation area, thereby limiting the overall power density. Summary of the invention

[0004] The present application provides an integrated semiconductor device and a packaging method, which can increase the overall heat dissipation area of ​​the integrated semiconductor device and improve the overall power density.

[0005] The present application provides an integrated semiconductor device, which includes: a half-bridge module, including two bridge arm structures connected to each other, the two bridge arm structures are arranged at intervals along a first direction, and each bridge arm structure includes a substrate, a cooling structure and a plurality of semiconductor chips, the plurality of semiconductor chips are arranged on the first surface of the substrate, and the cooling structure covers the second surface of the corresponding substrate for cooling the semiconductor chips; a packaging structure, connected between the two bridge arm structures and covering the first surface; a connecting terminal, the two bridge arm structures are conductively connected through the connecting terminal, and the connecting terminal extends from one side of the packaging structure to be conductively connected to an external circuit; wherein the first surface and the second surface are respectively located on both sides of the substrate in the first direction, the first surfaces of the two substrates are arranged close to each other, and the second surfaces of the two substrates are arranged far away from each other.

[0006] An integrated semiconductor device as above, wherein the substrate includes a conductive connection layer, an insulating layer and a bottom plate layer stacked along a first direction, the conductive connection layer and the bottom plate layer are both made of metal materials, the insulating layer is made of insulating material, the first surface is located on the side of the conductive connection layer away from the insulating layer, and the second surface is located on the side of the bottom plate layer away from the insulating layer; in the first direction, the thicknesses of the conductive connection layer, the insulating layer and the bottom plate layer of the two substrates are correspondingly equal, and the two conductive connection layers are symmetrically arranged in the first direction.

[0007] As above integrated semiconductor device, wherein each bridge arm structure has a power terminal, the conductive connection layer includes a conductive area and an output area which are separated from each other, the conductive area is conductively connected to the corresponding power terminal, and the power terminals of the two bridge arm structures extend from the same side of the packaging structure and are conductively connected to the external circuit, and the output areas of the two bridge arm structures are connected via a connecting terminal.

[0008] In the above integrated semiconductor device, the two power terminals are arranged at intervals in the first direction and the second direction, and the connection terminal and the power terminal are respectively arranged on two opposite sides of the integrated semiconductor device in the third direction.

[0009] As above, the integrated semiconductor device, wherein the bottom plate layer includes a first connection layer, a second connection layer, a third connection layer and a fourth connection layer stacked along a first direction, the first connection layer is connected to the insulating layer, the fourth connection layer is connected to the cooling structure, and in a plane perpendicular to the first direction, the projections of the first connection layer, the second connection layer and the fourth connection layer are all within the projection range of the third connection layer, and the circumferential edge of the second connection layer has a plurality of connection grooves spaced apart.

[0010] An integrated semiconductor device as above, wherein the connecting terminal includes an elastic connecting portion and an extension portion, the elastic connecting portion extends along a first direction and is telescopically arranged along the first direction, the two ends of the elastic connecting portion are respectively connected to the two bridge arm structures, one end of the extension portion is connected to the elastic connecting portion at an inclined angle, and the other end is conductively connected to the external circuit, and the extension portion is spaced apart from the two bridge arm structures in the first direction.

[0011] As above, the integrated semiconductor device further comprises: a support structure made of insulating material, the support structure and the connecting terminal are spaced apart and supported between the two bridge arm structures; a packaging structure is made of resin material, covering the plurality of semiconductor chips, the first surface, the support structure and part of the connecting terminals, and the surrounding side of the packaging structure also has a protruding spacing beam.

[0012] As above integrated semiconductor device, wherein the conductive connection layer also includes a driving connection area, the driving connection area is arranged separately from the conductive area and the output area, each semiconductor chip is connected to the driving connection area through a first connector, the driving connection area is conductively connected to the external circuit through a driving terminal, each semiconductor chip of one bridge arm structure is arranged in the output area and connected to the conductive area through a second connector; each semiconductor chip of the other bridge arm structure is arranged in the conductive area and connected to the output area through a second connector.

[0013] On the other hand, the present application also provides a packaging method for an integrated semiconductor device, wherein the packaging method is used to package the above-mentioned integrated semiconductor device, and the packaging method includes:

[0014] Arrange two bridge arm structures spaced apart from each other along a first direction, and arrange the semiconductor chips of the two bridge arm structures facing each other;

[0015] A supporting structure is provided between the two bridge arm structures;

[0016] A connecting terminal is arranged between the two bridge arm structures so that the connecting terminal is located at a position spaced apart from the supporting structure;

[0017] Injection molding is performed at the interval between the two bridge arm structures to form a packaging structure that wraps the semiconductor chip, the support structure and part of the connecting terminals.

[0018] The packaging method of the integrated semiconductor device as above, wherein before the step of providing two bridge arm structures spaced apart along the first direction, further comprises:

[0019] Separating the conductive connection layer of the bridge arm structure to form a conductive area, an output area and a driving connection area;

[0020] printing a sintering slurry on the conductive area or the output area;

[0021] The semiconductor chip is bonded to the sintering slurry and heated and sintered;

[0022] Conductively connecting the semiconductor chip to the output region or the conductive region;

[0023] Conductively connecting the semiconductor chip to the driving connection area;

[0024] A power terminal is arranged in the conductive area, and a driving terminal is arranged in the driving connection area to form a complete bridge arm structure.

[0025] The integrated semiconductor device of the present application includes a half-bridge module, a packaging structure and a connecting terminal. The half-bridge module includes two bridge arm structures that are connected to each other. The two bridge arm structures are arranged at intervals along a first direction. The bridge arm structure includes a substrate, a cooling structure and a plurality of semiconductor chips. In the bridge arm structure, the plurality of semiconductor chips and the cooling structure are respectively arranged on the first surface and the second surface on both sides of the substrate, and the first surfaces of the two half-bridge modules are close to each other, so that the semiconductor chips of the two half-bridge modules can be arranged toward the inside of the integrated semiconductor device. The connecting terminal is used to make a conductive connection between the semiconductor chips of the two half-bridge modules to form a complete half-bridge circuit, and the two bridge arm structures are packaged using a packaging structure so that the connecting terminal part extends out of the packaging structure to be connected to the external circuit as a common output end of the two bridge arm structures, thereby realizing the packaging of the entire half-bridge module.

[0026] In the overall packaging structure of the integrated semiconductor device, the semiconductor chips are packaged inside the packaging structure at intervals in the first direction, and the cooling structure is arranged on the two second surfaces that are not packaged, so that the multiple semiconductor chips of the respective bridge arm structures can be cooled respectively, thereby achieving the double-sided cooling effect for the half-bridge module. In addition, since the half-bridge module is divided into two bridge arm structures, half the number of semiconductor chips are arranged on each of the two bridge arm structures, which increases the unit heat dissipation area of ​​each semiconductor chip, further improves the cooling effect of the integrated semiconductor device, and thus improves the overall power density. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 An exploded view of a half-bridge module of an integrated semiconductor device according to an embodiment of the present application;

[0029] Figure 2 A schematic diagram of the connection of two bridge arm structures of the integrated semiconductor device according to an embodiment of the present application;

[0030] Figure 3 An isometric view of an integrated semiconductor device according to an embodiment of the present application;

[0031] Figure 4 A partial schematic diagram of a substrate of an integrated semiconductor device according to an embodiment of the present application;

[0032] Figure 5 A schematic diagram of the structure of a bottom plate layer of an integrated semiconductor device according to an embodiment of the present application;

[0033] Figure 6 A top view of a bottom plate layer of an integrated semiconductor device according to an embodiment of the present application;

[0034] Figure 7 A schematic diagram of one of the bridge arm structures of the integrated semiconductor device according to an embodiment of the present application after a semiconductor chip is installed;

[0035] Figure 8 A complete structural diagram of one of the bridge arm structures of the integrated semiconductor device according to an embodiment of the present application;

[0036] Fig. 9 A complete structural schematic diagram of another bridge arm structure of the integrated semiconductor device according to an embodiment of the present application;

[0037] Fig.10 A schematic diagram of the structure of the connection terminal of the integrated semiconductor device according to an embodiment of the present application;

[0038] Fig.11 A flowchart of a packaging method for an integrated semiconductor device according to an embodiment of the present application;

[0039] Fig.12 A schematic diagram of a substrate of one of the bridge arm structures of the integrated semiconductor device according to an embodiment of the present application;

[0040] Fig.13 A schematic diagram of one of the bridge arm structures of the integrated semiconductor device according to an embodiment of the present application after printing and sintering slurry;

[0041] Fig.14 It is a schematic diagram of a bridge arm structure of the integrated semiconductor device according to an embodiment of the present application after connecting a first connector and a second connector;

[0042] Fig.15 A circuit diagram of an integrated semiconductor device according to an embodiment of the present application;

[0043] Fig.16 A schematic diagram of the distance between the substrate and the power terminal of each bridge arm structure of the integrated semiconductor device according to an embodiment of the present application;

[0044] Fig.17 A schematic diagram of the current direction of one of the bridge arm structures of the integrated semiconductor device according to an embodiment of the present application;

[0045] Fig.18 A schematic diagram of the current direction of another bridge arm structure of the integrated semiconductor device according to an embodiment of the present application;

[0046] Fig.19 A schematic diagram of the internal current direction of the integrated semiconductor device according to an embodiment of the present application;

[0047] Fig. 20 A schematic structural diagram of a substrate of an integrated semiconductor device according to an embodiment of the present application;

[0048] Fig.21 A schematic structural diagram of another substrate of an integrated semiconductor device according to an embodiment of the present application.

[0049] Description of reference numerals:

[0050] 100, half-bridge module; 110, bridge arm structure; 200, packaging structure; 210, spacer beam; 300, connection terminal; 310, elastic connection part; 320, extension part; 400, support structure;

[0051] 10. substrate; 101. first surface; 102. second surface; 11. conductive connection layer; 111. conductive area; 112. output area; 113. drive connection area; 12. insulation layer; 13. bottom plate layer; 131. first connection layer; 132. second connection layer; 133. third connection layer; 134. fourth connection layer; 135. sealing area; 14. foolproof structure; 15. welding layer; 16. metal connection layer; 17. ceramic layer; 20. cooling structure; 30. semiconductor chip; 40. power terminal; 50. first connection member; 60. drive terminal; 70. second connection member;

[0052] D1, first distance; D2, second distance;

[0053] X, first direction; Y, second direction; Z, third direction. DETAILED DESCRIPTION

[0054] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0055] In the semiconductor field, high-power semiconductor devices usually generate high power and power consumption during operation, resulting in serious heating problems.

[0056] At present, in order to dissipate heat for parts such as chips in semiconductor devices, a heat dissipation device is usually added to the surface of the semiconductor device, such as an air cooling structure, a water cooling structure, etc., and single-sided cooling or double-sided cooling is used to dissipate heat. However, due to the high density of chips and circuit structures inside semiconductor devices, especially in semiconductor devices such as half-bridge modules that require multiple circuits, the chips and circuits are more concentrated, resulting in a smaller overall heat dissipation area, thereby limiting the power density of the semiconductor device. Therefore, the embodiment of the present application provides an integrated semiconductor device based on the characteristics of the semiconductor device of the half-bridge circuit, which ensures the overall heat dissipation area of ​​the integrated semiconductor device, thereby ensuring the heat dissipation effect for the chips and circuits, and making the overall power density of the integrated semiconductor device higher.

[0057] like Figures 1 to 21As shown, an embodiment of the present application provides an integrated semiconductor device, which includes: a half-bridge module 100, including two bridge arm structures 110 connected to each other, the two bridge arm structures 110 are arranged at intervals along a first direction X, and the bridge arm structures 110 each include a substrate 10, a cooling structure 20 and a plurality of semiconductor chips 30, the plurality of semiconductor chips 30 are arranged on a first surface 101 of the substrate 10, and the cooling structure 20 covers the second surface 102 of the corresponding substrate 10 for cooling the semiconductor chips 30; a packaging structure 200, connected between the two bridge arm structures 110 and covering the first surface 101; a connecting terminal 300, the two bridge arm structures 110 are conductively connected through the connecting terminal 300, and the connecting terminal 300 extends from one side of the packaging structure 200 to be conductively connected to an external circuit; wherein the first surface 101 and the second surface 102 are respectively located on both sides of the substrate 10 in the first direction X, the first surfaces 101 of the two substrates 10 are arranged close to each other, and the second surfaces 102 of the two substrates 10 are arranged far away from each other.

[0058] It should be noted that the half-bridge module 100 can be divided into two bridge arm structures 110, and both bridge arm structures 110 are quarter bridge arms, namely, an upper bridge arm structure and a lower bridge arm structure. Fig. 9 It is the upper arm structure. Figure 8 The lower bridge arm structure is a semiconductor chip 30 of the two bridge arm structures 110, and a complete half-bridge circuit can be formed by connecting the semiconductor chips 30 of the two bridge arm structures 110. Moreover, each bridge arm structure 110 has a plurality of semiconductor chips 30, and the number of semiconductor chips 30 of the two bridge arm structures 110 is equal, so the half-bridge module 100 can form a plurality of half-bridge circuits. In the embodiment of the present application, the number of semiconductor chips 30 is not specifically limited.

[0059] In a specific implementation, the integrated semiconductor device of the embodiment of the present application includes a half-bridge module 100, a packaging structure 200 and a connection terminal 300. The half-bridge module 100 includes two bridge arm structures 110 connected to each other. The two bridge arm structures 110 are arranged at intervals along a first direction X. The bridge arm structure 110 includes a substrate 10, a cooling structure 20 and a plurality of semiconductor chips 30. In the bridge arm structure 110, the plurality of semiconductor chips 30 and the cooling structure 20 are respectively arranged on a first surface 101 and a second surface 102 on both sides of the substrate 10, and the two half-bridge The first surfaces 101 of the modules 100 are close to each other, so that the semiconductor chips 30 of the two half-bridge modules 100 can be arranged toward the inside of the integrated semiconductor device. The connecting terminals 300 are used to make conductive connections between the semiconductor chips 30 of the two half-bridge modules 100 to form a complete half-bridge circuit. The two bridge arm structures 110 are packaged using a packaging structure 200, so that the connecting terminals 300 partially extend out of the packaging structure 200 and are connected to an external circuit, serving as a common output terminal of the two bridge arm structures 110, thereby realizing the packaging of the entire half-bridge module.

[0060] After the two bridge arm structures 110 are packaged using the packaging structure 200, the semiconductor chips 30 of the two bridge arm structures 110 are conductively connected only through the connecting terminals 300. Therefore, the packaging structure 200 between the semiconductor chips 30 of the two bridge arm structures 110 has an electrical isolation effect, thereby avoiding the phenomenon of the semiconductor chips 30 being penetrated, resulting in the inability to form a complete half-bridge circuit.

[0061] In the overall packaging structure of the integrated semiconductor device, the semiconductor chips 30 are packaged inside the packaging structure 200 at intervals in the first direction X, and the cooling structure 20 is arranged on the two unpackaged second surfaces 102, which can cool the multiple semiconductor chips 30 of the respective bridge arm structures 110, respectively, and achieve the double-sided cooling effect of the half-bridge module 100. In addition, since the half-bridge module 100 is divided into two bridge arm structures 110, half the number of semiconductor chips 30 are arranged on each of the two bridge arm structures 110, the unit heat dissipation area of ​​each semiconductor chip 30 is increased, and the cooling effect of the integrated semiconductor device is further improved, thereby improving the overall power density.

[0062] Furthermore, the stacking design of the upper and lower bridge arm structures 110 of the half-bridge module 100 increases the distance between the semiconductor chips 30 of the two bridge arm structures 110 and reduces the concentration of the circuits used to connect the semiconductor chips 30, thereby effectively reducing the stray inductance in the integrated semiconductor device.

[0063] like Figure 4 As shown, an integrated semiconductor device of an embodiment of the present application, wherein the substrate 10 includes a conductive connection layer 11, an insulating layer 12 and a bottom plate layer 13 stacked along a first direction X, the conductive connection layer 11 and the bottom plate layer 13 are both made of metal materials, the insulating layer 12 is made of insulating material, the first surface 101 is located on the side of the conductive connection layer 11 away from the insulating layer 12, and the second surface 102 is located on the side of the bottom plate layer 13 away from the insulating layer 12.

[0064] In a specific implementation, the semiconductor chip 30 is disposed on the first surface 101 , ie, the surface of the conductive connection layer 11 , so that the semiconductor chip 30 and the conductive connection layer 11 can be conductively connected by direct contact or connecting wires, thereby forming a complete half-bridge circuit.

[0065] The insulating layer 12 is arranged between the conductive connection layer 11 and the bottom plate layer 13, so that there is a certain insulation distance between the two, thereby avoiding conductive connection between the conductive connection layer 11 and the bottom plate layer 13, and avoiding leakage of the conductive connection layer 11 to the cooling structure 20 connected to the bottom plate layer 13, thereby ensuring the overall safety of the integrated semiconductor device and avoiding external influences on the half-bridge circuit.

[0066] Specifically, the area of ​​the insulating layer 12 is larger than the area of ​​the conductive connection layer 11, so that the conductive connection layer 11 can have a sufficient layout area. When the cooling structure 20 dissipates heat, heat is exchanged with the conductive connection layer 11 through the insulating layer 12. The larger area of ​​the insulating layer 12 can ensure the heat exchange effect with the conductive connection layer 11, thereby ensuring the overall power density of the bridge arm structure 110.

[0067] In the first direction X, the thicknesses of the conductive connection layer 11, the insulating layer 12 and the bottom plate layer 13 of the two substrates 10 are correspondingly equal, ensuring the consistency of the two substrates 10, so that the currents passing through the two bridge arm structures 110 can be kept consistent to ensure the effect of the half-bridge circuit; and the two conductive connection layers 11 are symmetrically arranged in the first direction X, and the currents passing through the two bridge arm structures 110 are in opposite directions, thereby forming two loops with opposite current directions in the spatial structure of the integrated semiconductor device to produce an inductive coupling effect.

[0068] It should be noted that if Fig. 20 As shown, the substrate 10 in the embodiment of the present application is an IMS (Insulated Metal Substrate, metal-based insulating substrate), such as Fig.21 As shown, a DBC (Direct Bond Copper) structure can also be selected, that is, a copper layer is directly bonded on the surface of the ceramic layer to realize the setting of the substrate structure. When the substrate 10 adopts a DBC board, as shown in FIG. Fig.21 As shown, it includes a base plate layer 13, a welding layer 15, a metal connection layer 16, a ceramic layer 17 and a conductive connection layer 11 which are stacked.

[0069] In the embodiment of the present application, the two bridge arm structures 110 of the half-bridge module 100 have the same area of ​​the main circuit for connecting the semiconductor chip 30, that is, the overall area or conductive area of ​​the conductive connection layer 11 is the same, thereby ensuring that the losses between the two bridge arm structures 110 are the same; and the cooling structures 20 provided on the two second surfaces 102 are also exactly the same, which can ensure that the cooling efficiency between the two bridge arm structures 110 is the same, thereby ensuring the consistency of the temperature between the two.

[0070] like Figure 7 and Figure 8As shown, an integrated semiconductor device of an embodiment of the present application, wherein each bridge arm structure 110 has a power terminal 40, the conductive connection layer 11 includes a conductive area 111 and an output area 112 that are separated from each other, the conductive area 111 is conductively connected to the corresponding power terminal 40, and the power terminals 40 of the two bridge arm structures 110 extend from the same side of the packaging structure 200 and are conductively connected to the external circuit, and the output areas 112 of the two bridge arm structures 110 are connected via a connecting terminal 300.

[0071] In a specific implementation, one end of the power terminal 40 of the bridge arm structure 110 is connected to the conductive area 111, and the other end extends from the side of the package structure 200 to be conductively connected to the external circuit. The connecting terminal 300 can be connected to the output areas 112 of the two bridge arm structures 110 respectively, so that the output areas 112 of the two bridge arm structures 110 can be conductively connected, and the connecting terminal 300 can also extend from the side of the package structure 200 and be conductively connected to the external circuit. In the half-bridge circuit of the integrated semiconductor device, there are two current paths between the two bridge arm structures 110 and the connecting terminal 300, such as Fig.18 As shown, one line is input from the power terminal 40 of one of the bridge arm structures 110 and output from the connection terminal 300; Fig.17 As shown, the other one is inputted by the connection terminal 300 and outputted by the power terminal 40 of another bridge arm structure 110, thereby forming a circuit structure of a complete half-bridge circuit.

[0072] And, if Fig.19 As shown, the power terminals 40 of the two bridge arm structures 110 extend from the same side of the packaging structure 200. Combined with the directions of the two current paths mentioned above, in the specific structure of the integrated semiconductor device, the currents passing through the two bridge arm structures 110 are in opposite directions, thereby generating an inductive coupling effect, reducing the inductance of the integrated semiconductor device, and because the two bridge arm structures 110 are spaced apart in the first direction X, the opposite currents are spaced a certain distance apart, further reducing the inductance of the integrated semiconductor device, thereby improving the overall efficiency of the integrated semiconductor device.

[0073] like Figure 2 and Figure 3 As shown, in the integrated semiconductor device of the embodiment of the present application, two power terminals 40 are arranged at intervals in the first direction X and the second direction Y, and the connection terminal 300 and the power terminal 40 are respectively arranged on opposite sides of the integrated semiconductor device in the third direction Z.

[0074] In a specific implementation, the two power terminals 40 are spaced apart in the first direction X and the second direction Y, so that the two power terminals 40 are arranged at diagonal positions, ensuring that there is sufficient creepage distance and electrical clearance between the two to avoid conductive connection between the two. In addition, when the volume of the power terminal 40 needs to be increased, the gap between the two can also ensure that the power terminal 40 has sufficient installation and setting space.

[0075] Specifically, Fig.16 As shown, along the first direction X, the first distance D1 and the second distance D2 between the two power terminals 40 and their respective corresponding substrates 10 are equal, thereby ensuring that the creepage distance and the electrical clearance between the power terminals 40 and the conductive connection layer 11 are equal, ensuring the parameter consistency of the two bridge arm structures 110, and thus ensuring the working effect of the half-bridge circuit.

[0076] The connection terminal 300 and the power terminal 40 are respectively disposed on two opposite sides of the integrated semiconductor device in the third direction Z, so that the connection terminal 300 and the power terminal 40 can be kept at the farthest distance from each other, thereby avoiding mutual influence between the connection terminal 300 and the power terminal 40 .

[0077] Specifically, Figure 2 As shown, the distances between the connecting terminal 300 and the substrates 10 of the two bridge arm structures 110 are equal, so that the creepage distances and electrical clearances between the connecting terminal 300 and the two bridge arm structures 110 are equal, thereby further ensuring the parameter consistency of the two bridge arm structures 110 .

[0078] In the embodiment of the present application, the two bridge arm structures 110 are respectively an upper bridge arm structure and a lower bridge arm structure. The upper bridge arm structure is arranged above the package structure 200 in the first direction X, and its corresponding power terminal 40 is a P+ terminal. The lower bridge arm structure is arranged below the package structure 200 in the first direction X, and its corresponding power terminal 40 is an N-terminal. In order to distinguish the two bridge arm structures 110, the substrate 10 of the upper bridge arm structure with the P+ terminal has an anti-fool structure 14, and the anti-fool structure 14 is a corner of the substrate 10, and the anti-fool structure 14 is chamfered, and the other corners of the substrate 10 are rounded structures, while the corners of the substrate 10 of the lower bridge arm structure with the N-terminal are all rounded structures. Therefore, when conducting a conductive connection with an external circuit, the two power terminals 40 can be distinguished by the anti-fool structure 14.

[0079] like Figure 5As shown, an integrated semiconductor device of an embodiment of the present application, wherein the base layer 13 includes a first connection layer 131, a second connection layer 132, a third connection layer 133 and a fourth connection layer 134 stacked along a first direction X, the first connection layer 131 is connected to the insulating layer 12, the fourth connection layer 134 is connected to the cooling structure 20, and in a plane perpendicular to the first direction X, the projections of the first connection layer 131, the second connection layer 132 and the fourth connection layer 134 are all within the projection range of the third connection layer 133, and the circumferential edge of the second connection layer 132 has a plurality of connection grooves spaced apart.

[0080] In a specific implementation, in a plane perpendicular to the first direction X, the projections of the first connection layer 131, the second connection layer 132 and the fourth connection layer 134 are all within the projection range of the third connection layer 133, that is, the area of ​​the third connection layer 133 is larger than the areas of the first connection layer 131, the second connection layer 132 and the fourth connection layer 134, and the first connection layer 131, the second connection layer 132 and the fourth connection layer 134 are all within the coverage range of the third connection layer 133. In the process of encapsulating the half-bridge module 100 and forming the encapsulation structure 200, the unplasticized encapsulation structure 200 covers and combines with the edges of the first connection layer 131 and the second connection layer 132, and will not exceed the area range of the third connection layer 133. Therefore, the third connection layer 133 prevents the unplasticized encapsulation structure 200 from overflowing. In addition, as Figure 6 As shown, an annular sealing area 135 can be formed between the edge of the fourth connecting layer 134 and the edge of the third connecting layer 133, and a sealing structure such as a sealing ring can be placed on this sealing area to seal the cooling structure 20 to prevent cooling water from overflowing during the cooling process of the cooling structure 20.

[0081] The circumferential edge of the second connection layer 132 has a plurality of spaced connection grooves. When the packaging structure 200 is combined with the circumferential edge of the second connection layer 132, at least a portion of the connection grooves can be formed in the connection grooves. The groove walls of the connection grooves can restrict the packaging structure 200, making the connection between the packaging structure 200 and the second connection layer 132 more secure, thereby achieving stable packaging of the two bridge arm structures 110 by the packaging structure 200.

[0082] Specifically, the bottom plate layer 13 and the cooling structure 20 are both made of copper metal material. The bottom plate layer 13 and the cooling structure 20 are an integrated structure, which is made by an integrated molding process. This manufacturing process can not only ensure the connection strength between the layers of the bottom plate layer 13, but also ensure the connection strength between the bottom plate layer 13 and the cooling structure 20, thereby achieving stable cooling of the bottom plate layer 13 and the semiconductor chip 30 by the cooling structure 20.

[0083] The cooling structure 20 includes but is not limited to water-cooling structures such as water-cooling pin fins. Multiple circular water-cooling pin fins can be arranged in an array within the coverage area of ​​the fourth connecting layer 134, and the sealing area 135 is arranged around the multiple water-cooling pin fins to facilitate the setting of a sealing ring for sealing.

[0084] like Fig.10 As shown, an integrated semiconductor device of an embodiment of the present application, wherein the connecting terminal 300 includes an elastic connecting portion 310 and an extending portion 320, the elastic connecting portion 310 extends along a first direction X and is telescopically arranged along the first direction X, two ends of the elastic connecting portion 310 are respectively connected to two bridge arm structures 110, one end of the extending portion 320 is connected to the elastic connecting portion 310 at an inclined angle, and the other end is conductively connected to an external circuit, and the extending portion 320 is spaced apart from the two bridge arm structures 110 in the first direction X.

[0085] In a specific implementation, the two ends of the elastic connection part 310 of the connecting terminal 300 are respectively connected to the two bridge arm structures 110. When the two bridge arm structures 110 are connected to the elastic connection part 310 and subsequently packaged, the interval can be adjusted by the elastic deformation of the elastic connection part 310 in the first direction X, so that after packaging, the parallelism between the connecting terminal 300, the power terminal 40 and the two bridge arm structures 110 meets the requirements, thereby ensuring that the integrated semiconductor device meets the working requirements.

[0086] Specifically, the extension portion 320 is vertically connected to the middle portion of the elastic connection portion 310 in the first direction X, so that the distance between the extension portion 320 and the two bridge arm structures 110 is equal, thereby ensuring parameter consistency of the two bridge arm structures 110 .

[0087] like Figure 1 As shown, the integrated semiconductor device of an embodiment of the present application, wherein the integrated semiconductor device also includes: a support structure 400, made of an insulating material, the support structure 400 and the connecting terminal 300 are arranged at an interval and supported between the two bridge arm structures 110; the packaging structure 200 is made of a resin material, covering multiple semiconductor chips 30, the first surface 101, the support structure 400 and part of the connecting terminal 300, and the surrounding side of the packaging structure 200 also has a protruding spacing beam 210.

[0088] In a specific implementation, the support structure 400 is made of an insulating material. When the packaging structure 200 is used to package the two bridge arm structures 110, the support structure 400 and the connecting terminal 300 can be spaced apart to achieve two-point support for the two bridge arm structures 110, thereby avoiding the situation where there is only one supporting point between the two bridge arm structures 110, resulting in the two bridge arm structures 110 being unable to be arranged in parallel. Therefore, the supporting function of the support structure 400 ensures the packaging stability of the integrated semiconductor device.

[0089] Specifically, the support structure 400 is supported on the surface of the conductive connection layer 11 and is disposed away from the semiconductor chip 30 to prevent the support force thereof from damaging the semiconductor chip 30 .

[0090] The packaging structure 200 has a plurality of spacer beams 210, which are arranged on the same side as the power terminal 40, and are arranged on both sides of the power terminal 40 in the first direction X, for isolating the two power terminals 40, and the power terminal 40 from the substrate 10, thereby increasing the creepage distance and electrical clearance between the power terminals 40.

[0091] like Figure 7 and Figure 8 As shown, an integrated semiconductor device of an embodiment of the present application, wherein the conductive connection layer 11 also includes a driving connection area 113, the driving connection area 113 is arranged separately from the conductive area 111 and the output area 112, each semiconductor chip 30 is connected to the driving connection area 113 through a first connector 50, and the driving connection area 113 is conductively connected to the external circuit through a driving terminal 60, wherein each semiconductor chip 30 of one bridge arm structure 110 is arranged in the output area 112 and connected to the conductive area 111 through a second connector 70; each semiconductor chip 30 of another bridge arm structure 110 is arranged in the conductive area 111 and connected to the output area 112 through a second connector 70.

[0092] In a specific implementation, each semiconductor chip 30 of the upper bridge arm structure of the two bridge arm structures 110 is arranged in the conductive area 111, so as to be directly conductively connected to the power terminal 40 through the conductive area 111, and the semiconductor chip is connected to the driving connection area 113 through the first connector 50 and connected to the output area 112 through the second connector 70. When the external circuit is driven through the driving terminal 60 of the driving connection area 113, the current can flow from the semiconductor chip 30 to the connection terminal 300 of the output area 112 through the second connector 70, thereby realizing the connection of the upper bridge circuit; each semiconductor chip 30 of the lower bridge arm structure is arranged in the output area 112, so as to be directly conductively connected to the connection terminal 300 through the output area 112, and the semiconductor chip is connected to the driving connection area 113 through the first connector 50 and connected to the conductive area 111 through the second connector 70. When the external circuit is driven through the driving terminal 60 of the driving connection area 113, the current can flow from the semiconductor chip 30 to the power terminal of the conductive area 111 through the second connector 70, thereby realizing the connection of the lower bridge circuit.

[0093] Specifically, each bridge arm structure 110 includes two spaced-apart driving connection areas 113 and two driving terminals 60, the two driving terminals 60 are respectively connected to the two driving connection areas 113, the two driving terminals 60 are respectively a G terminal and an S terminal, one driving connection area 113 is semi-surrounded by the other driving connection area 113 arranged in a straight structure, so as to facilitate connection with the semiconductor chips 30 on both sides, and the output area 112 is surrounded by the driving connection area 113, and the conductive area 111 is surrounded by the output area 112. Such an area arrangement can provide sufficient installation space for the semiconductor chip 30 and facilitate the connection of the semiconductor chip 30 through the first connector 50 and the second connector 70.

[0094] like Fig.11 As shown, an embodiment of the present application further provides a packaging method for an integrated semiconductor device, wherein the packaging method is used to package the above-mentioned integrated semiconductor device, and the packaging method includes:

[0095] S110, disposing two bridge arm structures 110 spaced apart along the first direction X, and disposing the semiconductor chips 30 of the two bridge arm structures 110 facing each other, that is, disposing the first surfaces 101 of the two substrates 10 facing each other, and disposing the second surfaces 102 of the two substrates 10 facing each other;

[0096] S120, disposing a support structure 400 between the two bridge arm structures 110, so that two ends of the support structure 400 are respectively supported on the conductive connection layers 11 of the upper and lower substrates 10 and avoid the semiconductor chip 30;

[0097] S130, arranging a connection terminal 300 between the two bridge arm structures 110, so that the connection terminal 300 is located at a position spaced apart from the support structure 400, so that the two bridge arm structures 110 can have two supporting points when the connection terminals 300 are connected, and the two bridge arm structures 110 can be arranged in parallel; and the output areas 112 of the two bridge arm structures 110 are respectively connected to the two ends of the elastic connection part 310 of the connection terminal 300;

[0098] S140. Injection molding is performed at the interval between the two bridge arm structures 110 to form a packaging structure 200 that wraps the semiconductor chip 30, the support structure 400 and part of the connecting terminals 300. When wrapping the above structures, the packaging structure 200 can cover the first surface 101 to the third connecting layer 133 of the substrate 10. The third connecting layer 133 has the effect of preventing the packaging structure 200 from overflowing, thereby completing the complete packaging of the packaging structure.

[0099] Among them, the support structure 400 can be made of insulating material, and it does not need to be taken out separately during packaging to ensure the support effect for the two bridge arm structures 110, thereby ensuring the structural stability of the overall packaging structure and avoiding the two bridge arm structures 110 from being unable to be arranged in parallel.

[0100] In a specific implementation, the packaging method of the integrated semiconductor device of the present application is used to package an integrated semiconductor device, wherein the integrated semiconductor device includes a half-bridge module 100, a packaging structure 200 and a connecting terminal 300, wherein the half-bridge module 100 includes two bridge arm structures 110 connected to each other, wherein the two bridge arm structures 110 are arranged at intervals along a first direction X, wherein the bridge arm structure 110 includes a substrate 10, a cooling structure 20 and a plurality of semiconductor chips 30, wherein the plurality of semiconductor chips 30 and the cooling structure 20 are respectively arranged on a first surface 101 and a second surface 102 on both sides of the substrate 10. The first surfaces 102 of the two half-bridge modules 100 are close to each other, so that the semiconductor chips 30 of the two half-bridge modules 100 can be arranged toward the inside of the integrated semiconductor device. The connecting terminals 300 are used to make conductive connections between the semiconductor chips 30 of the two half-bridge modules 100 to form a complete half-bridge circuit. The packaging structure 200 is used to package the two bridge arm structures 110, so that the connecting terminals 300 partially extend out of the packaging structure 200 and are connected to the external circuit, serving as the common output terminal of the two bridge arm structures 110, thereby realizing the packaging of the overall half-bridge module.

[0101] In the overall packaging structure of the integrated semiconductor device, the semiconductor chips 30 are packaged inside the packaging structure 200 at intervals in the first direction X, and the cooling structure 20 is arranged on the two unpackaged second surfaces 102, which can cool the multiple semiconductor chips 30 of the respective bridge arm structures 110, respectively, and achieve the double-sided cooling effect of the half-bridge module 100. In addition, since the half-bridge module 100 is divided into two bridge arm structures 110, half the number of semiconductor chips 30 are arranged on each of the two bridge arm structures 110, the unit heat dissipation area of ​​each semiconductor chip 30 is increased, and the cooling effect of the integrated semiconductor device is further improved, thereby improving the overall power density.

[0102] The packaging method of the integrated semiconductor device of the embodiment of the present application, before the step of providing two bridge arm structures 110 spaced apart along the first direction X, further includes:

[0103] like Fig.12 As shown, the conductive connection layer 11 of the separated bridge arm structure 110 forms a conductive area 111, an output area 112 and a driving connection area 113, wherein the conductive area 111 surrounds the output area 112, the output area 112 surrounds the driving connection area 113, and the driving connection area 113 is divided into two areas, respectively used to connect two driving terminals 60;

[0104] like Fig.13 As shown, sintering paste is printed on the conductive area 111 or the output area 112 to provide a mounting basis for the installation of the semiconductor chip 30 and the conductive connection with the two areas, wherein the upper bridge arm structure prints sintering paste on the conductive area 111, and the lower bridge arm structure prints sintering paste on the output area 112;

[0105] like Figure 7 As shown, the semiconductor chip 30 is bonded to the sintering paste and heated and sintered;

[0106] like Fig.14 As shown, the semiconductor chip 30 is conductively connected to the output region 112 or the conductive region 111, wherein the upper bridge arm structure is conductively connected to the output region 112 via the second connector 70, and the lower bridge arm structure is conductively connected to the conductive region 111 via the second connector 70;

[0107] like Fig.14 As shown, the semiconductor chip 30 is conductively connected to the driving connection area 113, and the conductive connection is connected through the first connection member 50;

[0108] like Figure 8 As shown, a power terminal 40 is disposed in the conductive area 111 , and a driving terminal 60 is disposed in the driving connection area 113 , so as to form a complete bridge arm structure 110 .

[0109] The first connector 50 and the second connector 70 may be welded copper clips or bonded wires, and the power terminal 40 , the drive terminal 60 and the connection terminal 300 are connected by ultrasonic welding.

[0110] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0111] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. An integrated semiconductor device, characterized in that: include: A half-bridge module, comprising two bridge arm structures connected to each other, the two bridge arm structures being arranged at intervals along a first direction, the bridge arm structures each comprising a substrate, a cooling structure and a plurality of semiconductor chips, the plurality of semiconductor chips being arranged on a first surface of the substrate, the cooling structure covering a second surface corresponding to the substrate, and being used to cool the semiconductor chips; A packaging structure connected between the two bridge arm structures and covering the first surface; A connecting terminal, wherein the two bridge arm structures are conductively connected to each other through the connecting terminal, and the connecting terminal extends from one side of the packaging structure to be conductively connected to an external circuit, the connecting terminal comprises an elastic connecting portion and an extending portion, the elastic connecting portion extends along the first direction and is telescopically arranged along the first direction, two ends of the elastic connecting portion are respectively connected to the two bridge arm structures, one end of the extending portion is connected to the elastic connecting portion at an inclined angle, and the other end is conductively connected to an external circuit, and the extending portion is spaced apart from the two bridge arm structures in the first direction; The first surface and the second surface are respectively located on two sides of the substrate in the first direction, the first surfaces of the two substrates are arranged close to each other, and the second surfaces of the two substrates are arranged far from each other.

2. The integrated semiconductor device according to claim 1, characterized in that: The substrate comprises a conductive connection layer, an insulating layer and a bottom plate layer stacked along a first direction, the conductive connection layer and the bottom plate layer are both made of metal materials, the insulating layer is made of insulating material, the first surface is located on a side of the conductive connection layer away from the insulating layer, and the second surface is located on a side of the bottom plate layer away from the insulating layer; In the first direction, the thicknesses of the conductive connection layer, the insulating layer and the bottom plate layer of the two substrates are correspondingly equal, and the two conductive connection layers are symmetrically arranged in the first direction.

3. The integrated semiconductor device according to claim 2, characterized in that: Each of the bridge arm structures has a power terminal, and the conductive connection layer includes a conductive area and an output area that are separated from each other. The conductive area is conductively connected to the corresponding power terminal, and the power terminals of the two bridge arm structures extend from the same side of the packaging structure and are conductively connected to the external circuit, and the output areas of the two bridge arm structures are connected through the connecting terminal.

4. The integrated semiconductor device according to claim 3, characterized in that: The two power terminals are arranged at intervals in the first direction and the second direction, and the connection terminal and the power terminal are respectively arranged on two opposite sides of the integrated semiconductor device in the third direction.

5. The integrated semiconductor device according to claim 2, characterized in that: The bottom plate layer includes a first connection layer, a second connection layer, a third connection layer and a fourth connection layer stacked along a first direction, the first connection layer is connected to the insulating layer, the fourth connection layer is connected to the cooling structure, and in a plane perpendicular to the first direction, the projections of the first connection layer, the second connection layer and the fourth connection layer are all within the projection range of the third connection layer, and the circumferential edge of the second connection layer has a plurality of connection grooves arranged at intervals.

6. The integrated semiconductor device according to claim 1, characterized in that The integrated semiconductor device further comprises: A support structure, made of insulating material, the support structure is spaced apart from the connecting terminal and supported between the two bridge arm structures; The packaging structure is made of resin material, covering the plurality of semiconductor chips, the first surface, the support structure and part of the connection terminals. The peripheral side of the packaging structure also has protruding spacing beams.

7. The integrated semiconductor device according to claim 3, characterized in that The conductive connection layer further includes a driving connection area, which is separated from the conductive area and the output area, each of the semiconductor chips is connected to the driving connection area through a first connection member, and the driving connection area is conductively connected to an external circuit through a driving terminal. The semiconductor chips of one of the bridge arm structures are arranged in the output area and connected to the conductive area through a second connecting member; the semiconductor chips of the other bridge arm structure are arranged in the conductive area and connected to the output area through the second connecting member.

8. A method for packaging an integrated semiconductor device, characterized in that: For packaging an integrated semiconductor device as claimed in any one of claims 1 to 7, the packaging method comprising: Arrange two bridge arm structures spaced apart from each other along a first direction, and arrange the semiconductor chips of the two bridge arm structures facing each other; A supporting structure is provided between the two bridge arm structures; Disposing a connecting terminal between the two bridge arm structures so that the connecting terminal is located at a position spaced apart from the supporting structure; Injection molding is performed at the interval between the two bridge arm structures to form a packaging structure that wraps around the semiconductor chip, the support structure and part of the connecting terminals.

9. The packaging method of an integrated semiconductor device according to claim 8, characterized in that: Before the step of providing two bridge arm structures spaced apart along the first direction, the method further includes: Separating the conductive connection layer of the bridge arm structure to form a conductive area, an output area and a driving connection area; printing a sintering slurry on the conductive area or the output area; The semiconductor chip is bonded to the sintering slurry and heated and sintered; Conductively connecting the semiconductor chip to the output region or the conductive region; Conductively connecting the semiconductor chip to the driving connection area; A power terminal is arranged in the conductive area, and a driving terminal is arranged in the driving connection area to form a complete bridge arm structure.

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