Semiconductor package and method of manufacturing the same

Abstract

The invention provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a substrate having a lower substrate surface and an upper substrate surface; a first interposer attached on the upper substrate surface; at least one first electronic component mounted on the first interposer and electrically connected to the first interposer; a second interposer disposed over the at least one first electronic component, where the second interposer has a recessed portion in which the at least one first electronic component is accommodated and a protruding portion mounted on the upper substrate surface; and at least one second electronic component mounted on the second interposer and electrically connected to the second interposer.

Description

Technical Field

[0001] The present application relates generally to semiconductor technology, and more particularly to a semiconductor package and a method of manufacturing the same. Background Art

[0002] As consumers want their electronic devices to be smaller, faster, and higher performing, and as more and more functions are packed into a single device, the semiconductor industry continues to face the challenge of complex integration. One solution is the System-in-Package (SiP). A SiP is a functional electronic system or subsystem that contains two or more heterogeneous semiconductor dies, such as logic chips, memories, integrated passive devices (IPDs), RF filters, sensors, heat sinks, or antennas, in a single package. Recently, SiPs have used double-sided molding (DSM) technology to further shrink the overall package size. However, it has been found that the package size still increases, and / or significant signal loss occurs.

[0003] Therefore, the structural arrangement of SiP needs to be further improved. Summary of the invention

[0004] An object of the present application is to provide a semiconductor package with less signal loss and reduced package size.

[0005] According to one aspect of an embodiment of the present application, a semiconductor package is provided. The semiconductor package may include: a substrate having a lower substrate surface and an upper substrate surface; a first interposer attached to the upper substrate surface; at least one first electronic component mounted on the first interposer and electrically connected to the first interposer; a second interposer disposed above the at least one first electronic component, wherein the second interposer has a recessed portion and a protruding portion, the at least one first electronic component is accommodated in the recessed portion, and the protruding portion is mounted on the upper substrate surface; and at least one second electronic component mounted on the second interposer and electrically connected to the second interposer.

[0006] According to another aspect of an embodiment of the present application, a method for forming a semiconductor package is provided. The method may include: providing a substrate having a lower substrate surface and an upper substrate surface; attaching a first interposer on the upper substrate surface; mounting at least one first electronic component on the first interposer, the at least one first electronic component being electrically connected to the first interposer; mounting a second interposer above the at least one first electronic component, wherein the second interposer has a recessed portion and a protruding portion, the at least one first electronic component being accommodated in the recessed portion, and the protruding portion being mounted on the upper substrate surface; and mounting at least one second electronic component on the second interposer, the at least one second electronic component being electrically connected to the second interposer.

[0007] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory and do not limit the present invention. In addition, the accompanying drawings, which are incorporated in this specification and constitute a part of this specification, illustrate embodiments of the present invention and are used together with the description to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings cited herein form part of the specification. The features shown in the drawings only illustrate some embodiments of the present application, rather than all embodiments of the present application, unless the specific implementation mode clearly indicates otherwise, and the reader of this specification should not make an inference to the contrary.

[0009] Figure 1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present application.

[0010] Figure 2 is a cross-sectional view showing a semiconductor package according to another embodiment of the present application.

[0011] Figure 3 is a cross-sectional view showing a semiconductor package according to another embodiment of the present application.

[0012] Figure 4 is a cross-sectional view showing a semiconductor package according to another embodiment of the present application.

[0013] FIG. 5A to FIG. 5J are cross-sectional views showing respective steps of a method for manufacturing a semiconductor package according to an embodiment of the present application.

[0014] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0015] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of the description. The accompanying drawings illustrate specific exemplary embodiments in which the present application can be practiced. The detailed description including the accompanying drawings describes these embodiments in sufficient detail to enable a person skilled in the art to practice the present application. A person skilled in the art may further utilize other embodiments of the present application and make logical, mechanical and other changes without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0016] In this application, unless otherwise specifically stated, the use of the singular includes the plural. In this application, unless otherwise specified, the use of "or" means "and / or". In addition, the use of the term "includes" and other forms such as "includes" and "contains" is not restrictive. In addition, unless otherwise specifically stated, terms such as "element" or "component" cover both elements and components including one unit and elements and components including more than one subunit. In addition, the section headings used herein are for organizational purposes only and should not be interpreted as limiting the desired subject matter in any way.

[0017] As used herein, for ease of description, spatially relative terms such as "under," "below," "above," "above," "up," "upper," "lower," "left," "right," "vertical," "horizontal," "side," etc. may be used herein to describe the relationship of an element or feature to another element (or elements) or feature (or features) as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" another element or "coupled to" another element, the element may be directly connected to or coupled to another element, or there may be intermediate elements.

[0018] refer to Figure 1 , which shows a cross-sectional view of a semiconductor package 100 according to an embodiment of the present application.

[0019] like Figure 1 As shown in , the semiconductor package 100 may include a substrate 100 having an upper substrate surface 110a and a lower substrate surface 110b. At least one first interposer 122 is attached to the upper substrate surface 110a, and at least one first electronic component 125 is mounted on the first interposer 122 and electrically connected to the first interposer 122. A second interposer 130 is disposed above the at least one first electronic component 125. The second interposer 130 may have a recessed portion 130a and a protruding portion 130b, the at least one first electronic component 125 is accommodated in the recessed portion 130a, and the protruding portion 130b is mounted on the upper substrate surface 110a. In addition, at least one second electronic component 145 is mounted on the second interposer 130 and electrically connected to the second interposer 130. Since the first electronic component 125 is accommodated in the recessed portion 130a, the overall size of the semiconductor package 100 can be reduced. Furthermore, the first interposer 122 and the second interposer 130 may provide high connectivity for electronic components mounted thereon, and thus may improve integration density and performance of the semiconductor package 100 .

[0020] Specifically, substrate 110 may provide support and connectivity for electronic components and devices. As an example, substrate 110 may include a printed circuit board (PCB), a carrier substrate, a semiconductor substrate with electrical interconnects, or a ceramic substrate. However, substrate 110 is not limited to these examples. In some other examples, substrate 110 may include a laminate interposer, a strip interposer, a lead frame, or other suitable substrates.

[0021] In some embodiments, substrate 110 may include a plurality of interconnect structures. The interconnect structures may provide connectivity for electronic components mounted on substrate 110. The interconnect structures may define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically across substrate 110. For example, Figure 1 As shown in FIG. 1 , the interconnect structure may include a redistribution structure, and the redistribution structure may provide contact pads along the upper substrate surface 110 a and / or the lower substrate surface 110 b .

[0022] The first interposer 122 may be made of a semiconductor material, glass, or an organic material, in which a redistribution layer or wiring pattern is formed. Preferably, the first interposer 122 is a silicon-based interposer (also referred to as a silicon bridge). The first interposer 122 may be manufactured using any suitable IC manufacturing process and may provide a variety of advantages. For example, the first interposer 122 may support fine pitches of through silicon vias (TSVs) and traces for signal and power distribution, and may have a thermal expansion coefficient that can match the thermal expansion coefficient of a semiconductor die or chiplet that contacts the first interposer 122. For example, the first interposer 122 may include a semiconductor layer, a plurality of wiring patterns formed on the semiconductor layer, and a plurality of contact pads connected to the wiring patterns. The wiring pattern may include TSVs and traces with fine pitches. The contact pads may provide connectivity for electronic components mounted thereon.

[0023] Continue to refer Figure 1 , at least one first electronic component 125 is mounted on the first interposer 122 and is electrically connected to the first interposer 122 .

[0024] The at least one first electronic component 125 may include any of a variety of semiconductor dies, semiconductor packages, or discrete devices. For example, the at least one first electronic component 125 may include a digital signal processor (DSP), a microcontroller, a microprocessor, a network processor, a power management processor, an audio processor, a video processor, an RF circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, a memory controller, a memory device, an application-specific integrated circuit (ASIC), etc. In some embodiments, the at least one first electronic component 125 may be a small IC chip containing different well-defined functional subsets, and allows a variety of different architectures, different process nodes, and even dedicated silicon modules or intellectual property (IP) modules from different foundries to be integrated into a single package. The at least one first electronic component 125 may be mounted on the first interposer 122 by flip chip bonding or any other suitable surface mounting technology.

[0025] In a specific example, the at least one first electronic component 125 may include a central processing unit (CPU) and a high bandwidth memory (HBM). The CPU and the HBM are mounted on the first interposer 122 using corresponding solder bumps. Specifically, the CPU may overlap with a first portion of the first interposer 122, and the HBM may overlap with a second portion of the first interposer 122. Therefore, the CPU and the HBM may be electrically connected to each other via the contact pads of the first interposer 122 and the first wiring pattern. In addition, some terminals of the CPU and / or the HBM may be electrically connected to the contact pads formed on the upper substrate surface 110a via conductive bumps.

[0026] Further, the second interposer 130 is disposed above the at least one first electronic component 125. The second interposer 130 may also be made of a semiconductor material, glass, or an organic material, in which a redistribution layer or a wiring pattern is formed. Figure 1 In the example shown in , a plurality of redistribution layers 135 are formed in the second interposer 130, and contact pads may be provided along the upper and lower surfaces thereof. The first electronic component 125 is accommodated in the recessed portion 130a of the second interposer 130 so as to reduce the overall size of the semiconductor package 100. A plurality of conductive bumps (such as solder bumps, copper pillars, or electronic strip conductive structures) may be formed on the contact pads at the protruding portion 130b of the second interposer 130. Then, the second interposer 130 may be mounted on the upper substrate surface 110a via the plurality of conductive bumps, and may be electrically connected to the contact pads formed on the upper substrate surface 110a.

[0027] In some embodiments, Figure 1, a first encapsulant 120 is formed between the upper substrate surface 110a and the second interposer 130 to seal the first interposer 122 and the at least one first electronic component 125. The first encapsulant 120 may be made of, for example, epoxy molding compound (EMC) or polyamide compound, and may provide mechanical protection, environmental protection, and hermetic sealing for electronic components and structures in the semiconductor package 100.

[0028] In addition, at least one second electronic component 145 is mounted on the second interposer 130 and is electrically connected to the second interposer 130. The at least one second electronic component 145 may also include any of a variety of types of semiconductor dies, semiconductor packages, or discrete devices. For example, the at least one second electronic component 145 may include a graphics processing unit (GPU) and a high bandwidth memory (HBM). Similarly, the at least one second electronic component 145 may also be a small IC chip containing different well-defined functional subsets. The at least one second electronic component 145 may be mounted on the second interposer 130 by flip chip bonding or any other suitable surface mounting technology.

[0029] In some embodiments, Figure 1 , the second sealant 140 is formed on the second interposer 130 to seal at least one second electronic element 145. The second sealant 140 may be made of the same material as the first sealant 120. However, the present application is not limited thereto.

[0030] Continue to refer Figure 1 , a first heat sink 150 is formed on the second sealant 140, a first heat transfer channel 142 extends through the second sealant 140 and the second interposer 130, and extends between the first heat sink 150 and at least one first electronic component 125; and a second heat transfer channel 144 extends through a portion of the second sealant 140, and extends between the first heat sink 150 and at least one second electronic component 145.

[0031] The first heat sink 150 may include a material having a thermal conductivity at least higher than that of the second sealant 140. For example, the first heat sink 150 may include a conductive material such as aluminum (Al), tin (Sn), copper (Cu), silver (Ag), aluminum oxide (Al2O3), zinc oxide (ZnO), silicon carbide (SiC), aluminum nitride (AlN), boron nitride (BN), diamond, or any combination thereof. In some embodiments, the first heat transfer channel 142 and / or the second heat transfer channel 144 may include a thermally conductive layer. The thermally conductive layer may include a thermally conductive material such as the first heat sink 150, or include a thermal interface material (TIM), a thermally conductive paste, a thermally conductive ink, or a thermally conductive epoxy resin, which will not be described in detail herein.

[0032] It can be appreciated that when heat is generated from the first electronic component 125 and the second electronic component 145, the heat can be easily transferred to the first heat sink 150 through the first heat transfer channel 142 and the second heat transfer channel 144. Therefore, the semiconductor package 100 can have improved heat dissipation capability.

[0033] Reference Figure 2 , which shows a semiconductor package 200 according to another embodiment of the present application. The semiconductor package 200 may have Figure 1 The similar or identical parts between the semiconductor package 200 and the semiconductor package 100 will not be repeated herein.

[0034] Figure 2 The semiconductor package 200 and Figure 1 The semiconductor package 100 is different in that Figure 2 The semiconductor package 200 includes stacked first heat transfer channels.

[0035] Specifically, if Figure 2 , the first heat transfer channel 242 extends through the second sealant 240 and the second interposer 230, and extends between the first heat sink 250 and the at least one first electronic component 225. The first heat transfer channel 242 may include a metal column 242a, a lower heat conductive layer 242b disposed between the lower end of the metal column 242a and the at least one first electronic component 225, and an upper heat conductive layer 242c disposed between the upper end of the metal column 242a and the first heat sink 250. The metal column 242a may include Al, Cu, Ag, or other metal materials with suitable thermal conductivity. The lower heat conductive layer 242b and / or the upper heat conductive layer 242c may include a thermal interface material, a thermal conductive paste, a thermal conductive ink, or a thermal conductive epoxy resin.

[0036] Reference Figure 3 , which shows a semiconductor package 300 according to another embodiment of the present application. The semiconductor package 300 may have Figure 1 The similar or identical parts between the semiconductor package 300 and the semiconductor package 100 will not be repeated herein.

[0037] Figure 3 The semiconductor package 300 and Figure 1 The semiconductor package 100 is different in that Figure 3 The semiconductor package 300 does not include a second encapsulant but includes stacked first heat transfer channels.

[0038] Specifically, if Figure 3, the first heat transfer channel 342 extends through the second interposer 330 and extends between the first heat sink 350 and the at least one first electronic component 325. The first heat transfer channel 342 may include a metal column 342a, and a heat conductive layer 342b disposed between the lower end of the metal column 342a and the at least one first electronic component 325. The metal column 342a may include Al, Cu, Ag, or other metal materials with suitable thermal conductivity. The heat conductive layer 342b may include a thermal interface material, a thermal conductive paste, a thermal conductive ink, or a thermal conductive epoxy resin.

[0039] In some embodiments, the metal pillar 342a and the first heat sink 350 are formed as a whole. In other embodiments, the metal pillar 342a can be directly attached to the first heat sink 350 by any suitable attachment means, such as welding or adhesive. In other words, the metal pillar 342a and the first heat sink 350 can be different parts of the metal frame, and the metal frame can be attached to the first heat sink 350 without the metal frame. Figure 1 or Figure 2 In the case of the second sealant 140 or 240 shown in Figure 3 The vertically extending posts shown in FIG. 3 are directly attached to the second interposer 330 and the thermally conductive layer 342 b.

[0040] Reference Figure 4 , which shows a semiconductor package 400 according to another embodiment of the present application. The semiconductor package 400 may have Figure 1 The similar or identical parts between the semiconductor package 400 and the semiconductor package 100 will not be repeated herein.

[0041] Figure 4 The semiconductor package 400 and Figure 1 The semiconductor package 100 is different in that Figure 4 The semiconductor package 400 is formed using a double-sided molding (DSM) technique.

[0042] Specifically, if Figure 4 As shown in FIG. 4 , the semiconductor package 400 further includes a third interposer 462, and the third interposer 462 is attached to the lower substrate surface 410b of the substrate 410. The third interposer 462 may have Figure 1. At least one third electronic component 465 is mounted on the third interposer 462 and is electrically connected to the third interposer 462. A third sealant 460 is formed on the lower substrate surface 460b of the substrate 460 to seal the at least one third electronic component 465. A second heat sink 470 is formed on the third sealant 460, and a third heat transfer channel 464 is formed in the third sealant 460 and extends between the second heat sink 470 and the at least one third electronic component 465. The third heat transfer channel 464 may include a metal material, a thermal interface material, a thermally conductive paste, a thermally conductive ink, a thermally conductive epoxy resin, etc.

[0043] In addition, the third sealant 460 has a plurality of cavities exposing a plurality of contact pads formed on the lower substrate surface 460b, and a plurality of conductive bumps 468 are formed in the plurality of cavities, respectively. Figure 4 In the example shown in , the conductive bump 468 is shown as a solder bump, but the present application is not limited thereto. In some other embodiments, the conductive bump 468 may include a conductive column or a copper ball. In the case where the semiconductor package 400 is mounted on an external device or substrate (such as a printed circuit board (PCB)), the conductive bump 468 can be used to electrically connect the semiconductor package 400 to the external device or substrate.

[0044] According to another aspect of the present application, a method for forming a semiconductor package is provided. The method can be used to manufacture, for example, Figures 1 to 4 Any of the semiconductor packages shown in .

[0045] refer to FIG. 5A to FIG. 5J , which shows a cross-sectional view of a method for manufacturing a semiconductor package according to an embodiment of the present application. For example, the method can be used to manufacture Figure 1 The semiconductor package 100 shown in FIG.

[0046] like Figure 5A As shown in , a substrate 510 is provided. The substrate 510 has an upper surface 510a and a lower surface 510b. The substrate 510 is attached to a carrier 505.

[0047] Specifically, substrate 510 can provide support and connectivity for electronic components and devices. In some embodiments, substrate 510 can include a plurality of interconnect structures. The interconnect structures can provide connectivity for electronic components mounted on substrate 510. The interconnect structures can define pads, traces, and plugs through which electrical signals or voltages can be distributed horizontally and vertically across substrate 510. For example, Figure 5A As shown in FIG. 5 , the interconnect structure may include a plurality of redistribution structures 512 , and the redistribution structures 512 may provide contact pads along the upper surface 510 a and the lower surface 510 b .

[0048] Carrier 505 can be a flat sheet of organic material, glass, silicon, polymer, or any other material suitable for providing physical support for substrate 510 during the manufacturing process. Optional double-sided tape, thermal release layer, UV release layer, or other suitable interface layer can be disposed between carrier 505 and substrate 510.

[0049] refer to Figure 5B , at least one first interposer 522 is attached to the upper substrate surface 510a.

[0050] In some embodiments, the at least one first interposer 522 may be attached to the upper substrate surface 510a using an adhesive. For example, the adhesive is first attached to the upper substrate surface 510a, and then the first interposer 522 is attached to the upper substrate surface 510a by the adhesive. The adhesive may include a non-conductive film, an anisotropic conductive film, an ultraviolet (UV) film, an instant adhesive, a thermosetting adhesive, or any other suitable adhesive material.

[0051] The first interposer 522 may be made of a semiconductor material, glass, or an organic material with a redistribution layer or wiring pattern formed therein. Preferably, the first interposer 522 is a silicon-based interposer. The first interposer 522 may support fine pitches of TSVs and traces for signal and power distribution, and may have a thermal expansion coefficient that may match the thermal expansion coefficient of a semiconductor die or chiplet in contact with the first interposer 522. For example, the first interposer 522 may include a semiconductor layer, a plurality of wiring patterns formed on the semiconductor layer, and a plurality of contact pads connected to the wiring patterns. The wiring pattern may include TSVs and traces with fine pitches. The contact pads may provide connectivity for electronic components mounted thereon.

[0052] refer to Figure 5C , at least one first electronic component 525 is mounted on the first intermediary layer 522 , and at least one first electronic component 525 is electrically connected to the first intermediary layer 522 .

[0053] The first electronic component 525 can be mounted on the first interposer 522 by flip chip bonding or other suitable surface mounting technology. For example, solder paste can be deposited or printed on the contact pads to which the first electronic component 525 is to be surface mounted. Then, the first electronic component 525 can be placed on the upper surface of the first interposer 522, with the terminals of the first electronic component 525 in contact with and over the solder paste. The solder paste can be reflowed to mechanically and electrically couple the first electronic component 525 to the contact pads on the upper surface of the first interposer 522.

[0054] The first electronic component 525 may include any of a variety of types of semiconductor dies, semiconductor packages, or discrete devices. For example, the at least one first electronic component 525 may include a central processing unit (CPU) and a high bandwidth memory (HBM). The CPU and the HBM are mounted on the first interposer 522 using corresponding solder bumps. In some embodiments, as shown in FIG. Figure 5C As shown in FIG. 5 , some terminals of the first electronic component 525 may be electrically connected to contact pads formed on the upper substrate surface 510 a via conductive bumps.

[0055] refer to Figure 5D , the second interposer 530 is mounted above the at least one first electronic component 525. The second interposer 530 may have a concave portion 530a and a protruding portion 530b. The at least one first electronic component 525 is accommodated in the concave portion 530a, and the protruding portion 530b is mounted on the upper substrate surface 510a.

[0056] In some embodiments, a plurality of conductive bumps (such as solder bumps, copper pillars, or electrical strip conductive structures) may be formed on contact pads at the protruding portion 530b of the second interposer 530. Then, the second interposer 530 may be mounted on the upper substrate surface 510a via the plurality of conductive bumps.

[0057] The second interposer 530 may be made of a semiconductor material, glass, or an organic material, in which a redistribution layer or a wiring pattern is formed. Figure 5D As shown in FIG. 5 , a plurality of redistribution layers 535 are formed in the second interposer 530 to provide contact pads along the upper and lower surfaces thereof.

[0058] refer to Figure 5E , a first sealant 520 is formed between the upper substrate surface 510 a and the second interposer 530 to seal the first interposer 522 and the at least one first electronic component 525 .

[0059] In some embodiments, a molding process such as a compression molding process or an injection molding process may be used to form the first sealant 520. In some other embodiments, paste printing, transfer molding, liquid sealing molding, vacuum lamination, or other suitable processes may be used to form the first sealant 520. The first sealant 520 may be made of a polymer composite material such as epoxy resin with fillers, epoxy acrylate with fillers, or a polymer with appropriate fillers, but the scope of the present application is not limited thereto.

[0060] refer to Fig. 5F , at least one second electronic component 545 is mounted on the second interposer 530 , and the at least one second electronic component 545 is electrically connected to the second interposer 530 .

[0061] The second electronic component 545 may be mounted on the second interposer 530 by flip chip bonding or other suitable surface mounting techniques. The at least one second electronic component 545 may also include any of a variety of types of semiconductor dies, semiconductor packages, or discrete devices. For example, the at least one second electronic component 545 may include a graphics processing unit (GPU) and a high bandwidth memory (HBM).

[0062] refer to Figure 5G , a second sealant 540 is formed on the second interposer 530 to seal at least one second electronic component 545 .

[0063] In some embodiments, a molding process such as a compression molding process or an injection molding process may be used to form the second sealant 540. In some other embodiments, paste printing, transfer molding, liquid sealing molding, vacuum lamination, spin coating, or other suitable processes may be used to form the second sealant 540. The second sealant 540 may be made of a polymer composite material such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler, but the scope of the present application is not limited thereto. In some examples, the second sealant 540 may be planarized if necessary.

[0064] refer to Figure 5H A first groove 541 is formed to expose an upper surface of at least one first electronic component 525 , and a second groove 543 is formed in the second sealant 540 to expose an upper surface of at least one second electronic component 545 .

[0065] First trench 541 extends through second encapsulant 540 and second interposer 530. In some cases, if a portion of first encapsulant 520 is formed between the upper surface of first electronic component 525 and second interposer 530, first trench 541 also extends through this portion of first encapsulant 520.

[0066] In some embodiments, a laser ablation process may be used to form the first groove 541 and / or the second groove 543. The laser ablation technique may accurately control the shape and / or depth of the first groove 541 and / or the second groove 543. However, the present application is not limited thereto. In other embodiments, the first groove 541 and / or the second groove 543 may be formed by a saw blade, a dry etching process or a wet etching process, or any other process known in the art, as long as the sealant and the middle layer material can be removed as needed. In some other embodiments, after the grooves are formed, a cleaning process for removing the residue of the sealing material at the grooves may be further performed.

[0067] refer to Figure 5H and Fig.5IIn both cases, the first heat transfer channel 542 is formed in the first groove 541 , and the second heat transfer channel 544 is formed in the second groove 543 .

[0068] In some embodiments, the first heat transfer channel 542 and / or the second heat transfer channel 544 may include a heat conductive layer. The heat conductive layer may include a heat conductive material such as a metal material, a thermal interface material (TIM), a heat conductive paste, a heat conductive ink, a heat conductive epoxy resin, etc.

[0069] In some embodiments, the first heat transfer channel 542 and / or the second heat transfer channel 544 may be formed by plating, spraying, sputtering or any other suitable deposition process. In some embodiments, the first heat transfer channel 542 and / or the second heat transfer channel 544 may be planarized if necessary.

[0070] Finally, reference Figure 5J The first heat sink 550 is formed on the second sealant 540. The first heat sink 550 contacts the first heat transfer channel 542 and the second heat transfer channel 544.

[0071] In some embodiments, the first heat sink 550 may be attached to the second encapsulant 540. In some other embodiments, the first heat sink 550 may be formed on the second encapsulant 540 by plating, spraying, sputtering, or any other suitable deposition process. The first heat sink 550 may include a material having a higher thermal conductivity than at least the second encapsulant 540. After the first heat sink 550 is formed on the second encapsulant 540, the carrier 505 is also removed from the substrate 510.

[0072] In addition, despite FIG. 5A to FIG. 5J The steps of FIG. 1 and FIG. 2 show only a single unit of a semiconductor package, but the semiconductor package may be used. FIG. 5A to FIG. 5J The process shown in the embodiment of the present invention is used to manufacture a strip type semiconductor package, that is, a plurality of semiconductor packages are formed on a substrate strip. Figure 5J After the step of forming the first heat sink 550 shown in FIG. 5 , a singulation step is performed on the strips.

[0073] Although the corresponding FIG. 5A to FIG. 5J A method for manufacturing the semiconductor package of the present application is described, but it will be appreciated by those skilled in the art that modifications and adaptations may be made to the method without departing from the scope of the present invention.

[0074] In some other embodiments, Figure 5HAfter forming the first groove 541 as shown in FIG. 5 , different first heat transfer channels may be formed in the first groove 541. The first heat transfer channel may include a metal column, a lower heat conduction layer disposed between the lower end of the metal column and at least one first electronic component, and an upper heat conduction layer disposed between the upper end of the metal column and the first heat sink. Therefore, the method described above can be used to manufacture Figure 2 The semiconductor package 200 shown in FIG.

[0075] In some other embodiments, in the second electronic component 545 such as Fig. 5F After being mounted on the second interposer 530 as shown in FIG. , a first groove is formed to extend through the second interposer and expose the upper surface of at least one first electronic component. Next, a first heat conducting layer is formed in the first groove, and a second heat conducting layer is formed on at least one second electronic component. Finally, a metal frame is mounted on the second interposer. The metal frame includes a metal column attached to the first heat conducting layer and a metal plate attached to the second heat conducting layer. The metal plate can act as a first heat sink, and the metal column can act as a first heat transfer channel. Thus, a heat dissipation channel can be formed. Figure 3 The semiconductor package 300 shown in FIG.

[0076] In some other embodiments, the first heat sink 550 is Figure 5J After being formed on the second sealant 540 as shown in , a third interposer is attached to the surface of the lower substrate, and at least one third electronic component is mounted on the third interposer. At least one third electronic component can be electrically connected to the third interposer. Then, a third sealant is formed on the surface of the lower substrate to seal at least one third electronic component, and a third groove is formed in the second sealant to expose the surface of at least one third electronic component. Then, a third heat transfer channel is formed in the third groove, and a second heat sink is formed on the third sealant. The second heat sink is in contact with the third heat transfer channel. In addition, a plurality of cavities are formed in the third sealant to expose a plurality of contact pads formed on the surface of the lower substrate, and a plurality of conductive bumps are respectively formed in the plurality of cavities. Therefore, a Figure 4 The semiconductor package 400 shown in FIG.

[0077] The discussion herein includes numerous illustrative drawings showing various portions of semiconductor packages and methods of making them. For clarity, such drawings do not show all aspects of each example package. Any example package and / or method provided herein may share any or all features with any or all other devices and / or methods provided herein.

[0078] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and variations may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. In addition, other embodiments will be apparent to those skilled in the art by consideration of the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that the present application and the examples herein be considered merely exemplary, with the true scope and spirit of the invention being indicated by the following enumeration of the exemplary claims.

Claims

1. A semiconductor package, characterized in that: The semiconductor package comprises: a substrate having a lower substrate surface and an upper substrate surface; a first interposer, the first interposer being attached to the upper substrate surface; at least one first electronic component mounted on the first interposer and electrically connected to the first interposer; a second interposer disposed above the at least one first electronic component, wherein the second interposer has a concave portion and a protruding portion, the at least one first electronic component being accommodated in the concave portion and the protruding portion being mounted on the upper substrate surface; and At least one second electronic component is mounted on the second interposer and is electrically connected to the second interposer.

2. The semiconductor package according to claim 1, wherein: The semiconductor package further comprises: A first sealant is disposed on the surface of the upper substrate and seals the first interposer and the at least one first electronic component.

3. The semiconductor package according to claim 1, wherein: The semiconductor package further comprises: A second sealant is disposed on the second interposer and seals the at least one second electronic component.

4. The semiconductor package according to claim 1, wherein: The semiconductor package further comprises: a first heat sink, the first heat sink being disposed above the at least one second electronic component; a first heat transfer channel extending between the first heat sink and the at least one first electronic component; and A second heat transfer channel extends between the first heat sink and the at least one second electronic component.

5. The semiconductor package according to claim 4, wherein: The first heat transfer channel or the second heat transfer channel includes a heat conductive layer, and the heat conductive layer includes a thermal interface material, a heat conductive paste, a heat conductive ink or a heat conductive epoxy resin.

6. The semiconductor package according to claim 4, wherein: The first heat transfer channel includes a metal column, a lower heat conduction layer disposed between a lower end of the metal column and the at least one first electronic component, and an upper heat conduction layer disposed between an upper end of the metal column and the first heat sink.

7. The semiconductor package according to claim 4, wherein: The first heat transfer channel includes a metal column and a heat conductive layer disposed between a lower end of the metal column and the at least one first electronic component, and The metal column and the first heat sink are formed as a whole, or the metal column is directly attached to the first heat sink.

8. The semiconductor package according to claim 1, wherein: The semiconductor package further comprises: a third intermediary layer, the third intermediary layer being disposed on the surface of the lower substrate; at least one third electronic component mounted on the third interposer and electrically connected to the third interposer; a second heat sink disposed below the at least one third electronic component; and A third heat transfer channel extends between the second heat sink and the at least one third electronic component.

9. The semiconductor package according to claim 8, wherein: The semiconductor package further comprises: a third sealant disposed on the lower substrate surface and sealing the at least one third electronic component, wherein the third sealant has a plurality of cavities respectively exposing a plurality of contact pads formed on the lower substrate surface; and A plurality of conductive bumps are formed in the plurality of cavities respectively.

10. A method for forming a semiconductor package, characterized in that: The method comprises: providing a substrate having a lower substrate surface and an upper substrate surface; attaching a first interposer onto the upper substrate surface; Mounting at least one first electronic component on the first interposer, the at least one first electronic component being electrically connected to the first interposer; mounting a second interposer over the at least one first electronic component, wherein the second interposer has a recessed portion and a protruding portion, the at least one first electronic component being received in the recessed portion and the protruding portion being mounted on the upper substrate surface; and At least one second electronic component is mounted on the second interposer, and the at least one second electronic component is electrically connected to the second interposer.

11. The method according to claim 10, characterized in that After mounting the second interposer over the at least one first electronic component, the method further comprises: A first sealant is formed between the upper substrate surface and the second interposer to seal the first interposer and the at least one first electronic component.

12. The method according to claim 11, characterized in that After mounting the at least one second electronic component on the second interposer, the method further comprises: A second sealant is formed on the second interposer to seal the at least one second electronic component.

13. The method according to claim 12, characterized in that The method further comprises: forming a first trench extending through the second encapsulant and the second interposer to expose an upper surface of the at least one first electronic component; forming a second groove in the second encapsulant to expose an upper surface of the at least one second electronic component; forming a first heat transfer channel in the first groove; forming a second heat transfer channel in the second groove; and A first heat sink is formed on the second sealant, the first heat sink being in contact with the first heat transfer channel and the second heat transfer channel.

14. The method according to claim 13, characterized in that The first heat transfer channel or the second heat transfer channel includes a heat conductive layer, and the heat conductive layer includes a thermal interface material, a heat conductive paste, a heat conductive ink or a heat conductive epoxy resin.

15. The method according to claim 13, characterized in that The first heat transfer channel includes a metal column, a lower heat conduction layer disposed between a lower end of the metal column and the at least one first electronic component, and an upper heat conduction layer disposed between an upper end of the metal column and the first heat sink.

16. The method according to claim 11, characterized in that The method further comprises: forming a first trench extending through the second interposer to expose an upper surface of the at least one first electronic component; forming a first heat conducting layer in the first trench; forming a second heat conducting layer on the at least one second electronic component; and A metal frame is mounted on the second interposer, wherein the metal frame includes metal pillars attached to the first thermally conductive layer and a metal plate attached to the second thermally conductive layer.

17. The method according to claim 11, characterized in that The method further comprises: attaching a third interposer to the lower substrate surface; Mounting at least one third electronic component on the third interposer, wherein the at least one third electronic component is electrically connected to the third interposer; forming a third sealant on the lower substrate surface to seal the at least one third electronic component; forming a third groove in the second encapsulant to expose a surface of the at least one third electronic component; forming a third heat transfer channel in the third groove; and A second heat sink is formed on the third sealant, and the second heat sink is in contact with the third heat transfer channel.

18. The method according to claim 11, characterized in that The method further comprises: forming a plurality of cavities in the third encapsulant to expose a plurality of contact pads formed on the lower substrate surface; and A plurality of conductive bumps are formed in the plurality of cavities respectively.

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