Display panel, manufacturing method thereof and tiled display device

Abstract

The invention provides a display panel, a manufacturing method thereof and a tiled display device.The display panel comprises a substrate with a plurality of substrate via holes penetrating through the thickness direction, and the substrate via holes communicate with a first surface and a second surface, opposite to each other, of the substrate; the pixel driving circuit and the micro light-emitting diodes are located on one side of the first surface and deviate from the substrate in sequence; the plurality of driving signal lines are positioned on one side of the first surface and are electrically connected with the pixel driving circuit; the plurality of conductive parts are arranged in the plurality of substrate via holes in a one-to-one correspondence manner; the plurality of binding terminals are positioned on one side of the second surface; and at least one driving signal line in the plurality of driving signal lines is electrically connected with the binding terminal through the corresponding conductive part.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a spliced ​​display device. Background Art

[0002] Sub-millimeter light emitting diode (Mini LED) or micro light emitting diode (Micro LED) is a miniaturized LED array structure with self-luminous display characteristics. Each pixel can be addressed and driven individually to emit light. It has the advantages of high brightness, low power consumption, small size, ultra-high resolution and color saturation, and is widely used.

[0003] Among them, LED display stands out in outdoor and central control large-screen display, becoming a hot display carrier in the industry; currently, to apply LED display to long-distance viewing, it is necessary to use small screen splicing to achieve seamless splicing and ultra-large screen display. Full-screen borderless display products can give users a better viewing experience and are increasingly favored by users. Summary of the invention

[0004] The present disclosure provides a display panel, a manufacturing method thereof, and a spliced ​​display device, and the specific scheme is as follows:

[0005] The present disclosure provides a display panel, comprising:

[0006] A base substrate having a plurality of base substrate vias extending through the thickness direction, each of the base substrate vias being connected to a first surface and a second surface of the base substrate that are oppositely disposed;

[0007] A pixel driving circuit and a plurality of micro light emitting diodes located on one side of the first surface and sequentially away from the base substrate;

[0008] a plurality of driving signal lines located on one side of the first surface and electrically connected to the pixel driving circuit;

[0009] a plurality of conductive parts disposed in the plurality of substrate via holes in a one-to-one correspondence, and a plurality of binding terminals located on one side of the second surface;

[0010] At least one driving signal line among the plurality of driving signal lines is electrically connected to the binding terminal through a corresponding conductive portion.

[0011] Optionally, in the embodiment of the present disclosure, the entire space within the substrate via hole is filled with the conductive part.

[0012] Part of the space in the substrate via hole is filled with the conductive part, and the other part of the space is filled with the insulating part.

[0013] Optionally, in the embodiment of the present disclosure, the conductive portion and the binding terminal are integrally formed.

[0014] Optionally, in the embodiment of the present disclosure, it also includes an electrostatic protection portion located on one side of the second surface and not overlapping with the binding terminal.

[0015] Optionally, in an embodiment of the present disclosure, the electrostatic protection portion and the plurality of binding terminals are provided in the same layer and with the same material.

[0016] Optionally, in the embodiment of the present disclosure, it also includes a plurality of adapter pads located on one side of the first surface and arranged one-to-one corresponding to the plurality of substrate vias, and at least one of the plurality of drive signal lines is electrically connected to the binding terminal in turn through the corresponding adapter pad and the conductive part.

[0017] Optionally, in an embodiment of the present disclosure, along the direction from the second surface to the first surface, the conductive layer of the pixel driving circuit includes a first gate layer, an active layer, a second gate layer, a first source-drain electrode layer and a second source-drain electrode layer which are arranged in sequence; an insulating layer is arranged between two adjacent conductive layers in the pixel driving circuit; and the multiple transfer pads are arranged on at least one of the first gate layer, the second gate layer, the first source-drain electrode layer and the second source-drain electrode layer.

[0018] Optionally, in the embodiment of the present disclosure, any one of the plurality of driving signal lines is a power line;

[0019] The power line is arranged on the second source-drain electrode layer, and is electrically connected to the corresponding conductive part through the adapter pad located on the first source-drain electrode layer.

[0020] Optionally, in the embodiment of the present disclosure, any one of the plurality of driving signal lines is a data line;

[0021] The data line is arranged on the first source-drain electrode layer, and is electrically connected to the corresponding conductive part through the transfer pad located on the first gate layer or the second gate layer.

[0022] Optionally, in the embodiment of the present disclosure, any one of the plurality of driving signal lines is a gate line;

[0023] The gate line is arranged on the second gate layer, and is electrically connected to the corresponding conductive part through the transfer pad located on the first source-drain electrode layer.

[0024] Optionally, in an embodiment of the present disclosure, along the direction from the second surface to the first surface, a variation trend of the cross-sectional area of ​​each substrate via or a cross-sectional area of ​​each conductive portion is any one of the following:

[0025] A tendency to decrease first and then increase;

[0026] A tendency to increase first and then decrease;

[0027] The tendency to increase;

[0028] decreasing trend;

[0029] The same big trend.

[0030] Optionally, in the embodiment of the present disclosure, the plurality of substrate via holes are arranged in an edge region and / or a middle region of the display panel.

[0031] Optionally, in an embodiment of the present disclosure, the plurality of substrate via holes are arranged in at least one row along a direction parallel to a side extension direction of the display panel.

[0032] Accordingly, an embodiment of the present disclosure further provides a spliced ​​display device, comprising:

[0033] A plurality of display panels as described in any one of the above items.

[0034] Accordingly, a method for manufacturing a display panel includes:

[0035] A plurality of substrate via holes are provided along a thickness direction of the substrate, each of the substrate via holes being connected to a first surface and a second surface of the substrate that are oppositely disposed;

[0036] disposing a filling material in the plurality of substrate via holes;

[0037] A pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit are sequentially formed on one side of the first surface;

[0038] forming a plurality of binding terminals on one side of the second surface so that at least one of the plurality of driving signal lines is electrically connected to the binding terminal through the conductive portion obtained by the filling material;

[0039] The pixel driving circuit is bound and connected to a plurality of micro light emitting diodes.

[0040] Optionally, in an embodiment of the present disclosure, providing a filling material in the plurality of substrate via holes includes:

[0041] The filling material is obtained by filling the plurality of substrate via holes with an inorganic insulating material and / or an organic insulating material.

[0042] Optionally, in an embodiment of the present disclosure, forming a plurality of binding terminals on the second surface includes:

[0043] After sequentially forming a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit on the first surface, opening a through hole on the second surface along a thickness direction penetrating the filling material;

[0044] Conductive material is deposited in a region corresponding to the through hole, and the conductive material is patterned to form the conductive portion in the through hole, and a plurality of binding terminals integrally formed with the conductive portion are formed on the second surface.

[0045] Optionally, in an embodiment of the present disclosure, providing a filling material in the plurality of substrate via holes includes:

[0046] The metal material is filled into the plurality of substrate via holes through an electroplating process to obtain the filling material, and the filling material is used as the conductive part.

[0047] Optionally, in an embodiment of the present disclosure, forming a plurality of binding terminals on the second surface includes:

[0048] After the metal material is filled in the plurality of substrate via holes to obtain the filling material and before a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit are sequentially formed on the first surface, a whole electrostatic protection layer is formed on the second surface;

[0049] The electrostatic protection layer is patterned to obtain an electrostatic protection portion and the plurality of binding terminals.

[0050] Optionally, in an embodiment of the present disclosure, forming a plurality of binding terminals on the second surface includes:

[0051] After the metal material is filled in the plurality of substrate via holes to obtain the filling material and before a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit are sequentially formed on the first surface, a whole electrostatic protection layer is formed on the second surface;

[0052] After sequentially forming a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit on the first surface, the electrostatic protection layer is patterned to obtain an electrostatic protection portion and the plurality of binding terminals. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1a A schematic diagram of a top view of the front side of a miniaturized LED frameless back panel in the related art;

[0054] Figure 1b for Figure 1a A schematic diagram of a top view of the back side of a corresponding miniaturized LED frameless back panel;

[0055] Figure 2 for Figure 1a and Figure 1b A schematic diagram of one of the stacked structures of the corresponding miniaturized LED frameless backplane;

[0056] Figure 3 for Figure 1a and Figure 1b The corresponding manufacturing process flow chart of the front and back connection process (including the side process) of the miniaturized LED frameless back panel;

[0057] Figure 4 for Figure 1a and Figure 1b The corresponding miniaturized LED frameless backplane has a backplane lamination structure after the backplane process and the backend process;

[0058] Figure 5 A schematic diagram of a top view structure of a display panel provided in an embodiment of the present disclosure;

[0059] Figure 6 For along Figure 5 A schematic diagram of one of the cross-sectional structures in the direction indicated by MM;

[0060] Figure 7 A schematic diagram of a cross-sectional structure of a conductive portion disposed in a display panel provided in an embodiment of the present disclosure;

[0061] Figure 8 A schematic diagram of a top view structure of a conductive portion disposed in a display panel provided in an embodiment of the present disclosure;

[0062] Fig. 9 for Figure 8 A corresponding schematic diagram of one of the cross-sectional structures;

[0063] Fig.10 A schematic diagram of a top view structure of a conductive portion disposed in a display panel provided in an embodiment of the present disclosure;

[0064] Fig.11 for Fig.10 A corresponding schematic diagram of one of the cross-sectional structures;

[0065] Fig.12 A schematic diagram of a top view structure of a conductive portion disposed in a display panel provided in an embodiment of the present disclosure;

[0066] Fig.13 For along Figure 5 A schematic diagram of one of the cross-sectional structures in the direction indicated by MM;

[0067] Fig.14 For combination Figure 6 A schematic diagram of one of the configuration structures of the electrostatic protection portion of the exemplary embodiment shown;

[0068] Fig.15 For combination Fig.13 A schematic diagram of one of the configuration structures of the electrostatic protection portion of the exemplary embodiment shown;

[0069] Fig.16 A schematic diagram of a structure arrangement in which driving signal lines of a display panel provided by an embodiment of the present disclosure are power lines, data lines and gate lines;

[0070] Fig.17 A schematic diagram of a structure arrangement in which driving signal lines of a display panel provided by an embodiment of the present disclosure are power lines, data lines and gate lines;

[0071] Fig.18 A schematic diagram of a structure arrangement in which driving signal lines of a display panel provided by an embodiment of the present disclosure are power lines, data lines and gate lines;

[0072] Fig.19 A schematic diagram of a cross-sectional shape between a substrate via hole and a conductive portion in a display panel provided by an embodiment of the present disclosure;

[0073] Fig. 20 A schematic diagram of the arrangement of substrate via holes in a display panel provided in an embodiment of the present disclosure;

[0074] Fig.21 A schematic diagram of a structure of a spliced ​​display device provided in an embodiment of the present disclosure;

[0075] Fig. 22 A method flow chart of a method for manufacturing a display panel provided in an embodiment of the present disclosure;

[0076] Fig.23 for Fig. 22 A method flow chart of step S104;

[0077] Fig.24 Prepared using TGV technology Fig.18 The process flow chart corresponding to the display panel shown;

[0078] Fig.25 for Fig. 22 A method flow chart of step S104;

[0079] Fig.26 Prepared using TGV technology Fig.17 The process flow chart corresponding to the display panel shown;

[0080] Fig. 27 for Fig. 22 A method flow chart of step S104;

[0081] Fig.28 Prepared using TGV technology Fig.17 The process flow chart corresponding to the display panel shown;

[0082] Fig.29 Based on Fig.26 A schematic diagram of the back-end process production flow corresponding to the embodiment. DETAILED DESCRIPTION

[0083] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0084] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0085] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0086] In the related art, for the seamless splicing solution of Micro / Mini LED, it is necessary to bond the integrated circuit (IC) chip or the flexible printed circuit board (FPC) to the back of the substrate, and connect the signal traces on the front of the substrate to the back of the substrate, which requires complex side and back processes. Figure 1a , Figure 1b to Figure 3 As shown, Figure 1a This is a schematic diagram of a top view of the front side of a miniaturized LED frameless back panel in the related art. Figure 1b A schematic diagram of a top view of the back of a corresponding miniaturized LED frameless back panel. Figure 2 It is a schematic diagram of one of the stacking structures corresponding to the backplane process section of the corresponding miniaturized LED frameless backplane. Figure 3 The following is a process flow chart of the front and back connection process (including the side process) of the corresponding miniaturized LED frameless backplane. Figure 3 The manufacturing process flow chart shown realizes the manufacturing of the side connecting lines. Figure 4 The backplane stacking structure of the corresponding miniaturized LED frameless backplane after the backplane process and the backend process. Figure 1a As shown, conventionally, on the array backplane, the signal line connection pad is placed on the DP side of the panel. Among them, the number 01 represents the DP side, the number 02 represents the signal line connection pad, 03 represents the side connection line, and 04 represents the binding pin for binding the FPC or IC. Figure 3 The production process flow chart shown in the figure shows that in actual production, the following steps are performed in sequence:

[0087] S01: Front film;

[0088] S02: Laser film cutting and tearing;

[0089] S03: process edge cutting;

[0090] S04: Edging;

[0091] S05: Back film;

[0092] S06: 3D sputter, film tearing;

[0093] S07: Laser etching (side & back);

[0094] S08: Flying probe test & OC protection;

[0095] S09: Apply protective film (back circuit protection).

[0096] It should be noted that in Figure 3 In the manufacturing process flow chart shown, after executing step S05, illustratively, by 3D sputtering process, Ti / Cu / Ti metal is plated at the corresponding position of the signal line routing connection pad (Pad) on the front of the backplane, and Ti / Cu / Ti metal film layer is plated at the fan-out area (fanout) on the side and back of the backplane; then, by laser etching, the spacing between two adjacent signal line routing connection pads on the front of the backplane is etched open, the spacing between the connection lines on the side of the panel is etched open, and the fan-out area and the binding terminals for binding FPC or IC are etched on the back. In this way, the signal line routing connection pad on the front of the backplane is connected to the fan-out area on the back of the backplane through Ti / Cu / Ti, and is connected to the final binding terminal.

[0097] The inventors found in actual research that Figure 3 The following problems exist in the manufacturing process shown:

[0098] Due to the roughness of the backplane side, short circuits, disconnections and metal corrosion are likely to occur during the preparation of the side connection wires, resulting in low yield rates in the later stages of the process.

[0099] At the same time, since the front and back film lamination, film cutting and film tearing processes need to be performed multiple times, especially during the lamination and tearing process, KV-level electrostatic discharge (ESD) is generated. The ESD damages the related signal lines and the thin film transistor (TFT) devices in the pixel driving circuit through the exposed connection pads on the front side, resulting in poor display of the module;

[0100] Since it is necessary to take into account the front connection pad connection, the side connection line preparation and the back fanout routing preparation at the same time, the overall process flow is high and difficult, there are many restrictions on the back-end process solutions, and there are few optional back-end process solutions.

[0101] It can be seen that during the entire back-end process, the yield loss is serious due to the complexity of the process.

[0102] In view of this, the embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a spliced ​​display device, which are used to optimize the manufacturing process, reduce defects, and improve the yield.

[0103] Combination Figure 5 and Figure 6 As shown, Figure 5 A schematic diagram of a top view of a display panel provided in an embodiment of the present disclosure is shown in FIG. Figure 6 For along Figure 5 Specifically, the display panel provided by the embodiment of the present disclosure includes:

[0104] A base substrate 10 having a plurality of base vias V extending through the thickness direction, each of the base vias V connecting a first surface 11 and a second surface 12 of the base substrate 10 that are oppositely disposed;

[0105] A pixel driving circuit 20 and a plurality of micro light emitting diodes 30 located on one side of the first surface 11 and sequentially away from the base substrate 10;

[0106] A plurality of driving signal lines 40 located at one side of the first surface 11 and electrically connected to the pixel driving circuit 20;

[0107] a plurality of conductive parts 50 disposed in the plurality of substrate via holes V in a one-to-one correspondence, and a plurality of binding terminals 60 located on one side of the second surface 12;

[0108] At least one driving signal line 40 among the plurality of driving signal lines 40 is electrically connected to the binding terminal 60 through a corresponding conductive portion 50 .

[0109] The above-mentioned display panel provided by the embodiment of the present disclosure is provided by opening a plurality of substrate via holes V penetrating the thickness direction on the base substrate 10, and setting corresponding conductive parts 50 in the base via holes V; sequentially setting the pixel driving circuit 20 and a plurality of micro-light-emitting diodes 30 on one side of the first surface 11 of the base substrate 10, and setting a plurality of driving signal lines 40 electrically connected to the pixel driving circuit 20 on one side of the first surface 11; wherein the driving signal line 40 may be made of the same layer and the same material as a part of the conductive film layer in the pixel driving circuit 20; in addition, a plurality of binding terminals 60 are set on one side of the second surface 12 of the base substrate 10 opposite to the first surface 11; and at least one of the plurality of driving signal lines 40 is electrically connected to the binding terminal 60 through the corresponding conductive part 50. In this way, after the binding terminal 60 is bound to the flexible circuit board or the driving chip, the signal can be transmitted to the corresponding driving signal line 40 through the binding terminal 60, so as to drive and control the corresponding micro-light-emitting diode 30. In addition, there is no need to set up relevant wiring on the side, and the electrical connection between the driving signal line 40 and the binding terminal 60 on the two surfaces can be achieved through the substrate via V opened on the base substrate 10, thereby improving the manufacturing yield of the display panel. In this way, while taking into account the driving performance, the narrow frame design and manufacturing yield of the display panel are guaranteed.

[0110] In the specific implementation process, the display panel includes a base substrate 10 having a plurality of base vias V running through the thickness direction, and each base via V connects the first surface 11 and the second surface 12 of the base substrate 10 which are arranged oppositely. Exemplarily, the base substrate 10 can be a rigid substrate, such as a glass substrate, a silicon-based substrate, etc.; it can also be a flexible substrate, such as a polyimide (PI) substrate. Of course, the specific material of the base substrate 10 can be set according to the actual application needs, which is not limited here. In addition, the specific number of the plurality of base vias V running through the thickness direction of the base substrate 10 can be set according to the actual application needs, which is not limited here. Exemplarily, when the material of the base substrate 10 is glass, a through glass via (TGV) process can be used to open a through substrate via V on the base substrate 10. Exemplarily, when the material of the base substrate 10 is PI, a through PI via (TPV) process can be used to open a base via V on the base substrate 10. Of course, the substrate via hole V may be opened on the base substrate 10 by adopting corresponding processes according to actual application needs, which is not limited here.

[0111] Moreover, the display panel further includes a pixel driving circuit 20 and a plurality of micro-LEDs 30 located on one side of the first surface 11 and facing away from the base substrate 10 in sequence. Exemplarily, the plurality of micro-LEDs 30 are distributed in an array, and the specific number of the plurality of micro-LEDs 30 can be set according to actual application needs, which is not limited here. In addition, the micro-LEDs 30 can be Mini LEDs or Micro LEDs, which are not limited here.

[0112] The display panel also includes a plurality of drive signal lines 40 located on one side of the first surface 11 and electrically connected to the pixel drive circuit 20. The specific number of the plurality of drive signal lines 40 can be set according to actual application needs, which is not limited here. In the specific implementation process, any drive signal line 40 can be one of a gate line, a data line, and a power line, which is not limited here.

[0113] Moreover, the display panel further includes a plurality of conductive portions 50 disposed in a one-to-one correspondence in the plurality of substrate via holes V, that is, a conductive portion 50 is disposed in each substrate via hole V. In addition, the display panel further includes a plurality of binding terminals 60 located on one side of the second surface 12. The specific number of the plurality of binding terminals 60 can be determined according to actual application requirements and is not limited here.

[0114] In the embodiment of the present disclosure, the conductive portion 50 may be arranged in the following manners, but is not limited to the following manners and is not limited here.

[0115] In one exemplary embodiment, in combination Figure 7 The cross-sectional structure diagram of the base substrate 10 is shown, and the entire space in the substrate via hole V is filled with the conductive part 50 .

[0116] In another exemplary embodiment, in combination Figures 8 to 12 As shown, part of the space in the substrate via hole V is filled with the conductive part 50 , and the other part of the space is filled with the insulating part 70 .

[0117] Still combined Figure 8 and Fig. 9 As shown, the insulating portion 70 may be disposed around the conductive portion 50. Fig.10 and Fig.11 As shown, the insulating portion 70 is disposed on one side of the conductive portion 50. Fig.12 As shown, the insulating portion 70 is partially disposed around the conductive portion 50. Of course, the positional relationship between the insulating portion 70 and the conductive portion 50 can also be set according to actual application requirements, which is not limited here.

[0118] In the embodiments of the present disclosure, Fig.13 Shown along Figure 5 One of the cross-sectional structural schematic diagrams in the direction shown by MM, the conductive part 50 and the binding terminal 60 are integrally formed.

[0119] In the embodiment of the present disclosure, the display panel further includes an electrostatic protection portion 80 located at one side of the second surface 12 and not overlapping with the binding terminal 60 .

[0120] Combination Figure 6 In the exemplary embodiment shown, the static protection unit 80 is arranged as follows Fig.14 As shown. Combined Fig.13 In the exemplary embodiment shown, the static protection unit 80 is arranged as follows Fig.15 shown.

[0121] In the embodiment of the present disclosure, the electrostatic protection part 80 is provided in the same layer and the same material as the plurality of binding terminals 60. In one exemplary embodiment, the electrostatic protection part 80 is provided in the same layer and the same material as the plurality of binding terminals 60. Accordingly, the electrostatic protection part 80 can be manufactured together with the plurality of binding terminals 60, thereby simplifying the manufacturing process and reducing the manufacturing cost.

[0122] In the embodiment of the present disclosure, the display panel further includes a plurality of adapter pads 90 located on one side of the first surface 11 and arranged one-to-one corresponding to the plurality of substrate via holes V, and at least one of the plurality of drive signal lines 40 is electrically connected to the binding terminal 60 in sequence through the corresponding adapter pad 90 and the conductive portion 50. The specific arrangement of the plurality of adapter pads 90 may refer to the following implementations, but is not limited thereto.

[0123] In the embodiment of the present disclosure, Figures 16 to 18 As shown, along the direction from the second surface 12 to the first surface 11, the conductive layer of the pixel driving circuit 20 includes a first gate layer 21, an active layer 22, a second gate layer 23, a first source-drain electrode layer 24, and a second source-drain electrode layer 25 arranged in sequence; an insulating layer is arranged between two adjacent conductive layers in the pixel driving circuit 20; and the plurality of transfer pads 90 are arranged on at least one of the first gate layer 21, the second gate layer 23, the first source-drain electrode layer 24, and the second source-drain electrode layer 25. Exemplarily, the insulating layer includes a first gate insulating layer 27 arranged between the first gate layer 21 and the active layer 22, a second gate insulating layer 28 arranged between the active layer 22 and the second gate layer 23, an interlayer insulating layer 29 arranged between the second gate layer 23 and the first source-drain electrode layer 24, and a first planar layer 201 and a first passivation layer 202 arranged between the first source-drain electrode layer 24 and the second source-drain electrode layer 25. The insulating layer also includes a buffer layer 26 between the first gate layer 21 and the base substrate 10, and a second passivation layer 203 and a second planarization layer 204 located on the side of the second source and drain electrode layer 25 away from the base substrate 10. Of course, the insulating layer can also be provided according to actual application requirements, which is not limited here.

[0124] Exemplarily, any one of the plurality of driving signal lines 40 is a power line;

[0125] The power line is arranged in the second source-drain electrode layer 25, and is electrically connected to the corresponding conductive part 50 through the adapter pad 90 located in the first source-drain electrode layer 24. In one exemplary embodiment, the power line is a high potential power line. In another exemplary embodiment, the power line is a low potential power line. Of course, the power line can also be arranged according to the actual application needs, which is not limited here.

[0126] Exemplarily, any one of the plurality of driving signal lines 40 is a data line;

[0127] The data line is disposed on the first source-drain electrode layer 24 , and is electrically connected to the corresponding conductive part 50 via the transfer pad 90 located on the first gate layer 21 or the second gate layer 23 .

[0128] Exemplarily, any one of the plurality of driving signal lines 40 is a gate line;

[0129] The gate line is disposed on the second gate layer 23 , and is electrically connected to the corresponding conductive part 50 through the transfer pad 90 located on the first source-drain electrode layer 24 .

[0130] exist Fig.16 In the exemplary embodiment shown, the transfer pad 90 is located in the first source-drain electrode layer 24; wherein the dashed frame A is the structural setting at the substrate via hole V when the driving signal line 40 is a power line, the dashed frame B is the structural setting at the substrate via hole V when the driving signal line 40 is a data line, and the dashed frame C is the structural setting at the substrate via hole V when the driving signal line 40 is a gate line. Accordingly, in this exemplary embodiment, the power line is arranged in the second source-drain electrode layer 25, and the power line is electrically connected to the corresponding conductive part 50 through the transfer pad 90 located in the first source-drain electrode layer 24; the data line is arranged in the first source-drain electrode layer 24, and is directly electrically connected to the corresponding conductive part 50; the gate line is arranged in the second gate layer 23, and is electrically connected to the corresponding conductive part 50 through the transfer pad 90 located in the first source-drain electrode layer 24.

[0131] exist Fig.17 In the exemplary embodiment shown, the transfer pad 90 is located in the first gate layer 21; wherein the dashed frame D is the structural setting at the substrate via V when the driving signal line 40 is a power line, the dashed frame E is the structural setting at the substrate via V when the driving signal line 40 is a data line, and the dashed frame F is the structural setting at the substrate via V when the driving signal line 40 is a gate line. Accordingly, in this exemplary embodiment, the power line is arranged in the second source-drain electrode layer 25, and the power line is electrically connected to the corresponding conductive part 50 through the first source-drain electrode layer 24 and the transfer pad 90 located in the first gate layer 21; the data line is arranged in the first source-drain electrode layer 24, and is electrically connected to the corresponding conductive part 50 through the transfer pad 90 located in the first gate layer 21; the gate line is arranged in the second gate layer 23, and is electrically connected to the transfer pad 90 located in the first gate layer 21 through the first source-drain electrode layer 24.

[0132] exist Fig.18In the exemplary embodiment shown, the transfer pad 90 is located in the first gate layer 21; wherein the dashed frame G is the structural setting at the substrate via V when the driving signal line 40 is a power line, the dashed frame H is the structural setting at the substrate via V when the driving signal line 40 is a data line, and the dashed frame I is the structural setting at the substrate via V when the driving signal line 40 is a gate line. Accordingly, in this exemplary embodiment, the power line is arranged in the second source-drain electrode layer 25, and the power line is electrically connected to the corresponding conductive part 50 through the first source-drain electrode layer 24 and the transfer pad 90 located in the first gate layer 21; the data line is arranged in the first source-drain electrode layer 24, and is electrically connected to the corresponding conductive part 50 through the transfer pad 90 located in the first gate layer 21; the gate line is arranged in the second gate layer 23, and is electrically connected to the transfer pad 90 located in the first gate layer 21 through the first source-drain electrode layer 24.

[0133] In the embodiment of the present disclosure, Fig.19 As shown, along the direction from the second surface 12 to the first surface 11, the variation trend of the cross-sectional area of ​​each substrate via V or the cross-sectional area of ​​each conductive portion 50 is any one of the following:

[0134] A tendency to decrease first and then increase;

[0135] A tendency to increase first and then decrease;

[0136] The tendency to increase;

[0137] decreasing trend;

[0138] The same big trend.

[0139] In one exemplary embodiment, along the direction from the second surface 12 to the first surface 11, the variation trend of the cross-sectional area of ​​the substrate via hole V and the variation trend of the cross-sectional area of ​​the corresponding conductive portion 50 can be the same variation trend or different variation trends, which are not limited here. In this way, a diversified design of the display panel is achieved.

[0140] In the embodiment of the present disclosure, the plurality of substrate via holes V are arranged in the edge region and / or the middle region of the display panel.

[0141] In the embodiment of the present disclosure, the plurality of substrate via holes V are arranged in at least one row along a direction parallel to the side extension direction of the display panel.

[0142] In a specific implementation process, the arrangement of the plurality of substrate vias V can be: Fig. 20Any one of the above. Among them, a means that the substrate vias V are arranged horizontally along the edge of the display panel, b means that the substrate vias V are arranged in the middle area of ​​the display panel, c means that the substrate vias V are arranged in two rows along the side extension direction parallel to the display panel, d means that the substrate vias V are arranged vertically along the edge of the display panel, and e means that the substrate vias V are arranged in a special shape. Of course, multiple substrate vias V can also be arranged according to actual application needs, which is not limited here. In this way, a diversified design of the substrate vias V is achieved.

[0143] It should be noted that, in addition to the aforementioned structure, the display panel provided in the embodiment of the present disclosure may also be provided with other film layer structures, which are not limited here.

[0144] Based on the same public concept, Fig.21 As shown, the embodiment of the present disclosure further provides a splicing display device, the splicing display device comprising:

[0145] A plurality of display panels 100 as described in any one of the above.

[0146] Since the principle of solving the problem by the spliced ​​display device is similar to that of the aforementioned display panel, the implementation of the spliced ​​display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be repeated.

[0147] In the specific implementation process, in the spliced ​​display device provided by the embodiment of the present disclosure, each display panel is connected to the binding terminal through the substrate via hole that penetrates the base substrate, and the driving signal line is electrically connected to the binding terminal through the conductive part in the substrate via hole, thereby ensuring seamless splicing between multiple display panels in the spliced ​​display device and improving the user experience.

[0148] Based on the same public concept, Fig. 22 As shown, the embodiment of the present disclosure further provides a method for manufacturing a display panel, wherein the specific structure of the display panel can refer to the description of the above-mentioned related parts, and will not be repeated here. Specifically, the manufacturing method includes:

[0149] S101: opening a plurality of substrate via holes along a thickness direction of the substrate, each of the substrate via holes being connected to a first surface and a second surface of the substrate that are oppositely disposed;

[0150] S102: Disposing a filling material in the plurality of substrate via holes;

[0151] S103: sequentially forming a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit on one side of the first surface;

[0152] S104: forming a plurality of binding terminals on one side of the second surface, so that at least one of the plurality of driving signal lines is electrically connected to the binding terminal through the conductive portion obtained by the filling material;

[0153] S105: Binding and connecting the pixel driving circuit to a plurality of micro light emitting diodes.

[0154] In the specific implementation process, the specific implementation process of step S101 to step S105 is as follows:

[0155] First, a plurality of substrate vias are opened along the thickness direction of the substrate substrate. Each substrate via connects the first surface and the second surface of the substrate substrate that are arranged opposite to each other. In one exemplary embodiment, the substrate substrate is a glass substrate, and a plurality of substrate vias are opened along the thickness direction of the substrate substrate by using the TGV process. In another exemplary embodiment, the substrate substrate is a flexible PI substrate, a rigid substrate is attached to the second surface of the flexible substrate, and a plurality of substrate vias are opened along the thickness direction of the substrate substrate by using the TPV process. In this exemplary embodiment, the rigid substrate is torn off after the required related film layers are prepared.

[0156] Then, filler materials are placed in the plurality of substrate vias; then, a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit are sequentially formed on one side of the first surface; then, a plurality of binding terminals are formed on one side of the second surface, so that at least one of the plurality of driving signal lines is electrically connected to the binding terminal through the conductive portion obtained by the filler materials; then, the pixel driving circuit is bound and connected to the plurality of micro-LEDs, thereby obtaining a display panel.

[0157] In the specific implementation process, the filling material can be set in the following ways, but it is not limited to the following ways.

[0158] In one exemplary embodiment, providing a filling material in the plurality of substrate vias includes:

[0159] The filling material is obtained by filling the plurality of substrate via holes with an inorganic insulating material and / or an organic insulating material.

[0160] Accordingly, in this exemplary embodiment, Fig.23 As shown, step S104: forming a plurality of binding terminals on the second surface, including:

[0161] S201: after sequentially forming a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit on the first surface, opening a through hole on the second surface along a thickness direction penetrating the filling material;

[0162] S202: depositing a conductive material in a region corresponding to the through hole, and patterning the conductive material to form the conductive portion in the through hole, and forming a plurality of binding terminals integrally formed with the conductive portion on the second surface.

[0163] In the specific implementation process, when the filling material is an inorganic insulating material and / or an organic insulating material, based on Fig.23 The process flow chart shown is prepared using TGV technology Fig.18 The process flow chart corresponding to the display panel shown is as follows Fig.24 As shown. Taking the front and back signal connection at the splicing edge of the display panel as an example, first, the TGV technology is used on the substrate substrate to prepare the signal connection line vias required for the splicing edge at the signal input position of the splicing edge of the display panel. Exemplarily, an inorganic insulating material or an organic insulating material is coated on the place where the glass substrate has a TGV via, and the TGV via is filled; then, the relevant film layers of the pixel driving circuit and other protective film layers are made on the first surface of the substrate substrate. Taking the LTPS PMOS process as an example, a buffer layer, a first gate layer, a first gate insulating layer, an active layer, a second gate insulating layer, a second gate layer, an interlayer insulating layer, a first source and drain electrode layer, a first flat layer, a first passivation layer, a second source and drain electrode layer, a second passivation layer and a second flat layer are sequentially stacked on the first surface. It should be noted that the relevant conductive layers in the pixel driving circuit are electrically connected to each other through vias that penetrate the insulating layer. The specific opening of the vias can be achieved by referring to the relevant technology, which will not be described in detail here.

[0164] After the front process of the substrate is completed, the organic insulating material and / or inorganic insulating material at the TGV via is etched on the second surface of the substrate to form a through hole in the thickness direction of the filling material. Then, a conductive material is deposited on the second surface of the substrate and in the through hole at the TGV opening through the back-end process, for example, the conductive material is a metal material, such as Cu. For another example, the conductive material is ITO. The conductive material is patterned to form a conductive part in the through hole, and a plurality of binding terminals integrally formed with the conductive part are formed on the second surface. In this way, the plurality of binding terminals can be electrically connected to the relevant conductive layer in the pixel driving circuit through the conductive part, thereby realizing the connection of the signals on the front and back of the substrate, and ensuring the driving ability of the display panel. Then, the flexible circuit board is electrically connected to the plurality of binding terminals, thereby ensuring the transmission of the control signal of the flexible circuit board through the plurality of binding terminals. Then, the plurality of micro-light-emitting diodes are transferred to the display panel through the solid crystal process and electrically connected to the pixel driving circuit. The figure only illustrates the binding of the micro-light-emitting diodes when the drive signal line is a power line. Among them, the die bonding process can be specifically implemented by referring to the relevant technology and will not be described in detail here.

[0165] In another exemplary embodiment, providing a filling material in the plurality of substrate via holes includes:

[0166] The metal material is filled into the plurality of substrate via holes through an electroplating process to obtain the filling material, and the filling material is used as the conductive part.

[0167] Accordingly, in this exemplary embodiment, Fig.25 As shown, step S104: forming a plurality of binding terminals on the second surface, including:

[0168] S301: filling metal material in the plurality of substrate vias, and forming a whole electrostatic protection layer on the second surface after obtaining the filling material and before sequentially forming a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit on the first surface;

[0169] S302: performing patterning on the electrostatic protection layer to obtain an electrostatic protection portion and the plurality of binding terminals.

[0170] In the specific implementation process, when the filling material is an inorganic insulating material and / or an organic insulating material, based on Fig.25 As shown, prepared using TGV technology Fig.17 The process flow chart corresponding to the display panel shown is as follows Fig.26 As shown. Taking the front and back signal connection at the splicing edge of the display panel as an example, first, the TGV technology is used on the substrate substrate to prepare the signal connection line vias required for the splicing edge at the signal input position of the splicing edge of the display panel. Accordingly, a plurality of substrate vias are opened along the thickness direction of the substrate substrate, and each substrate via connects the first surface and the second surface of the substrate substrate that are relatively arranged. Exemplarily, the Cu electroplating technology is used to make Cu connecting wires at the place where the glass substrate has TGV vias to form a conductive part. Then, a whole layer of electrostatic protection layer is formed on the second surface. For example, an ITO film layer. Then, the electrostatic protection layer is patterned to obtain an electrostatic protection part and a plurality of binding terminals. In this way, the part located at the TGV via can protect the conductive part to prevent the influence of the subsequent process film layer etching on the conductive part; in addition, the part located at the TGV via can be used as a plurality of binding terminals, which simplifies the manufacturing process and reduces the manufacturing cost; moreover, the electrostatic protection part can reduce the electrostatic discharge caused by processes such as film pasting and tearing.

[0171] Then, a glass substrate with a Cu connection line and a back electrostatic protection layer is used to design the front (i.e., the first surface side) TFT-related film layer, that is, the design of the relevant film layer of the pixel drive circuit and other protective film layers. Taking the LTPS PMOS process as an example, a buffer layer, a first gate layer, a first gate insulation layer, an active layer, a second gate insulation layer, a second gate layer, an interlayer insulation layer, a first source-drain electrode layer, a first flat layer, a first passivation layer, a second source-drain electrode layer, a second passivation layer, and a second flat layer are sequentially stacked on the first surface. It should be noted that the relevant conductive layers in the pixel drive circuit are electrically connected to each other through vias that penetrate the insulating layer. The specific opening of the vias can be achieved by referring to the relevant technology, which will not be described in detail here. During production, the transfer pad needs to match the position of the conductive part. After the front process of the substrate substrate is completed, multiple binding terminals can be electrically connected to the relevant conductive layers in the pixel drive circuit through the conductive part, thereby realizing the connection of the front and back signals of the substrate substrate and ensuring the driving ability of the display panel. Then, the flexible circuit board is electrically connected to the multiple binding terminals, thereby ensuring the transmission of the control signal of the flexible circuit board through the multiple binding terminals. Then, the plurality of micro-LEDs are transferred to the display panel through a die bonding process and electrically connected to the pixel driving circuit. The die bonding process can be specifically implemented with reference to the relevant technology and will not be described in detail here.

[0172] Accordingly, in this exemplary embodiment, Fig. 27 As shown, step S104: forming a plurality of binding terminals on the second surface, including:

[0173] S401: filling metal material in the plurality of substrate vias, and forming a whole electrostatic protection layer on the second surface after obtaining the filling material and before sequentially forming a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit on the first surface;

[0174] S402: After sequentially forming a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit on the first surface, patterning the electrostatic protection layer to obtain an electrostatic protection portion and the plurality of binding terminals.

[0175] In the specific implementation process, when the filling material is an inorganic insulating material and / or an organic insulating material, based on Fig. 27 As shown, prepared using TGV technology Fig.17 The process flow chart corresponding to the display panel shown is as follows Fig.28As shown. Taking the front and back signal connections at the splicing edge of the display panel as an example, first, the TGV technology is used on the substrate to prepare the signal connection line vias required for the splicing edge at the signal input position of the splicing edge of the display panel. Accordingly, a plurality of substrate vias are opened along the thickness direction of the substrate substrate, and each substrate via connects the first surface and the second surface of the substrate substrate that are relatively arranged. Exemplarily, the Cu electroplating technology is used to make Cu connecting lines at the places where there are TGV vias on the glass substrate to form a conductive part. Then, a whole layer of electrostatic protection layer is formed on the second surface. The electrostatic protection layer can be an ITO film layer. ESD protection can be better performed by the whole layer of electrostatic protection layer.

[0176] Then, a glass substrate with a Cu connection line and a back electrostatic protection layer is used to design the front (i.e., one side of the first surface) TFT-related film layers, i.e., the design of the relevant film layers of the pixel drive circuit and other protective film layers. Taking the LTPSPMOS process as an example, a buffer layer, a first gate layer, a first gate insulation layer, an active layer, a second gate insulation layer, a second gate layer, an interlayer insulation layer, a first source-drain electrode layer, a first flat layer, a first passivation layer, a second source-drain electrode layer, a second passivation layer, and a second flat layer are sequentially stacked on the first surface. It should be noted that the relevant conductive layers in the pixel drive circuit are electrically connected to each other through vias that penetrate the insulating layer. The specific opening of the vias can be achieved by referring to the relevant technology, which will not be described in detail here. During production, the transfer pad needs to match the position of the conductive part. After the front process of the substrate is completed, the electrostatic protection layer is patterned by the back-end process, for example, laser etching is used to obtain an electrostatic protection part and a plurality of binding terminals. Each binding terminal is located at a corresponding position of the conductive part. The electrostatic protection part and the plurality of binding terminals do not overlap each other. Multiple binding terminals can be electrically connected to the relevant conductive layer in the pixel driving circuit through the conductive part, thereby realizing the connectivity of the signals on the front and back of the substrate, and ensuring the driving ability of the display panel. Then, the flexible circuit board is electrically connected to the multiple binding terminals, thereby ensuring the transmission of control signals by the flexible circuit board through the multiple binding terminals. Then, the multiple micro-light-emitting diodes are transferred to the display panel through the die bonding process and electrically connected to the pixel driving circuit. Among them, the die bonding process can be specifically implemented with reference to the relevant technology, and will not be described in detail here.

[0177] In the specific implementation process, Fig.29 Shown is based on Fig.26 The following is a schematic diagram of the back-end process manufacturing process corresponding to the embodiment of the present invention. Accordingly, the following steps are performed in sequence:

[0178] S10: front film;

[0179] S20: laser etching;

[0180] S30: flying probe test;

[0181] S40: Apply protective film (to protect the back circuit).

[0182] It should be noted that Fig.29 Compared to Figure 3 For the process flow shown, there is no Connect Pad on the front, so after the front film is applied, there is no need to cut or tear the film to expose the Connect Pad; moreover, there is no need for side process, and accordingly, there is no need for side laser etching process and edge grinding process. In this way, there is no need for side binding process, which avoids side short circuit, open circuit and corrosion; there is no need for coating protection layer (Over Coating, OC) protection. In this way, the process flow and preparation time are greatly shortened, and the related defects of the side process are eliminated, which improves the production line yield. In addition, since substrate vias can be opened on the substrate substrate through relevant opening technology in the embodiment of the present disclosure, such as TGV technology or TPV technology, the electrical connection of the relevant routing can be realized. Based on the higher opening accuracy of the opening technology, the pitch and size of the conductive part can be made smaller, for example, the size of the conductive part is ≥50μm, and the pitch is ≥100μm. In this way, the miniaturization design of the display panel is guaranteed.

[0183] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0184] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: include: A base substrate having a plurality of base substrate vias extending through the thickness direction, each of the base substrate vias being connected to a first surface and a second surface of the base substrate that are oppositely disposed; A pixel driving circuit and a plurality of micro light emitting diodes located on one side of the first surface and sequentially away from the base substrate; a plurality of driving signal lines located on one side of the first surface and electrically connected to the pixel driving circuit; a plurality of conductive parts disposed in the plurality of substrate via holes in a one-to-one correspondence, and a plurality of binding terminals located on one side of the second surface; At least one driving signal line among the plurality of driving signal lines is electrically connected to the binding terminal through a corresponding conductive portion.

2. The display panel according to claim 1, wherein: The entire space in the substrate via hole is filled with the conductive portion.

3. The display panel according to claim 1, wherein: Part of the space in the substrate via hole is filled with the conductive part, and the other part of the space is filled with the insulating part.

4. The display panel according to any one of claims 1 to 3, wherein: The conductive portion and the binding terminal are integrally formed.

5. The display panel according to claim 4, wherein: It also includes an electrostatic protection portion which is located at one side of the second surface and does not overlap with the binding terminal.

6. The display panel according to claim 5, wherein: The electrostatic protection portion and the plurality of binding terminals are provided in the same layer and made of the same material.

7. The display panel according to any one of claims 1 to 6, wherein: It also includes a plurality of transfer pads located on one side of the first surface and arranged one-to-one corresponding to the plurality of substrate vias, and at least one drive signal line among the plurality of drive signal lines is electrically connected to the binding terminal through the corresponding transfer pad and the conductive part in sequence.

8. The display panel according to claim 7, wherein: Along the second surface pointing to the first surface direction, the conductive layer of the pixel driving circuit includes a first gate layer, an active layer, a second gate layer, a first source-drain electrode layer and a second source-drain electrode layer which are arranged in sequence; an insulating layer is arranged between two adjacent conductive layers in the pixel driving circuit; and the multiple transfer pads are arranged on at least one layer of the first gate layer, the second gate layer, the first source-drain electrode layer and the second source-drain electrode layer.

9. The display panel according to claim 8, wherein: Any one of the plurality of driving signal lines is a power line; The power line is arranged on the second source-drain electrode layer, and is electrically connected to the corresponding conductive part through the adapter pad located on the first source-drain electrode layer.

10. The display panel according to claim 8, wherein: Any one of the plurality of driving signal lines is a data line; The data line is arranged on the first source-drain electrode layer, and is electrically connected to the corresponding conductive part through the transfer pad located on the first gate layer or the second gate layer.

11. The display panel according to claim 8, wherein: Any one of the plurality of driving signal lines is a gate line; The gate line is arranged on the second gate layer, and is electrically connected to the corresponding conductive part through the transfer pad located on the first source-drain electrode layer.

12. The display panel according to any one of claims 1 to 11, wherein: Along the direction from the second surface to the first surface, the variation trend of the cross-sectional area of ​​each substrate via hole or the cross-sectional area of ​​each conductive portion is any one of the following: A tendency to decrease first and then increase; A tendency to increase first and then decrease; The tendency to increase; decreasing trend; The same big trend.

13. The display panel according to any one of claims 1 to 12, wherein: The plurality of substrate via holes are disposed in an edge region and / or a middle region of the display panel.

14. The display panel according to claim 13, wherein: The plurality of substrate via holes are arranged in at least one row along a direction parallel to a side extension of the display panel.

15. A spliced ​​display device, wherein: include: A plurality of display panels according to any one of claims 1 to 14.

16. A method for manufacturing a display panel, wherein: include: A plurality of substrate via holes are provided along a thickness direction of the substrate, each of the substrate via holes being connected to a first surface and a second surface of the substrate that are oppositely disposed; disposing a filling material in the plurality of substrate via holes; A pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit are sequentially formed on one side of the first surface; forming a plurality of binding terminals on one side of the second surface so that at least one of the plurality of driving signal lines is electrically connected to the binding terminal through the conductive portion obtained by the filling material; The pixel driving circuit is bound and connected to a plurality of micro light emitting diodes.

17. The method of claim 16, wherein: Providing a filling material in the plurality of substrate via holes, comprising: The filling material is obtained by filling the plurality of substrate via holes with an inorganic insulating material and / or an organic insulating material.

18. The method of claim 16, wherein: The forming of a plurality of binding terminals on the second surface comprises: After sequentially forming a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit on the first surface, opening a through hole on the second surface along a thickness direction penetrating the filling material; Conductive material is deposited in a region corresponding to the through hole, and the conductive material is patterned to form the conductive portion in the through hole, and a plurality of binding terminals integrally formed with the conductive portion are formed on the second surface.

19. The method of claim 16, wherein: Providing a filling material in the plurality of substrate via holes, comprising: The metal material is filled into the plurality of substrate via holes through an electroplating process to obtain the filling material, and the filling material is used as the conductive part.

20. The method of claim 19, wherein: The forming of a plurality of binding terminals on the second surface comprises: After the metal material is filled in the plurality of substrate via holes to obtain the filling material and before a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit are sequentially formed on the first surface, a whole electrostatic protection layer is formed on the second surface; The electrostatic protection layer is patterned to obtain an electrostatic protection portion and the plurality of binding terminals.

21. The method of claim 19, wherein: The forming of a plurality of binding terminals on the second surface comprises: After the metal material is filled in the plurality of substrate via holes to obtain the filling material and before a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit are sequentially formed on the first surface, a whole electrostatic protection layer is formed on the second surface; After sequentially forming a pixel driving circuit and a plurality of driving signal lines electrically connected to the pixel driving circuit on the first surface, the electrostatic protection layer is patterned to obtain an electrostatic protection portion and the plurality of binding terminals.

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