Distributed phased array system and electronic equipment

Abstract

The present application discloses a distributed phased array system and electronic equipment, which relates to the field of signal processing technology, including: multiple antenna units; active transceiver units connected one-to-one with each antenna unit; a frequency source connected to each active transceiver unit, used to control the frequency conversion synchronization in each active transceiver unit and synchronize and calibrate the clock of each active transceiver unit; a signal processing unit connected to each active transceiver unit, used to synchronize the signal processing of each active transceiver unit based on the clock after synchronization calibration. By ensuring the frequency conversion synchronization, clock synchronization and signal processing synchronization between each active transceiver unit, the synchronization of the transmitted signals in each active transceiver unit can be ensured, that is, the synchronization of multi-channel signal input and output can be improved, and the synchronization performance between multi-channel signal transceiver channels can be improved.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a distributed phased array system and electronic equipment. Background Art

[0002] With the development of radar, 5G communication and satellite communication technologies, digital phased array technology has become one of the key technologies in these fields. Digital phased array technology can realize the control of beam direction in radar systems and communication systems, and has the advantages of flexible beam pointing, large target capacity, and strong anti-interference ability. However, in large-scale digital phased array systems, distributed radar systems, and distributed ultra-large-scale MIMO (Multiple Input Multiple Output) systems, the input and output synchronization of multiple signals has become a technical challenge.

[0003] Therefore, it is necessary to study a new synchronous input and output technology to solve the problem of poor synchronization of multi-channel signal input and output and improve the synchronization performance between multi-channel signal transmission and reception channels. Summary of the invention

[0004] The main purpose of the present application is to provide a distributed phased array system, a distributed phased array system and an electronic device, aiming to solve the technical problem of poor synchronization of multi-channel signal input and output.

[0005] To achieve the above objectives, the present application proposes a distributed phased array system, which includes:

[0006] multiple antenna elements;

[0007] An active transceiver unit connected one-to-one with each antenna unit;

[0008] A frequency source connected to each active transceiver unit, used to control the frequency conversion synchronization in each active transceiver unit and to perform synchronization calibration on the clock of each active transceiver unit;

[0009] The signal processing unit connected to each active transceiver unit is used to synchronize the signal processing of each active transceiver unit based on the synchronously calibrated clock.

[0010] In one embodiment, a local oscillator phase-locked loop, a sampling clock phase-locked loop and a reference clock phase-locked loop are provided in the active transceiver unit;

[0011] The local oscillator phase-locked loop receives the clock signal output by the frequency source and generates a local oscillation signal according to the clock signal;

[0012] The sampling clock phase-locked loop receives the clock signal output by the frequency source and generates a sampling clock signal according to the clock signal;

[0013] The reference clock phase-locked loop receives the clock signal output by the frequency source and generates an output reference clock signal based on the clock signal.

[0014] In one embodiment, each active transceiver unit further includes an analog-to-digital signal transmission channel and a digital-to-analog signal transmission channel;

[0015] The analog-to-digital signal transmission channel is used to perform first signal transmission on a first signal received from the antenna unit;

[0016] The digital-to-analog signal transmission channel is used to perform second signal transmission on a second signal received from the signal processing unit.

[0017] In one embodiment, the analog-to-digital signal transmission channel includes a low noise amplifier, a first multiplier, an analog-to-digital converter, and a signal collector;

[0018] The input end of the low noise amplifier is connected to the corresponding antenna unit, the output end of the low noise amplifier is connected to the first input end of the first multiplier, and the second input end of the first multiplier is connected to the local oscillation signal to control the first multiplier in each analog-to-digital signal transmission channel to synchronously perform the frequency conversion operation in the first signal transmission;

[0019] The output end of the first multiplier is connected to the first input end of the analog-to-digital converter, and the second output end of the analog-to-digital converter is connected to the sampling clock signal to provide the same first time reference for the analog-to-digital converters in each analog-to-digital signal transmission channel;

[0020] The output end of the analog-to-digital converter is connected to the first input end of the signal collector, and the second input end of the signal collector is connected to the reference clock signal to calibrate the collection clock of the signal collector in each analog-to-digital signal transmission channel.

[0021] In one embodiment, the digital-to-analog signal transmission channel includes a power amplifier, a second multiplier, a digital-to-analog converter, and a signal player;

[0022] The first input terminal of the signal player is connected to the signal processing unit, and the second input terminal of the signal player is connected to the reference clock signal to calibrate the playing clock of the signal player in each digital-analog signal transmission channel;

[0023] The output end of the signal player is connected to the first input end of the digital-to-analog converter, and the second input end of the digital-to-analog converter is connected to the sampling clock signal to provide the same second time reference for the digital-to-analog converters in each digital-to-analog signal transmission channel;

[0024] The output end of the digital-to-analog converter is connected to the first input end of the second multiplier, and the second input end of the second multiplier is connected to the local oscillation signal to control the second multipliers in each digital-to-analog signal transmission channel to synchronously perform the frequency conversion operation in the second signal transmission;

[0025] The output end of the second multiplier is connected to the input end of the power amplifier, and the output end of the power amplifier is connected to the corresponding antenna unit.

[0026] In one embodiment, a signal processing unit;

[0027] It is used to output a synchronous trigger pulse signal to the signal collector according to the connected reference clock signal, so as to control the signal collector in each active transceiver unit to perform the collection operation in the first signal transmission at the same time point.

[0028] In one embodiment, a plurality of first-in-first-out devices are provided in the signal processing unit, the number of the first-in-first-out devices corresponds to the number of the active transceiver units, and one first-in-first-out device is connected to the signal collector in the corresponding active transceiver unit;

[0029] A first-in-first-out device, used for storing the first signal transmitted from the signal collector;

[0030] The signal processing unit is further used to read the first signal stored in each first-in-first-out device and perform a signal processing operation when it is detected that the corresponding first signal is stored in each first-in-first-out device.

[0031] In one embodiment, the distributed phased array system further includes a calibration network and a calibration module;

[0032] Each antenna unit is connected to a corresponding active transceiver unit via a calibration network, a first interactive end of the calibration module is connected to the calibration network, and a second interactive end of the calibration module is connected to a frequency source;

[0033] A calibration network, used for collecting each time point at which each active transceiver unit transmits the second signal to the corresponding antenna unit, and sending each time point to the calibration module;

[0034] The calibration module is used to calibrate the time frequency of the local oscillation signal output by the frequency source, the time frequency of the sampling clock signal and the time frequency of the reference clock signal according to each accessed time point.

[0035] In one embodiment, the active transceiver unit further includes an optical module;

[0036] One end of the optical module is connected to the signal collector and the signal player respectively, and the other end of the optical module is connected to the signal processing unit;

[0037] It is used to convert the first signal transmitted by the signal collector into a collection light signal and transmit it to the signal processing unit, and to convert the playback light signal transmitted by the signal processing unit into a second signal and transmit it to the signal player.

[0038] In addition, to achieve the above-mentioned purpose, the present application also proposes an electronic device, which includes the distributed phased array system as described above.

[0039] One or more technical solutions proposed in this application have at least the following technical effects:

[0040] A distributed phased array system is proposed, which includes: a plurality of antenna units; an active transceiver unit connected one-to-one with each antenna unit; a frequency source connected to each active transceiver unit, used to control the frequency conversion synchronization in each active transceiver unit and to synchronize and calibrate the clock of each active transceiver unit; and a signal processing unit connected to each active transceiver unit, used to synchronize the signal processing of each active transceiver unit based on the clock after synchronization and calibration.

[0041] Through frequency conversion synchronization, it is possible to ensure that each active transceiver unit performs frequency conversion at the same time point, and maintain the consistency of the phase of the first signal received from the corresponding antenna unit; and through clock synchronization, it is possible to ensure that each transceiver unit uses the same time reference, and ensure that signal acquisition and signal processing are performed at precisely aligned time points; then based on signal processing synchronization, it is possible to ensure that the first signal on the active transceiver unit is sampled and converted to the second signal at the same time. Therefore, by ensuring frequency conversion synchronization, clock synchronization and signal processing synchronization between each active transceiver unit, the synchronization of the transmitted signals in each active transceiver unit can be ensured, that is, the synchronization of multi-channel signal input and output can be improved, and the synchronization performance between multi-channel signal transceiver channels can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 This is a schematic diagram of the structure of the distributed phased array system of this application;

[0045] Figure 2 This is a schematic diagram of the connection between the frequency source and the active transceiver unit of this application;

[0046] Figure 3 This is a schematic diagram of the structure of the analog-to-digital signal transmission channel and the digital-to-analog signal transmission channel of the present application;

[0047] Figure 4 This is a schematic diagram of the requirements for generating a synchronous trigger pulse signal for this application;

[0048] Figure 5 A schematic diagram of the generation requirements for the acquisition trigger signal for this application;

[0049] Figure 6 This is a schematic diagram of the connection between the first-in-first-out device in the signal processing unit of the present application and the signal collector in the active transceiver unit;

[0050] Figure 7 This is a schematic diagram of the structure of the signal transceiver processing board of this application;

[0051] Figure 8 The figure is a schematic diagram of the test results of signal synchronization input and output between signal transceiver processing boards in the distributed phased array system proposed in the present application.

[0052] Description of Figure Numbers:

[0053] 10. Antenna unit; 20. Active transceiver unit;

[0054] U1, low noise amplifier; MUX1, first multiplier;

[0055] U2, power amplifier; MUX2, second multiplier;

[0056] FIFO, first-in-first-out device.

[0057] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0058] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0059] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0060] The main solution of the embodiment of the present application is: a distributed phased array system is proposed, which includes: multiple antenna units; an active transceiver unit connected one-to-one with each antenna unit; a frequency source connected to each active transceiver unit, used to control the frequency conversion synchronization in each active transceiver unit and synchronize and calibrate the clock of each active transceiver unit; a signal processing unit connected to each active transceiver unit, used to synchronize the signal processing of each active transceiver unit based on the clock after synchronization and calibration.

[0061] Due to the existing technology, the input and output synchronization of multiple signals has become a technical challenge in large digital phased array systems, distributed radar systems, and distributed ultra-large-scale MIMO systems. Therefore, it is necessary to study a new synchronous input and output technology to solve the problem of poor synchronization of multiple signal input and output and improve the synchronization performance between multiple signal transceiver channels.

[0062] The present application provides a solution, which can ensure that each active transceiver unit performs frequency conversion at the same time point through frequency conversion synchronization, and maintain the consistency of the phase of the first signal received from the corresponding antenna unit; and through clock synchronization, it can ensure that each transceiver unit uses the same time reference, and ensure that signal acquisition and signal processing are performed at precisely aligned time points; then based on signal processing synchronization, it can ensure that the first signal on the active transceiver unit is sampled and converted into the second signal at the same time. Therefore, by ensuring the frequency conversion synchronization, clock synchronization and signal processing synchronization between each active transceiver unit, the synchronization of the transmission signal in each active transceiver unit can be ensured, that is, the synchronization of multi-channel signal input and output can be improved, and the synchronization performance between multi-channel signal transceiver channels can be improved.

[0063] It should be noted that the execution subject of this embodiment may be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, etc. The following takes an electronic device as an example to illustrate this embodiment and the following embodiments.

[0064] Based on this, the embodiment of the present application provides a distributed phased array system, referring to Figure 1 , Figure 1 This is a schematic diagram of the structure of the distributed phased array system of this application.

[0065] In this embodiment, the distributed phased array system includes:

[0066] A plurality of antenna units 10; an active transceiver unit 20 connected one-to-one with each antenna unit 10; a frequency source connected to each active transceiver unit 20, used to control the frequency conversion synchronization in each active transceiver unit 20 and to synchronize and calibrate the clock of each active transceiver unit 20; a signal processing unit connected to each active transceiver unit 20, used to synchronize the signal processing of each active transceiver unit 20 based on the synchronized and calibrated clock.

[0067] according to Figure 1It can be seen that in the present embodiment, the connection path of an antenna unit 10-an active transceiver unit 20-a signal processing unit is equal to a signal input and output path. In order to improve the signal input and output synchronization between the signal input and output paths, it is proposed to set a frequency source, and synchronize and calibrate the frequency conversion and clock in each active transceiver unit 20 through the frequency source, so that each active transceiver unit 20 can synchronously perform the frequency conversion operation of the first signal connected at the same time point, realize the phase unification of the first signal in each active transceiver unit 20, and unify the time base of the active transceiver unit 20, so as to avoid the situation that the signal input and output process cannot be unified due to the inconsistent time of each active transceiver unit 20.

[0068] At the same time, through the signal processing unit connected to each active transceiver unit 20, based on the synchronously calibrated clock, a synchronous signal processing operation is performed on the first signal connected from each active transceiver unit 20 at the same time point as each active transceiver unit 20, which can ensure that each active transceiver unit 20 is aligned on the time axis, and the signal processing operation of the signal processing unit on each active transceiver unit 20 will not produce a phase difference or time misalignment due to time delay, which can ensure the synchronization of the signal processing operation between each active transceiver unit 20, and further ensure that the first signal on each active transceiver unit 20 can be connected by the signal processing unit for signal processing at the same time, converted into a second signal and returned to each active transceiver unit 20, so as to be transmitted to the corresponding antenna unit 10 for playback, that is, it can ensure that each active transceiver unit 20 can perform signal input and signal output at the same time, so as to capture or form a specific beam, improve the performance of the distributed phased array system, and reduce errors.

[0069] Specifically, refer to Figure 2 As shown, the active transceiver unit 20 is provided with a local oscillator phase-locked loop, a sampling clock phase-locked loop and a reference clock phase-locked loop;

[0070] The local oscillator phase-locked loop is connected to the clock signal output by the frequency source, and generates a local oscillation signal based on the clock signal; the sampling clock phase-locked loop is connected to the clock signal output by the frequency source, and generates a sampling clock signal based on the clock signal; the reference clock phase-locked loop is connected to the clock signal output by the frequency source, and generates an output reference clock signal based on the clock signal.

[0071] It should be noted that the locking loop in the active transceiver unit 20 is used to access the signal output by the frequency source, and after corresponding conversion, transmit it to the corresponding device.

[0072] Specifically, the frequency source in this embodiment is a high-stability clock source + a power divider amplifier, because according to Figure 2It can be seen that a clock signal output by a high-stable clock source needs to be distributed to the local oscillator phase-locked loop, sampling clock phase-locked loop and reference clock phase-locked loop of each active transceiver unit 20. Therefore, it is necessary to configure a power divider amplifier based on the high-stable clock source, and use the power divider amplifier to divide the clock signal into multiples of three identical clock signals, and then amplify the multiples of three clock signals and distribute them to the local oscillator phase-locked loop, sampling clock phase-locked loop and reference clock phase-locked loop of each active transceiver unit 20 respectively, so as to achieve output of the same clock signal to the local oscillator phase-locked loop, sampling clock phase-locked loop and reference clock phase-locked loop while ensuring that the clock signal has sufficient power during the distribution process, which can meet the power requirements of each phase-locked loop for the clock signal and compensate for the signal loss caused by power division.

[0073] Based on Figure 2 It can be seen that a centimeter amplifier and a local oscillator are provided in the local oscillator phase-locked loop, wherein the centimeter amplifier is used to provide a stable gain, ensuring that the clock signal level of the entire local oscillator phase-locked loop is appropriate, and the performance of the entire local oscillator phase-locked loop will not be affected by the fluctuation of the clock signal strength; and the local oscillator, as a key component in the entire local oscillator phase-locked loop, is used to generate a local oscillation signal whose frequency can be controlled by the local oscillator phase-locked loop. The related devices in each active transceiver unit 20 are connected to the same local vibration signal, so that each active transceiver unit 20 can perform a frequency conversion operation of the first signal based on the same local oscillation signal, and realize the phase unification of the first signal after the frequency conversion.

[0074] A centimeter amplifier and a sampling clock are provided in the sampling clock phase-locked loop, wherein the centimeter amplifier is used to provide a stable gain, ensuring that the clock signal level of the entire sampling clock phase-locked loop is appropriate, and the performance of the entire sampling clock phase-locked loop will not be affected by the fluctuation of the clock signal strength; and the sampling clock is a key component in the entire sampling clock phase-locked loop, and is used to generate a sampling clock signal whose frequency can be controlled by the sampling clock phase-locked loop. The relevant devices in each active transceiver unit 20 are connected to the sampling clock signal, so that each active transceiver unit 20 can set a unified time reference based on the same sampling clock signal.

[0075] A centimeter amplifier and a reference clock are provided in the reference clock phase-locked loop, wherein the centimeter amplifier is used to provide a stable gain, ensuring that the clock signal level of the entire reference clock phase-locked loop is appropriate, and the performance of the entire reference clock phase-locked loop will not be affected by the fluctuation of the clock signal strength; and the reference clock is a key component in the entire reference clock phase-locked loop, and is used to generate a reference clock signal whose frequency can be controlled by the reference clock phase-locked loop. The related devices in each active transceiver unit 20 are connected to the reference clock signal, which enables each active transceiver unit 20 to calibrate the set time base based on the same reference clock signal, further improving the alignment of the time bases of each active transceiver unit 20.

[0076] Because the present embodiment is based on a frequency source transmitting an identical clock signal to the phase-locked loop in each active transceiver unit 20, the clock signal can be distributed at multiple points in the distributed phased array system, rather than being transmitted from a frequency source to each active transceiver unit 20. Therefore, some active transceiver units 20 can directly obtain the clock signal from the adjacent active transceiver units 20, thereby reducing the number of RF cables connecting the active transceiver units 20 to the frequency source. At the same time, because the high-stability clock source outputs a low-frequency clock signal, the requirements for the RF cable connected between the frequency source and the active transceiver unit 20 are not high.

[0077] Furthermore, each active transceiver unit 20 also includes an analog-to-digital signal transmission channel and a digital-to-analog signal transmission channel;

[0078] The analog-to-digital signal transmission channel is used to perform the first signal transmission of the first signal received from the antenna unit 10, that is, the analog-to-digital signal transmission channel is equivalent to the signal input channel, which receives the first signal input by the antenna unit 10 from the antenna unit 10 to which its active transceiver unit 20 is connected, and performs the corresponding first signal transmission processing operation.

[0079] The digital-to-analog signal transmission channel is used to perform a second signal transmission on a second signal connected from the signal processing unit, that is, the digital-to-analog signal transmission channel is equivalent to a signal output channel, which receives the second signal generated after signal processing from the signal processing unit connected to the active transceiver unit 20 to which it belongs, and performs the corresponding second signal transmission processing operation.

[0080] Further, refer to Figure 1 It can be seen that the distributed phased array system also includes a calibration network and a calibration module;

[0081] Each antenna unit 10 is connected to the corresponding active transceiver unit 20 via a calibration network, the first interactive end of the calibration module is connected to the calibration network, and the second interactive end of the calibration module is connected to the frequency source; the calibration network is used to collect each time point when each active transceiver unit 20 transmits the second signal to the corresponding antenna unit 10, and send each time point to the calibration module; the calibration module is used to calibrate the time frequency of the local oscillation signal output by the frequency source, the time frequency of the sampling clock signal, and the time frequency of the reference clock signal according to each connected time point.

[0082] In order to further improve the synchronization of signal input and output, a calibration network and a calibration module are further provided in the distributed phased array system in this embodiment.

[0083] Among them, the calibration network is connected between each antenna unit 10 and its corresponding active transceiver unit 20 transceiver unit, and is used to obtain the time point when each active transceiver unit 20 transmits the second signal to its corresponding antenna unit 10 when the active transceiver unit 20 transmits the second signal to its corresponding antenna unit 10, and send each time point to the calibration module. The calibration module analyzes the received time points to determine whether the time points are aligned. If the time points can be aligned, it means that each active transceiver unit 20 can transmit the second signal to its corresponding antenna unit 10 at the same time point, and the signal output has high synchronization.

[0084] If the clocks at different time points cannot be aligned, it means that some active transceiver units 20 cannot transmit the second signal to their corresponding antenna units 10 at the same time point. The calibration module will adjust the time frequency of the current clock signal connected from the frequency source based on the access time point, return the adjusted clock signal to the frequency source, and control the frequency source to output a new clock signal according to the adjusted clock signal, so as to calibrate the time point of signal output and improve the synchronization of signal output.

[0085] In one possible implementation, refer to Figure 3 As shown, each active transceiver unit 20 also includes an analog-to-digital signal transmission channel, and the analog-to-digital signal transmission channel is used to perform a first signal transmission on a first signal received from the antenna unit 10;

[0086] The analog-to-digital signal transmission channel includes a low-noise amplifier U1, a first multiplier MUX1, an analog-to-digital converter and a signal collector.

[0087] The input end of the low noise amplifier U1 is connected to the corresponding antenna unit 10, the output end of the low noise amplifier U1 is connected to the first input end of the first multiplier MUX1, and the second input end of the first multiplier MUX1 is connected to the local oscillation signal to control the first multiplier MUX1 in each analog-to-digital signal transmission channel to synchronously perform the frequency conversion operation in the first signal transmission. In order to ensure the analog-to-digital signal transmission channel in each active transceiver unit 20, the first signal received from the corresponding antenna unit 10 can be frequency-converted and converted into an intermediate frequency at the same time point. After the low noise amplifier U1 in the analog-to-digital signal transmission channel in this embodiment receives the first signal transmitted by the corresponding antenna unit 10, the noise in the first signal is first filtered by the low noise amplifier U1, and then amplified, so as to effectively reduce the noise coefficient received and improve the signal-to-noise ratio while increasing the power level of the first signal. The filtered first signal is then transmitted to the first multiplier MUX1. The first multiplier MUX1 multiplies the connected first signal by the connected local oscillation signal to frequency-convert the first signal to obtain the frequency-converted first signal, and transmits the frequency-converted first signal to the analog-to-digital converter. Since the first multipliers MUX1 in the active transceiver units 20 in the same distributed phased array system are connected to the same local oscillation signal, the phases of the first signals after frequency conversion by each first multiplier MUX1 are the same, thereby achieving frequency conversion local oscillation synchronization of each active transceiver unit 20.

[0088] The output end of the first multiplier MUX1 is connected to the first input end of the analog-to-digital converter, and the second output end of the analog-to-digital converter is connected to the sampling clock signal to provide the same first time reference for the analog-to-digital converters in each analog-to-digital signal transmission channel. When the analog-to-digital converter in each active transceiver unit 20 is connected to the first signal transmitted by the corresponding first multiplier MUX1, the analog-to-digital converter will first calibrate the internal clock based on the connected sampling clock signal. Because the analog-to-digital converters in the active transceiver units 20 in the same distributed phased array system are connected to the same sampling clock signal, the first time reference obtained after calibration based on the same sampling clock signal is the same, so that each analog-to-digital converter can perform analog-to-digital conversion of the first signal at the same time point, unifying the conversion time of each analog-to-digital converter.

[0089] The output end of the analog-to-digital converter is connected to the first input end of the signal collector, and the second input end of the signal collector is connected to the reference clock signal to calibrate the acquisition clock of the signal collector in each analog-to-digital signal transmission channel. The signal acquisition in each active transceiver unit 20 will first calibrate the internal signal acquisition clock based on the connected reference clock signal. Because the signal collectors in the active transceiver units 20 in the same distributed phased array system are connected to the same reference clock signal, the signal acquisition clocks calibrated based on the same reference clock signal are the same, so that each signal collector can collect the first signal converted in its corresponding analog-to-digital converter at the same time point, unifying the acquisition time of each signal collector.

[0090] In one possible implementation, refer to Figure 3 As shown, the digital-to-analog signal transmission channel includes a power amplifier, a second multiplier MUX2, a digital-to-analog converter and a signal player;

[0091] The first input end of the signal player is connected to the signal processing unit, and the second input end of the signal player is connected to the reference clock signal to calibrate the playback clock of the signal player in each digital-to-analog signal transmission channel. The signal playback in each active transceiver unit 20 will first calibrate the internal signal playback clock based on the reference clock signal that is connected. Because the signal players in the active transceiver units 20 in the same distributed phased array system are connected to the same reference clock signal, the signal playback clocks calibrated based on the same reference clock signal are the same, so that each signal player can play the second signal connected from the signal processor at the same time point, unifying the playback time of each signal player playing the connected second signal to the digital-to-analog converter.

[0092] The output end of the signal player is connected to the first input end of the digital-to-analog converter, and the second input end of the digital-to-analog converter is connected to the sampling clock signal to provide the same second time reference for the digital-to-analog converters in each digital-to-analog signal transmission channel. When the digital-to-analog converter in each active transceiver unit 20 is connected to the second signal transmitted by its corresponding signal player, the digital-to-analog converter will first calibrate the internal clock based on the connected sampling clock signal. Because the digital-to-analog converters in the active transceiver units 20 in the same distributed phased array system are connected to the same sampling clock signal, the second time reference obtained after calibration based on the same sampling clock signal is the same, so that each digital-to-analog converter can perform digital-to-analog conversion of the second signal at the same time point, unifying the conversion time of each digital-to-analog converter.

[0093] The output end of the digital-to-analog converter is connected to the first input end of the second multiplier MUX2, and the second input end of the second multiplier MUX2 is connected to the local oscillation signal to control the second multiplier MUX2 in each digital-to-analog signal transmission channel to synchronously perform the frequency conversion operation in the second signal transmission. The second multiplier MUX2 multiplies the second signal transmitted by its corresponding digital-to-analog converter by the connected local oscillation signal to convert the frequency of the second signal to obtain the second signal after the frequency conversion, and transmits the second signal after the frequency conversion to the power amplifier, wherein, because the second multiplier MUX2 in the active transceiver unit 20 in the same distributed phased array system is connected to the same local oscillation signal, the phase of the second signal after the frequency conversion by each second multiplier MUX2 is the same, so that the frequency conversion local oscillation synchronization of each active transceiver unit 20 is achieved.

[0094] The output end of the second multiplier MUX2 is connected to the input end of the power amplifier, and the output end of the power amplifier is connected to the corresponding antenna unit 10. After receiving the second signal transmitted by the corresponding second multiplier MUX2, the power amplifier in the digital-to-analog signal transmission channel in this embodiment amplifies the output second signal and then transmits it to the corresponding antenna unit 10.

[0095] It should be noted that according to Figure 1 It can be seen that the signal player and the signal collector in this embodiment can be arranged in the same integrated circuit board.

[0096] in, Figure 3 LO is the local oscillator phase-locked loop, Clock is the sampling clock phase-locked loop, and Pulse is the reference clock phase-locked loop.

[0097] In a feasible implementation manner, the active transceiver unit 20 further includes an optical module;

[0098] One end of the optical module is connected to the signal collector and the signal player respectively, and the other end of the optical module is connected to the signal processing unit; it is used to convert the first signal transmitted from the signal collector into a collection optical signal and transmit it to the signal processing unit, and to convert the playback optical signal transmitted from the signal processing unit into a second signal and transmit it to the signal player.

[0099] In this embodiment, the first signal transmitted by the signal collector is converted into a collected optical signal through an optical module, and the playback optical signal transmitted by the signal processing unit is converted into a second signal, so that the signal between the active transceiver unit 20 and the signal processing unit uses optical fiber as the data transmission medium, thereby reducing the attenuation of the signal transmission between the active transceiver unit 20 and the signal processing unit, thereby ensuring the effective transmission and quality of the signal.

[0100] In a feasible implementation, the signal processing unit is used to output a synchronous trigger pulse signal to the signal collector based on the connected reference clock signal to control the signal collectors in each active transceiver unit 20 to perform the collection operation in the first signal transmission at the same time point.

[0101] In order to further improve the synchronization of the first signal acquisition from the corresponding analog-to-digital converter of each signal collector in this embodiment, it is proposed to trigger the acquisition operation of the signal collector through the signal processing unit. Specifically, the reference clock signal is accessed through the signal processing unit, and the clock in the signal processing unit is calibrated, so that the signal processing unit is aligned with the time in the signal collector, and then a synchronous trigger pulse signal is output to each signal processing unit. Because the time in the signal processing unit and each signal collector is aligned, each signal collector can be controlled to collect the first signal in its corresponding analog-to-digital converter at the same time point, thereby improving the synchronization of the first signal acquisition between each signal collector.

[0102] For details, refer to Figure 4 As shown, the clock used by the synchronous trigger pulse signal sent by the signal processing unit (i.e. Figure 4 The DBF_CLK in the signal collector must be consistent with the acquisition clock used by each signal collector (i.e. Figure 4 FPGA1_CLK, FPGA2_CLK and FPGAn_CLK in the signal processing unit use the same frequency, which is usually between 10 MHz and 100 MHz. At the same time, refer to the synchronous trigger pulse signal sent by the signal processing unit (i.e. Figure 4 The frequency of the DBF_PRT in the signal collector and the synchronous trigger pulse signal received by the signal collector (i.e. Figure 4 It can be seen from FPGA1_PRT, FPGA2_PRT and FPGAn_PRT in the figure that the time for the synchronization pulse signal sent by the signal processing unit to be recognized by the signal collector is short, and each signal collector can recognize the synchronization trigger pulse signal generated by the same frequency at the same time to collect the first signal, which further improves the synchronization of signal collection. In order to ensure the stability and reliability of the synchronization trigger pulse signal, the signal amplitude and phase of the synchronization trigger pulse signal are constant or change very little.

[0103] At the same time, refer to Figure 5 As shown, if the signal collector collects the acquisition trigger signal (i.e. Figure 5 No OK ADC_TRI) in the parameter clock signal (i.e. Figure 5When the ADC_CLK in the ADC is established near the rising edge, there will be a metastable state when different signal collectors among the multiple active transceiver units 20 collect the first signal of the corresponding analog-to-digital converter, which will cause uncertainty in the synchronization of the first signal collection of different signal collectors. Therefore, in order to ensure the consistency of the first signal collected by different signal collectors, it is necessary to ensure that the signal collectors collect the analog-to-digital converter in the safe collection range (i.e. Figure 5 Nok in), and set the sampling trigger signal (ie Figure 5 The REF_CLK in the parameter clock signal is established near the falling edge of the parameter clock signal, that is, the reverse edge triggering mode of the same source clock is adopted, which can not only reduce the cable synchronization requirements of the synchronous trigger pulse signal, but also ensure the collection consistency of each signal collector to the corresponding analog-to-digital converter, thereby improving the synchronization accuracy of the reception and transmission of the distributed phased array system frequency signal.

[0104] In one possible implementation, refer to Figure 6 As shown, a plurality of first-in-first-out devices FIFO are provided in the signal processing unit, the number of the first-in-first-out device FIFO corresponds to the number of the active transceiver units 20, and one first-in-first-out device FIFO is connected to the signal collector in the corresponding active transceiver unit 20;

[0105] The first-in-first-out device FIFO is used to store the first signal transmitted by the signal collector; the signal processing unit is also used to read the first signal stored in each first-in-first-out device FIFO and perform signal processing operations when it is detected that the corresponding first signal is stored in each first-in-first-out device FIFO.

[0106] When frequency conversion synchronization and acquisition synchronization are achieved through the above content, because the first signal between the signal collector and the signal processing unit is converted into optical signal data based on the optical module and then transmitted through the optical fiber, and due to the difference in optical fiber length, the first signal received by the signal processing unit from each signal collector has an access time difference, which in turn makes the signal processing unit have a difference in the signal processing operation of the first signal transmitted from each signal collector, resulting in asynchrony in the operation of reaching the signal processing unit and performing signal processing.

[0107] Therefore, in order to ensure that the first signal in each signal collector can be synchronously processed in the signal processing unit, this embodiment proposes to set up the same number of first-in-first-out devices FIFO as the active transceiver units 20 in the signal processing unit. Because one signal collector is set in one active transceiver unit 20, one first-in-first-out device FIFO can be connected to one signal collector accordingly. After the signal collector acquires the first signal from its corresponding analog-to-digital converter according to the synchronous trigger pulse signal, the signal collector converts the first signal into optical signal data through the optical module, and then transmits the optical signal data to the connected first-in-first-out device FIFO through the optical fiber, and first stores the optical signal data in the first-in-first-out device FIFO. At the same time, the signal processing unit detects whether each first-in-first-out device FIFO stores optical signal data. If it is detected that there is a first-in-first-out device FIFO that does not store optical signal data, the operation of signal processing on the optical signal data is not performed at this time, and the optical signal data is controlled to be stored in the first-in-first-out device FIFO; if it is detected that each first-in-first-out device FIFO stores optical signal data, the signal processing unit will simultaneously read the optical signal data stored in each first-in-first-out device FIFO, obtain the optical signal data in each first-in-first-out device FIFO, and simultaneously perform signal processing on each optical signal data, so as to ensure that the first signal in each signal collector can be simultaneously subjected to signal processing operations in the signal processing unit, so as to achieve signal processing synchronization between each active transceiver unit 20.

[0108] It should be noted that after the signal processing unit reads the optical signal data stored in each FIFO unit, in order to ensure that the next signal processing operation will not be affected by the current signal processing operation, it is necessary to perform a synchronous reset operation on each FIFO unit so that each FIFO unit can be restored to its initial state to avoid data interference caused by the current optical signal data stored therein to the next signal processing operation. In addition, in order to avoid data loss due to overload when the FIFO device receives the optical signal data transmitted by the signal collector to which it is connected, it is also proposed to set an overflow protection mechanism in each FIFO device.

[0109] The present application also provides an electronic device, which includes the distributed phased array system as described above.

[0110] The signal transceiver processing board corresponding to an active transceiver unit in the distributed phased array system proposed in the present application can be composed of Figure 7As shown, a signal transceiver processing board is equivalent to one signal input and output. The signal transceiver processing board mainly consists of 1 FPGA (used to set the signal collector and signal player, its model is XC7K325T-FFG900), 1 multi-channel high-speed ADC chip (i.e. the analog-to-digital converter in the above embodiment, its model is AD9680), 1 multi-channel high-speed DAC chip (i.e. the digital-to-analog converter in the above embodiment, its model is AD9164), 1 clock phase-locked loop chip (used to set the local oscillator phase-locked loop, the sampling clock phase-locked loop and the reference clock phase-locked loop, its model is HMC7004), an optical module, two memories (i.e. Figure 7 The storage memory is 128Kb EEPROM and the storage memory is 256Mb SPI Flash), serial communication interface (ie Figure 7 RS422 in), power management module (ie Figure 7 Power), high-speed serial interface (i.e. Figure 7 JESD204B) and data interface (i.e. Figure 7 J30J data interface in the ).

[0111] As can be seen from the figure, the clock phase-locked loop chip is external (i.e. Figure 7 The SMP in the Figure 7 RF_SYNC) and the clock signal (i.e. Figure 7 The Ref Clock in the clock signal is used to realize the synchronization function of the intermediate frequency signal reception and transmission of each signal reception and processing board, which reduces the interconnection mode in each signal reception and processing board. At the same time, based on one clock signal, it saves clock resources and reduces the system cost of the distributed phased array system. The clock phase-locked loop chip processes the clock signal and the RF synchronization signal accordingly and outputs the clock signal (i.e. Figure 7 Clock in) and the sampling clock signal (i.e. Figure 7 CLK in the analog-to-digital converter and the digital-to-analog converter, outputting the reference clock signal (i.e. Figure 7 SYSREF) and the clock signal (i.e. Figure 7 The analog-to-digital converter and the digital-to-analog converter are connected to the FPGA based on the JJEDE204B interface, and clock synchronization calibration (i.e., SPI&SYNC in 7) is performed between the analog-to-digital converter, the digital-to-analog converter, the clock phase-locked loop chip and the FPGA.

[0112] The analog-to-digital converter in this embodiment can realize the acquisition input of two first signals, and the digital-to-analog converter can realize the playback output of one second signal.

[0113] and Figure 8Based on the test results of signal synchronous input and output between each signal transceiver processing board in the distributed phased array system proposed in this embodiment, it can be seen that the signal input and output synchronization between each signal transceiver processing board is high, wherein, when the ambient temperature change rate is less than 5°C, the signal input and output synchronization accuracy is ≤0.2°, and when the ambient temperature is between -40°C and 70°C, the input and output synchronization accuracy is set to ≤5°. Figure 8 The horizontal axis is time and the vertical axis is signal amplitude.

[0114] Furthermore, the distributed phased array system in this embodiment is composed of 96 signal transceiver processing boards, which can realize 96-way synchronous signal input and output. In order to realize convenient monitoring of the distributed phased array system composed of multiple signal transceiver processing boards, it is proposed to perform real-time monitoring of the operating status of the signal transceiver processing board in the distributed phased array system, and display the corresponding status query information and the time point of signal input and output on the terminal device, so as to perform real-time and convenient monitoring of the synchronization of the distributed phased array system.

[0115] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A distributed phased array system, characterized in that: The distributed phased array system comprises: multiple antenna elements; an active transceiver unit connected one-to-one with each of the antenna units; A frequency source connected to each of the active transceiver units, used to control the frequency conversion synchronization in each of the active transceiver units and to perform synchronization calibration on the clocks of each of the active transceiver units; A signal processing unit connected to each of the active transceiver units, used to synchronize the signal processing of each of the active transceiver units based on the synchronously calibrated clock; The active transceiver unit is provided with a local oscillator phase-locked loop, a sampling clock phase-locked loop and a reference clock phase-locked loop; The local oscillator phase-locked loop receives the clock signal output by the frequency source and generates a local oscillation signal according to the clock signal; The sampling clock phase-locked loop receives the clock signal output by the frequency source and generates a sampling clock signal according to the clock signal; The reference clock phase-locked loop receives the clock signal output by the frequency source and generates an output reference clock signal according to the clock signal.

2. The distributed phased array system according to claim 1, characterized in that: Each of the active transceiver units also includes an analog-to-digital signal transmission channel and a digital-to-analog signal transmission channel; The analog-to-digital signal transmission channel is used to perform a first signal transmission on a first signal received from an antenna unit; The digital-to-analog signal transmission channel is used to perform second signal transmission on a second signal received from the signal processing unit.

3. The distributed phased array system according to claim 2, characterized in that: The analog-to-digital signal transmission channel includes a low noise amplifier, a first multiplier, an analog-to-digital converter and a signal collector; The input end of the low noise amplifier is connected to the corresponding antenna unit, the output end of the low noise amplifier is connected to the first input end of the first multiplier, and the second input end of the first multiplier is connected to the local oscillation signal to control the first multiplier in each of the analog-to-digital signal transmission channels to synchronously perform the frequency conversion operation in the first signal transmission; The output end of the first multiplier is connected to the first input end of the analog-to-digital converter, and the second output end of the analog-to-digital converter is connected to the sampling clock signal to provide the same first time reference for the analog-to-digital converters in each of the analog-to-digital signal transmission channels; The output end of the analog-to-digital converter is connected to the first input end of the signal collector, and the second input end of the signal collector is connected to the reference clock signal to calibrate the collection clock of the signal collector in each of the analog-to-digital signal transmission channels.

4. The distributed phased array system according to claim 3, characterized in that: The digital-to-analog signal transmission channel includes a power amplifier, a second multiplier, a digital-to-analog converter and a signal player; The first input terminal of the signal player is connected to the signal processing unit, and the second input terminal of the signal player is connected to the reference clock signal to calibrate the playing clock of the signal player in each of the digital-analog signal transmission channels; The output end of the signal player is connected to the first input end of the digital-to-analog converter, and the second input end of the digital-to-analog converter is connected to the sampling clock signal to provide the same second time reference for the digital-to-analog converters in each of the digital-to-analog signal transmission channels; The output end of the digital-to-analog converter is connected to the first input end of the second multiplier, and the second input end of the second multiplier is connected to the local oscillation signal to control the second multipliers in each of the digital-to-analog signal transmission channels to synchronously perform the frequency conversion operation in the second signal transmission; The output end of the second multiplier is connected to the input end of the power amplifier, and the output end of the power amplifier is connected to the corresponding antenna unit.

5. The distributed phased array system according to claim 4, characterized in that: The signal processing unit; It is used to output a synchronous trigger pulse signal to the signal collector according to the reference clock signal connected, so as to control the signal collectors in each active transceiver unit to perform the collection operation in the first signal transmission at the same time point.

6. The distributed phased array system according to claim 5, characterized in that: The signal processing unit is provided with a plurality of first-in-first-out devices, the number of which corresponds to the number of the active transceiver units, and one of the first-in-first-out devices is connected to a signal collector in a corresponding active transceiver unit; The first-in-first-out device is used to store the first signal transmitted by the signal collector; The signal processing unit is further configured to read the first signal stored in each of the first-in-first-out devices and perform a signal processing operation when it is detected that the corresponding first signal is stored in each of the first-in-first-out devices.

7. The distributed phased array system according to claim 6, characterized in that: The distributed phased array system also includes a calibration network and a calibration module; Each of the antenna units is connected to a corresponding active transceiver unit via the calibration network, a first interactive end of the calibration module is connected to the calibration network, and a second interactive end of the calibration module is connected to the frequency source; The calibration network is used to collect each time point at which each active transceiver unit transmits the second signal to the corresponding antenna unit, and send each time point to the calibration module; The calibration module is used to calibrate the time frequency of the local oscillation signal output by the frequency source, the time frequency of the sampling clock signal and the time frequency of the reference clock signal according to each accessed time point.

8. The distributed phased array system according to claim 7, characterized in that: The active transceiver unit also includes an optical module; One end of the optical module is connected to the signal collector and the signal player respectively, and the other end of the optical module is connected to the signal processing unit; It is used to convert the first signal transmitted by the signal collector into a collection light signal and transmit it to the signal processing unit, and to convert the playback light signal transmitted by the signal processing unit into a second signal and transmit it to the signal player.

9. An electronic device, characterized in that: The electronic device comprises a distributed phased array system as described in any one of claims 1-8.

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