System, method and device for realizing power trigger control in burst communication based on FPGA (Field Programmable Gate Array), processor and readable storage medium thereof

Abstract

The invention relates to a system for realizing power trigger control in burst communication based on an FPGA (Field Programmable Gate Array), which comprises a digital down-conversion module, a trigger judgment module and a trigger data storage module, and is characterized in that the digital down-conversion module is used for carrying out digital down-conversion, generating IQ data with different sampling rates through a half-band filter and transmitting the IQ data into the trigger judgment module; after the trigger judgment module receives the IQ data, a power value is calculated through modulo operation, a moving average algorithm is achieved, and a Trigger signal is obtained; and the trigger data storage module is used for judging the received signal and storing required IQ data. The invention also relates to a method and a device for realizing power trigger control in burst communication based on the FPGA, a processor and a computer readable storage medium thereof. By adopting the system, the method, the device, the processor and the computer readable storage medium for realizing the power trigger control in the burst communication based on the FPGA, the effective initial position of a required signal can be quickly captured, the processing time of a signal tracking synchronization algorithm is reduced, the hardware cost is low, and the application is wider.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency instruments, and in particular to the field of wireless communication testing, and specifically refers to a system, method, device, processor and computer-readable storage medium thereof for realizing power trigger control in burst communication based on FPGA. Background Art

[0002] Burst communication, also known as burst communication, is a very high-speed communication method. The technology of burst communication is to store the processed and compressed information first, and then send it out quickly at a speed 10 to 100 times higher than the normal rate, or even higher, in a short moment when the transmission channel is favorable. Its main feature is to win by speed, converting the user's low-speed information into high-speed information transmitted by the channel to reduce the residence time of the information in the air. It emphasizes the change of working frequency and the implementation of covert sudden transmission among many signals in other high-frequency spectrums. On the one hand, a larger pulse power can be used to resist intentional interference. On the other hand, due to the randomness of the transmission time and the short time of information exposure in the channel, the probability of successful direction finding and interception of electronic reconnaissance will be greatly reduced.

[0003] Therefore, in most cases, the burst signal has the characteristic of being short-lived, so the starting point and starting position of the burst signal are uncertain compared to the continuous signal with a long duration. Therefore, the burst signal cannot generally be captured and processed in the same way as the traditional continuous signal.

[0004] For continuous signal processing, people do not care about the start and end of the signal, as long as it can be captured, and then handed over to the tracking algorithm to complete the synchronization. But for burst signals, in the case of non-cooperative communication, since the receiver does not have accurate prior knowledge of the signal, it is necessary to determine the start and sometimes the end of the signal, which is also the main content of burst signal capture. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a system, method, device, processor and computer-readable storage medium for implementing power trigger control in burst communication based on FPGA, which is simple to operate and has a wide range of applications.

[0006] In order to achieve the above-mentioned object, the system, method, device, processor and computer-readable storage medium for realizing power trigger control in burst communication based on FPGA of the present invention are as follows:

[0007] The system for realizing power trigger control in burst communication based on FPGA has the following main features: the system comprises a digital down-conversion module, a trigger decision module and a trigger data storage module; the trigger decision module is connected to the digital down-conversion module, the digital down-conversion module is connected to the trigger data storage module, and the output end of the trigger decision module is connected to the trigger data storage module; the digital down-conversion module is used for performing digital down-conversion on data collected by ADC, and generating IQ data with different sampling rates through a half-band filter and transmitting the data to the trigger decision module; after receiving the IQ data, the trigger decision module calculates the power value through a modulo operation, and implements a sliding average algorithm through FIFO_0, compares the power value with the Trigger_level sent by the host computer to obtain a Trigger_flag, and determines the rising edge or falling edge of the signal through a trigger signal recognition module to obtain a Trigger_en signal; the trigger data storage module is used for determining the received signal and storing the required IQ data.

[0008] Preferably, the digital down-conversion module includes a digital local oscillator NCO unit, a multiplier NUM unit and an HB filter unit. The digital local oscillator NCO unit is respectively connected to two multiplier NUM units, and the output end of the multiplier NUM unit is connected to the HB filter unit. The digital local oscillator NCO unit generates a SIN signal and a COS signal and outputs them to the multiplier NUM unit. The multiplier NUM unit multiplies the AD data with the SIN signal and the COS signal respectively to obtain I1 data and Q1 data, and the HB filter unit extracts I data and Q data with different sampling rates.

[0009] Preferably, the trigger decision module includes a modulo unit, a FIFO_0 unit and a trigger signal identification unit, the output end of the modulo unit is connected to the FIFO_0 unit, the output end of the FIFO_0 unit is connected to the trigger signal identification unit, the modulo unit performs a modulo operation on the received I and Q data, and stores the calculated result in the FIFO_0 unit, the FIFO_0 unit realizes a 128-point power sliding average, and the power average result is compared with the Trigger_level sent by the host computer to obtain the Trigger_flag; the trigger signal identification unit is used to judge the received Trigger_flag value, judge the accurate rising edge or falling edge position, and thus give a Trigger_en signal.

[0010] Preferably, if the Trigger_flag is a rising edge trigger, it is greater than or equal to the Trigger_level value of 1 and less than the Trigger_level value of 0; if it is a falling edge trigger, it is greater than or equal to the Trigger_level value of 0 and less than the Trigger_level value of 1.

[0011] Preferably, the trigger data storage module processes the data received from the host computer and the Trigger_en signal obtained from the trigger decision module, and saves the I data and Q data of different starting positions.

[0012] The method for implementing power trigger control in burst communication based on FPGA is mainly characterized in that the method comprises the following steps:

[0013] (1) Receive Trigger_delaytime data from the host computer;

[0014] (2) Determine whether the trigger delay is positive or negative. If Trigger_delaytime < 0, proceed to step (3); if Trigger_delaytime ≥ 0, proceed to step (5);

[0015] (3) The received I and Q data are stored in DDR3, and the counter Count_1 starts counting. When the counter Count_1 is equal to the absolute value of Trigger_delaytime, this loop is exited;

[0016] (4) I and Q data continue to be stored in DDR3, and counting starts when the Trigger_en signal is high. When the counter Count_2 is equal to Trigger_Length, data storage ends;

[0017] (5) Wait until the Trigger_en signal is high and the counter Count_3 starts counting;

[0018] (6) When the counter Count_3 is equal to Trigger_delaytime, the received I and Q data are stored in DDR3; when the counter Count_4 is equal to Trigger_Length, the data storage ends.

[0019] The device for realizing power trigger control in burst communication based on FPGA has the following main features:

[0020] a processor configured to execute computer executable instructions;

[0021] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for implementing power trigger control in burst communication based on FPGA are implemented.

[0022] The main feature of the processor for implementing power trigger control in burst communication based on FPGA is that the processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for implementing power trigger control in burst communication based on FPGA are implemented.

[0023] The main feature of the computer-readable storage medium is that a computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for implementing power trigger control in burst communication based on FPGA.

[0024] The system, method, device, processor and computer-readable storage medium thereof for implementing power trigger control in burst communication based on FPGA of the present invention can quickly capture the effective starting position of the required signal and reduce the processing time of the signal tracking synchronization algorithm; the synchronization method described in the present invention has low hardware cost and is more widely used. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The present invention is a schematic diagram of the structure of a system for realizing power trigger control in burst communication based on FPGA.

[0026] Figure 2 The present invention is a schematic diagram of the structure of a digital down-conversion module of a system for realizing power trigger control in burst communication based on FPGA.

[0027] Figure 3 The present invention is a schematic diagram of the structure of the trigger decision module of the system for realizing power trigger control in burst communication based on FPGA.

[0028] Figure 4 The present invention is a schematic diagram of the structure of the trigger data storage module of the system for realizing power trigger control in burst communication based on FPGA. DETAILED DESCRIPTION

[0029] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0030] The system for realizing power trigger control in burst communication based on FPGA of the present invention comprises a digital down-conversion module, a trigger decision module and a trigger data storage module, wherein the trigger decision module is connected to the digital down-conversion module, the digital down-conversion module is connected to the trigger data storage module, and the output end of the trigger decision module is connected to the trigger data storage module; the digital down-conversion module is used for performing digital down-conversion on the data collected by ADC, and generating IQ data with different sampling rates through a half-band filter and transmitting the data to the trigger decision module; after receiving the IQ data, the trigger decision module calculates the power value through a modulo operation, and implements a sliding average algorithm through FIFO_0, compares the power value with the Trigger_level sent by the host computer to obtain a Trigger_flag, and determines the rising edge or falling edge of the signal through a trigger signal recognition module to obtain a Trigger_en signal; the trigger data storage module is used for determining the received signal and storing the required IQ data.

[0031] Preferably, the digital down-conversion module includes a digital local oscillator NCO unit, a multiplier NUM unit and an HB filter unit. The digital local oscillator NCO unit is respectively connected to two multiplier NUM units, and the output end of the multiplier NUM unit is connected to the HB filter unit. The digital local oscillator NCO unit generates a SIN signal and a COS signal and outputs them to the multiplier NUM unit. The multiplier NUM unit multiplies the AD data with the SIN signal and the COS signal respectively to obtain I1 data and Q1 data, and the HB filter unit extracts I data and Q data with different sampling rates.

[0032] Preferably, the trigger decision module includes a modulo unit, a FIFO_0 unit and a trigger signal identification unit, the output end of the modulo unit is connected to the FIFO_0 unit, the output end of the FIFO_0 unit is connected to the trigger signal identification unit, the modulo unit performs a modulo operation on the received I and Q data, and stores the calculated result in the FIFO_0 unit, the FIFO_0 unit realizes a 128-point power sliding average, and the power average result is compared with the Trigger_level sent by the host computer to obtain the Trigger_flag; the trigger signal identification unit is used to judge the received Trigger_flag value, judge the accurate rising edge or falling edge position, and thus give a Trigger_en signal.

[0033] Preferably, if the Trigger_flag is a rising edge trigger, it is greater than or equal to the Trigger_level value of 1 and less than the Trigger_level value of 0; if it is a falling edge trigger, it is greater than or equal to the Trigger_level value of 0 and less than the Trigger_level value of 1.

[0034] Preferably, the trigger data storage module processes the data received from the host computer and the Trigger_en signal obtained from the trigger decision module, and saves the I data and Q data of different starting positions.

[0035] The method of the present invention using the above system to implement power trigger control in burst communication based on FPGA includes the following steps:

[0036] (1) Receive Trigger_delaytime data from the host computer;

[0037] (2) Determine whether the trigger delay is positive or negative. If Trigger_delaytime < 0, proceed to step (3); if Trigger_delaytime ≥ 0, proceed to step (5);

[0038] (3) The received I and Q data are stored in DDR3, and the counter Count_1 starts counting. When the counter Count_1 is equal to the absolute value of Trigger_delaytime, this loop is exited;

[0039] (4) I and Q data continue to be stored in DDR3, and counting starts when the Trigger_en signal is high. When the counter Count_2 is equal to Trigger_Length, data storage ends;

[0040] (5) Wait until the Trigger_en signal is high and the counter Count_3 starts counting;

[0041] (6) When the counter Count_3 is equal to Trigger_delaytime, the received I and Q data are stored in DDR3; when the counter Count_4 is equal to Trigger_Length, the data storage ends.

[0042] The device for realizing power trigger control in burst communication based on FPGA of the present invention, wherein the device comprises:

[0043] a processor configured to execute computer executable instructions;

[0044] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for implementing power trigger control in burst communication based on FPGA are implemented.

[0045] The processor of the present invention is used to implement power trigger control in burst communication based on FPGA, wherein the processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the various steps of the method for implementing power trigger control in burst communication based on FPGA are implemented.

[0046] The computer-readable storage medium of the present invention stores a computer program thereon, and the computer program can be executed by a processor to implement the various steps of the method for implementing power trigger control in burst communication based on FPGA.

[0047] In a specific embodiment of the present invention, a method for realizing power triggering in burst communication based on FPGA is provided. The purpose of the present invention is achieved through the following technical solutions:

[0048] A method for realizing power triggering in burst communication based on FPGA includes: a digital down-conversion module, a trigger judgment module, and a trigger data storage module. The digital down-conversion module performs digital down-conversion on the data collected by the ADC, generates IQ data with different sampling rates through a half-band filter, and transmits it to the trigger judgment module. After receiving the IQ data, the trigger judgment module calculates the power value through modulo operation, and then implements the sliding average algorithm through FIFO_0, compares it with the Trigger_level sent by the host computer to obtain Trigger_flag, and further determines the rising edge or falling edge of the signal through the trigger signal recognition module to obtain the Trigger_en signal. The trigger data storage module judges the received signal and saves the required IQ data.

[0049] like Figure 2 As shown in the figure, the digital down-conversion module includes a digital local oscillator NCO, a multiplier NUM, and an HB filter. The FPGA generates SIN and COS signals through the digital local oscillator NCO, and multiplies them with the received AD data to obtain I1 and Q1 data with a data rate of 245.76MHz. This data is extracted into I and Q data with different sampling rates through the HB filter, supporting 122.88MHz, 61.44MHz, 30.72MHz, 15.36MHz, 7.68MHz, 3.84MHz, and 1.92MHz. The host computer can obtain I and Q data at a suitable sampling rate selected by the demodulated symbol rate. For example, if the symbol rate is 1MHz, I and Q data with a sampling rate of 7.68MHz can be selected.

[0050] like Figure 3 As shown, the trigger judgment module includes a modulus calculation module, a FIFO_0 module, and a trigger signal identification module. The modulus calculation module performs modulus calculation on the received I and Q data, and the calculated result is stored in the FIFO_0 module. The FIFO_0 module realizes a 128-point power sliding average. The power average result is compared with the Trigger_level sent by the host computer to obtain the Trigger_flag. For the value of Trigger_flag, if it is a rising edge trigger, it is greater than or equal to the Trigger_level value of 1, and less than the Trigger_level value of 0; if it is a falling edge trigger, it is greater than or equal to the Trigger_level value of 0, and less than the Trigger_level value of 1. The trigger signal identification module judges the received Trigger_flag value, determines the exact rising edge or falling edge position, and thus gives the Trigger_en signal.

[0051] The specific implementation method is to store the received Trigger_flag signal in a 32-bit register. Each time a Trigger_en signal is updated, the register moves one bit to the left, and so on. When the upper 8 bits of the register are all 0 and the lower 8 bits are all 1, the Trigger_en value is 1, which can effectively determine the rising edge or falling edge of the signal and avoid false triggering.

[0052] like Figure 4 As shown, the trigger data storage module is mainly used to process the Trigger_delaytime, Trigger_Length and other data received from the host computer and the Trigger_en signal obtained from the trigger decision module to save the I and Q data of different starting positions.

[0053] The main process is as follows:

[0054] 1. After the power trigger function starts, the Trigger_delaytime data from the host computer is received. Because there is a trigger delay option in the power trigger, the corresponding data is Trigger_delaytime. The trigger delay has positive and negative options, and the positive and negative of the trigger delay need to be judged.

[0055] 2. When Trigger_delaytime is less than 0, the received I and Q data are directly stored in DDR3, and the counter Count_1 starts counting. When the counter Count_1 is equal to the absolute value of Trigger_delaytime, this loop is exited. The I and Q data continue to be stored in DDR3, and the counting starts when the Trigger_en signal is high. When the counter Count_2 is equal to Trigger_Length, the data storage ends. This approach ensures that the data before the trigger can be saved, achieving the effect of trigger delay.

[0056] 3. When Trigger_delaytime≥0, wait for the Trigger_en signal to be high and then counter Count_3 starts counting. When counter Count_3 equals Trigger_delaytime, the received I and Q data are stored in DDR3. When counter Count_4 equals Trigger_Length, data storage ends.

[0057] The main purpose of the technical solution of the present invention is to quickly capture the effective starting position of the required signal, and at the same time, the data of different starting positions can be obtained through the parameter setting of the host computer, which reduces the processing time of the signal tracking synchronization algorithm, has low hardware cost and is more widely used. The technical solution realizes the function of power triggering, consumes less resources, does not require a large number of multipliers of FPGA to participate in the calculation, and has lower hardware cost.

[0058] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0059] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0060] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0061] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0062] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0063] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the corresponding program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0064] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0065] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0066] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0067] The system, method, device, processor and computer-readable storage medium thereof for implementing power trigger control in burst communication based on FPGA of the present invention can quickly capture the effective starting position of the required signal and reduce the processing time of the signal tracking synchronization algorithm; the synchronization method described in the present invention has low hardware cost and is more widely used.

[0068] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system for realizing power trigger control in burst communication based on FPGA, It is characterized in that The system comprises a digital down-conversion module, a trigger decision module, and a trigger data storage module. The trigger decision module is connected to the digital down-conversion module, the digital down-conversion module is connected to the trigger data storage module, and the output end of the trigger decision module is connected to the trigger data storage module; the digital down-conversion module is used to perform digital down-conversion on the data collected by the ADC, and generate IQ data with different sampling rates through a half-band filter and transmit them to the trigger decision module; After receiving the IQ data, the trigger judgment module calculates the power value through modulo operation, and implements the sliding average algorithm through FIFO_0, compares it with the Trigger_level sent by the host computer to obtain Trigger_flag, and determines the rising edge or falling edge of the signal through the trigger signal identification module to obtain the Trigger_en signal; the trigger data storage module is used to judge the received signal and save the required IQ data.

2. The system for realizing power trigger control in burst communication based on FPGA according to claim 1, It is characterized in that The digital down-conversion module includes a digital local oscillator NCO unit, a multiplier NUM unit and an HB filter unit. The digital local oscillator NCO unit is respectively connected to two multiplier NUM units, and the output end of the multiplier NUM unit is connected to the HB filter unit. The digital local oscillator NCO unit generates a SIN signal and a COS signal and outputs them to the multiplier NUM unit. The multiplier NUM unit multiplies AD data with the SIN signal and the COS signal respectively to obtain I1 data and Q1 data. The HB filter unit extracts I data and Q data with different sampling rates.

3. The system for realizing power trigger control in burst communication based on FPGA according to claim 1, It is characterized in that The trigger judgment module includes a modulus seeking unit, a FIFO_0 unit and a trigger signal identification unit. The output end of the modulus seeking unit is connected to the FIFO_0 unit, and the output end of the FIFO_0 unit is connected to the trigger signal identification unit. The modulus seeking unit performs modulus operation on the received I and Q data and stores the calculated result in the FIFO_0 unit. The FIFO_0 unit realizes a 128-point power sliding average. The power average result is compared with the Trigger_level sent by the host computer to obtain the Trigger_flag; the trigger signal identification unit is used to judge the received Trigger_flag value, judge the accurate rising edge or falling edge position, and thus give a Trigger_en signal.

4. The system for realizing power trigger control in burst communication based on FPGA according to claim 1, It is characterized in that If the Trigger_flag is a rising edge trigger, it is greater than or equal to the Trigger_level value of 1, and less than the Trigger_level value of 0; if it is a falling edge trigger, it is greater than or equal to the Trigger_level value of 0, and less than the Trigger_level value of 1.

5. The system for realizing power trigger control in burst communication based on FPGA according to claim 1, It is characterized in that The trigger data storage module processes the data received from the host computer and the Trigger_en signal obtained from the trigger decision module, and saves the I data and Q data of different starting positions.

6. A method for implementing power trigger control in burst communication based on FPGA using the system of claim 1, It is characterized in that The method comprises the following steps: (1) Receive Trigger_delaytime data from the host computer; (2) Determine whether the trigger delay is positive or negative. If Trigger_delaytime < 0, proceed to step (3); if Trigger_delaytime ≥ 0, proceed to step (5); (3) The received I and Q data are stored in DDR3, and the counter Count_1 starts counting. When the counter Count_1 is equal to the absolute value of Trigger_delaytime, this loop is exited; (4) I and Q data continue to be stored in DDR3, and counting starts when the Trigger_en signal is high. When the counter Count_2 is equal to Trigger_Length, data storage ends; (5) Wait until the Trigger_en signal is high and the counter Count_3 starts counting; (6) When the counter Count_3 is equal to Trigger_delaytime, the received I and Q data are stored in DDR3; when the counter Count_4 is equal to Trigger_Length, the data storage ends.

7. A device for realizing power trigger control in burst communication based on FPGA, It is characterized in that The device comprises: a processor configured to execute computer executable instructions; The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for realizing power trigger control in burst communication based on FPGA as described in claim 6 are implemented.

8. A processor for implementing power trigger control in burst communication based on FPGA, It is characterized in that The processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for implementing power trigger control in burst communication based on FPGA as described in claim 6 are implemented.

9. A computer-readable storage medium, It is characterized in that A computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for implementing power trigger control in burst communication based on FPGA as described in claim 6.

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