Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of circuit units, each circuit unit comprises a pixel driving circuit, and the pixel driving circuit at least comprises a plurality of transistors; in a plane perpendicular to the display substrate, the circuit unit comprises a semiconductor layer arranged on the substrate, the semiconductor layer at least comprises a first active pattern (10) and a second active pattern (20), the first active pattern (10) comprises an active layer of at least one transistor, and the second active pattern (20) comprises an active layer of at least one transistor; in at least one circuit unit, the first active pattern (10) and the second active pattern (20) are arranged at intervals, and active layers of the plurality of transistors in the circuit unit and active layers of the plurality of transistors in the adjacent circuit unit in the unit row direction are arranged at intervals. And the active layers of the plurality of transistors in the circuit units and the active layers of the plurality of transistors in the adjacent circuit units in the unit column direction are arranged at intervals.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; on a plane perpendicular to the display substrate, at least one circuit unit comprising a semiconductor layer arranged on a base and a plurality of conductive layers arranged on a side of the semiconductor layer away from the base, the semiconductor layer comprising at least an active layer of a plurality of transistors, the semiconductor layer comprising at least a first active pattern and a second active pattern, the first active pattern comprising an active layer of at least one transistor, the second active pattern comprising an active layer of at least one transistor; in at least one circuit unit, the first active pattern and the second active pattern are arranged alternately, the active layers of the plurality of transistors in the circuit unit are arranged alternately with the active layers of the plurality of transistors in the circuit unit adjacent in the unit row direction, and the active layers of the plurality of transistors in the circuit unit are arranged alternately with the active layers of the plurality of transistors in the circuit unit adjacent in the unit column direction.

[0006] In an exemplary embodiment, the first active pattern includes active layers of two transistors, which are connected to each other as an integral structure; and the second active pattern includes active layers of seven transistors, which are connected to each other as an integral structure.

[0007] In an exemplary embodiment, the pixel driving circuit includes a first transistor and a seventh transistor as initialization transistors, a second transistor as a compensation transistor, a third transistor as a driving transistor, a fourth transistor as a data writing transistor, a fifth transistor and a sixth transistor as light-emitting transistors, and an eighth transistor and a ninth transistor as reference transistors, the first active pattern includes an active layer of the fourth transistor and an active layer of the ninth transistor, and the second active pattern includes active layers of the first to third transistors and active layers of the fifth to eighth transistors.

[0008] In an exemplary embodiment, the pixel driving circuit further includes a first storage capacitor and a second storage capacitor; the first storage capacitor includes at least a first plate and a third plate, and the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate; the second storage capacitor includes at least a second plate and a fourth plate, and the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate; the first plate serves as the gate electrode of the third transistor, the second plate is connected to the third plate, and the fourth plate is connected to the first power line.

[0009] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate; the first electrode plate and the second electrode plate are arranged in the first conductive layer, the third electrode plate and the fourth electrode plate are arranged in the second conductive layer, the first power line is arranged in the fourth conductive layer, and the second electrode plate is connected to the third electrode plate via a connecting electrode arranged in the third conductive layer.

[0010] In an exemplary embodiment, a first electrode plate connecting line extending toward the fourth electrode plate is provided on the third electrode plate, and a first groove recessed away from the third electrode plate is provided on the fourth electrode plate. The first electrode plate connecting line is provided in the first groove, and the end of the first electrode plate connecting line away from the third electrode plate is connected to the connecting electrode through a via.

[0011] In an exemplary embodiment, the pixel driving circuit further includes an additional capacitor, a lower plate of the additional capacitor being arranged in the semiconductor layer, an upper plate of the additional capacitor being arranged in the second conductive layer, an orthographic projection of the upper plate on the substrate at least partially overlapping with an orthographic projection of the lower plate on the substrate, the lower plate being connected to the second plate, and the upper plate being connected to the fourth plate.

[0012] In an exemplary embodiment, the lower plate includes the second region of the active layer of the fourth transistor, the second plate is connected to the second region of the active layer of the fourth transistor via a connecting electrode provided in the third conductive layer, and the upper plate and the fourth plate are an integral structure connected to each other.

[0013] In an exemplary embodiment, the gate electrode of the first transistor is connected to a fourth scan signal line, the gate electrode of the second transistor is connected to a fifth scan signal line, the gate electrode of the fourth transistor is connected to a third scan signal line, the gate electrode of the fifth transistor and the gate electrode of the sixth transistor are connected to a light emitting signal line, the gate electrode of the seventh transistor and the gate electrode of the eighth transistor are connected to the first scan signal line, and the gate electrode of the ninth transistor is connected to the second scan signal line, and the second scan signal line and the fifth scan signal line output the same scan signal.

[0014] In an exemplary embodiment, the display substrate further includes a second scan connection line, the second scan signal line and the second scan connection line are arranged in different conductive layers, the orthographic projection of the second scan signal line on the substrate at least partially overlaps with the orthographic projection of the second scan connection line on the substrate, and the second scan signal line is connected to the second scan connection line through a via, forming a double-layer structure of the scan signal line.

[0015] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate; the second scanning connection line is arranged in the first conductive layer, and the second scanning signal line is arranged in the third conductive layer.

[0016] In an exemplary embodiment, the display substrate further includes a fifth scan connection line, the fifth scan signal line and the fifth scan connection line are arranged in different conductive layers, the orthographic projection of the fifth scan signal line on the substrate at least partially overlaps with the orthographic projection of the fifth scan connection line on the substrate, and the fifth scan signal line is connected to the fifth scan connection line through a via hole, forming a double-layer structure of the scan signal line.

[0017] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate; the fifth scan connection line is arranged in the second conductive layer, and the fifth scan signal line is arranged in the third conductive layer.

[0018] In an exemplary embodiment, at least one circuit unit further includes a first shielding electrode, wherein an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor on the substrate, and an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor on the substrate.

[0019] In an exemplary embodiment, at least one circuit unit further includes a second shielding electrode, an orthographic projection of the second shielding electrode on the substrate at least partially overlapping with an orthographic projection of the second electrode of the fourth transistor and the second electrode of the ninth transistor on the substrate.

[0020] In an exemplary embodiment, at least one circuit unit further includes a third shielding electrode, an orthographic projection of the third shielding electrode on the substrate at least partially overlapping an orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor on the substrate.

[0021] In an exemplary embodiment, at least one circuit unit further includes a fourth shielding electrode, an orthographic projection of the fourth shielding electrode on the substrate at least partially overlapping an orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor on the substrate.

[0022] In an exemplary embodiment, the display substrate further includes at least one first power connection line extending along a unit row direction and at least one first power line extending along a unit column direction; the first power line and the first power connection line are arranged in different conductive layers, and the first power line and the first power connection line are connected through a via to form a mesh structure for transmitting a first power signal.

[0023] In an exemplary embodiment, the display substrate further includes at least one second power connection line extending along a unit row direction and at least one second power line extending along a unit column direction; the second power line and the second power connection line are arranged in different conductive layers, and the second power line and the second power connection line are connected through a via to form a mesh structure for transmitting a second power signal.

[0024] In an exemplary embodiment, the display substrate further includes at least one reference signal connection line extending along the unit row direction and at least one reference signal line extending along the unit column direction; the reference signal line and the reference signal connection line are arranged in different conductive layers, and the reference signal connection line is connected to the reference signal line through a via to form a mesh structure for transmitting the reference signal.

[0025] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0026] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; the manufacturing method comprising:

[0027] A semiconductor layer and a plurality of conductive layers are formed on a substrate and are arranged on a side of the semiconductor layer away from the substrate; the semiconductor layer includes at least active layers of a plurality of transistors, and the semiconductor layer includes at least a first active pattern and a second active pattern, the first active pattern includes the active layer of at least one transistor, and the second active pattern includes the active layer of at least one transistor; in at least one circuit unit, the first active pattern and the second active pattern are arranged alternately, the active layers of the plurality of transistors in the circuit unit are arranged alternately with the active layers of the plurality of transistors in the circuit unit adjacent in the unit row direction, and the active layers of the plurality of transistors in the circuit unit are arranged alternately with the active layers of the plurality of transistors in the circuit unit adjacent in the unit column direction.

[0028] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0030] FIG1 is a schematic structural diagram of a display device;

[0031] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0032] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0033] FIG4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0034] FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG6 is a schematic structural diagram of the semiconductor layer in FIG5 ;

[0036] FIG7 is a schematic structural diagram of the first storage capacitor and the second storage capacitor region in FIG5 ;

[0037] FIG8 is a schematic diagram of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0038] 9A and 9B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0039] 10A and 10B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0040] FIG11 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to the present disclosure;

[0041] 12A and 12B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0042] FIG13 is a schematic diagram of a display substrate after a fifth insulating layer pattern is formed according to the present disclosure;

[0043] 14A and 14B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed according to the present disclosure;

[0044] FIG15 is a schematic diagram of another planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0045] FIG16 is a schematic structural diagram of the second scanning signal line and the fifth scanning signal line in FIG15;

[0046] FIG17 is a schematic diagram of another display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0047] 18A and 18B are schematic diagrams of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0048] 19A and 19B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0049] FIG20 is a schematic diagram of another display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0050] 21A and 21B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0051] FIG22 is a schematic diagram of another display substrate according to the present disclosure after a fifth conductive layer pattern is formed;

[0052] 23A and 23B are schematic diagrams of another display substrate after forming a fourth conductive layer pattern according to the present disclosure.

[0053] Explanation of Reference Numerals: 10—first active pattern; 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 19—ninth active layer; 20—second active pattern; 21—first gate electrode; 22—second gate electrode; 24—fourth gate electrode; 25—fifth gate electrode; 26—sixth gate electrode; 29—ninth gate electrode; 31—first light-emitting signal line; 32—second light-emitting signal line; 33—repair line; 36—first shielding electrode; 37—second shielding electrode; 38—third shielding electrode; 39—fourth shielding electrode; 41—first connecting electrode; 42—second connecting electrode; 43—third connecting electrode; 44—fourth connecting electrode; 45—fifth connecting electrode; 46—sixth connecting electrode; 47—seventh connecting electrode; 48—eighth connecting electrode; 51—first power line; 52—second power line; 53—data signal line; 54—reference signal line; 55—anode connecting electrode; 61—first scanning signal line; 62—second scanning signal line; 62-1—second scanning line; 63—third scanning line; 64—fourth scanning line; 65—fifth scanning line; 65-1—fifth scanning line; 68—first power line; 69—second power line; 71—first plate; 72—second plate; 73—third plate; 74—fourth plate; 75—first opening; 76—second opening; 81—first initial signal line; 82—second initial signal line; 91—first reference signal line; 92—second reference signal line; 101—substrate; 102—driving circuit layer;103—light-emitting structure layer; 104—encapsulation structure layer. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0055] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0056] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0057] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0058] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0059] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0060] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0061] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0062] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0063] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0064] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0065] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0066] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0067] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a frame area located around the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting unit may include at least a light-emitting device. The light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0068] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0069] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0070] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels within the display substrate. As shown in Figure 4, in a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.

[0071] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least a light-emitting device, and the light-emitting device may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0072] In exemplary embodiments, the organic light-emitting layer may include an emission layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0073] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; on a plane perpendicular to the display substrate, the at least one circuit unit comprising a semiconductor layer disposed on a base and a plurality of conductive layers disposed on a side of the semiconductor layer away from the base, the semiconductor layer comprising at least active layers of a plurality of transistors, the semiconductor layer comprising at least a first active pattern and a second active pattern, the first active pattern comprising an active layer of at least one transistor, the second active pattern comprising an active layer of at least one transistor; in the at least one circuit unit, the first active pattern and the second active pattern are arranged alternately, the active layers of the plurality of transistors in the circuit unit are arranged alternately from the active layers of the plurality of transistors in the circuit unit adjacent in the unit row direction, and the active layers of the plurality of transistors in the circuit unit are arranged alternately from the active layers of the plurality of transistors in the circuit unit adjacent in the unit column direction.

[0074] In an exemplary embodiment, the first active pattern includes active layers of two transistors, which are connected to each other as an integral structure; and the second active pattern includes active layers of seven transistors, which are connected to each other as an integral structure.

[0075] In an exemplary embodiment, the pixel driving circuit includes a first transistor and a seventh transistor as initialization transistors, a second transistor as a compensation transistor, a third transistor as a driving transistor, a fourth transistor as a data writing transistor, a fifth transistor and a sixth transistor as light-emitting transistors, and an eighth transistor and a ninth transistor as reference transistors, the first active pattern includes an active layer of the fourth transistor and an active layer of the ninth transistor, and the second active pattern includes active layers of the first to third transistors and active layers of the fifth to eighth transistors.

[0076] In an exemplary embodiment, the pixel driving circuit further includes a first storage capacitor and a second storage capacitor; the first storage capacitor includes at least a first plate and a third plate, and the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate; the second storage capacitor includes at least a second plate and a fourth plate, and the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate; the first plate serves as the gate electrode of the third transistor, the second plate is connected to the third plate, and the fourth plate is connected to the first power line.

[0077] In an exemplary embodiment, the pixel driving circuit further includes an additional capacitor, a lower plate of the additional capacitor being arranged in the semiconductor layer, an upper plate of the additional capacitor being arranged in the second conductive layer, an orthographic projection of the upper plate on the substrate at least partially overlapping with an orthographic projection of the lower plate on the substrate, the lower plate being connected to the second plate, and the upper plate being connected to the fourth plate.

[0078] In an exemplary embodiment, a gate electrode of the ninth transistor is connected to a second scan signal line, a gate electrode of the second transistor is connected to a fifth scan signal line, and the second scan signal line and the fifth scan signal line output the same scan signal.

[0079] In an exemplary embodiment, the display substrate further includes a second scan connection line, the second scan signal line and the second scan connection line are arranged in different conductive layers, the orthographic projection of the second scan signal line on the substrate at least partially overlaps with the orthographic projection of the second scan connection line on the substrate, and the second scan signal line is connected to the second scan connection line through a via, forming a double-layer structure of the scan signal line.

[0080] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate; the second scanning connection line is arranged in the first conductive layer, and the second scanning signal line is arranged in the third conductive layer.

[0081] In an exemplary embodiment, the display substrate further includes a fifth scan connection line, the fifth scan signal line and the fifth scan connection line are arranged in different conductive layers, the orthographic projection of the fifth scan signal line on the substrate at least partially overlaps with the orthographic projection of the fifth scan connection line on the substrate, and the fifth scan signal line is connected to the fifth scan connection line through a via hole, forming a double-layer structure of the scan signal line.

[0082] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate; the fifth scan connection line is arranged in the second conductive layer, and the fifth scan signal line is arranged in the third conductive layer.

[0083] In an exemplary embodiment, at least one circuit unit further includes a first shielding electrode, wherein an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor on the substrate, and an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor on the substrate.

[0084] In an exemplary embodiment, at least one circuit unit further includes a second shielding electrode, an orthographic projection of the second shielding electrode on the substrate at least partially overlapping with an orthographic projection of the second electrode of the fourth transistor and the second electrode of the ninth transistor on the substrate.

[0085] In an exemplary embodiment, at least one circuit unit further includes a third shielding electrode, an orthographic projection of the third shielding electrode on the substrate at least partially overlapping an orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor on the substrate.

[0086] In an exemplary embodiment, at least one circuit unit further includes a fourth shielding electrode, an orthographic projection of the fourth shielding electrode on the substrate at least partially overlapping an orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor on the substrate.

[0087] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0088] FIG4 is an equivalent circuit diagram of a pixel driving circuit of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure. As shown in FIG4 , the pixel driving circuit of the exemplary embodiment of the present disclosure may be a 9T2C structure, which may include 9 transistors (a first transistor T1 to a ninth transistor T9) and 2 storage capacitors (a first storage capacitor C1 and a second storage capacitor C2), and the pixel driving circuit is connected to 12 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a first reference signal line REF1, a second reference signal line REF2, a data signal line DATA, and a first power line VDD).

[0089] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the first storage capacitor C1, respectively; the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the eighth transistor T8, and the second electrode of the fifth transistor T5, respectively; the third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively; and the fifth node N5 is connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the second end of the first storage capacitor C1, and the second end of the second storage capacitor C2, respectively.

[0090] In an exemplary embodiment, a first end of the first storage capacitor C1 is connected to the first node N1, a second end of the first storage capacitor C1 is connected to the fifth node N5, a first end of the second storage capacitor C2 is connected to the first power line VDD, and a second end of the second storage capacitor C2 is connected to the fifth node N5.

[0091] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the fourth scan signal line S4, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor is connected to the first node N1. When a turn-on signal is applied to the fourth scan signal line S4, the first transistor T1 transmits a first initialization voltage to the gate electrode of the third transistor T3 and the first end of the first storage capacitor C1, thereby releasing the charge accumulated in the first storage capacitor C1 and achieving initialization.

[0092] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. When a turn-on signal is applied to the second scan signal line S2, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0093] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the first storage capacitor C1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the magnitude of the driving current based on the potential difference between its gate electrode and the first electrode.

[0094] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the fifth node N5. When a turn-on signal is applied to the third scan signal line S3, the fourth transistor T4 inputs a data voltage of the data signal line DATA to the second end of the first storage capacitor C1 and the second end of the second storage capacitor C2.

[0095] In the exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the first light emission signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the second light emission signal line EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. When a turn-on signal is applied to the first light emission signal line EM1 and the second light emission signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power supply line VDD and the second power supply line VSS, thereby causing the light emitting device EL to emit light.

[0096] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. When a turn-on signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initialization voltage to the first electrode of the light-emitting device EL, thereby releasing the charge accumulated in the first electrode of the light-emitting device EL and achieving initialization.

[0097] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, a first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and a second electrode of the eighth transistor T8 is connected to the second node N2. When a turn-on signal is applied to the first scan signal line S1, the eighth transistor T8 transmits the second reference signal to the second node N2.

[0098] In an exemplary embodiment, a gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, a first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and a second electrode of the ninth transistor T9 is connected to the fifth node N5. When a turn-on signal is applied to the second scan signal line S2, the ninth transistor T9 transmits the first reference signal to the fifth node N5.

[0099] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0100] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the ninth transistor T9 may include P-type transistors and N-type transistors.

[0101] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0102] Figure 5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of the pixel driving circuit in three circuit units (a first circuit unit, a second circuit unit, and a third circuit unit) in the display substrate. In an exemplary embodiment, the display substrate may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate. The driving circuit layer may include at least a plurality of circuit units, the light-emitting structure layer may include at least a plurality of light-emitting units, at least one circuit unit includes a pixel driving circuit, and at least one light-emitting unit includes a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode, and the anode in the light-emitting unit is connected to the pixel driving circuit in the corresponding circuit unit. In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to an area divided according to the pixel driving circuit, and the light-emitting unit referred to in the present disclosure refers to an area divided according to the light-emitting device. In an exemplary embodiment, the position of the orthogonal projection of the light-emitting unit on the substrate may correspond to the position of the orthogonal projection of the circuit unit on the substrate, or the position of the orthogonal projection of the light-emitting unit on the substrate may not correspond to the position of the orthogonal projection of the circuit unit on the substrate.

[0103] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X intersects the second direction Y.

[0104] As shown in Figure 5, in an exemplary embodiment, the driving circuit layer may further include at least one first power connection line 68 extending along the first direction X and at least one first power line 51 extending along the second direction Y. The first power line 51 is connected to the pixel driving circuit in the plurality of circuit units. The first power line 51 is configured to continuously provide a high-level signal to the pixel driving circuit. The first power line 51 extending along the second direction Y is interconnected with the first power connection line 68 extending along the first direction X to form a mesh structure for transmitting the first power signal.

[0105] In an exemplary embodiment, the driving circuit layer may further include at least one second power connection line 69 extending along the first direction X and at least one second power line 52 extending along the second direction Y, the second power line 52 being connected to the cathodes of the plurality of light-emitting units, the second power line 52 being configured to continuously provide a low-level signal to the cathodes, the second power line 52 extending along the second direction Y being interconnected with the second power connection line 69 extending along the first direction X, forming a mesh structure for transmitting the second power signal.

[0106] In an exemplary embodiment, the driving circuit layer may further include at least one first reference signal line 91 extending along the first direction X and at least one reference signal connection line 54 extending along the second direction Y. The first reference signal line 91 is connected to the pixel driving circuit in the plurality of circuit units. The first reference signal line 91 is configured to provide a first reference signal to the pixel driving circuit. The first reference signal line 91 extending along the first direction X and the reference signal connection line 54 extending along the second direction Y are interconnected to form a mesh structure for transmitting the first reference signal.

[0107] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.

[0108] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a base. The first power line 51 and the first power connection line 68 may be disposed in different conductive layers, and the first power line 51 and the first power connection line 68 may be connected via a via. The second power line 52 and the second power connection line 69 may be disposed in different conductive layers, and the second power line 52 and the second power connection line 69 may be connected via a via. The first reference signal line 91 and the reference signal connection line 54 may be disposed in different conductive layers, and the first reference signal line 91 and the reference signal connection line 54 may be connected via a via.

[0109] In an exemplary embodiment, the first power line 51, the second power line 52 and the reference signal connection line 54 can be set in the same layer and formed synchronously through the same patterning process, and the first power connection line 68, the second power connection line 69 and the first reference signal line 91 can be set in the same layer and formed synchronously through the same patterning process.

[0110] In an exemplary embodiment, the first power connection line 68 , the second power connection line 69 , and the first reference signal line 91 may be disposed in the third conductive layer, and the first power line 51 , the second power line 52 , and the reference signal connection line 54 may be disposed in the fourth conductive layer.

[0111] Figure 6 is a schematic diagram of the structure of the semiconductor layer in Figure 5, illustrating the structure of the first active pattern and the second active pattern in a circuit unit. As shown in Figure 6, at least one circuit unit may include multiple transistors, and the semiconductor layer of at least one circuit unit may include at least the active layers of the multiple transistors.

[0112] In example embodiments, the semiconductor layer of at least one circuit unit may include at least a first active pattern 10 , which may include an active layer of at least one transistor, and a second active pattern 20 , which may include an active layer of at least one transistor.

[0113] In an exemplary embodiment, in at least one circuit unit, the first active pattern 10 is spaced apart from the second active pattern 20 , ie, the active layer of the transistor in the first active pattern 10 is not connected to the active layer of the transistor in the second active pattern 20 .

[0114] In an exemplary embodiment, in at least one circuit unit, the active layers of multiple transistors are spaced apart from the active layers of multiple transistors in the circuit unit adjacent in the unit row direction, that is, in the unit row direction, the active layers of multiple transistors in one circuit unit are not connected to the active layers of multiple transistors in the adjacent circuit unit.

[0115] In an exemplary embodiment, in at least one circuit unit, the active layers of multiple transistors are spaced apart from the active layers of multiple transistors in the circuit unit adjacent in the unit column direction, that is, in the unit column direction, the active layers of multiple transistors in one circuit unit are not connected to the active layers of multiple transistors in the adjacent circuit unit.

[0116] In an exemplary embodiment, the first active pattern 10 may include active layers of two transistors connected as one body, and the second active pattern 20 may include active layers of seven transistors connected as one body.

[0117] In an exemplary embodiment, the pixel driving circuit in at least one circuit unit may include a first transistor T1 and a seventh transistor T7 as initialization transistors, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 and a sixth transistor T6 as light emitting transistors, and an eighth transistor T8 and a ninth transistor T9 as reference transistors. The first active pattern 10 may include an active layer of the fourth transistor T4 and an active layer of the ninth transistor T9, and the second active pattern 20 may include an active layer of the first to third transistors T1 to T3 and an active layer of the fifth to eighth transistors T5 to T8.

[0118] Figure 7 is a schematic diagram of the structure of the first storage capacitor and the second storage capacitor region in Figure 5. As shown in Figures 5 and 7, in an exemplary embodiment, the first storage capacitor may include at least a first electrode plate 71 and a third electrode plate 73, wherein the orthographic projection of the third electrode plate 73 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 71 on the substrate. The second storage capacitor may include at least a second electrode plate 72 and a fourth electrode plate 74, wherein the orthographic projection of the fourth electrode plate 74 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 72 on the substrate.

[0119] In an exemplary embodiment, the first electrode 71 may serve as a gate electrode of the third transistor T3 , the second electrode 72 is connected to the third electrode 73 , and the fourth electrode 74 is connected to the first power line 51 .

[0120] In an exemplary embodiment, the plurality of conductive layers includes at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are sequentially arranged in a direction away from the substrate. The first electrode plate 71 and the second electrode plate 72 may be arranged in the first conductive layer, the third electrode plate 73 and the fourth electrode plate 74 may be arranged in the second conductive layer, the first power line 51 may be arranged in the fourth conductive layer, and the second electrode plate 72 may be connected to the third electrode plate 73 via a connecting electrode arranged in the third conductive layer.

[0121] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 64, the first electrode of the first transistor T1 is connected to the first initial signal line 81, and the second electrode of the first transistor T1 is respectively connected to the first electrode of the second transistor T2 and the first plate 71 of the first storage capacitor. The gate electrode of the second transistor T2 is connected to the fifth scan signal line 65, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The gate electrode of the third transistor T3 serves as the first plate 71 of the first storage capacitor, and the first electrode of the third transistor T3 is respectively connected to the second electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, the first electrode of the fourth transistor T4 is connected to the data signal line 53, and the second electrode of the fourth transistor T4 is respectively connected to the second electrode of the ninth transistor T9, the third plate 73 of the first storage capacitor, and the second plate 72 of the second storage capacitor. The gate electrode of the fifth transistor T5 is connected to the first light emission signal line 31, and the first electrode of the fifth transistor T5 is connected to the first power line 51. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line 32, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the first scanning signal line 61, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 82. The gate electrode of the eighth transistor T8 is connected to the first scanning signal line 61, and the first electrode of the eighth transistor T8 is connected to the second reference signal line 92. The gate electrode of the ninth transistor T9 is connected to the second scanning signal line 62, and the first electrode of the ninth transistor T9 is connected to the first reference signal line 91.

[0122] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 transmit the same scan signal.

[0123] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first light-emitting signal line 31, the second light-emitting signal line 32, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91 and the second reference signal line 92 can be line shapes whose main parts extend along the first direction X, and the shapes of the first power line 51 and the data signal line 53 can be line shapes whose main parts extend along the second direction Y.

[0124] In an exemplary embodiment, at least one circuit unit may further include an anode connection electrode 55 connected to the second electrodes of the sixth and seventh transistors T6 and T7 , respectively, and to the anode of the light emitting unit.

[0125] In an exemplary embodiment, the driving circuit layer may further include a repair line 33. The shape of the repair line 33 may be a line shape in which the main portion extends along the first direction X. The orthographic projection of the repair line 33 on the substrate at least partially overlaps with the orthographic projection of the anode connection electrode 55 on the substrate. The repair line 33 is configured to input a signal to the anode of the sub-pixel with the poor bright spot through the repair line 33 when a poor bright spot occurs on the display substrate, thereby repairing it into a dark spot.

[0126] In an exemplary embodiment, at least one circuit unit may further include a first connection electrode 41, which is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first plate 71 of the first storage capacitor. The first connection electrode 41 can serve as a first node of the pixel driving circuit.

[0127] In an exemplary embodiment, at least one circuit unit may further include a power shielding block 51-1, which is connected to the first power line 51, and the positive projection of the power shielding block 51-1 on the substrate at least partially overlaps with the positive projection of the first connection electrode 41 on the substrate to shield the influence of other signals in the pixel driving circuit on the first node.

[0128] In an exemplary embodiment, at least one circuit unit may further include a second connection electrode 42, which is respectively connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third plate 73 of the first storage capacitor, and the second plate 72 of the second storage capacitor. The second connection electrode 42 can serve as the fifth node N5 in the pixel driving circuit.

[0129] In an exemplary embodiment, an orthographic projection of the first power line 51 on the substrate at least partially overlaps an orthographic projection of the second connection electrode 42 on the substrate to shield the fifth node from influence of other signals in the pixel driving circuit.

[0130] In an exemplary embodiment, at least one circuit unit may further include a first shielding electrode 36. The first shielding electrode 36 is connected to the fourth electrode plate 74. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 on the substrate. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the first transistor T1 and the second transistor T2 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0131] In an exemplary embodiment, at least one circuit unit may further include a second shielding electrode 37. The second shielding electrode 37 is connected to the fourth electrode plate 74. The orthographic projection of the second shielding electrode 37 on the substrate at least partially overlaps with the orthographic projections of the second electrode of the fourth transistor T4 and the second electrode of the ninth transistor T9 on the substrate. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the fifth node from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0132] In an exemplary embodiment, the fourth plate 74 , the first shield electrode 36 , and the second shield electrode 37 may be an integral structure connected to each other.

[0133] In an exemplary embodiment, at least one circuit unit may further include an additional capacitor of the second storage capacitor, the lower plate of the additional capacitor is arranged in the semiconductor layer, the upper plate of the additional capacitor is arranged in the second conductive layer, the orthographic projection of the upper plate on the substrate and the orthographic projection of the lower plate on the substrate at least partially overlap, the lower plate is connected to the second plate, and the upper plate is connected to the fourth plate.

[0134] In this exemplary embodiment, the lower plate of the additional capacitor is the second region of the active layer of the fourth transistor T4 (also the second region of the active layer of the ninth transistor T9), and the upper plate of the additional capacitor is the second shielding electrode 37. Since the second region of the active layer of the fourth transistor T4 is connected to the second plate 72 via the second connecting electrode 42, and the second shielding electrode 37 and the fourth plate 74 are interconnected and integrated, they form an additional capacitor for the second storage capacitor. The additional capacitor is connected in parallel with the second storage capacitor, effectively increasing the total capacity of the second storage capacitor, improving the operating performance of the pixel driving circuit, and enhancing the display effect.

[0135] In an exemplary embodiment, at least one circuit unit may further include a third shielding electrode 38. The third shielding electrode 38 is connected to the second reference signal line 92. The orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 on the substrate. In an exemplary embodiment, the third shielding electrode 38 is configured to shield the fourth transistor T4 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0136] In an exemplary embodiment, at least one circuit unit may further include a fourth shielding electrode 39. The fourth shielding electrode 39 is connected to the second reference signal line 92. The orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor T9 on the substrate. In an exemplary embodiment, the fourth shielding electrode 39 is configured to shield the ninth transistor T9 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0137] In an exemplary embodiment, the third shielding electrode 38 , the fourth shielding electrode 39 , and the second reference signal line 92 may be an integral structure connected to each other.

[0138] In an exemplary embodiment, a first plate connecting wire 73-1 is provided on a side of the third plate 73 of at least one circuit unit close to the fourth plate 74, and a first groove K1 is provided on a side of the fourth plate 74 close to the third plate 73, which is recessed away from the third plate 73. The first plate connecting wire 73-1 is provided in the first groove K1, and an end of the first plate connecting wire 73-1 away from the third plate 73 is connected to the second connecting electrode 42 through a via.

[0139] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0140] In an exemplary embodiment, taking three circuit units (a first circuit unit, a second circuit unit, and a third circuit unit) in an n-th unit row as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0141] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as shown in FIG8 .

[0142] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display substrate may include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9, and the first to third active layers 11 to 13 and the fifth to eighth active layers 15 to 18 may be an integrated structure connected to each other, and the fourth active layer 14 and the ninth active layer 19 may be an integrated structure connected to each other.

[0143] In an exemplary embodiment, the fourth active layer 14 and the ninth active layer 19 of the nth unit row may be located on a side of the third active layer 13 close to the (n-1)th unit row, that is, the fourth active layer 14 and the ninth active layer 19 may be located on a side of the third active layer 13 of the circuit unit opposite to the second direction Y. The first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 of the nth unit row may be located on a side of the third active layer 13 close to the (n+1)th unit row, that is, the first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 may be located on a side of the third active layer 13 of the circuit unit in the second direction Y.

[0144] In an exemplary embodiment, the first active layer 11 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the fifth active layer 15 may be located on one side of the first active layer 11 of the present circuit unit in the second direction Y, and the eighth active layer 18 may be located on one side of the fifth active layer 15 of the present circuit unit in the second direction Y. The second active layer 12 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the sixth active layer 16 may be located on one side of the second active layer 12 of the present circuit unit in the second direction Y, and the seventh active layer 17 may be located on one side of the sixth active layer 16 of the present circuit unit in the second direction Y.

[0145] In an exemplary embodiment, the first active layer 11, the fourth active layer 14, the fifth active layer 15 and the eighth active layer 18 can be located on one side of the first direction X of the circuit unit (such as the side opposite to the first direction X), and the second active layer 12, the sixth active layer 16, the seventh active layer 17 and the ninth active layer 19 can be located on the other side of the first direction X of the circuit unit (such as one side of the first direction X).

[0146] In an exemplary embodiment, the first active layer 11 and the second active layer 12 may have an L shape, the third active layer 13 may have a C shape, the fourth active layer 14 and the ninth active layer 19 may have an N shape, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may have an I shape.

[0147] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be interconnected, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, and the second region 18-2 of the eighth active layer may be interconnected, and the first region 13-1 of the third active layer may serve as both the second region 15-2 of the fifth active layer and the second region 18-2 of the eighth active layer, forming a second node N2 of the pixel driving circuit. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be interconnected, and the second region 13-2 of the third active layer may serve as both the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, forming a third node N3 of the pixel driving circuit. The second region 14-2 of the fourth active layer and the second region 19-2 of the ninth active layer may be connected to each other, and the second region 14-2 of the fourth active layer may serve as the second region 19-2 of the ninth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer, forming a fourth node N4 of the pixel driving circuit. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the first region 19-1 of the ninth active layer may be separately provided. The first region 14-1 of the fourth active layer may be located on a side of the channel region of the fourth active layer closer to the third active layer 13, and the first region 19-1 of the ninth active layer may be located on a side of the channel region of the ninth active layer closer to the third active layer 13.

[0148] In an exemplary embodiment, the semiconductor layer of at least one circuit unit may include at least a first active pattern 10 and a second active pattern 20, the first active pattern 10 may include an active layer of the fourth transistor T4 and an active layer of the ninth transistor T9, and the second active pattern 20 may include active layers of the first to third transistors T1 to T3 and active layers of the fifth to eighth transistors T5 to T8.

[0149] In an exemplary embodiment, in at least one circuit unit, the first active pattern 10 is spaced apart from the second active pattern 20 , ie, the active layer of the transistor in the first active pattern 10 is not connected to the active layer of the transistor in the second active pattern 20 .

[0150] In an exemplary embodiment, in at least one unit row, the semiconductor layers in the circuit units adjacent in the first direction X are spaced apart from each other, that is, the semiconductor layer of the first circuit unit in the n-th unit row is not connected to the semiconductor layer of the second circuit unit in the n-th unit row, and the semiconductor layer of the second circuit unit in the n-th unit row is not connected to the semiconductor layer of the third circuit unit in the n-th unit row.

[0151] In an exemplary embodiment, in at least one unit column, the semiconductor layers in the circuit units adjacent in the second direction Y are spaced apart from each other, that is, the semiconductor layer of the first circuit unit in the n-1th unit row is not connected to the semiconductor layer of the first circuit unit in the nth unit row, and the semiconductor layer of the first circuit unit in the nth unit row is not connected to the semiconductor layer of the first circuit unit in the n+1th unit row.

[0152] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG9A and FIG9B , FIG9B being a schematic diagram of the first conductive layer in FIG9A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0153] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scan signal line 61, a first plate 71 of a first storage capacitor, and a second plate 72 of a second storage capacitor.

[0154] In an exemplary embodiment, the first gate electrode 21 may be in an L-shape and may be located on one side of the first electrode 71 in the second direction Y. The region where the first gate electrode 21 overlaps with the first active layer may serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0155] In an exemplary embodiment, the second gate electrode 22 can be in a "T" shape and can be located on one side of the first electrode 71 in the second direction Y. The area where the second gate electrode 22 overlaps with the second active layer can serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0156] In an exemplary embodiment, the fourth gate electrode 24 may be in an "L" shape and may be located on the side of the second electrode 72 in the opposite direction of the second direction Y. The area where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4 of the dual-gate structure.

[0157] In an exemplary embodiment, the fifth gate electrode 25 may be in the shape of a strip extending along the second direction Y and may be located on one side of the first gate electrode 21 in the second direction Y. The area where the fifth gate electrode 25 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5.

[0158] In an exemplary embodiment, the sixth gate electrode 26 may be in a strip shape extending along the first direction X and may be located on one side of the second gate electrode 22 in the second direction Y. The area where the sixth gate electrode 26 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0159] In an exemplary embodiment, the shape of the ninth gate electrode 29 can be a strip shape extending along the first direction X, and can be located on the side of the second electrode 72 in the opposite direction of the second direction Y. The area where the ninth gate electrode 29 overlaps with the ninth active layer can serve as the gate electrode of the ninth transistor T9 of the dual-gate structure.

[0160] In an exemplary embodiment, the first scan signal line 61 may be shaped as a line having a main portion extending along the first direction X, and may be located on one side of the fifth gate electrode 25 and the sixth gate electrode 26 in the second direction Y. The region where the first scan signal line 61 overlaps with the seventh active layer may serve as the gate electrode of the seventh transistor T7, and the region where the first scan signal line 61 overlaps with the eighth active layer may serve as the gate electrode of the eighth transistor T8.

[0161] In an exemplary embodiment, the shape of the first electrode 71 of the first storage capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode 71 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. The first electrode 71 can serve as the lower plate of the first storage capacitor and the gate electrode of the third transistor T3 at the same time.

[0162] In an exemplary embodiment, the second plate 72 of the second storage capacitor may be rectangular, with chamfered corners. The second plate 72 may be located on a side of the first plate 71 opposite to the second direction Y, and on a side of the fourth gate electrode 24 and the ninth gate electrode 29 in the second direction Y. That is, in the second direction Y, the second plate 72 is located between the first plate 71 and the fourth gate electrode 24 (ninth gate electrode 29), and the orthographic projection of the second plate 72 on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate. In an exemplary embodiment, the second plate 72 may serve as the lower plate of the second storage capacitor.

[0163] In an exemplary embodiment, the orthographic projection areas of the first electrode plate 71 and the second electrode plate 72 on the substrate may be the same or different. For example, the orthographic projection area of ​​the second electrode plate 72 on the substrate may be larger than the orthographic projection area of ​​the first electrode plate 71 on the substrate.

[0164] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the ninth active layer are all conductorized.

[0165] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a schematic diagram of the second conductive layer in FIG10A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0166] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a fourth shielding electrode 39, a third plate 73 of a first storage capacitor, a fourth plate 74 of a second storage capacitor, and a second reference signal line 92.

[0167] In an exemplary embodiment, the shapes of the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33 and the second reference signal line 92 can be a line shape in which the main part extends along the first direction X, the first light-emitting signal line 31, the second light-emitting signal line 32 and the repair line 33 can be located between the first gate electrode 21 and the first scanning signal line 61, and the second reference signal line 92 can be located on the side of the fourth gate electrode 24 in the opposite direction of the second direction Y.

[0168] In an exemplary embodiment, the first light-emitting signal line 31 can be located on one side of the second direction Y of the first gate electrode 21 of the present circuit unit, the second light-emitting signal line 32 can be located on one side of the second direction Y of the first light-emitting signal line 31 of the present circuit unit, and the repair line 33 can be located on one side of the second direction Y of the second light-emitting signal line 32 of the present circuit unit, that is, the second light-emitting signal line 32 can be located between the first light-emitting signal line 31 and the repair line 33.

[0169] In an exemplary embodiment, a first light-emitting connection block 31-1 is provided on one side of the first light-emitting signal line 31 close to the second light-emitting signal line 32. The first light-emitting connection block 31-1 can be provided in each circuit unit. The first end of the first light-emitting connection block 31-1 is connected to the first light-emitting signal line 31, and the second end of the first light-emitting connection block 31-1 extends toward the second light-emitting signal line 32. The first light-emitting connection block 31-1 is configured to be connected to the fifth gate electrode 25 through a seventh connection electrode formed subsequently. In an exemplary embodiment, the first light-emitting signal line 31 and the plurality of first light-emitting connection blocks 31-1 can be an integrated structure connected to each other.

[0170] In an exemplary embodiment, a second light-emitting connection block 32-1 is provided on one side of the second light-emitting signal line 32 close to the first light-emitting signal line 31. The second light-emitting connection block 32-1 can be provided in each circuit unit. The first end of the second light-emitting connection block 32-1 is connected to the second light-emitting signal line 32, and the second end of the second light-emitting connection block 32-1 extends toward the direction of the first light-emitting signal line 31. The second light-emitting connection block 32-1 is configured to be connected to the sixth gate electrode 26 through the eighth connection electrode formed later. In an exemplary embodiment, the second light-emitting signal line 32 and the plurality of second light-emitting connection blocks 32-1 can be an integrated structure connected to each other.

[0171] In an exemplary embodiment, a second reference connection block 92-1 is provided on a side of the second reference signal line 92 of the nth cell row away from the second electrode plate 72 of the nth cell row. The second reference connection block 92-1 can be provided in each circuit cell. The first end of the second reference connection block 92-1 is connected to the second reference signal line 92, and the second end of the second reference connection block 92-1 extends in a direction away from the second electrode plate 72, that is, toward the n-1th cell row. In an exemplary embodiment, the second reference connection block 92-1 of the second reference signal line 92 in the nth cell row is configured to be connected to the first region of the eighth active layer in the n-1th cell row via a subsequently formed sixth connection electrode, thereby providing a second reference signal to the first electrode of the eighth transistor T8 in the n-1th cell row. In an exemplary embodiment, the second reference signal line 92 and the plurality of second reference connection blocks 92-1 can be an integrated structure connected to each other.

[0172] In an exemplary embodiment, the contour shape of the third plate 73 of the first storage capacitor can be rectangular, the corners of the rectangle can be chamfered, and it can be located between the first light-emitting signal line 31 and the second reference signal line 92 of the circuit unit. The positive projection of the third plate 73 on the substrate at least partially overlaps with the positive projection of the first plate 71 on the substrate. The third plate 73 can serve as the upper plate of the first storage capacitor (the second end of the first storage capacitor C1), and the first plate 71 and the third plate 73 constitute the first storage capacitor C1 of the pixel driving circuit.

[0173] In an exemplary embodiment, the outline shape of the fourth plate 74 of the second storage capacitor can be rectangular, the corners of the rectangle can be chamfered, and it can be located between the second reference signal line 92 and the third plate 73 of the circuit unit. The positive projection of the fourth plate 74 on the substrate at least partially overlaps with the positive projection of the second plate 72 on the substrate. The fourth plate 74 can serve as the upper plate of the second storage capacitor (the first end of the second storage capacitor C2), and the second plate 72 and the fourth plate 74 constitute the second storage capacitor C2 of the pixel driving circuit.

[0174] In an exemplary embodiment, the orthographic projection areas of the third electrode plate 73 and the fourth electrode plate 74 on the substrate may be the same or different. For example, the orthographic projection area of ​​the fourth electrode plate 74 on the substrate may be larger than the orthographic projection area of ​​the third electrode plate 73 on the substrate.

[0175] In an exemplary embodiment, a first plate connecting line 73-1 is provided on a side of the third plate 73 close to the fourth plate 74. A first end of the first plate connecting line 73-1 is connected to the third plate 73, and a second end of the first plate connecting line 73-1 extends toward the second reference signal line 92. The first plate connecting line 73-1 is configured to be connected to the second region of the fourth active layer (also the second region of the ninth active layer) through a second connecting electrode formed subsequently, so that the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, and the third plate 73 have the same potential.

[0176] In an exemplary embodiment, a second plate connection line 74-1 may be provided on one side of the fourth plate 74 in the first direction X or in the direction opposite to the first direction X. The first end of the second plate connection line 74-1 is connected to the fourth plate 74 of the current circuit unit, and the second end of the second plate connection line 74-1 extends along the first direction X or in the direction opposite to the first direction X to connect to the fourth plate 74 of an adjacent circuit unit, thereby interconnecting the fourth plates 74 of adjacent circuit units in a row. In an exemplary embodiment, multiple fourth plates 74 and multiple second plate connection lines 74-1 may be interconnected integrally. Because the fourth plates 74 are connected to a subsequently formed first power line, the integrated fourth plates 74 of multiple circuit units can be reused as transverse power lines extending in the first direction X. This not only ensures that the multiple fourth plates in a row have the same potential, but also reduces the voltage drop of the first power signal, thereby improving panel uniformity, preventing display defects on the display substrate, and ensuring the display quality of the display substrate.

[0177] In an exemplary embodiment, a first groove K1 may be formed between the mutually adjacent edges of two fourth plates 74 and the edge of the second plate connecting line 74-1 adjacent in the first direction X. The first groove K1 is configured to accommodate the first plate connecting line 73-1. The first plate connecting line 73-1 on the third plate 73 extends within the first groove K1 toward the second reference signal line 92, so that a subsequently formed twelfth via hole can be moved as upward as possible and as close as possible to the second region of the fourth active layer (also the second region of the ninth active layer). The twelfth via hole is configured to connect a subsequently formed second connecting electrode to the first plate connecting line 73-1 through the via hole. The second connecting electrode is also connected to the second region of the fourth active layer (also the second region of the ninth active layer) through the via hole, so that the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, and the third plate 73 have the same potential.

[0178] In an exemplary embodiment, a first opening 75 is provided on the third electrode plate 73 of each circuit unit. The first opening 75 may be located in the middle of the third electrode plate 73 and may be rectangular, forming a ring-shaped structure. The first opening 75 exposes the third insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 on the substrate includes the orthographic projection of the first opening 75 on the substrate. In an exemplary embodiment, the first opening 75 is configured to accommodate a tenth via hole formed subsequently. The tenth via hole is located within the first opening 75 and exposes the first electrode plate 71, allowing a first connecting electrode formed subsequently to connect to the first electrode plate 71.

[0179] In an exemplary embodiment, a second opening 76 is provided on the fourth electrode plate 74 of each circuit unit. The second opening 76 may be located in the middle of the fourth electrode plate 74 and may be rectangular, forming a ring-shaped structure. The second opening 76 exposes the third insulating layer covering the second electrode plate 72, and the orthographic projection of the second electrode plate 72 on the substrate includes the orthographic projection of the second opening 76 on the substrate. In an exemplary embodiment, the second opening 76 is configured to accommodate a subsequently formed eleventh via. The eleventh via is located within the second opening 76 and exposes the second electrode plate 72, allowing a subsequently formed second connecting electrode to be connected to the second electrode plate 72.

[0180] In an exemplary embodiment, the first shielding electrode 36 may be T-shaped and may be located on a side of the fourth electrode plate 74 that is adjacent to the first light-emitting signal line 31. The first shielding electrode 36 may be provided in each circuit unit. The T-shaped first shielding electrode 36 may include a first extension segment 36-1 and a first shielding segment 36-2. The first end of the first extension segment 36-1 is connected to the fourth electrode plate 74, and the second end of the first extension segment 36-1 extends toward the first light-emitting signal line 31 and is connected to the first shielding segment 36-2. The first shielding segment 36-2 can be shaped like a strip extending along the first direction X. For the first shielding end of the first shielding segment 36-2 located on one side of the first extension segment 36-1 in the first direction X, and the second shielding end located on the opposite side of the first extension segment 36-1 in the first direction X, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 in the current circuit unit on the substrate. The orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the first transistor T1 and the second transistor T2 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving display quality.

[0181] In an exemplary embodiment, the second shielding electrode 37 may be L-shaped and may be located on a side of the fourth plate 74 near the second reference signal line 92. The second shielding electrode 37 may be provided in each circuit unit. The L-shaped second shielding electrode 37 may include a second extension segment 37-1 and a second shielding segment 37-2. The first end of the second extension segment 37-1 is connected to the fourth plate 74, and the second end of the second extension segment 37-1 extends toward the second reference signal line 92 and then connects to the second shielding segment 37-2. The second shielding segment 37-2 may be in the shape of a strip extending along the first direction X. The orthographic projection of the second shielding segment 37-2 on the substrate at least partially overlaps with the orthographic projections of the second region of the fourth active layer and the second region of the ninth active layer in the circuit unit on the substrate. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the fifth node N5 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0182] In an exemplary embodiment, the first shield electrode 36 , the second shield electrode 37 , and the fourth electrode plate 74 may be an integral structure connected to each other.

[0183] In an exemplary embodiment, since the second region of the fourth active layer (the second region of the ninth active layer) is a conductor layer that has been subjected to a conductorization process, the second shielding electrode 37 of the second conductive layer is also a conductor layer. Therefore, the second region of the fourth active layer (the second region of the ninth active layer) and the second shielding electrode 37 can form an additional capacitor of the second storage capacitor. The lower electrode of the additional capacitor is provided in the semiconductor layer and is connected to the second electrode plate 72 through a second connecting electrode formed subsequently. The upper electrode plate of the additional capacitor (the second shielding electrode 37) is provided in the second conductive layer and is an integral structure interconnected with the fourth electrode plate 74, thereby forming an additional capacitor of the second storage capacitor, and the additional capacitor is connected in parallel with the second storage capacitor. By forming an additional capacitor of the second storage capacitor, the present disclosure can effectively increase the total capacity of the second storage capacitor, improve the operating performance of the pixel driving circuit, and improve the display effect.

[0184] In an exemplary embodiment, the third and fourth shielding electrodes 38 and 39 may be rectangular in shape and may be located on the side of the second reference signal line 92 near the fourth electrode plate 74. The third and fourth shielding electrodes 38 and 39 may be provided in each circuit unit. The first ends of the third and fourth shielding electrodes 38 and 39 are connected to the second reference signal line 92, and the second ends of the third and fourth shielding electrodes 38 and 39 extend toward the fourth electrode plate 74. The orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor T4 in this circuit unit. The orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the ninth active layer between the two gate electrodes of the ninth transistor T9 in this circuit unit. In an exemplary embodiment, the third shielding electrode 38 is configured to shield the fourth transistor T4 from the effects of data voltage jumps, and the fourth shielding electrode 39 is configured to shield the ninth transistor T9 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driver circuit and improving display quality.

[0185] In an exemplary embodiment, the third shielding electrode 38 , the fourth shielding electrode 39 , and the second reference signal line 92 may be an integral structure connected to each other.

[0186] In an exemplary embodiment, the repair line 33 is a pre-set repair signal line, which is configured to input a signal to the anode of the sub-pixel with the bright spot defect through the repair line 33 to repair it into a dark spot when a bright spot defect occurs on the display substrate.

[0187] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided in each circuit unit, as shown in FIG. 11 .

[0188] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21 and a twenty-second via V22.

[0189] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first initial signal line to the first region of the first active layer through the via hole.

[0190] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second via hole V2 is configured to connect the subsequently formed first connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0191] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the third via hole V3 are etched away to expose the surface of the first area of ​​the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0192] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the fourth active layer (also the second area of ​​the ninth active layer) on the substrate, and the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of ​​the fourth active layer (also the second area of ​​the ninth active layer), and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second area of ​​the fourth active layer (also the second area of ​​the ninth active layer) through the via hole.

[0193] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first region of the fifth active layer, and the fifth via hole V5 is configured to connect a subsequently formed fourth connecting electrode to the first region of the fifth active layer through the via hole.

[0194] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the sixth via hole V6 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0195] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first region of the seventh active layer, and the seventh via V7 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via.

[0196] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the first region of the eighth active layer, and the eighth via V8 is configured to connect the subsequently formed sixth connecting electrode to the first region of the eighth active layer through the via hole.

[0197] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first region of the ninth active layer, and the ninth via V9 is configured to connect a subsequently formed first reference signal line to the first region of the ninth active layer through the via.

[0198] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first opening 75 of the third electrode plate 73 on the substrate, the fourth insulating layer and the third insulating layer in the tenth via hole V10 are etched away, exposing the surface of the first electrode plate 71, and the tenth via hole V10 is configured to connect the subsequently formed first connecting electrode to the first electrode plate 71 through the via hole.

[0199] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second opening 76 of the fourth electrode plate 74 on the substrate, the fourth insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the second electrode plate 72, and the eleventh via hole V11 is configured to connect a subsequently formed second connecting electrode to the second electrode plate 72 through the via hole.

[0200] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first electrode connecting line 73-1 of the third electrode 73 on the substrate, the fourth insulating layer in the twelfth via hole V12 is etched away, exposing the surface of the first electrode connecting line 73-1, and the twelfth via hole V12 is configured to connect the subsequently formed second connecting electrode to the first electrode connecting line 73-1 through the via hole.

[0201] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the fourth electrode plate 74 on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the fourth electrode plate 74, and the thirteenth via hole V13 is configured to connect a subsequently formed first power connection line to the fourth electrode plate 74 through the via hole.

[0202] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the fourth insulating layer and the third insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the first gate electrode 21, and the fourteenth via hole V14 is configured to connect the subsequently formed fourth scanning signal line to the first gate electrode 21 through the via hole.

[0203] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second gate electrode 22 on the substrate, the fourth insulating layer and the third insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the second gate electrode 22, and the fifteenth via hole V15 is configured to connect the subsequently formed fifth scan signal line to the second gate electrode 22 through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the fourth gate electrode 24 on the substrate, the fourth insulating layer and the third insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the fourth gate electrode 24, and the sixteenth via hole V16 is configured to connect the subsequently formed third scan signal line to the fourth gate electrode 24 through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the fifth gate electrode 25 on the substrate, the fourth insulating layer and the third insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the fifth gate electrode 25, and the seventeenth via hole V17 is configured to connect the subsequently formed seventh connecting electrode to the fifth gate electrode 25 through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the fourth insulating layer and the third insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the sixth gate electrode 26, and the eighteenth via hole V18 is configured to connect the subsequently formed eighth connecting electrode to the sixth gate electrode 26 through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the ninth gate electrode 29 on the substrate, the fourth insulating layer and the third insulating layer in the nineteenth via hole V19 are etched away to expose the surface of the ninth gate electrode 29, and the nineteenth via hole V19 is configured to connect a subsequently formed second scanning signal line to the ninth gate electrode 29 through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the first light-emitting connection block 31-1 of the first light-emitting signal line 31 on the substrate, the fourth insulating layer in the twentieth via hole V20 is etched away, exposing the surface of the first light-emitting connection block 31-1, and the twentieth via hole V20 is configured to connect the subsequently formed seventh connection electrode to the first light-emitting connection block 31-1 through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second light-emitting connection block 32-1 of the second light-emitting signal line 32 on the substrate, the fourth insulating layer in the twenty-first via hole V21 is etched away, exposing the surface of the second light-emitting connection block 32-1, and the twenty-first via hole V21 is configured to connect the subsequently formed eighth connection electrode to the second light-emitting connection block 32-1 through the via hole.

[0210] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the second reference connection block 92-1 of the second reference signal line 92 on the substrate, the fourth insulating layer in the twenty-second via V22 is etched away to expose the surface of the second reference connection block 92-1, and the twenty-second via V22 is configured to connect the subsequently formed sixth connection electrode to the second reference connection block 92-1 through the via.

[0211] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0212] In an exemplary embodiment, the third conductive layer patterns of multiple circuit units in the display substrate may include: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a fifth scan signal line 65, a first power connection line 68, a second power connection line 69, a first initial signal line 81, a second initial signal line 82 and a first reference signal line 91.

[0213] In an exemplary embodiment, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second power connection line 69, the first initial signal line 81, the second initial signal line 82, and the first reference signal line 91 may be in the shape of lines whose main portions extend along the first direction X. The second scan signal line 62, the third scan signal line 63, and the first reference signal line 91 may be located on a side of the fourth electrode plate 74 opposite to the second direction Y, the fourth scan signal line 64, the fifth scan signal line 65, the first initial signal line 81, and the second initial signal line 82 may be located on a side of the third electrode plate 73 in the second direction Y, the first power connection line 68 may be located in the region where the fourth electrode plate 74 is located, the second power connection line 69 may be located in the region where the third electrode plate 73 is located, and the second power connection line 69 may be located on one side of the first power connection line 68 in the second direction Y.

[0214] In an exemplary embodiment, the first reference signal line 91 can be located on the side of the fourth electrode 74 opposite to the second direction Y, the second scanning signal line 62 can be located on the side of the first reference signal line 91 opposite to the second direction Y, and the third scanning signal line 63 can be located on the side of the second scanning signal line 62 opposite to the second direction Y.

[0215] In an exemplary embodiment, the fourth scan signal line 64 can be located on one side of the third electrode 73 in the second direction Y, the first initial signal line 81 can be located on one side of the fourth scan signal line 64 in the second direction Y, the fifth scan signal line 65 can be located on one side of the first initial signal line 81 in the second direction Y, and the second initial signal line 82 can be located on one side of the fifth scan signal line 65 in the second direction Y.

[0216] In an exemplary embodiment, the first power connection line 68 can be located on a side of the fourth electrode plate 74 close to the third electrode plate 73, and the orthographic projection of the first power connection line 68 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 on the substrate. The first power connection line 68 is configured to be connected to the subsequently formed first power line to form a high-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0217] In an exemplary embodiment, the second power connection line 69 can be located on a side of the third electrode plate 73 close to the fourth electrode plate 74, and the orthographic projection of the second power connection line 69 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 73 on the substrate. The second power connection line 69 is configured to be connected to a second power line formed subsequently to form a low-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0218] In an exemplary embodiment, the second scan signal line 62 is connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via V19, thereby realizing that the second scan signal line 62 is connected to the ninth gate electrode 29 of the ninth transistor T9, and the second scan signal line 62 can control the conduction and disconnection of the ninth transistor T9.

[0219] In an exemplary embodiment, the fifth scan signal line 65 is connected to the second gate electrode 22 in each circuit unit through the fifteenth via V15, thereby achieving the connection between the fifth scan signal line 65 and the second gate electrode 22 of the second transistor T2, and the fifth scan signal line 65 can control the conduction and disconnection of the second transistor T2.

[0220] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 can be extended to the frame area and connected to the same gate driving circuit to output the same scan signal, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.

[0221] In an exemplary embodiment, the third scan signal line 63 is connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, thereby realizing that the third scan signal line 63 is connected to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0222] In an exemplary embodiment, the fourth scan signal line 64 is connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, thereby connecting the fourth scan signal line 64 to the first gate electrode 21 of the first transistor T1. The fourth scan signal line 64 can control the on and off of the first transistor T1.

[0223] In an exemplary embodiment, the first initial signal line 81 is connected to the first region of the first active layer in each circuit unit through the first via V1, thereby achieving the connection between the first initial signal line 81 and the first electrode of the first transistor T1. The first initial signal line 81 can write the first initial signal into the first electrode of the first transistor T1.

[0224] In an exemplary embodiment, the second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby realizing that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal into the first electrode of the seventh transistor T7.

[0225] In an exemplary embodiment, the first reference signal line 91 is connected to the first region of the ninth active layer in each circuit unit through the ninth via V9, thereby realizing that the first reference signal line 91 is connected to the first electrode of the ninth transistor T9, and the first reference signal line 91 can write the first reference signal into the first electrode of the ninth transistor T9.

[0226] In an exemplary embodiment, a reference connection block 91-1 is provided on one side of the first reference signal line 91 close to the first power connection line 68, a first end of the reference connection block 91-1 is connected to the first reference signal line 91, and a second end of the reference connection block 91-1 extends toward the direction of the first power connection line 68, and the reference connection block 91-1 is configured to be connected to a reference signal connection line formed subsequently.

[0227] In the exemplary embodiment, the first power connection line 68 is connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via V13, thereby achieving the connection between the first power connection line 68 and the fourth electrode plate 74. Since the first power connection line 68 is connected to the first power line formed later, the first power connection line 68 can write the first power signal to the upper electrode plate of the second storage capacitor (the first end of the second storage capacitor).

[0228] In the exemplary embodiment, a first power connection block 68-1 is provided on a side of the first power connection line 68 away from the second power connection line 69. A first end of the first power connection block 68-1 is connected to the first power connection line 68, and a second end of the first power connection block 68-1 extends in a direction away from the second power connection line 69. In the exemplary embodiment, the first power connection block 68-1 is configured to be connected to the fourth electrode plate 74 through the thirteenth via V13, and is also configured to be connected to the first power line formed later.

[0229] In an exemplary embodiment, in at least one circuit unit, a second power connection block 69-1 is provided on a side of the second power connection line 69 away from the first power connection line 68. A first end of the second power connection block 69-1 is connected to the second power connection line 69, and a second end of the second power connection block 69-1 extends in a direction away from the first power connection line 68. The second power connection block 69-1 is configured to be connected to a second power line formed later. In an exemplary embodiment, the second power connection block 69-1 can be provided between the first circuit unit and the second circuit unit.

[0230] In an exemplary embodiment, the first connection electrode 41 may be in the shape of a strip with a main portion extending along the second direction Y. The first connection electrode 41 may be located between the fourth scan signal line 64 and the second power connection line 69. A first end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via hole V2, and a second end of the first connection electrode 41 is connected to the first electrode plate 71 via a tenth via hole V10. In an exemplary embodiment, the first connection electrode 41 enables the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first storage capacitor (i.e., the first end of the first storage capacitor) to have the same potential. The first connection electrode 41 may serve as the first node N1 of the pixel driving circuit.

[0231] In an exemplary embodiment, the second connection electrode 42 may be shaped like a zigzag line with a main portion extending along the second direction Y. The second connection electrode 42 may be located between the first reference signal line 91 and the first power connection line 68. A first end of the second connection electrode 42 is connected to the second region of the fourth active layer (also the second region of the ninth active layer) via a fourth via V4. A second end of the second connection electrode 42 is connected to the first plate connection line 73-1 via a twelfth via V12. A third end between the first and second ends is connected to the second plate 72 via an eleventh via V11. In an exemplary embodiment, the second connection electrode 42 causes the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third plate 73 of the first storage capacitor (i.e., the second end of the first storage capacitor), and the second plate 72 of the second storage capacitor (i.e., the second end of the second storage capacitor) to have the same potential. The second connection electrode 42 may serve as the fifth node N5 of the pixel driving circuit.

[0232] In an exemplary embodiment, the third connection electrode 43 may be rectangular in shape and may be located between the first reference signal line 91 and the first power connection line 68. The third connection electrode 43 is connected to the first region of the fourth active layer through a third via V3. In an exemplary embodiment, the third connection electrode 43 may serve as a first electrode of the fourth transistor T4 and may be configured to be connected to a subsequently formed data signal line.

[0233] In an exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape and may be located between the fifth scan signal line 65 and the second initial signal line 82. The fourth connection electrode 44 is connected to the first region of the fifth active layer through a fifth via hole V5. In an exemplary embodiment, the fourth connection electrode 44 may serve as a first electrode of the fifth transistor T5 and may be configured to be connected to a first power line formed subsequently.

[0234] In an exemplary embodiment, the fifth connection electrode 45 may be in an "L" shape and may be located between the fifth scan signal line 65 and the second initial signal line 82. The fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a sixth via hole V6. In an exemplary embodiment, the fifth connection electrode 45 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 and is configured to be connected to an anode connection electrode formed subsequently.

[0235] In an exemplary embodiment, the sixth connection electrode 46 may be in the shape of a strip with a main portion extending along the first direction X. The sixth connection electrode 46 may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the sixth connection electrode 46 is connected to the first region of the eighth active layer via an eighth via hole V8, and a second end of the sixth connection electrode 46 is connected to the second reference connection block 92-1 via a twenty-second via hole V22. In an exemplary embodiment, the sixth connection electrode 46 may serve as the first electrode of the eighth transistor T8. Since the second reference connection block 92-1 is connected to the second reference signal line 92, the second reference signal line 92 is connected to the first electrode of the eighth transistor T8. The second reference signal line 92 in the nth cell row may write the second reference signal into the first electrode of the eighth transistor T8 in the (n-1)th cell row.

[0236] In an exemplary embodiment, the seventh connection electrode 47 may be in the shape of a bar with a main portion extending along the first direction X. The seventh connection electrode 47 may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the seventh connection electrode 47 is connected to the fifth gate electrode 25 via a seventeenth via hole V17, and a second end of the seventh connection electrode 47 is connected to the first light-emitting connection block 31-1 via a twentieth via hole V20. Since the first light-emitting connection block 31-1 is connected to the first light-emitting signal line 31, the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5. The first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0237] In an exemplary embodiment, the eighth connection electrode 48 may be in the shape of a bar with a main portion extending along the first direction X. The eighth connection electrode 48 may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the eighth connection electrode 48 is connected to the sixth gate electrode 26 via an eighteenth via hole V18, and a second end of the eighth connection electrode 48 is connected to the second light-emitting connection block 32-1 via a twenty-first via hole V21. Since the second light-emitting connection block 32-1 is connected to the second light-emitting signal line 32, the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6. The second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0238] (16) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein a plurality of vias are provided in each circuit unit, as shown in FIG. 13 .

[0239] In an exemplary embodiment, the plurality of via holes of each circuit unit in the display substrate includes at least a thirty-first via hole V31 , a thirty-second via hole V32 , a thirty-third via hole V33 , a thirty-fourth via hole V34 , and a thirty-fifth via hole V35 .

[0240] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the third connecting electrode 43 on the substrate, the fifth insulating layer in the thirty-first via hole V31 is removed, exposing the surface of the third connecting electrode 43, and the thirty-first via hole V31 is configured to connect a subsequently formed data signal line to the third connecting electrode 43 through the via hole.

[0241] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the fifth insulating layer in the thirty-second via V32 is removed, exposing the surface of the fourth connecting electrode 44, and the thirty-second via V32 is configured to connect the subsequently formed first power line to the fourth connecting electrode 44 through the via.

[0242] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate, the fifth insulating layer in the thirty-third via V33 is removed, exposing the surface of the fifth connecting electrode 45, and the thirty-third via V33 is configured to connect the subsequently formed anode connecting electrode to the fifth connecting electrode 45 through the via.

[0243] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the reference connection block 91-1 of the first reference signal line 91 on the substrate, the fifth insulating layer in the thirty-fourth via V34 is removed, exposing the surface of the reference connection block 91-1, and the thirty-fourth via V34 is configured to connect the subsequently formed reference signal connection line to the reference connection block 91-1 through the via.

[0244] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first power connection block 68-1 of the first power connection line 68 on the substrate, the fifth insulating layer in the thirty-fifth via V35 is removed, exposing the surface of the first power connection block 68-1, and the thirty-fifth via V35 is configured to connect the subsequently formed first power line to the first power connection block 68-1 through the via.

[0245] In an exemplary embodiment, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 on the substrate is located within the orthographic projection of the second power connection block 69-1 of the second power connection line 69 on the substrate. The fifth insulating layer within the thirty-sixth via V36 is removed, exposing the surface of the second power connection block 69-1. The thirty-sixth via V36 is configured to connect a subsequently formed second power line to the second power connection block 69-1 through the via. In an exemplary embodiment, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0246] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer, as shown in Figures 14A and 14B, where Figure 14B is a schematic diagram of the fourth conductive layer in Figure 14A. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0247] In an exemplary embodiment, each of the fourth conductive layer patterns of the plurality of circuit units in the display substrate may include a first power supply line 51 , a data signal line 53 , a reference signal connection line 54 , and an anode connection electrode 55 .

[0248] In an exemplary embodiment, the shape of the first power line 51, the data signal line 53 and the reference signal connection line 54 can be a strip shape with the main portion extending along the second direction Y, the first power line 51 can be located on one side of the data signal line 53 in the first direction X, and the reference signal connection line 54 can be located on one side of the first power line 51 in the first direction X, that is, the first power line 51 can be located between the data signal line 53 and the reference signal connection line 54.

[0249] In an exemplary embodiment, the first power line 51 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first power line 51 is connected to the fourth connection electrode 44 via the thirty-second via V32 and to the first power connection block 68-1 via the thirty-fifth via V35. Since the fourth connection electrode 44 is connected to the first region of the fifth active layer via the via, the first power line 51 writes the first power signal to the first electrode of the fifth transistor T5. Since the first power connection block 68-1 is connected to the first power connection line 68, the first power connection line 68, whose main portion extends along the first direction X, is interconnected with the first power line 51, whose main portion extends along the second direction Y. The first power lines 51 and 68 form a mesh structure on the display substrate that transmits the first power signal. This effectively reduces the resistance of the first power line 51 and the voltage drop of the first power signal, and also effectively improves the uniformity of the first power signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0250] In an exemplary embodiment, a power shielding block 51-1 is disposed on a side of the first power line 51 near the reference signal connection line 54. A first end of the power shielding block 51-1 is connected to the first power line 51, and a second end of the power shielding block 51-1 extends toward the reference signal connection line 54. The power shielding block 51-1 may be rectangular in shape, and the orthographic projection of the power shielding block 51-1 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 41 on the substrate. Because the first connection electrode 41 serves as the first node N1 in the pixel driving circuit, the constant voltage power shielding block 51-1 can effectively shield the first node N1 from the effects of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0251] In an exemplary embodiment, the first power line 51 and the power shielding block 51 - 1 may be an integral structure connected to each other.

[0252] In an exemplary embodiment, the orthographic projection of the power shielding block 51 - 1 on the substrate may include the orthographic projection of the first connection electrode 41 on the substrate.

[0253] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 42 on the substrate. Because the second connection electrode 42 serves as the fifth node N5 in the pixel driving circuit, the constant voltage first power line 51 can effectively shield the fifth node N5 from the influence of other signals in the pixel driving circuit, preventing other signals from affecting the potential of the fifth node N5 of the pixel driving circuit, thereby improving the display effect.

[0254] In an exemplary embodiment, the first power lines 51 may be designed with unequal widths. The unequal width design of the first power lines 51 not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power lines and the data signal lines.

[0255] In an exemplary embodiment, the data signal line 53 may be in the shape of a straight line with a main portion extending along the second direction Y. The data signal line 53 is connected to the third connection electrode 43 through the thirty-first via hole V31. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via hole, the data signal line 53 writes the data signal to the first electrode of the fourth transistor T4.

[0256] In an exemplary embodiment, the reference signal connection line 54 may be shaped as a straight line with a main portion extending along the second direction Y. The reference signal connection line 54 is connected to the reference connection block 91-1 via a thirty-fourth via V34. Since the reference connection block 91-1 is connected to the first reference signal line 91, the first reference signal line 91, whose main portion extends along the first direction X, is interconnected with the reference signal connection line 54, whose main portion extends along the second direction Y. This allows the first reference signal line 91 and the reference signal connection line 54 to form a mesh structure on the display substrate for transmitting the first reference signal. This effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, and also effectively improves the uniformity of the first reference signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0257] In an exemplary embodiment, the anode connection electrode 55 may be rectangular in shape and is connected to the fifth connection electrode 45 via a thirty-third via hole V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via the via hole, the anode connection electrode 55 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the anode connection electrode 55 is configured to be connected to a subsequently formed anode, thereby enabling the pixel driving circuit to drive the light-emitting device.

[0258] In an exemplary embodiment, an orthographic projection of the anode connection electrode 55 on the substrate at least partially overlaps with an orthographic projection of the repair line 33 on the substrate.

[0259] In an exemplary embodiment, the fourth conductive layer in at least one circuit unit may further include a second power line 52. The second power line 52 may be shaped as a straight line with a main portion extending along the second direction Y. The second power line 52 is connected to the second power connection block 69-1 via a thirty-sixth via V36. The connection between the second power connection block 69-1 and the second power connection line 69 establishes a connection between the second power connection line 69, whose main portion extends along the first direction X, and the second power line 52, whose main portion extends along the second direction Y. This allows the second power lines 52 and 69 to form a mesh structure on the display substrate that transmits the second power signal. This not only effectively reduces the resistance of the second power line 52 and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal across the display substrate, effectively enhancing display uniformity and improving display quality. In an exemplary embodiment, the second power line 52 may be located between the reference signal connection line 54 of the first circuit unit and the data signal line 53 of the second circuit unit.

[0260] In an exemplary embodiment, the first power connection line 68 of the third conductive layer can be set in each unit row, and the first power line 51 of the fourth conductive layer can be set in each unit column. Multiple first power lines 51 are respectively connected to multiple first power connection lines 68 to form a mesh structure for transmitting the first power signal.

[0261] In an exemplary embodiment, the first reference signal line 91 of the third conductive layer can be set in each unit row, and the reference signal connection line 54 of the fourth conductive layer can be set in each unit column. Multiple first reference signal lines 91 are respectively connected to multiple reference signal connection lines 54 to form a mesh structure for transmitting the first reference signal.

[0262] In an exemplary embodiment, the second power connection line 69 of the third conductive layer can be arranged in each unit row, and the second power line 52 of the fourth conductive layer can be arranged every two unit columns. Multiple second power lines 52 are respectively connected to multiple second power connection lines 69 to form a mesh structure for transmitting the second power signal.

[0263] The subsequent preparation process may include forming a first flat layer pattern, a plurality of anode vias are provided on the first flat layer, the orthographic projection of the anode vias on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, the first flat layer in the anode via is removed to expose the surface of the anode connecting electrode, and the anode via is configured to connect the subsequently formed anode to the anode connecting electrode through the via.

[0264] At this point, the driving circuit layer of this embodiment is prepared on the substrate. In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer and an encapsulation structure layer can be sequentially prepared on the driving circuit layer, which will not be described in detail here.

[0265] Figure 15 is a schematic diagram of the planar structure of another display substrate in an exemplary embodiment of the present disclosure, illustrating the structure of the pixel driving circuit in three circuit units (first circuit unit, second circuit unit, and third circuit unit) in the display substrate. Figure 16 is a schematic diagram of the structure of the second scanning signal line and the fifth scanning signal line in Figure 15. As shown in Figures 15 and 16, the main structure of the pixel driving circuit in this exemplary embodiment is substantially the same as that in the aforementioned embodiment, except that the second scanning connection line 62 and the fifth scanning signal line 65 in this embodiment are double-layered scanning signal lines.

[0266] In an exemplary embodiment, the first power lines 51 extending along the second direction Y are connected to the first power connection lines 68 extending along the first direction X to form a mesh structure for transmitting the first power signal. The second power lines 52 extending along the second direction Y are connected to the second power connection lines 69 extending along the first direction X to form a mesh structure for transmitting the second power signal. The reference signal connection lines 54 extending along the second direction Y are connected to the first reference signal lines 91 extending along the first direction X to form a mesh structure for transmitting the first reference signal.

[0267] In an exemplary embodiment, at least one circuit unit may further include a first shielding electrode 36, a third shielding electrode 38, and a fourth shielding electrode 39. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 on the substrate. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate. The orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 on the substrate. The orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor T9 on the substrate. Because the active layer structures of the fourth transistor T4 and the ninth transistor T9 in this embodiment are different, a second shielding electrode is not provided in this embodiment.

[0268] In an exemplary embodiment, the first scan signal line 61 can be set in the first conductive layer, the repair line 33 can be set in the second conductive layer, the first light-emitting signal line 31, the second light-emitting signal line 32, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second power connection line 69, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91 and the second reference signal line 92 can be set in the third conductive layer, and the first power line 51, the second power line 52, the data signal line 53, the reference signal connection line 54 and the anode connection electrode 55 can be set in the fourth conductive layer.

[0269] In an exemplary embodiment, the driving circuit layer may further include a second scan connection line 62-1. The shape of the second scan connection line 62-1 may be a line shape in which the main portion extends along the first direction X. The orthographic projection of the second scan connection line 62-1 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line 62 on the substrate. The second scan signal line 62 is connected to the second scan connection line 62-1 to form a double-layer structure of a scan signal line.

[0270] In an exemplary embodiment, the second scan signal line 62 and the second scan connection line 62 - 1 may be disposed in different conductive layers, and the second scan signal line 62 and the second scan connection line 62 - 1 may be connected through a via.

[0271] In an exemplary embodiment, the second scan link line 62 - 1 may be disposed in the first conductive layer, and the second scan signal line 62 may be disposed in the third conductive layer.

[0272] In an exemplary embodiment, the driving circuit layer may further include a fifth scan connection line 65-1. The shape of the fifth scan connection line 65-1 may be a line shape in which the main portion extends along the first direction X. The orthographic projection of the fifth scan connection line 65-1 on the substrate at least partially overlaps with the orthographic projection of the fifth scan signal line 65 on the substrate. The fifth scan signal line 65 is interconnected with the fifth scan connection line 65-1 to form a double-layer structure of scan signal lines.

[0273] In an exemplary embodiment, the fifth scan signal line 65 and the fifth scan connection line 65 - 1 may be disposed in different conductive layers, and the fifth scan signal line 65 and the fifth scan connection line 65 - 1 may be connected through a via hole.

[0274] In an exemplary embodiment, the fifth scan link line 65 - 1 may be disposed in the second conductive layer, and the fifth scan signal line 65 may be disposed in the third conductive layer.

[0275] In an exemplary embodiment, this embodiment shows that the substrate preparation process may include the following operations.

[0276] (21) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as shown in FIG. 17 .

[0277] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display substrate may include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9, and the first to third active layers 11 to 13 and the fifth to eighth active layers 15 to 18 may be an integrated structure connected to each other, and the fourth active layer 14 and the ninth active layer 19 may be an integrated structure connected to each other.

[0278] In an exemplary embodiment, the structures and connection relationships of the first active layer 11 to the ninth active layer 19 are substantially the same as those of the aforementioned embodiment, except that the fourth active layer 14 may be shaped like an "n", and the first region 14-1 of the fourth active layer may be located on a side of the channel region of the fourth active layer close to the third active layer 13, while the ninth active layer 19 may be shaped like a broken line, and the first region 19-1 of the ninth active layer may be located on a side of the channel region of the ninth active layer away from the third active layer 13.

[0279] In an exemplary embodiment, the semiconductor layer of at least one circuit unit may include at least a first active pattern 10 and a second active pattern 20, the first active pattern 10 may include an active layer of the fourth transistor T4 and an active layer of the ninth transistor T9, and the second active pattern 20 may include active layers of the first to third transistors T1 to T3 and active layers of the fifth to eighth transistors T5 to T8.

[0280] In an exemplary embodiment, in at least one circuit unit, the first active pattern 10 is spaced apart from the second active pattern 20 , ie, the active layer of the transistor in the first active pattern 10 is not connected to the active layer of the transistor in the second active pattern 20 .

[0281] In an exemplary embodiment, in at least one unit row, the semiconductor layers in the circuit units adjacent in the first direction X are spaced apart from each other, that is, the semiconductor layer of the first circuit unit in the n-th unit row is not connected to the semiconductor layer of the second circuit unit in the n-th unit row, and the semiconductor layer of the second circuit unit in the n-th unit row is not connected to the semiconductor layer of the third circuit unit in the n-th unit row.

[0282] In an exemplary embodiment, in at least one unit column, the semiconductor layers in the circuit units adjacent in the second direction Y are spaced apart from each other, that is, the semiconductor layer of the first circuit unit in the n-1th unit row is not connected to the semiconductor layer of the first circuit unit in the nth unit row, and the semiconductor layer of the first circuit unit in the nth unit row is not connected to the semiconductor layer of the first circuit unit in the n+1th unit row.

[0283] (22) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG18A and FIG18B , where FIG18B is a schematic diagram of the first conductive layer in FIG18A .

[0284] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a first scan signal line 61, a second scan connection line 62-1, a first plate 71 of a first storage capacitor, and a second plate 72 of a second storage capacitor.

[0285] In the exemplary embodiment, the structures and connection relationships of the first gate electrode 21, the second gate electrode 22, the fifth gate electrode 25, the sixth gate electrode 26, the first scan signal line 61 and the first plate 71 of the first storage capacitor are substantially the same as those of the aforementioned embodiment.

[0286] In an exemplary embodiment, the fourth gate electrode 24 may be in the shape of a strip extending along the first direction X, and may be located between the second scan connection line 62-1 and the second electrode plate 72. The region where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4 of the dual-gate structure.

[0287] In an exemplary embodiment, the second scan connection line 62-1 may be shaped as a line extending along the first direction X and may be located on a side of the second electrode plate 72 opposite to the second direction Y. A gate block 62-10 is provided on a side of the second scan connection line 62-1 close to the second electrode plate 72. A first end of the gate block 62-10 is connected to the second scan connection line 62-1, and a second end of the gate block 62-10 extends toward the second electrode plate 72. The region where the second scan connection line 62-1 and the gate block 62-10 overlap with the ninth active layer may serve as the gate electrode of the ninth transistor T9 of the dual-gate structure. In an exemplary embodiment, the second scan connection line 62-1 may serve as a lower layer signal line of the second scan signal line of the dual-layer structure.

[0288] In an exemplary embodiment, the second plate 72 of the second storage capacitor may be rectangular, with chamfered corners, and may be located between the first plate 71 and the fourth gate electrode 24. The orthographic projection of the second plate 72 on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate. In an exemplary embodiment, the second plate 72 may serve as the lower plate of the second storage capacitor.

[0289] In an exemplary embodiment, a first groove K1 is provided on a side of the second electrode plate 72 close to the first electrode plate 71 . The first groove K1 is configured to accommodate the first electrode plate connecting wire 73 - 1 .

[0290] Different from the above-mentioned embodiment, in this embodiment, a second scan connection line 62 - 1 is provided in the first conductive layer, and thus a ninth gate electrode is not provided.

[0291] (23) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG19A and FIG19B , where FIG19B is a schematic diagram of the second conductive layer in FIG19A .

[0292] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a repair line 33, a first shielding electrode 36, a third shielding electrode 38, a fourth shielding electrode 39, a fifth scan connection line 65-1, a third plate 73 of the first storage capacitor, and a fourth plate 74 of the second storage capacitor.

[0293] In an exemplary embodiment, the shapes of the fifth scan connection line 65-1 and the repair line 33 can be line shapes whose main parts extend along the first direction X, the fifth scan connection line 65-1 can be located between the first gate electrode 21 and the fifth gate electrode 25, and the repair line 33 can be located between the fifth gate electrode 25 and the first scan signal line 61.

[0294] In an exemplary embodiment, the fifth scan connection line 65-1 may include a straight segment and a bent segment. The straight segment may be a straight line extending along the first direction X, and the bent segment may protrude toward the repair line 33 to avoid the second gate electrode 22. This ensures that the orthographic projection of the fifth scan connection line 65-1 on the substrate does not overlap with the orthographic projection of the second gate electrode 22 on the substrate. In an exemplary embodiment, the fifth scan connection line 65-1 may serve as a lower layer signal line of a double-layer structured fifth scan signal line.

[0295] In the exemplary embodiment, the position and structure of the repair line 33 are substantially the same as those in the previous embodiment.

[0296] In an exemplary embodiment, the contour shape of the third plate 73 of the first storage capacitor can be substantially similar to the shape of the first plate 71, and the orthographic projection of the third plate 73 on the substrate at least partially overlaps with the orthographic projection of the first plate 71 on the substrate. The third plate 73 can serve as the upper plate of the first storage capacitor, and the first plate 71 and the third plate 73 constitute the first storage capacitor C1 of the pixel driving circuit.

[0297] In an exemplary embodiment, the contour shape of the fourth plate 74 of the second storage capacitor can be substantially similar to the shape of the second plate 72, and the orthographic projection of the fourth plate 74 on the substrate at least partially overlaps with the orthographic projection of the second plate 72 on the substrate. The fourth plate 74 can serve as the upper plate of the second storage capacitor, and the second plate 72 and the fourth plate 74 constitute the second storage capacitor C2 of the pixel driving circuit.

[0298] In an exemplary embodiment, a first electrode plate connecting wire 73-1 is provided on a side of the third electrode plate 73 close to the fourth electrode plate 74. A first end of the first electrode plate connecting wire 73-1 is connected to the third electrode plate 73, and a second end of the first electrode plate connecting wire 73-1 extends toward the fourth electrode plate 74 and is located in a first groove K1 formed in the fourth electrode plate 74. The position, connection structure, and function of the first electrode plate connecting wire 73-1 are substantially the same as those in the aforementioned embodiment.

[0299] In an exemplary embodiment, a second plate connecting line 74 - 1 may be provided on one side of the fourth plate 74 in the first direction X or on the side opposite to the first direction X. The position, connection structure and function of the second plate connecting line 74 - 1 are substantially the same as those in the previous embodiment.

[0300] In an exemplary embodiment, a first opening 75 is provided on the third electrode plate 73 of each circuit unit, and a second opening 76 is provided on the fourth electrode plate 74 of each circuit unit. The positions, connection structures and functions of the first opening 75 and the second opening 76 are substantially the same as those in the aforementioned embodiment.

[0301] In an exemplary embodiment, the first shielding electrode 36 can be in a "T" shape and can be located on the fourth electrode 74 near the fifth scan connection line 65-1. The first shielding electrode 36 can be set in each circuit unit. The "T"-shaped first shielding electrode 36 can include a first extension segment 36-1 and a first shielding segment 36-2. The position, connection structure and function of the first extension segment 36-1 and the first shielding segment 36-2 are basically the same as those in the aforementioned embodiment.

[0302] In an exemplary embodiment, the third shielding electrode 38 may be L-shaped and may be located on a side of the fourth electrode plate 74 near the second scan connection line 62-1. The third shielding electrode 38 may be provided in each circuit unit. The third shielding electrode 38 may include a third extension segment 38-1 and a third shielding segment 38-2. The first end of the third extension segment 38-1 is connected to the fourth electrode plate 74, and the third end of the third extension segment 38-1 extends toward the second scan connection line 62-1 and is connected to the third shielding segment 38-2. The third shielding segment 38-2 may be in the shape of a strip extending along the first direction X. The orthographic projection of the third shielding segment 38-2 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor T4 in this circuit unit on the substrate. The third shielding electrode 38 is configured to shield the fourth transistor T4 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0303] In an exemplary embodiment, the fourth shielding electrode 39 may be in the shape of a strip extending along the second direction Y and may be located on a side of the fourth electrode plate 74 near the second scan connection line 62-1. The fourth shielding electrode 39 may be provided in each circuit unit. A first end of the fourth shielding electrode 39 is connected to the fourth electrode plate 74, and a second end of the fourth shielding electrode 39 extends in the direction of the second scan connection line 62-1. The orthographic projection of the second end of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the ninth active layer between the two gate electrodes of the ninth transistor T9 in this circuit unit on the substrate. In an exemplary embodiment, the fourth shielding electrode 39 is configured to shield the ninth transistor T9 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0304] In an exemplary embodiment, the fourth plate 74 , the first shield electrode 36 , the third shield electrode 38 , and the fourth shield electrode 39 may be an integral structure connected to one another.

[0305] Different from the above-mentioned embodiment, in this embodiment, a second scanning connection line 62 - 1 is provided in the second conductive layer, but no transverse second reference signal line, first light-emitting signal line and second light-emitting signal line are provided.

[0306] (24) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided in each circuit unit, as shown in FIG. 20 .

[0307] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a twenty-third via V23 and a twenty-fourth via V24.

[0308] In an exemplary embodiment, the positions, connection structures and functions of the first via hole V1 to the eighteenth via hole V18 are substantially the same as those in the aforementioned embodiment, except that the eighth via hole V8 is configured to connect the subsequently formed second reference signal line to the first region of the eighth active layer through the via hole, the seventeenth via hole V17 is configured to connect the subsequently formed first light-emitting signal line to the fifth gate electrode 25 through the via hole, and the eighteenth via hole V18 is configured to connect the subsequently formed second light-emitting signal line to the sixth gate electrode 26 through the via hole.

[0309] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the second scan connection line 62-1 on the substrate, the fourth insulating layer and the third insulating layer in the twenty-third via hole V23 are etched away to expose the surface of the second scan connection line 62-1, and the twenty-third via hole V23 is configured to connect the subsequently formed second scan signal line to the second scan connection line 62-1 through the via hole.

[0310] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the fifth scan connection line 65-1 on the substrate, the fourth insulating layer in the twenty-fourth via V24 is etched away, exposing the surface of the fifth scan connection line 65-1, and the twenty-fourth via V24 is configured to connect the subsequently formed fifth scan signal line to the fifth scan connection line 65-1 through the via.

[0311] (25) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG. 21A and FIG. 21B , where FIG. 21B is a schematic diagram of the third conductive layer in FIG. 21A .

[0312] In an exemplary embodiment, the third conductive layer patterns of multiple circuit units in the display substrate may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a first light-emitting signal line 31, a second light-emitting signal line 32, a second scanning signal line 62, a third scanning signal line 63, a fourth scanning signal line 64, a fifth scanning signal line 65, a first power connection line 68, a second power connection line 69, a first initial signal line 81, a second initial signal line 82, a first reference signal line 91 and a second reference signal line 92.

[0313] In an exemplary embodiment, the shapes of the first light-emitting signal line 31, the second light-emitting signal line 32, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second power connection line 69, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91 and the second reference signal line 92 can be a line shape in which the main part extends along the first direction X. The second scanning signal line 62, the third scanning signal line 63 and the first reference signal line 91 can be located on the side of the fourth electrode 74 in the opposite direction Y of the second direction, the first light-emitting signal line 31, the second light-emitting signal line 32, the fourth scanning signal line 64, the fifth scanning signal line 65, the first initial signal line 81, the second initial signal line 82 and the second reference signal line 92 can be located on the side of the second direction Y of the third electrode 73, the first power connection line 68 can be located in the area where the fourth electrode 74 is located, the second power connection line 69 can be located in the area where the third electrode 73 is located, and the second power connection line 69 can be located on the side of the second direction Y of the first power connection line 68.

[0314] In an exemplary embodiment, the third scan signal line 63 can be located on the side of the fourth electrode 74 opposite to the second direction Y, the second scan signal line 62 can be located on the side of the third scan signal line 63 opposite to the second direction Y, and the first reference signal line 91 can be located on the side of the second scan signal line 62 opposite to the second direction Y.

[0315] In an exemplary embodiment, the fourth scan signal line 64 can be located on one side of the third electrode 73 in the second direction Y, the first initial signal line 81 can be located on one side of the fourth scan signal line 64 in the second direction Y, the fifth scan signal line 65 can be located on one side of the first initial signal line 81 in the second direction Y, the first light-emitting signal line 31 can be located on one side of the fifth scan signal line 65 in the second direction Y, the second light-emitting signal line 32 can be located on one side of the first light-emitting signal line 31 in the second direction Y, the second reference signal line 92 can be located on one side of the second light-emitting signal line 32 in the second direction Y, and the second initial signal line 82 can be located on one side of the second reference signal line 92 in the second direction Y.

[0316] In an exemplary embodiment, the first power connection line 68 can be located on a side of the fourth electrode plate 74 close to the third electrode plate 73, and the orthographic projection of the first power connection line 68 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 on the substrate. The first power connection line 68 is configured to be connected to the subsequently formed first power line to form a high-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0317] In an exemplary embodiment, the second power connection line 69 can be located on a side of the third electrode plate 73 close to the fourth electrode plate 74, and the orthographic projection of the second power connection line 69 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 73 on the substrate. The second power connection line 69 is configured to be connected to a second power line formed subsequently to form a low-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0318] In an exemplary embodiment, the shape of the first light-emitting signal line 31 can be a straight line with the main portion extending along the first direction X. The first light-emitting signal line 31 is connected to the fifth gate electrode 25 of each circuit unit through the seventeenth via hole V17, thereby realizing that the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5. The first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0319] In an exemplary embodiment, the shape of the second light-emitting signal line 32 can be a broken line with the main portion extending along the first direction X. The second light-emitting signal line 32 is connected to the sixth gate electrode 26 of each circuit unit through the eighteenth via V18, thereby realizing that the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6. The second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0320] In an exemplary embodiment, the second scan signal line 62 may be shaped like a zigzag line extending along the first direction X. The orthographic projection of the second scan signal line 62 on the substrate at least partially overlaps with the orthographic projection of the second scan connection line 62-1 on the substrate, and the second scan signal line 62 is connected to the second scan connection line 62-1 via a twenty-third via hole V23. The second scan signal line 62 may serve as an upper layer signal line of a second scan signal line of a double-layer structure. The second scan connection line 62-1 located on the first conductive layer and the second scan signal line 62 located on the third conductive layer constitute the second scan signal line of the double-layer structure. This enables the second scan signal to be connected to the gate electrode of the ninth transistor T9, and the second scan signal line can control the conduction and disconnection of the ninth transistor T9.

[0321] In an exemplary embodiment, the shape of the third scan signal line 63 can be a straight line with a main portion extending along the first direction X. The third scan signal line 63 is connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, thereby realizing that the third scan signal line 63 is connected to the fourth gate electrode 24 of the fourth transistor T4. The third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0322] In an exemplary embodiment, the shape of the fourth scan signal line 64 can be a straight line with a main portion extending along the first direction X. The fourth scan signal line 64 is connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, thereby realizing that the fourth scan signal line 64 is connected to the first gate electrode 21 of the first transistor T1. The fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.

[0323] In an exemplary embodiment, the fifth scan signal line 65 may be shaped as a straight line extending along the first direction X. The orthographic projection of the fifth scan signal line 65 on the substrate at least partially overlaps with the orthographic projection of the fifth scan connection line 65-1 on the substrate. The fifth scan signal line 65 is connected to the second gate electrode 22 via the fifteenth via hole V15 and to the fifth scan connection line 65-1 via the twenty-fourth via hole V24. The fifth scan signal line 65 may serve as the upper layer signal line of a double-layer structure. The fifth scan connection line 65-1 located on the second conductive layer and the fifth scan signal line 65 located on the third conductive layer constitute the fifth scan signal line of the double-layer structure. This allows the fifth scan signal to be connected to the second gate electrode 22 of the second transistor T2. The second scan signal line can control the conduction and disconnection of the second transistor T2.

[0324] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 can be extended to the frame area and connected to the same gate driving circuit to output the same scan signal, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.

[0325] The present disclosure provides a double-layer structure for the second scanning signal line and the fifth scanning signal line, which can effectively reduce the resistance of the signal line and the voltage drop of the scanning signal, thereby improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0326] In an exemplary embodiment, the first power connection line 68 may be in the shape of a straight line with a main portion extending along the first direction X. The first power connection line 68 is connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via V13, thereby achieving the connection between the first power connection line 68 and the fourth electrode plate 74. Since the first power connection line 68 is connected to the first power line formed later, the first power connection line 68 can write the first power signal to the upper electrode plate of the second storage capacitor.

[0327] In the exemplary embodiment, a first power connection block 68-1 is provided on a side of the first power connection line 68 away from the second power connection line 69. A first end of the first power connection block 68-1 is connected to the first power connection line 68, and a second end of the first power connection block 68-1 extends in a direction away from the second power connection line 69. In the exemplary embodiment, the first power connection block 68-1 is configured to be connected to the fourth electrode plate 74 through the thirteenth via V13, and is also configured to be connected to the first power line formed later.

[0328] In an exemplary embodiment, in at least one circuit unit, a second power connection block 69-1 is provided on a side of the second power connection line 69 away from the first power connection line 68. A first end of the second power connection block 69-1 is connected to the second power connection line 69, and a second end of the second power connection block 69-1 extends in a direction away from the first power connection line 68. The second power connection block 69-1 is configured to be connected to a second power line formed later. In an exemplary embodiment, the second power connection block 69-1 can be provided between the first circuit unit and the second circuit unit.

[0329] In an exemplary embodiment, the shape of the first initial signal line 81 can be a straight line with a main portion extending along the first direction X. The first initial signal line 81 is connected to the first region of the first active layer in each circuit unit through the first via V1, thereby realizing that the first initial signal line 81 is connected to the first electrode of the first transistor T1. The first initial signal line 81 can write the first initial signal into the first electrode of the first transistor T1.

[0330] In an exemplary embodiment, the shape of the second initial signal line 82 can be a straight line with a main portion extending along the first direction X. The second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby realizing that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7. The second initial signal line 82 can write the second initial signal into the first electrode of the seventh transistor T7.

[0331] In an exemplary embodiment, the shape of the first reference signal line 91 can be a straight line with a main portion extending along the first direction X. The first reference signal line 91 is connected to the first region of the ninth active layer in each circuit unit through the ninth via V9, thereby realizing that the first reference signal line 91 is connected to the first electrode of the ninth transistor T9. The first reference signal line 91 can write the first reference signal into the first electrode of the ninth transistor T9.

[0332] In an exemplary embodiment, a reference connection block 91-1 is provided on a side of the first reference signal line 91 close to the second scanning signal line 62, a first end of the reference connection block 91-1 is connected to the first reference signal line 91, and a second end of the reference connection block 91-1 extends toward the direction of the second scanning signal line 62, and the reference connection block 91-1 is configured to be connected to a reference signal connection line formed subsequently.

[0333] In an exemplary embodiment, the shape of the second reference signal line 92 can be a straight line with a main portion extending along the first direction X. The second reference signal line 92 is connected to the first region of the eighth active layer of each circuit unit through the eighth via V8, thereby realizing that the second reference signal line 92 is connected to the first electrode of the eighth transistor T8. The second reference signal line 92 in the nth unit row can write the second reference signal to the first electrode of the eighth transistor T8 in the nth unit row.

[0334] In an exemplary embodiment, the first connection electrode 41 may be in the shape of a strip with a main portion extending along the second direction Y. The first connection electrode 41 may be located between the fourth scan signal line 64 and the second power connection line 69. A first end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via hole V2, and a second end of the first connection electrode 41 is connected to the first electrode plate 71 via a tenth via hole V10. In an exemplary embodiment, the first connection electrode 41 enables the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first storage capacitor (i.e., the first end of the first storage capacitor) to have the same potential. The first connection electrode 41 may serve as a first node N1 in the pixel driving circuit.

[0335] In an exemplary embodiment, the second connection electrode 42 may be shaped like a zigzag line with a main portion extending along the second direction Y. The second connection electrode 42 may be located between the third scan signal line 63 and the first power connection line 68. A first end of the second connection electrode 42 is connected to the second region of the fourth active layer (also the second region of the ninth active layer) via a fourth via hole V4. A second end of the second connection electrode 42 is connected to the first plate connection line 73-1 via a twelfth via hole V12. A third end between the first and second ends is connected to the second plate 72 via an eleventh via hole V11. In an exemplary embodiment, the second connection electrode 42 causes the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third plate 73 of the first storage capacitor (i.e., the second end of the first storage capacitor), and the second plate 72 of the second storage capacitor (i.e., the second end of the second storage capacitor) to have the same potential. The second connection electrode 42 may serve as the fifth node N5 of the pixel driving circuit.

[0336] In an exemplary embodiment, the third connection electrode 43 may be rectangular in shape and may be located between the third scan signal line 63 and the first power connection line 68. The third connection electrode 43 is connected to the first region of the fourth active layer through a third via hole V3. In an exemplary embodiment, the third connection electrode 43 may serve as a first electrode of the fourth transistor T4 and may be configured to be connected to a subsequently formed data signal line.

[0337] In an exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape and may be located between the first light emitting signal line 31 and the second light emitting signal line 32. The fourth connection electrode 44 is connected to the first region of the fifth active layer through a fifth via hole V5. In an exemplary embodiment, the fourth connection electrode 44 may serve as a first electrode of the fifth transistor T5 and may be configured to be connected to a first power supply line formed subsequently.

[0338] In an exemplary embodiment, the fifth connection electrode 45 may be L-shaped and may be located between the second light-emitting signal line 32 and the second reference signal line 92. The fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a sixth via hole V6. In an exemplary embodiment, the fifth connection electrode 45 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 and is configured to be connected to a subsequently formed anode connection electrode.

[0339] Unlike the previous embodiment, this embodiment arranges the first light-emitting signal line 31, the second light-emitting signal line 32, and the second reference signal line 92 in the third conductive layer. On the one hand, the second reference signal line 92 in the third conductive layer is arranged between the first scan signal line 61 and the second initial signal line 82, enabling the second reference signal line 92 to be routed close to the eighth transistor T8, simplifying the connection structure. On the other hand, the first reference signal line 91 is arranged on the side of the second scan signal line 62 away from the second storage capacitor, and the second scan signal line 62 is arranged on the side of the third scan signal line 63 away from the second storage capacitor. That is, the second scan signal line 62 is arranged above the third scan signal line 63, and the first reference signal line 91 is arranged above the second scan signal line 62, making the wiring layout more reasonable.

[0340] (26) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein a plurality of vias are provided in each circuit unit, as shown in FIG. 22 .

[0341] In an exemplary embodiment, the plurality of via holes of each circuit unit in the display substrate includes at least a thirty-first via hole V31 , a thirty-second via hole V32 , a thirty-third via hole V33 , a thirty-fourth via hole V34 , and a thirty-fifth via hole V35 .

[0342] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the third connecting electrode 43 on the substrate, the fifth insulating layer in the thirty-first via hole V31 is removed, exposing the surface of the third connecting electrode 43, and the thirty-first via hole V31 is configured to connect a subsequently formed data signal line to the third connecting electrode 43 through the via hole.

[0343] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the fifth insulating layer in the thirty-second via V32 is removed, exposing the surface of the fourth connecting electrode 44, and the thirty-second via V32 is configured to connect the subsequently formed first power line to the fourth connecting electrode 44 through the via.

[0344] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate, the fifth insulating layer in the thirty-third via V33 is removed, exposing the surface of the fifth connecting electrode 45, and the thirty-third via V33 is configured to connect the subsequently formed anode connecting electrode to the fifth connecting electrode 45 through the via.

[0345] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the reference connection block 91-1 of the first reference signal line 91 on the substrate, the fifth insulating layer in the thirty-fourth via V34 is removed, exposing the surface of the reference connection block 91-1, and the thirty-fourth via V34 is configured to connect the subsequently formed reference signal connection line to the reference connection block 91-1 through the via.

[0346] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first power connection block 68-1 of the first power connection line 68 on the substrate, the fifth insulating layer in the thirty-fifth via V35 is removed, exposing the surface of the first power connection block 68-1, and the thirty-fifth via V35 is configured to connect the subsequently formed first power line to the first power connection block 68-1 through the via.

[0347] In an exemplary embodiment, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 on the substrate is located within the orthographic projection of the second power connection block 69-1 of the second power connection line 69 on the substrate. The fifth insulating layer within the thirty-sixth via V36 is removed, exposing the surface of the second power connection block 69-1. The thirty-sixth via V36 is configured to connect a subsequently formed second power line to the second power connection block 69-1 through the via. In an exemplary embodiment, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0348] (27) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer, as shown in FIG. 23A and FIG. 23B , where FIG. 23B is a schematic diagram of the fourth conductive layer in FIG. 23A .

[0349] In an exemplary embodiment, each of the fourth conductive layer patterns of the plurality of circuit units in the display substrate may include a first power supply line 51 , a data signal line 53 , a reference signal connection line 54 , and an anode connection electrode 55 .

[0350] In an exemplary embodiment, the shape of the first power line 51, the data signal line 53 and the reference signal connection line 54 can be a strip shape with the main portion extending along the second direction Y, the first power line 51 can be located on one side of the data signal line 53 in the first direction X, and the reference signal connection line 54 can be located on one side of the first power line 51 in the first direction X, that is, the first power line 51 can be located between the data signal line 53 and the reference signal connection line 54.

[0351] In an exemplary embodiment, the first power line 51 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first power line 51 is connected to the fourth connection electrode 44 via the thirty-second via V32 and to the first power connection block 68-1 via the thirty-fifth via V35. Since the fourth connection electrode 44 is connected to the first region of the fifth active layer via the via, the first power line 51 writes the first power signal to the first electrode of the fifth transistor T5. Since the first power connection block 68-1 is connected to the first power connection line 68, the first power connection line 68, whose main portion extends along the first direction X, is interconnected with the first power line 51, whose main portion extends along the second direction Y. The first power lines 51 and 68 form a mesh structure on the display substrate that transmits the first power signal. This effectively reduces the resistance of the first power line 51 and the voltage drop of the first power signal, and also effectively improves the uniformity of the first power signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0352] In an exemplary embodiment, a power shielding block 51-1 is disposed on a side of the first power line 51 near the reference signal connection line 54. A first end of the power shielding block 51-1 is connected to the first power line 51, and a second end of the power shielding block 51-1 extends toward the reference signal connection line 54. The power shielding block 51-1 may be rectangular in shape, and the orthographic projection of the power shielding block 51-1 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 41 on the substrate. Because the first connection electrode 41 serves as the first node N1 in the pixel driving circuit, the constant voltage power shielding block 51-1 can effectively shield the first node N1 from the effects of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0353] In an exemplary embodiment, the orthographic projection of the power shielding block 51 - 1 on the substrate may include the orthographic projection of the first connection electrode 41 on the substrate.

[0354] In an exemplary embodiment, a first power connection block 51-2 is provided on one side of the first power line 51 close to the reference signal connection line 54, and a first end of the first power connection block 51-2 is connected to the first power line 51. After the second end of the first power connection block 51-2 extends toward the direction of the reference signal connection line 54, it is connected to the first power connection block 68-1 through the thirty-fifth via V35.

[0355] In an exemplary embodiment, a second power connection block 51-3 is provided on the side of the first power line 51 close to the data signal line 53, and the first end of the second power connection block 51-3 is connected to the first power line 51. The second end of the second power connection block 51-3 extends toward the direction of the data signal line 53 and is connected to the fourth connection electrode 44 through the thirty-second via V32.

[0356] In an exemplary embodiment, the first power line 51 , the power shielding block 51 - 1 , the first power connection block 51 - 2 , and the second power connection block 51 - 3 may be an integral structure connected to each other.

[0357] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 42 on the substrate. Because the second connection electrode 42 serves as the fifth node N5 in the pixel driving circuit, the constant voltage first power line 51 can effectively shield the fifth node N5 from the influence of other signals in the pixel driving circuit, preventing other signals from affecting the potential of the fifth node N5 of the pixel driving circuit, thereby improving the display effect.

[0358] In an exemplary embodiment, the first power lines 51 may be designed with unequal widths. The unequal width design of the first power lines 51 not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power lines and the data signal lines.

[0359] In an exemplary embodiment, the data signal line 53 may be in the shape of a straight line with a main portion extending along the second direction Y. The data signal line 53 is connected to the third connection electrode 43 through the thirty-first via hole V31. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via hole, the data signal line 53 writes the data signal to the first electrode of the fourth transistor T4.

[0360] In an exemplary embodiment, the reference signal connection line 54 may be shaped as a straight line with a main portion extending along the second direction Y. The reference signal connection line 54 is connected to the reference connection block 91-1 via a thirty-fourth via V34. Since the reference connection block 91-1 is connected to the first reference signal line 91, the first reference signal line 91, whose main portion extends along the first direction X, is interconnected with the reference signal connection line 54, whose main portion extends along the second direction Y. This allows the first reference signal line 91 and the reference signal connection line 54 to form a mesh structure on the display substrate for transmitting the first reference signal. This effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, and also effectively improves the uniformity of the first reference signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0361] In an exemplary embodiment, the anode connection electrode 55 may be rectangular in shape and is connected to the fifth connection electrode 45 via a thirty-third via hole V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via the via hole, the anode connection electrode 55 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the anode connection electrode 55 is configured to be connected to a subsequently formed anode, thereby enabling the pixel driving circuit to drive the light-emitting device.

[0362] In an exemplary embodiment, at least one circuit unit may further include a second power line 52. The second power line 52 may be shaped as a straight line with a main portion extending along the second direction Y. The second power line 52 is connected to the second power connection block 69-1 via the thirty-sixth via V36. The connection between the second power connection block 69-1 and the second power connection line 69 establishes a connection between the second power connection line 69, whose main portion extends along the first direction X, and the second power line 52, whose main portion extends along the second direction Y. This allows the second power lines 52 and 69 to form a mesh structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line 52 and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal across the display substrate, effectively enhancing display uniformity and improving display quality. In an exemplary embodiment, the second power line 52 may be located between the reference signal connection line 54 of the first circuit unit and the data signal line 53 of the second circuit unit.

[0363] In an exemplary embodiment, the first power connection line 68 of the third conductive layer can be set in each unit row, and the first power line 51 of the fourth conductive layer can be set in each unit column. Multiple first power lines 51 are respectively connected to multiple first power connection lines 68 to form a mesh structure for transmitting the first power signal.

[0364] In an exemplary embodiment, the first reference signal line 91 of the third conductive layer can be set in each unit row, and the reference signal connection line 54 of the fourth conductive layer can be set in each unit column. Multiple first reference signal lines 91 are respectively connected to multiple reference signal connection lines 54 to form a mesh structure for transmitting the first reference signal.

[0365] In an exemplary embodiment, the second power connection line 69 of the third conductive layer can be arranged in each unit row, and the second power line 52 of the fourth conductive layer can be arranged every two unit columns. Multiple second power lines 52 are respectively connected to multiple second power connection lines 69 to form a mesh structure for transmitting the second power signal.

[0366] The subsequent preparation process may include forming a first flat layer pattern, a plurality of anode vias are provided on the first flat layer, the orthographic projection of the anode vias on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, the first flat layer in the anode via is removed to expose the surface of the anode connecting electrode, and the anode via is configured to connect the subsequently formed anode to the anode connecting electrode through the via.

[0367] At this point, the driving circuit layer of this embodiment is prepared on the substrate. In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer and an encapsulation structure layer can be sequentially prepared on the driving circuit layer, which will not be described in detail here.

[0368] In an exemplary embodiment, within a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a fifth scanning signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a second initial signal line, a first reference signal line, a second reference signal line, a first power supply line, and a data signal line connected to the pixel driving circuit. Within a plane perpendicular to the display substrate, the driving circuit layer may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer stacked sequentially on a base.

[0369] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0370] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The first insulating layer is called a buffer layer, the second insulating layer and the third insulating layer are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The first flat layer can be made of an organic material, such as a resin. The active layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.

[0371] In a display substrate, semiconductor layers in adjacent circuit units in a unit row are interconnected. For example, the first regions of the ninth active layer of multiple circuit units in a unit row are interconnected via a first active connection line, and the first regions of the seventh active layer of multiple circuit units in a unit row are interconnected via a second active connection line. The first active connection line and the second active connection line can be in the shape of lines extending along a first direction X. Studies have shown that the first active connection line and the second active connection line can affect the aperture (AA hole) structure of the display area, resulting in hole mura around the aperture, resulting in poor display. In addition, the display substrate also has the problem of large voltage drops of the first power signal, the second power signal, and the reference signal.

[0372] In the embodiment of the present disclosure, the semiconductor layer of a circuit unit is divided into a first active pattern and a second active pattern. The active layer of the transistor in the first active pattern is not connected to the active layer of the transistor in the second active pattern, and the semiconductor layers in adjacent circuit units in the unit rows and unit columns are isolated from each other, thereby eliminating the active connecting line structure. This prevents the semiconductor layer from affecting the open hole structure of the display area, minimizes the display defects caused by hole moiré, and improves the display quality.

[0373] In the embodiment of the present disclosure, a first power connection line extending along a first direction X and a first power line extending along a second direction Y are provided in the main portion, and the first power lines are connected to each other, so that the first power lines and the first power connection lines form a mesh structure on the display substrate for transmitting a first power signal. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves display uniformity, and improves display quality and display quality.

[0374] In the embodiment of the present disclosure, a second power connection line extending along a first direction X and a second power line extending along a second direction Y are provided in the main portion, and the second power lines are interconnected, so that the second power lines and the second power connection lines form a mesh structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power signal line and reduces the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improves display uniformity, and improves display quality.

[0375] In the embodiment of the present disclosure, a first reference signal line extending in a first direction X and a reference signal connection line extending in a second direction Y are provided in a main portion, and the first reference signal line and the reference signal connection line are connected to each other, so that the first reference signal line and the reference signal connection line form a mesh structure on the display substrate for transmitting the first reference signal. This not only effectively reduces the resistance of the first reference signal line and reduces the voltage drop of the first reference signal, but also effectively improves the uniformity of the first reference signal in the display substrate, effectively improves display uniformity, and improves display quality.

[0376] In the embodiment of the present disclosure, by providing a first shielding electrode, a second shielding electrode, a third shielding electrode, and a fourth shielding electrode, the influence of the data voltage jump on the first transistor T1, the second transistor T2, the fourth transistor T4, the ninth transistor T9, and the fifth node N5 can be shielded, thereby preventing the data voltage jump from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0377] The embodiment of the present disclosure forms an additional capacitor of the second storage capacitor by providing the second shielding electrode and the semiconductor layer, which can effectively increase the total capacity of the second storage capacitor, improve the working performance of the pixel driving circuit, and enhance the display effect.

[0378] The embodiment of the present disclosure can effectively reduce the resistance of the signal lines and the voltage drop of the scanning signals by setting up the second scanning signal lines and the fifth scanning signal lines with a double-layer structure, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0379] The embodiment of the present disclosure shields the first node N1 and the fifth node N5 by providing a first power line and a power shielding block, thereby effectively preventing other signals from affecting the potentials of the first node N1 and the fifth node N5 of the pixel driving circuit, thereby improving the display effect.

[0380] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0381] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs. For example, the second scan signal line and the fifth scan signal line in the display substrate shown in Figure 5 can adopt a double-layer structure. For another example, one or more of the first scan signal line, the third scan signal line, and the fourth scan signal line in the display substrate can adopt a double-layer structure. For another example, the reference signal connection line in the fourth conductive layer can be connected to the second reference signal line, so that the second reference signal line and the reference signal connection line form a mesh structure on the display substrate that transmits the second reference signal. For another example, the second power line in the fourth conductive layer can be modified into an initial connection line, and the initial connection line can be connected to the first initial signal line or the second initial signal line, so that the first initial signal line and the initial connection line form a mesh structure on the display substrate that transmits the first initial signal, or the second initial signal line and the initial connection line form a mesh structure on the display substrate that transmits the second initial signal. The present disclosure does not limit this.

[0382] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0383] The present disclosure also provides a method for preparing a display substrate, so as to prepare the display substrate provided in the above embodiment.

[0384] In an exemplary embodiment, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, and the pixel driving circuit includes at least a plurality of transistors. The method for preparing the display substrate may include:

[0385] A semiconductor layer and a plurality of conductive layers are formed on a substrate and are arranged on a side of the semiconductor layer away from the substrate; the semiconductor layer includes at least active layers of a plurality of transistors, and the semiconductor layer includes at least a first active pattern and a second active pattern, the first active pattern includes the active layer of at least one transistor, and the second active pattern includes the active layer of at least one transistor; in at least one circuit unit, the first active pattern and the second active pattern are arranged alternately, the active layers of the plurality of transistors in the circuit unit are arranged alternately with the active layers of the plurality of transistors in the circuit unit adjacent in the unit row direction, and the active layers of the plurality of transistors in the circuit unit are arranged alternately with the active layers of the plurality of transistors in the circuit unit adjacent in the unit column direction.

[0386] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0387] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; on a plane perpendicular to the display substrate, at least one circuit unit comprising a semiconductor layer arranged on a substrate and a plurality of conductive layers arranged on a side of the semiconductor layer away from the substrate, the semiconductor layer comprising at least active layers of a plurality of transistors, the semiconductor layer comprising at least a first active pattern and a second active pattern, the first active pattern comprising an active layer of at least one transistor, the second active pattern comprising an active layer of at least one transistor; in at least one circuit unit, the first active pattern and the second active pattern are arranged alternately, the active layers of the plurality of transistors in the circuit unit are arranged alternately with the active layers of the plurality of transistors in the circuit unit adjacent to the unit row direction, and the active layers of the plurality of transistors in the circuit unit are arranged alternately with the active layers of the plurality of transistors in the circuit unit adjacent to the unit column direction.

2. The display substrate according to claim 1, wherein: The first active pattern includes active layers of two transistors, and the active layers of the two transistors are interconnected as an integrated structure; the second active pattern includes active layers of seven transistors, and the active layers of the seven transistors are interconnected as an integrated structure.

3. The display substrate according to claim 2, wherein: The pixel driving circuit includes a first transistor and a seventh transistor as initialization transistors, a second transistor as a compensation transistor, a third transistor as a driving transistor, a fourth transistor as a data writing transistor, a fifth transistor and a sixth transistor as light emitting transistors, and an eighth transistor and a ninth transistor as reference transistors, the first active pattern includes an active layer of the fourth transistor and an active layer of the ninth transistor, and the second active pattern includes active layers of the first to third transistors and active layers of the fifth to eighth transistors.

4. The display substrate according to claim 3, wherein: The pixel driving circuit further includes a first storage capacitor and a second storage capacitor; the first storage capacitor includes at least a first electrode plate and a third electrode plate, and the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate; The second storage capacitor includes at least a second electrode plate and a fourth electrode plate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate; the first electrode plate serves as the gate electrode of the third transistor, the second electrode plate is connected to the third electrode plate, and the fourth electrode plate is connected to the first power line.

5. The display substrate according to claim 4, wherein: The multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are arranged in sequence along a direction away from the substrate; the first electrode plate and the second electrode plate are arranged in the first conductive layer, the third electrode plate and the fourth electrode plate are arranged in the second conductive layer, the first power line is arranged in the fourth conductive layer, and the second electrode plate is connected to the third electrode plate via a connecting electrode arranged in the third conductive layer.

6. The display substrate according to claim 5, wherein: The third electrode plate is provided with a first electrode plate connecting line extending toward the fourth electrode plate, the fourth electrode plate is provided with a first groove recessed away from the third electrode plate, the first electrode plate connecting line is arranged in the first groove, and the end of the first electrode plate connecting line away from the third electrode plate is connected to the connecting electrode through a via.

7. The display substrate according to claim 5, wherein: The pixel driving circuit also includes an additional capacitor, a lower plate of the additional capacitor is arranged in the semiconductor layer, an upper plate of the additional capacitor is arranged in the second conductive layer, an orthographic projection of the upper plate on the substrate at least partially overlaps with an orthographic projection of the lower plate on the substrate, the lower plate is connected to the second plate, and the upper plate is connected to the fourth plate.

8. The display substrate according to claim 7, wherein: The lower electrode plate includes the second area of ​​the active layer of the fourth transistor, the second electrode plate is connected to the second area of ​​the active layer of the fourth transistor via a connecting electrode arranged in the third conductive layer, and the upper electrode plate and the fourth electrode plate are an integral structure connected to each other.

9. The display substrate according to claim 3, wherein: The gate electrode of the first transistor is connected to the fourth scan signal line, the gate electrode of the second transistor is connected to the fifth scan signal line, the gate electrode of the fourth transistor is connected to the third scan signal line, the gate electrode of the fifth transistor and the gate electrode of the sixth transistor are connected to the light-emitting signal line, the gate electrode of the seventh transistor and the gate electrode of the eighth transistor are connected to the first scan signal line, the gate electrode of the ninth transistor is connected to the second scan signal line, and the second scan signal line and the fifth scan signal line output the same scan signal.

10. The display substrate according to claim 9, wherein: The display substrate also includes a second scan connection line, the second scan signal line and the second scan connection line are arranged in different conductive layers, the orthographic projection of the second scan signal line on the substrate at least partially overlaps with the orthographic projection of the second scan connection line on the substrate, and the second scan signal line is connected to the second scan connection line through a via hole to form a double-layer structure of the scan signal line.

11. The display substrate according to claim 10, wherein: The multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate; the second scan connection line is arranged in the first conductive layer, and the second scan signal line is arranged in the third conductive layer.

12. The display substrate according to claim 9, wherein: The display substrate also includes a fifth scan connection line, the fifth scan signal line and the fifth scan connection line are arranged in different conductive layers, the orthographic projection of the fifth scan signal line on the substrate at least partially overlaps with the orthographic projection of the fifth scan connection line on the substrate, and the fifth scan signal line is connected to the fifth scan connection line through a via hole to form a double-layer structure of the scan signal line.

13. The display substrate according to claim 12, wherein: The multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate; the fifth scan connection line is arranged in the second conductive layer, and the fifth scan signal line is arranged in the third conductive layer.

14. The display substrate according to claim 3, wherein: At least one circuit unit also includes a first shielding electrode, wherein the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor on the substrate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor on the substrate.

15. The display substrate according to claim 3, wherein: At least one circuit unit further includes a second shielding electrode, an orthographic projection of the second shielding electrode on the substrate at least partially overlapping with an orthographic projection of the second electrode of the fourth transistor and the second electrode of the ninth transistor on the substrate.

16. The display substrate according to claim 3, wherein: At least one circuit unit further includes a third shielding electrode, an orthographic projection of the third shielding electrode on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor on the substrate.

17. The display substrate according to claim 3, wherein: At least one circuit unit further includes a fourth shielding electrode, an orthographic projection of the fourth shielding electrode on the substrate at least partially overlapping an orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor on the substrate.

18. The display substrate according to any one of claims 1 to 17, wherein: The display substrate also includes at least one first power connection line extending along the unit row direction and at least one first power line extending along the unit column direction; the first power line and the first power connection line are arranged in different conductive layers, and the first power line and the first power connection line are connected through vias to form a mesh structure for transmitting the first power signal.

19. The display substrate according to any one of claims 1 to 17, wherein: The display substrate also includes at least one second power connection line extending along the unit row direction and at least one second power line extending along the unit column direction; the second power line and the second power connection line are arranged in different conductive layers, and the second power line and the second power connection line are connected through vias to form a mesh structure for transmitting the second power signal.

20. The display substrate according to any one of claims 1 to 17, wherein: The display substrate also includes at least one reference signal connection line extending along the unit row direction and at least one reference signal line extending along the unit column direction; the reference signal line and the reference signal connection line are arranged in different conductive layers, and the reference signal connection line is connected to the reference signal line through a via to form a mesh structure for transmitting the reference signal.

21. A display device, wherein: Comprising the display substrate according to any one of claims 1 to 20.

22. A method for preparing a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; the method comprising: Forming a semiconductor layer and a plurality of conductive layers on a substrate and arranged on a side of the semiconductor layer away from the substrate; The semiconductor layer includes at least active layers of a plurality of transistors, the semiconductor layer includes at least a first active pattern and a second active pattern, the first active pattern includes an active layer of at least one transistor, and the second active pattern includes an active layer of at least one transistor; In at least one circuit unit, the first active pattern is spaced apart from the second active pattern, the active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in the circuit unit adjacent in the unit row direction, and the active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in the circuit unit adjacent in the unit column direction.

Images