Method for manufacturing semiconductor device and semiconductor device

Abstract

This method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a multilayer wiring in which wiring layers and insulating layers are alternately laminated, in which the wiring layers adjacent to each other with the insulating layers interposed therebetween in the lamination direction are electrically connected via a conductor present in a through-hole provided in the insulating layers, the multilayer wiring is formed by: a step for providing the insulating layer on a substrate, the insulating layer having a metal protective film on the surface thereof and containing an inorganic filler having an average maximum particle length (B) of 1-100 [mu] m; a step of forming a through hole in the insulating layer; and a step of performing a dry slag removal process on the insulating layer in which the through hole is formed.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0002] To achieve high density and high performance in semiconductor packaging, a mounting method is proposed that integrates chips with different performance characteristics within a single package. In this case, cost-effective high-density interconnect technology between chips becomes important (see, for example, Patent Document 1).

[0003] Non-patent documents 1 and 2 describe a package-on-package (PoP) method that connects different packages by using flip-chip mounting on the package. This PoP method is widely used in smartphones, tablets, and the like.

[0004] Other methods for mounting multiple chips at high density include packaging technologies using organic substrates with high-density wiring, fan-out-wafer level packaging (FO-WLP) with through-mold vias (TMV), packaging technologies using silicon or glass interposers, packaging technologies using through-silicon vias (TSV), and packaging technologies using chips embedded in a substrate for inter-chip transfer.

[0005] In particular, when semiconductor chips are mounted on each other in a semiconductor wiring layer and FO-WLP, a fine wiring layer is required to enable the semiconductor chips to conduct to each other at a high density (see, for example, Patent Document 2).

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Publication No. 2012-529770

[0009] Patent Document 2: U.S. Patent Application Publication No. 2011 / 0221071

[0010] Non-patent literature

[0011] Non-patent document 1: Jinseong Kim et al., "Application of Through Mold Via (TMV) as PoP Base Package", Electronic Components and Technology Conference (ECTC), p.1089-1092 (2008)

[0012] Non-patent literature 2: SWYoon et al., “Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology”, ECTC, p. 1250-1254 (2012) Summary of the Invention

[0013] The technical problem that the invention aims to solve

[0014] Wiring layers (semiconductor wiring layers) are sometimes used in multilayer substrates, wafer-level packaging (WLP), fan-out PoP bottom packaging, etc., to mount multiple semiconductor chips.

[0015] The wiring layer is constructed as a multilayer wiring system consisting of alternating wiring layers and insulation layers. To reduce costs and suppress the increase in wiring resistance, copper, which has high conductivity, is sometimes used as the metal constituting the wiring layer. Furthermore, as a component constituting the insulation layer, a cured epoxy resin composition with an excellent balance of electrical properties, moisture resistance, heat resistance, and mechanical properties is sometimes used. To improve the strength of the cured product and adjust its thermal expansion characteristics, inorganic fillers are included in the epoxy resin composition. A higher content of inorganic fillers generally leads to easier improvement in the strength of the cured product and better suppression of thermal expansion; therefore, a high content of inorganic fillers in the epoxy resin composition is sometimes desirable. However, on the other hand, a higher content of inorganic fillers tends to increase the likelihood of the presence of large-particle-size inorganic filler particles.

[0016] To ensure conductivity between wiring layers, through-holes (vias) are sometimes formed in the insulating layer composed of a cured epoxy resin composition containing inorganic fillers. Methods for forming through-holes include laser processing. Sometimes, the inorganic filler material contained in the epoxy resin composition is exposed on the sidewalls of the through-hole. Due to the exposed inorganic filler material, unevenness is created on the sidewalls of the through-hole. This unevenness on the sidewalls of the through-hole can sometimes lead to a deterioration of the through-hole shape. This deterioration tends to worsen as the likelihood of the presence of large-diameter inorganic filler particles increases.

[0017] This disclosure is made in view of the aforementioned existing facts, and its object is to provide a method for manufacturing a semiconductor device capable of suppressing unevenness on the sides of through-holes. Furthermore, this disclosure aims to provide a semiconductor device with highly reliable multilayer wiring.

[0018] Means for solving technical problems

[0019] The specific means to achieve the above objectives are as follows.

[0020] <1> A method for manufacturing a semiconductor device, comprising a method for manufacturing a semiconductor device with multilayer wiring formed by alternating layers of wiring layers and insulating layers, wherein...

[0021] Electrical connections are made between adjacent wiring layers separated by the aforementioned insulating layers in the stacking direction through conductors present in through holes provided in the aforementioned insulating layers.

[0022] The above multilayer wiring is formed through the following steps:

[0023] The step of setting the above-mentioned insulating layer on the substrate, which has a metal protective film on its surface and contains an inorganic filler material with an average maximum particle length B of 1 μm to 100 μm;

[0024] The step of forming a through hole in the above-mentioned insulating layer; and

[0025] The step of performing dry slag removal treatment on the insulating layer that has formed the above-mentioned through holes.

[0026] <2> according to <1> The method for manufacturing the semiconductor device, wherein the above-mentioned dry descaling process is performed until the average height C of the protrusions from which the inorganic filler material originates in the side of the through hole and the average maximum particle length B of the inorganic filler material satisfy the following relationship (I).

[0027] B > 2C(I).

[0028] <3> according to <1> or <2> The method for manufacturing the semiconductor device, wherein when the average diameter of the through hole is set to A, the following relationship (II) is satisfied.

[0029] A > 3B(II).

[0030] <4> according to <1> ~ <3> The method for manufacturing a semiconductor device according to any one of the following, wherein the through-hole is formed using at least one of laser processing and photolithography.

[0031] <5> according to <4> In the method for manufacturing the semiconductor device, the through hole is formed as follows:

[0032] The region corresponding to the location where the through hole is to be set in the metal protective film is removed using the above photolithography method, and then the laser processing is performed on the location where the metal protective film has been removed.

[0033] <6> according to <4> The method for manufacturing the semiconductor device, wherein the through hole is formed by laser processing while the metal protective film is present on the surface of the insulating layer.

[0034] <7> according to <1> ~ <6> The method for manufacturing a semiconductor device according to any one of the following methods, wherein the insulating layer having the aforementioned metal protective film on its surface is deposited on the aforementioned substrate through the following steps:

[0035] The step of setting the above-mentioned insulating layer on the above-mentioned substrate;

[0036] The step of roughening the surface of the above-mentioned insulating layer; and

[0037] The step of depositing the metal protective film on the surface of the roughened insulating layer.

[0038] <8> according to <7> The method for manufacturing the semiconductor device wherein the surface of the insulating layer is roughened by at least one of grinding, chemical treatment and plasma etching.

[0039] <9> according to <7> or <8> The method for manufacturing the semiconductor device, wherein the metal protective film is formed by at least one of metal evaporation, electroless plating, and electrolytic plating.

[0040] <10> according to <7> ~ <9> The method for manufacturing a semiconductor device according to any one of the following methods, wherein the surface roughness Ra of the roughened insulating layer is 0.1 μm to 2.0 μm.

[0041] <11> according to <1> ~ <10> The method for manufacturing a semiconductor device according to any one of the following methods, wherein the insulating layer is a cured product of an epoxy resin composition.

[0042] <12> according to <1> ~ <6> According to any one of the methods for manufacturing a semiconductor device, the insulating layer having the aforementioned metal protective film on its surface is disposed on the substrate by contacting the epoxy resin composition layer in an adhesive film with a metal foil having an epoxy resin composition layer and a metal foil in sequence with the substrate, and then curing the epoxy resin composition layer.

[0043] <13> according to <1> ~ <12> The method for manufacturing a semiconductor device according to any one of the following methods further includes the step of forming a wiring layer on the insulating layer after the dry deslagging treatment.

[0044] <14> according to <13> In the method for manufacturing the semiconductor device, the wiring layer is formed by removing the metal protective film from the surface of the insulating layer.

[0045] <15> according to <13> The method for manufacturing the semiconductor device, wherein the wiring layer is formed on the metal protective film.

[0046] <16> according to <1> ~ <15> The method for manufacturing a semiconductor device according to any one of the above-mentioned dry slag removal processes, wherein at least one of wet slag removal and plasma ashing processes is further performed before the aforementioned dry slag removal process.

[0047] <17> A semiconductor device having:

[0048] Semiconductor components; and

[0049] Multilayer wiring is formed by alternating layers of wiring layers and insulating layers that are electrically connected to the aforementioned semiconductor elements;

[0050] in,

[0051] Electrical connections are made between adjacent wiring layers separated by the aforementioned insulating layers in the stacking direction through conductors present in through-holes provided in the aforementioned insulating layers.

[0052] The aforementioned insulating layer contains inorganic filler material with an average maximum particle length B of 1 μm to 100 μm.

[0053] When the average height of the protrusion from which the inorganic filling material originates on the side of the through hole is set as C, and the average diameter of the through hole is set as A, the following relationships (I) and (II) are satisfied.

[0054] B>2C(I)

[0055] A > 3B(II).

[0056] Invention Effects

[0057] According to this disclosure, a method for manufacturing a semiconductor device capable of suppressing unevenness on the sides of through-holes can be provided. Furthermore, according to this disclosure, a semiconductor device with highly reliable multilayer wiring can be provided. Attached Figure Description

[0058] Figure 1 This is a cross-sectional view showing the state in which an insulating layer 14 containing an inorganic filler material 12 with an average maximum particle length B of 1 μm to 100 μm is disposed on a semiconductor substrate 10.

[0059] Figure 2 This is a cross-sectional view showing the roughened state of the surface of the insulating layer 14.

[0060] Figure 3 This is a cross-sectional view showing the state in which a metal protective film 16 is provided on the surface of the roughened insulating layer 14.

[0061] Figure 4 This diagram shows the state after the area Q, corresponding to the location where the through hole is to be set, in the metal protective film 16 provided on the surface of the insulating layer 14 has been partially removed.

[0062] Figure 5 A cross-sectional view showing the state in which a through hole 18 is provided in the surface of the insulating layer 14.

[0063] Figure 6 This is a cross-sectional view showing the state of the insulating layer 14 after dry deslagging treatment was performed on the through hole 18. Detailed Implementation

[0064] The embodiments of this disclosure will be described in detail below. However, this disclosure is not limited to the following embodiments. In the following embodiments, the constituent elements (including element steps, etc.) are not essential unless specifically stated otherwise. Similarly, numerical values ​​and their ranges are not limiting to this disclosure.

[0065] In this disclosure, the numerical range represented by “~” includes the minimum and maximum values ​​recorded before and after “~”, respectively.

[0066] In this disclosure, within the numerical ranges described in stages, the upper or lower limit value recorded in one numerical range can be replaced with the upper or lower limit value of other numerical ranges described in stages. Furthermore, within the numerical ranges described in this disclosure, the upper or lower limit value can be replaced with the values ​​shown in the embodiments.

[0067] In this disclosure, each component may also contain multiple substances equivalent to it. When multiple substances equivalent to each component are present in the composition, the content or percentage of each component, unless otherwise specified, refers to the total content or percentage of the multiple substances present in the composition.

[0068] In this disclosure, the particles corresponding to each component may also include multiple particles. When multiple particles corresponding to each component are present in the composition, the particle size of each component, unless otherwise specified, refers to the value of the mixture of the multiple particles present in the composition.

[0069] In this disclosure, the terms "layer" or "film" refer to the presence of a layer or film in a region, including not only the layer or film that forms over the entire region, but also the layer or film that forms only over a portion of the region.

[0070] In this disclosure, the term "layering" refers to overlapping layers. Two or more layers can be combined together, or they can be detachable.

[0071] In this disclosure, the average thickness of a layer or film refers to the value obtained by measuring the thickness of five points of the layer or film to be targeted as their arithmetic mean.

[0072] The thickness of a layer or film can be measured using a micrometer or similar tool. In this disclosure, a micrometer is used when the thickness of a layer or film can be measured directly. On the other hand, when measuring the thickness of a single layer or the total thickness of multiple layers, an electron microscope can be used to observe the cross-section of the object being measured.

[0073] <Methods for Manufacturing Semiconductor Devices>

[0074] The semiconductor device manufacturing method disclosed herein relates to a method for manufacturing a semiconductor device having a multilayer wiring having alternating layers of wiring layers and insulating layers, wherein adjacent wiring layers separated by insulating layers are electrically connected in the stacking direction by conductors existing in through-holes provided in the insulating layers. In the semiconductor device manufacturing method of this disclosure, the multilayer wiring is formed by the following steps: forming an insulating layer on a substrate having a metal protective film on its surface and containing an inorganic filler material with an average maximum particle length B of 1 μm to 100 μm; forming through-holes in the insulating layer; and performing a dry deslagging treatment on the insulating layer with the through-holes formed.

[0075] According to the semiconductor device manufacturing method disclosed herein, unevenness on the side surface of a through-hole can be suppressed. The reason for this is unclear, but is speculated as follows.

[0076] When through-holes are created in the insulation layer using methods such as laser processing, inorganic filler material sometimes protrudes to the sides of the through-holes. In particular, when through-holes are created in the insulation layer using laser processing, although the resin components constituting the insulation layer are removed by laser irradiation, the inorganic filler material is difficult to remove and tends to protrude to the sides of the through-holes. Dry deslagging is an effective method to remove the inorganic filler material protruding to the sides of the through-holes. However, because dry deslagging removes not only the inorganic filler material but also the resin components constituting the insulation layer, the surface of the insulation layer can sometimes become rough and its insulation properties can deteriorate.

[0077] In this disclosure, the insulating layer is subjected to dry deslagging treatment while it has a metallic protective film on its surface. Since the metallic protective film is resistant to erosion caused by the dry deslagging treatment, it functions as a protective film for the insulating layer against the dry deslagging treatment. Therefore, inorganic filler material exposed to the side of the through-hole can be removed while suppressing surface roughness of the insulating layer. As a result, it is presumably possible to suppress unevenness on the side of the through-hole.

[0078] In this disclosure, the maximum particle length B of the inorganic filler material contained in the insulating layer is 1 μm to 100 μm. While a maximum particle length B of 1 μm to 100 μm in the insulating layer tends to improve the strength of the insulating layer and suppress thermal expansion, it also tends to increase the unevenness of the inorganic filler material on the sides of the through-hole and worsen the shape of the through-hole. The semiconductor device manufacturing method of this disclosure is also effective when forming through-holes in an insulating layer containing large-particle-size inorganic filler material.

[0079] The method for manufacturing the semiconductor device disclosed herein will now be described in detail.

[0080] Furthermore, in the following manufacturing method, the case where an insulating layer with a metal protective film on its surface is disposed on a substrate through the following steps is described: a step of disposing the insulating layer on the substrate; a step of roughening the surface of the insulating layer; and a step of depositing a metal protective film on the surface of the roughened insulating layer. However, the method of disposing the insulating layer with a metal protective film on the substrate is not limited to the above method. Additionally, in the following manufacturing method, the case where a through hole is formed is described as follows: the area corresponding to the location where the through hole is to be disposed in the metal protective film is removed using photolithography, and then the area where the metal protective film has been removed is laser-processed. However, the method of forming the through hole is not limited to the above method. Furthermore, the sizes of the components in each figure are schematic, and the relative sizes between components are not limited thereto. Also, components with substantially the same function are marked with the same symbol in all figures, and repeated descriptions are sometimes omitted.

[0081] Figure 1This is a cross-sectional view showing an insulating layer 14 containing an inorganic filler material 12 with an average maximum particle length B of 1 μm to 100 μm disposed on a semiconductor substrate 10, which is an example of a substrate. The insulating layer 14 is, for example, a cured epoxy resin composition. In addition to semiconductor substrates such as silicon substrates, other substrates include FO-WLP, WLCSP (Wafer Level Chip Scale Package), FI-WLP (Fan In Wafer Level Package), glass substrates, FR-4 substrates and other glass epoxy substrates, polyester substrates, polyimide substrates, BT resin substrates, polyphenylene ether substrates, etc.

[0082] From the viewpoint of ensuring insulation, the average thickness of the insulating layer 14 is preferably 5 μm or more, more preferably 10 μm or more, and even more preferably 20 μm or more. From the viewpoint of miniaturizing the semiconductor device, the average thickness of the insulating layer 14 is preferably 200 μm or less, more preferably 100 μm or less, and even more preferably 50 μm or less. The average thickness of the insulating layer 14 is preferably 5 μm to 200 μm, more preferably 10 μm to 100 μm, and even more preferably 20 μm to 50 μm.

[0083] The composition of the epoxy resin composition constituting the insulating layer 14 is not particularly limited, but it is preferably an epoxy resin composition that is solid at 25°C.

[0084] Epoxy resin compositions may contain, for example, epoxy resin, curing agent, and inorganic filler, and may also contain other components as needed.

[0085] The epoxy resin composition disclosed herein contains epoxy resin.

[0086] There are no particular restrictions on the types of epoxy resins as long as each molecule has two or more epoxy groups.

[0087] Specifically, examples include: phenolic varnish resins are obtained by polycondensation or co-polymerization of at least one phenolic compound selected from phenol, cresol, xylenol, resorcinol, catechol, bisphenol A, bisphenol F, and naphthol compounds such as α-naphthol, β-naphthol, and dihydroxynaphthol with aliphatic aldehyde compounds such as formaldehyde, acetaldehyde, and propionaldehyde under an acidic catalyst; phenolic varnish resins are then epoxidized to obtain phenolic varnish-type epoxy resins (phenolic varnish-type epoxy resins, o-cresol varnish-type epoxy resins, etc.); phenolic compounds are also obtained by polycondensation or co-polymerization of the above-mentioned phenolic compounds with aromatic aldehyde compounds such as benzaldehyde and salicylaldehyde under an acidic catalyst to obtain triphenylmethane-type phenolic resins; and triphenylmethane-type phenolic resins are then epoxidized. The obtained triphenylmethane-type epoxy resin; a copolymerized epoxy resin obtained by copolymerizing the above-mentioned phenolic compounds and naphthol compounds with aldehyde compounds under an acidic catalyst to obtain phenolic varnish resin, and then epoxidizing the obtained phenolic varnish resin; a diphenylmethane-type epoxy resin as a diglycidyl ether of bisphenol A, bisphenol F, etc.; a biphenyl-type epoxy resin as a diglycidyl ether of alkyl-substituted or unsubstituted bisphenols; a stilbene-type epoxy resin as a diglycidyl ether of stilbene-based phenolic compounds; a sulfur-containing atom-type epoxy resin as a diglycidyl ether of bisphenol S, etc.; an epoxy resin as a glycidyl ether of alcohols such as butanediol, polyethylene glycol, and polypropylene glycol; and an epoxy resin as a diglycidyl ether of phthalic acid, isophthalic acid, tetrahydrophthalic acid, etc. Glycidyl ester type epoxy resins of polycarboxylic acid compounds such as formic acid; glycidylamine type epoxy resins in which active hydrogen atoms bonded to nitrogen atoms of aniline, diaminodiphenylmethane, isocyanuric acid, etc., are replaced by glycidyl groups; dicyclopentadiene type epoxy resins in which a co-condensation resin of dicyclopentadiene and phenol compounds is epoxidized; alicyclic epoxy resins such as vinylcyclohexene diepoxide, 3,4-epoxycyclohexylmethyl-3,4-epoxycyclohexane carboxylate, and 2-(3,4-epoxy)cyclohexyl-5,5-spiro(3,4-epoxy)cyclohexane-m-dioxane are epoxidized by olefin bond epoxidation within the molecule; and p-xylene as a glycidyl ether of p-xylene-modified phenolic resin. Modified epoxy resins; glycidyl ether-based epoxy resins of m-xylene modified phenolic resins; terpene-modified epoxy resins of terpene-modified phenolic resins of glycidyl ethers; dicyclopentadiene-modified epoxy resins of dicyclopentadiene-modified phenolic resins of glycidyl ethers; cyclopentadiene-modified epoxy resins of cyclopentadiene-modified phenolic resins of glycidyl ethers; polycyclic aromatic ring-modified epoxy resins of glycidyl ethers of polycyclic aromatic ring-modified phenolic resins; naphthalene-type epoxy resins of glycidyl ethers of naphthalene-containing phenolic resins; halogenated phenolic varnish-type epoxy resins; hydroquinone-type epoxy resins; trimethylolpropane-type epoxy resins; linear aliphatic epoxy resins obtained by oxidizing olefin bonds using peracids such as peracetic acid.Aryl alkyl type epoxy resins are produced by epoxidizing aryl alkyl phenolic resins such as phenolic aryl alkyl resins and naphthol aryl alkyl resins. Furthermore, epoxy resins can also include epoxides of organosilicon resins and aminophenol-type epoxy resins made from glycidyl ethers of aminophenol. These epoxy resins can be used alone or in combination of two or more.

[0088] The epoxy resin composition disclosed herein contains a curing agent.

[0089] There are no particular restrictions on the type of curing agent, as long as it is a compound that undergoes a curing reaction with the epoxy resin used in combination. Examples of curing agents that can be used in combination with epoxy resin include phenolic curing agents, amine curing agents, acid anhydride curing agents, polythiol curing agents, polyaminoamide curing agents, isocyanate curing agents, and block isocyanate curing agents. A single curing agent can be used, or two or more can be used in combination. The curing agent can be solid or liquid at room temperature and pressure (e.g., 25°C, atmospheric pressure), but solid is preferred.

[0090] From the perspective of heat resistance, phenolic curing agents or amine curing agents are preferred.

[0091] Examples of phenolic curing agents include phenolic resins and polyphenolic compounds having two or more phenolic hydroxyl groups per molecule. Specifically, examples include: resorcinol, catechol, bisphenol A, bisphenol F, substituted or unsubstituted bisphenols, and other polyphenolic compounds; phenolic varnish-type phenolic resins obtained by polycondensation or co-polycondensation of at least one phenolic compound selected from phenol, cresol, xylenol, resorcinol, catechol, bisphenol A, bisphenol F, phenylphenol, aminophenol, and naphthol compounds such as α-naphthol, β-naphthol, and dihydroxynaphthol with aldehyde compounds such as formaldehyde, acetaldehyde, and propionaldehyde under an acidic catalyst; and phenolic aralkyl resins and naphthol aralkyl resins synthesized from the above phenolic compounds and dimethoxy-p-xylene, bis(methoxymethyl)biphenyl, etc. Aryl alkyl phenolic resins, such as alkyl phenolic resins; p-xylene-modified phenolic resins; m-xylene-modified phenolic resins; melamine-modified phenolic resins; terpene-modified phenolic resins; dicyclopentadiene-type phenolic resins and dicyclopentadiene-type naphthol resins synthesized by copolymerization of the above phenolic compounds and dicyclopentadiene; cyclopentadiene-modified phenolic resins; polycyclic aromatic ring-modified phenolic resins; biphenyl-type phenolic resins; triphenylmethane-type phenolic resins obtained by polycondensation or co-condensation of the above phenolic compounds with aromatic aldehydes such as benzaldehyde and salicylaldehyde under an acidic catalyst; and phenolic resins obtained by copolymerizing two or more of these. Furthermore, as phenolic curing agents, monophenolic compounds having one phenolic hydroxyl group in one molecule can also be cited. These phenolic curing agents can be used alone or in combination of two or more.

[0092] Examples of amine-based curing agents include: aliphatic amine compounds such as diethylenetriamine, triethylenetetramine, n-propylamine, 2-hydroxyethylaminopropylamine, cyclohexylamine, and 4,4'-diamino-dicyclohexylmethane; aromatic amine compounds such as diethyltoluenediamine, 3,3'-diethyl-4,4'-diaminodiphenylmethane, dimethylthiotoluenediamine, and 2-methylaniline; and imidazoline compounds such as imidazoline, 2-methylimidazoline, and 2-ethylimidazoline. From the viewpoint of storage stability, aromatic amine compounds are preferred, and diethyltoluenediamine, 3,3'-diethyl-4,4'-diaminodiphenylmethane, and dimethylthiotoluenediamine are more preferred.

[0093] There are no particular limitations on the functional group equivalent of the curing agent (for phenolic curing agents, this refers to the hydroxyl equivalent; for amine-based curing agents, this refers to the active hydrogen equivalent). From the viewpoint of balancing various properties such as formability, heat resistance, and electrical reliability, a value of 10 g / eq to 1000 g / eq is preferred, and 30 g / eq to 500 g / eq is more preferred.

[0094] The hydroxyl equivalent when used as a phenolic curing agent refers to the value calculated based on the hydroxyl value determined according to JIS K 0070:1992. Conversely, the active hydrogen equivalent when used as an amine curing agent refers to the value calculated based on the amine value determined according to JIS K 7237:1995.

[0095] In epoxy resin compositions, when the curing agent contains a phenolic curing agent, the epoxy resin composition may or may not contain a curing accelerator.

[0096] There are no particular restrictions on the type of curing accelerator; it can be selected based on the type of epoxy resin and the desired properties of the epoxy resin composition.

[0097] There are no particular limitations on the curing accelerator. For example, it can be selected from at least one of amine-based curing accelerators, imidazole-based curing accelerators, urea-based curing accelerators, and phosphorus-based curing accelerators.

[0098] Examples of amine-based curing accelerators include 1,8-diazabicyclo[5.4.0]-7-undecene and 1,5-diazabicyclo[4.3.0]-5-nonene.

[0099] Examples of imidazole-based curing accelerators include 2-phenyl-4-methylimidazole, 2-ethyl-4-methylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-phenylimidazole ontyl trimellitate, and 2-phenyl-4-methyl-5-hydroxymethylimidazole.

[0100] Examples of urea-based curing accelerators include 3-phenyl-1,1-dimethylurea.

[0101] Examples of phosphorus-based curing accelerators include triphenylphosphine and its addition reactants, diphenyl(p-tolyl)phosphine, tri(alkylphenyl)phosphine, tri(alkoxyphenyl)phosphine, tri(alkylalkoxyphenyl)phosphine, tri(dialkylphenyl)phosphine, tri(trialkylphenyl)phosphine, tri(tetraalkylphenyl)phosphine, tri(dialkoxyphenyl)phosphine, tri(trialkoxyphenyl)phosphine, tri(tetraalkoxyphenyl)phosphine, trialkylphosphine, dialkylarylphosphine, alkyldiarylphosphine, (4-hydroxyphenyl)diphenylphosphine, bis(4-hydroxyphenyl)phenylphosphine, and tri(4-hydroxyphenyl)phosphine.

[0102] When the epoxy resin composition contains a curing accelerator, the content of the curing accelerator relative to the total amount of epoxy resin and curing agent is preferably 0.1% to 8% by mass, more preferably 0.3% to 6% by mass, and even more preferably 0.5% to 5% by mass.

[0103] The epoxy resin composition disclosed herein contains inorganic filler materials.

[0104] There are no particular limitations on the types of inorganic filler materials. Specific examples include spherical silica, crystalline silica, glass, alumina, calcium carbonate, zirconium silicate, calcium silicate, silicon nitride, aluminum nitride, boron nitride, aluminum nitride, boehmite, beryllium oxide, magnesium oxide, zircon, zircon, forsterite, talc, spinel, mullite, titanium dioxide, talc, clay, mica, titanates, and other inorganic materials. Inorganic filler materials with flame-retardant properties can also be used. Examples of flame-retardant inorganic filler materials include aluminum hydroxide, magnesium hydroxide, composite metal hydroxides such as magnesium and zinc hydroxides, and zinc borate. From the perspective of reducing the coefficient of linear expansion, spherical silica is preferred, and from the perspective of high thermal conductivity, alumina is preferred. One type of inorganic filler material can be used alone, or two or more can be used in combination. Examples of the states of inorganic filler materials include powder, spheroidized powder beads, and fibers.

[0105] There is no particular limitation on the average particle size of the inorganic filler. For example, the volume average particle size is preferably 30 μm or less, more preferably 0.1 μm to 30 μm, even more preferably 0.2 μm to 25 μm, and particularly preferably 0.5 μm to 20 μm. When the volume average particle size is 30 μm or less, there is a tendency to improve the filling performance. In addition, when the volume average particle size is 0.1 μm or more, there is a tendency to further suppress the increase in viscosity of the epoxy resin composition.

[0106] The volume average particle size of inorganic filler materials can be measured using a laser diffraction scattering particle size distribution measuring device as the volume average particle size (D50).

[0107] From the viewpoint of the flowability of epoxy resin compositions, the particle shape of inorganic fillers is more preferably spherical than square, and it is also preferable that the particle size distribution of inorganic fillers is distributed over a wide range.

[0108] There is no particular limitation on the content of inorganic filler in the epoxy resin composition. From the viewpoint of flowability and strength, it is preferable that the content of inorganic filler in the epoxy resin composition is 60% by volume or more, more preferably 60% to 90% by volume, and even more preferably 62% to 88% by volume. When the content of inorganic filler in the epoxy resin composition is 60% by volume or more, the properties of the cured product, such as the coefficient of thermal expansion, thermal conductivity, and modulus of elasticity, tend to be further improved. When the content of inorganic filler in the epoxy resin composition is 90% by volume or less, the viscosity increase of the epoxy resin composition tends to be suppressed, the flowability is further improved, and the formability becomes better.

[0109] (Coloring agent)

[0110] The epoxy resin compositions disclosed herein may also contain colorants.

[0111] Examples of known colorants include carbon black, black titanium dioxide, organic dyes, organic pigments, red lead, and iron oxide. The content of the colorant can be appropriately selected according to the purpose. A single colorant can be used alone, or two or more can be used in combination.

[0112] When the epoxy resin composition contains a colorant, its content is preferably 0.01% to 5% by mass, more preferably 0.05% to 3% by mass.

[0113] (ion exchanger)

[0114] The epoxy resin compositions disclosed herein may also contain ion exchangers.

[0115] In particular, from the viewpoint of improving the moisture resistance and high-temperature storage characteristics of semiconductor devices, the presence of an ion exchanger is preferred. There are no particular limitations on the ion exchanger, and conventionally known products can also be used. Specifically, examples include hydrotalcite compounds and hydrated oxides selected from at least one element chosen from magnesium, aluminum, titanium, zirconium, and bismuth. One type of ion exchanger can be used alone, or two or more can be used in combination. Hydrotalcite, as shown in the following general formula (A), is preferred.

[0116] Mg (1-X) Al X (OH)2(CO3) X / 2 ·mH2O(A)

[0117] (0 < X ​​≤ 0.5, m is a positive number)

[0118] When the epoxy resin composition contains an ion exchanger, there is no particular limitation on the amount of the ion exchanger if it is sufficient to capture halogen ions, etc. For example, it is preferably 0.1 to 30 parts by weight, more preferably 1 to 5 parts by weight, relative to 100 parts by weight of epoxy resin.

[0119] (Mold release agent)

[0120] From the viewpoint of obtaining good mold release properties, the epoxy resin composition disclosed herein may also contain a mold release agent. There are no particular limitations on the mold release agent, and conventionally known products can be used. Specifically, examples include higher fatty acids such as carnauba wax, lignite acid, and stearic acid; ester waxes such as higher fatty acid metal salts and lignite esters; and polyolefin waxes such as oxidized polyethylene and non-oxidized polyethylene. One mold release agent may be used alone, or two or more may be used in combination.

[0121] When the epoxy resin composition contains a release agent, its content is preferably 0.01 to 15 parts by weight, more preferably 0.1 to 10 parts by weight, relative to 100 parts by weight of the epoxy resin. When the amount of release agent is 0.01 parts by weight or more relative to 100 parts by weight of the epoxy resin, it tends to provide sufficient release properties. When the amount of release agent is 15 parts by weight or less relative to 100 parts by weight of the epoxy resin, it tends to provide better adhesion.

[0122] (Flame retardant)

[0123] The epoxy resin composition disclosed herein may also contain a flame retardant. There are no particular limitations on the flame retardant; conventionally known products may be used. Specifically, examples include organic or inorganic compounds containing halogen, antimony, nitrogen, or phosphorus atoms, metal hydroxides, etc. One flame retardant may be used alone, or two or more may be used in combination.

[0124] When an epoxy resin composition contains a flame retardant, there is no particular limitation on the amount of the flame retardant, provided that it is sufficient to achieve the desired flame retardant effect. For example, it is preferably 1 to 30 parts by weight, and more preferably 2 to 20 parts by weight, relative to 100 parts by weight of epoxy resin.

[0125] (Stress reliever)

[0126] The epoxy resin composition disclosed herein may also contain stress-relieving agents such as silicone rubber particles. By containing stress-relieving agents in the epoxy resin composition, warpage and cracking of the insulation layer can be further reduced. Commonly used and known stress-relieving agents (flexibilizers) can be cited as examples. Specifically, examples include epoxy-modified thermoplastic elastomers such as silicone, styrene, olefin, urethane, polyester, polyether, polyamide, and polybutadiene; rubber particles such as NR (natural rubber), NBR (acrylonitrile-butadiene rubber), acrylic rubber, urethane rubber, and silicone powder; rubber particles with a core-shell structure such as methyl methacrylate-styrene-butadiene copolymer (MBS), methyl methacrylate-silicone copolymer, and methyl methacrylate-butyl acrylate copolymer; and copolymers of indene, alkyl indene, and other indene-based monomers with styrene, alkyl styrene, and other monomers used as needed, i.e., indene-containing copolymers. One stress-relieving agent may be used alone, or two or more may be used in combination.

[0127] When the epoxy resin composition contains a stress reliever, its content relative to 100 parts by weight of epoxy resin is preferably 0.1 to 30 parts by weight, more preferably 1 to 25 parts by weight.

[0128] (Coupled agent)

[0129] The epoxy resin composition disclosed herein may also contain a coupling agent. There are no particular limitations on the type of coupling agent; known coupling agents may be used. Examples of coupling agents include silane coupling agents and titanium coupling agents. A single coupling agent may be used, or two or more may be used in combination.

[0130] When the epoxy resin composition contains a coupling agent, the content of the coupling agent, from the viewpoint of the interfacial adhesion between the epoxy resin and the inorganic filler material, is preferably 0.001 to 10 parts by weight, more preferably 0.01 to 8 parts by weight, and even more preferably 0.05 to 5 parts by weight, relative to 100 parts by weight of the inorganic filler material.

[0131] There is no particular limitation on the method of applying the epoxy resin composition to the semiconductor substrate 10. For example, a solvent can be added to the epoxy resin composition to prepare a liquid epoxy resin composition, and the liquid epoxy resin composition can be applied to the semiconductor substrate 10 using a rod coating method, spin coating method, or the like, and then dried. Alternatively, an adhesive film comprising a support and an epoxy resin composition layer disposed on the support can be laminated onto the semiconductor substrate 10 in such a way that the epoxy resin composition layer is in contact with the semiconductor substrate 10.

[0132] As a support, there are no particular limitations on the shape and material if an epoxy resin composition layer can be formed on it; metal foil or resin film is preferred. Examples of metal foils include copper foil, aluminum foil, and nickel foil. As resin films, plastic films such as polyethylene terephthalate film, polyimide film, polyethylene film, polypropylene film, polytetrafluoroethylene film, polymethylpentene film, polyamide-imide film, polyether-imide film, polyethersulfone film, fully aromatic polyester film, polytetrafluoroethylene film, ethylene-tetrafluoroethylene copolymer film, tetrafluoroethylene-hexafluoropropylene copolymer film, and tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer film can be used. These plastic films can also be used after surface demolding treatment.

[0133] Alternatively, an epoxy resin composition can be applied to a support and dried to form an epoxy resin composition layer, after which a protective film can be laminated onto the epoxy resin composition layer. By setting the protective film on the epoxy resin composition layer, the processability of the adhesive film is improved. The same material as the support can be used as this protective film. When winding the adhesive film using a high-productivity roller coating method, a polyolefin film such as a polyethylene film or polypropylene film, which is more flexible than a polyethylene terephthalate film, is preferred as the protective film.

[0134] As a method for applying epoxy resin compositions to a support, known methods can be used, including dip coating, flow coating, spin coating, curtain coating, doctor blade coating, roller coating, wire rod coating, knife coating, comma coating, spray coating, ultrasonic coating, inkjet coating, mold coating, gravure coating, screen printing, wiping, brush coating, and sponge coating. Among these, comma coating or light-touch roller coating, which offer high productivity and allow for precise coating with uniform thickness, are preferred.

[0135] There are no particular limitations on the drying temperature of the epoxy resin composition applied to the support. When preparing a varnish-like epoxy resin composition by dissolving or dispersing the components in an organic solvent, from the viewpoint of suppressing the generation of bubbles in the adhesive film caused by foaming of the organic solvent during drying, it is preferable to perform drying at a temperature 10°C to 50°C lower than the boiling point of the organic solvent used. This means that the drying temperature is preferably 15°C to 45°C lower than the boiling point of the organic solvent, more preferably 20°C to 40°C lower.

[0136] The stacking of the semiconductor substrate 10 and the adhesive film can be performed using a vacuum lamination method. In the vacuum lamination method, the heating and pressing temperature is preferably 60°C to 160°C, more preferably 80°C to 140°C. The pressing pressure is preferably 0.1 MPa to 2 MPa, more preferably 0.3 MPa to 1.5 MPa. The pressing time is preferably 10 seconds to 500 seconds, more preferably 20 seconds to 400 seconds. The lamination is preferably performed under reduced pressure conditions of 30 hPa or less.

[0137] The curing conditions for the epoxy resin composition layer are not particularly limited. The preferred heat treatment temperature is 120°C to 200°C, more preferably 130°C to 180°C, and even more preferably 140°C to 170°C. The preferred heat treatment time is 5 minutes to 3 hours, more preferably 10 minutes to 2 hours.

[0138] An insulating layer 14 is formed on a semiconductor substrate 10 by curing an epoxy resin composition layer.

[0139] Other methods for forming an insulating layer 14 on a semiconductor substrate 10 include transfer molding, injection molding, compression molding, etc., which can be used as methods for sealing electronic component devices using epoxy resin compositions.

[0140] Figure 2 This is a cross-sectional view showing the roughened state of the surface of the insulating layer 14. The roughening method of the insulating layer 14 is not particularly limited; it can be either a dry method or a wet method.

[0141] Examples of dry roughening methods include mechanical grinding using grinding wheels or sandblasting, grinding using abrasive stones, and plasma etching using CF4 or SF6 gases. Examples of wet roughening methods include chemical treatments using oxidants such as permanganates, dichromates, ozone, hydrogen peroxide / sulfuric acid, and nitric acid, strong alkalis, and resin swelling solvents. Wet roughening methods can also include wet slag removal treatments, which will be described later.

[0142] The surface of the insulating layer 14 is preferably roughened by at least one of grinding, chemical treatment and plasma etching.

[0143] The surface roughness Ra of the roughened insulating layer 14 is preferably 0.1 μm to 2.0 μm, more preferably 0.2 μm to 0.5 μm, even more preferably 0.2 μm to 0.4 μm, and particularly preferably 0.2 μm to 0.3 μm.

[0144] In this disclosure, surface roughness Ra refers to the value measured based on JIS B0601:2013.

[0145] Figure 3 This is a cross-sectional view showing the state in which a metal protective film 16 is formed on the roughened surface of the insulating layer 14. The method for forming the metal protective film 16 on the surface of the insulating layer 14 is not particularly limited; it can be a dry method or a wet method, depending on the type of metal constituting the metal protective film 16.

[0146] Examples of metals constituting the metal protective film 16 include copper, copper alloys, and titanium.

[0147] As a dry method for metal evaporation, examples of physical methods include vacuum evaporation and sputtering, while examples of chemical methods include chemical vapor deposition (CVD).

[0148] Vacuum evaporation is a method that uses resistance heating or electron gun irradiation to heat and evaporate the film-forming material, forming a thin film on the object.

[0149] Sputtering is a method in which a voltage is applied between the anode and the cathode to ionize an inert gas such as Ar, and the inert gas ions bombard the target material placed on the cathode side to scatter the target material, which is then stacked on the object placed on the anode side.

[0150] Examples of wet methods include electroless plating and electrolytic plating. Electroless plating and electrolytic plating can also be combined.

[0151] The metal protective film is preferably formed using at least one of metal vapor deposition, electroless plating, and electrolytic plating.

[0152] The metal protective film can be a single layer or two or more layers. When the metal protective film consists of two or more layers, the types of metals contained in each layer can be the same or different.

[0153] The average thickness of the metal protective film 16 is preferably 0.1 μm to 2.0 μm, more preferably 0.1 μm to 1.0 μm, and even more preferably 0.1 μm to 0.5 μm. When the metal protective film 16 is composed of two or more layers, the average thickness of the metal protective film 16 refers to the average thickness of the entire metal protective film 16 composed of two or more layers.

[0154] Figure 4 This diagram shows the state after the metal protective film 16, which is provided on the surface of the insulating layer 14, has been partially removed from the region (region Q) corresponding to the location where the through hole is to be provided.

[0155] There is no particular limitation on the method for partially removing the metal protective film 16. The metal protective film 16 can be partially removed using photolithography, a known technique (lamination of dry film resist (DFR), UV curing, development of DFR, etching of metal protective film 16, and stripping of DFR).

[0156] The shape of region Q when viewed from the thickness direction of insulating layer 14 should match the shape of the predetermined through hole formed in insulating layer 14. The through hole and region Q are generally circular.

[0157] The ratio (Q / A) of the average diameter Q of region Q when viewed from the thickness direction of insulating layer 14 to the average diameter A of the predetermined through holes formed in insulating layer 14 is preferably 1.0 to 1.5, more preferably 1.0 to 1.2, and even more preferably 1.0 to 1.1.

[0158] Furthermore, in this disclosure, the diameter of the through hole refers to the equivalent circle diameter at the narrowest point of the through hole when viewed from the thickness direction of the insulating layer 14. Additionally, in this disclosure, the average diameter A of the through holes refers to the arithmetic mean of the equivalent circle diameters of the five through holes. Furthermore, the average diameter Q of region Q refers to the arithmetic mean of the equivalent circle diameters of the five regions Q.

[0159] For example, the cross-sectional shape of a through hole will be described later. Figure 6 When the shape is cone-shaped as shown in the diagram, the average diameter A of the through hole is described later. Figure 6 The figure shown refers to the arithmetic mean of the diameter at the bottom of the through hole.

[0160] Figure 5 This is a cross-sectional view showing the state in which through holes 18 are provided on the surface of the insulating layer 14. The through holes 18 on the insulating layer 14 can be formed using laser processing or the like. From the viewpoint of suppressing wiring damage, laser processing is preferred.

[0161] When forming the through hole 18 using laser processing, the laser used can be, for example, a carbon dioxide laser (CO2 laser), a UV laser, a YAG laser, an excimer laser, etc.

[0162] The wavelength, number of pulses, pulse amplitude, and power of the laser are selected according to the diameter of the through hole 18.

[0163] In the semiconductor device manufacturing method disclosed herein, when the average diameter of the through-hole 18 is set to A, it is preferable that A and B satisfy the following relationship (II). By ensuring that A and B satisfy the following relationship (II), the through-hole 18 is less likely to be blocked by the inorganic filler material 12 exposed to the side, thus tending to ensure the bonding strength of the conductor formed within the through-hole to the insulating layer and improve the reliability of multilayer wiring. The ratio of the average diameter A to the average maximum particle length B (A / B) is preferably 3.1 to 10.0, more preferably 3.5 to 8.0, and even more preferably 4.0 to 6.0.

[0164] A > 3B (II)

[0165] Figure 6 This is a cross-sectional view showing the state of the insulating layer 14 after dry deslagging treatment was performed on the through hole 18. (See diagram below.) Figure 5As shown, the inorganic filler material 12 may sometimes be exposed on the side of the through hole 18 formed in the insulating layer 14 by laser processing or the like. In locations other than where the through hole 18 is formed in the insulating layer 14, a metal protective film 16 remains on the surface of the insulating layer 14. Because the metal protective film 16 is resistant to dry deslagging treatment, when the insulating layer 14 is subjected to dry deslagging treatment, the side of the through hole 18 is treated intensively, reducing the unevenness on the side of the through hole 18 caused by the inorganic filler material 12.

[0166] Examples of dry slag removal processes include slag removal using plasma. Additionally, dry sandblasting, where abrasive materials are blown from a nozzle to grind the object being treated, can also be used as a dry slag removal process. Among these, slag removal using plasma, which exhibits excellent removal properties of the inorganic filler material 12, is preferred.

[0167] Examples of gases that can be used in plasma-based slag removal processes include O2, CF4, C2F4, C3F8, NF3, H2, Ar, N2, and mixtures thereof. The ambient gas pressure during plasma-based slag removal is preferably 200 Pa or less, more preferably 150 Pa or less, and even more preferably 100 Pa or less. The processing time during plasma-based slag removal is preferably 0.5 to 30 minutes, more preferably 1 to 10 minutes.

[0168] The dry deslagging treatment is preferably carried out until the average height C of the protrusions from the inorganic filler material 12 on the surface of the through hole 18 and the average maximum particle length B of the inorganic filler material 12 satisfy the following relationship (I). By performing the dry deslagging treatment until B and C satisfy the following relationship (I), the generation of unevenness on the side of the through hole 18 can be further suppressed. The ratio of the average maximum particle length B to the average height C of the protrusions (B / C) is preferably 2.1 to 4.0, more preferably 2.3 to 3.5, and even more preferably 2.5 to 3.0.

[0169] B>2C(I)

[0170] Prior to dry slag removal, at least one of wet slag removal and plasma ashing treatment can be further performed. By performing at least one of wet slag removal and plasma ashing treatment before dry slag removal, resin-derived slag generated during the formation of the through hole 18 can be efficiently removed, thereby improving the bonding strength between the wiring layer and the insulation layer 14 formed within the through hole 18.

[0171] Examples of wet slag removal treatments include swelling treatment of the insulation layer 14, neutralization treatment after oxidizing and decomposing the adhesive residue using an alkaline permanganate solution or chromate solution, and water washing treatment.

[0172] As an example of plasma ashing treatment, previous slag removal processes that used plasma can be cited.

[0173] After dry deslagging treatment, a wiring layer is formed on the insulation layer 14. The wiring layer can be formed using metal pattern forming methods known in the field of printed wiring boards, such as subtractive or semi-additive methods.

[0174] When forming a wiring layer on the insulating layer 14, the wiring layer can be formed after removing the metal protective film 16, or it can be formed on the metal protective film 16 using the method described above. When forming a wiring layer on the metal protective film 16, the metal protective film 16 constitutes part of the wiring layer. By forming a wiring layer on the insulating layer 14, a wiring layer can also be formed on the side of the through hole 18. The wiring layer on the side of the through hole 18 functions as a conductor existing within the through hole 18.

[0175] Examples of metals that can form wiring layers include copper, titanium, silver, gold, and their alloys.

[0176] By repeatedly forming the insulation layer 14 and the wiring layer, a multilayer wiring can be formed in which adjacent wiring layers separated by the insulation layer 14 are electrically connected by conductors in the through hole 18.

[0177] Figure 3 In this process, the insulating layer 14 having a metal protective film 16 on its surface can also be disposed on the semiconductor substrate 10 using an adhesive film with an epoxy resin composition layer and a metal foil in sequence. By contacting the epoxy resin composition layer in the adhesive film with the metal foil to the semiconductor substrate 10 and then curing the epoxy resin composition layer, the insulating layer 14 having a metal protective film 16 on its surface can be disposed on the semiconductor substrate 10.

[0178] As an adhesive film with a metal foil, one can be used where an epoxy resin composition layer is formed on the metal foil serving as a support. Details of the metal foil constituting the adhesive film with a metal foil and the epoxy resin composition, as well as the method for forming the epoxy resin composition layer, are described above.

[0179] Figure 4 In region Q, the metal protective film 16 is partially removed beforehand. However, as a method for forming the through hole 18, when a laser processing method that can form the through hole 18 in the insulating layer 14 while the metal protective film 16 is present is selected, it is not necessary to form region Q.

[0180] The height C of the protrusion from the inorganic filler material 12 refers to, for example, Figure 6 As shown, the height of the inorganic filler material 12 protruding from the side of the through hole 18 in the cross-section of the through hole 18 is shown.

[0181] The average height C of the protrusions from the inorganic filler material 12 is calculated by taking the height C of the protrusions from the inorganic filler material 12 in each of the five cross-sectional photographs of the through hole 18. The arithmetic mean of the heights C of the three highest points (a total of 15 heights C) is taken as the average height C of the protrusions from the inorganic filler material 12.

[0182] In addition, the average maximum particle length B of the inorganic filler material is calculated by taking the particle length B of the inorganic filler material 12 in each of the five cross-sectional photographs of the through hole 18, and the arithmetic mean of the particle lengths B of the three largest inorganic filler material 12 (a total of 15 particle lengths B) is taken as the average maximum particle length B of the inorganic filler material.

[0183] The average maximum particle length B of the inorganic filler material is preferably 1 μm to 50 μm, more preferably 1 μm to 30 μm, and even more preferably 5 μm to 10 μm.

[0184] <Manufacturing Method of Printed Wiring Boards>

[0185] The semiconductor device manufacturing method disclosed herein can also be applied to the manufacturing of printed wiring boards. Specifically, the printed wiring board manufacturing method of this disclosure is a method for manufacturing a multilayer printed wiring board having alternating layers of wiring layers and insulating layers. In this method, adjacent wiring layers separated by insulating layers in the stacking direction are electrically connected by conductors existing in through-holes disposed in the insulating layers. The multilayer wiring is formed through the following steps: providing an insulating layer on a substrate with a surface having a metal protective film and containing an inorganic filler material with an average maximum particle length B of 1 μm to 100 μm; forming through-holes in the insulating layer; and performing a dry deslagging treatment on the insulating layer with the through-holes formed.

[0186] In the method for manufacturing the printed wiring board disclosed herein, for example, in addition to... Figure 1 The semiconductor substrate 10 is transformed into a core substrate, and multilayer wiring is formed therein, thereby obtaining a printed wiring board as a multilayer wiring board. Examples of core substrates include glass epoxy boards such as FR-4 substrates, polyester substrates, polyimide substrates, BT resin substrates, and polyphenylene ether substrates.

[0187] Semiconductor Devices

[0188] The semiconductor device disclosed herein includes: a semiconductor element; and a multilayer wiring consisting of alternating layers of wiring layers and insulating layers electrically connected to the semiconductor element, wherein adjacent wiring layers separated by insulating layers in the stacking direction are electrically connected by conductors present in through holes provided in the insulating layers, the insulating layers containing an inorganic filling material with an average maximum particle length B of 1 μm to 100 μm, and when the average height of the protrusion from which the inorganic filling material originates on the side of the through hole is set as C and the average diameter of the through hole is set as A, the following relationships (I) and (II) are satisfied.

[0189] B>2C(I)

[0190] A > 3B (II)

[0191] Since the semiconductor device of this disclosure satisfies equations (I) and (II), unevenness on the side of the through-hole can be suppressed. As a result, it tends to ensure the bonding strength of the conductor to the insulating layer within the through-hole and improve the reliability of multilayer wiring.

[0192] There is no particular limitation on the method for forming the multilayer wiring of the semiconductor device, and it can be formed using the semiconductor device manufacturing method disclosed herein.

[0193] Example

[0194] The present disclosure is illustrated in more detail below with reference to the embodiments, but the scope of the present disclosure is not limited to these embodiments.

[0195] <Example 1>

[0196] [Formation of the insulating layer]

[0197] An insulating layer, consisting of a copper-plated laminate (Showa Denko Materials Co., Ltd., MCL-E-679FG) with a substrate thickness of 0.81 mm and a copper thickness of 18 μm, was formed on the side of a substrate with copper wiring formed thereon. This was achieved using a compression molding apparatus (TOWA Corporation, CMP-1000) under conditions of a load of 3 MPa, a pressing time of 600 seconds, a temperature of 150°C, and an average molding thickness of 0.1 mm. The insulating layer was a cured epoxy resin composition (containing 76 vol% silica particles with a volume average particle size of 5.7 μm as the inorganic filler). The average maximum particle length B of the inorganic filler in the insulating layer was 23 μm.

[0198] [Formation of a protective metal film]

[0199] The surface of the insulation layer obtained above was roughened by wet deslagging treatment. The surface roughness Ra of the roughened insulation layer was measured to be 0.32 μm using a contact height difference meter (Bruker DektakXT) according to JIS B0601:20113.

[0200] On the roughened insulating layer, titanium and copper are sequentially sputtered using a sputtering apparatus (ULVAC Co., Ltd., SIC-500) with a titanium thickness of 25 nm and a copper thickness of 150 nm to form a metal protective film.

[0201] [Partial removal of the metal protective coating]

[0202] On the surface of a metal protective film disposed on an insulating layer, a dry film resist (Showa Denko Materials Co., Ltd., RD-1215) is laminated using a vacuum laminator (Nikko Materials Co., Ltd., CV-300) under a load of 0.5 MPa and a temperature of 60°C. Next, exposure is performed using a photomask and a UV exposure machine (Mikasa Co., Ltd., ML-320), and development is performed using a 1% (w / w) sodium carbonate aqueous solution to form a pattern with a φ of 0.15 mm corresponding to the area (area Q) where the through-hole is to be set. Then, a seed etching solution (Mitsubishi GAS Chemical Co., Ltd., WLC-C2) is used to remove the portion of the metal protective film corresponding to area Q. Finally, a stripping solution (Mitsubishi GAS Chemical Co., Ltd., R-100S, R-100) is used to strip the dry film resist, obtaining an insulating layer with a metal protective film having an area Q with a φ of 0.15 mm formed on its surface.

[0203] [Formation of the through hole]

[0204] At the location where region Q is formed, a through hole is formed by laser processing using a CO2 laser processing machine, with a diameter of 0.15 mm, penetrating the insulating layer without penetrating the copper wiring on the copper-plated laminate. The average diameter A of the through hole is 132 μm.

[0205] [Implementation of dry slag removal]

[0206] For an insulating layer with through-holes, the surface of the inorganic filler material contained in the insulating layer is scraped off. Dry deslagging is performed under the condition that the average maximum particle length of the inorganic filler material is set as B and the average height of the protrusions from which the inorganic filler material originates on the side of the through-hole is set as C, satisfying the following relationship (I). As the dry deslagging process, a deslagging process using CF4 plasma is employed.

[0207] B>2C(I)

[0208] [Formation of the wiring layer]

[0209] Wiring was performed on an insulating layer with through holes after dry deslagging, using a semi-additive process (SAP) to connect the wiring on the insulating layer to the copper wiring on the substrate. In the resulting multilayer wiring, the average height C of the protrusions derived from the inorganic filler material on the side of the through holes was 8 μm.

[0210] <Comparative Example 1>

[0211] Except for omitting the "formation of the metal protective film" and "partial removal of the metal protective film" in Example 1, the wiring on the insulating layer is connected to the copper wiring on the substrate. In the resulting multilayer wiring, the average height C of the protrusions from the inorganic filler material on the side of the through hole is 17 μm.

[0212] All documents, patent applications and technical standards described in this specification are incorporated herein by reference to the specific documents, patent applications and technical standards mentioned herein, to an equal degree.

[0213] Symbol Explanation

[0214] 10 Semiconductor substrate

[0215] 12 Inorganic filler materials

[0216] 14 Insulation layer

[0217] 16 Metal Protective Film

[0218] 18 Through holes

[0219] Q corresponds to the area where the through hole is to be installed.

Claims

1. A method for manufacturing a semiconductor device, which is a method for manufacturing a semiconductor device having a multilayer wiring in which wiring layers and insulating layers are alternately stacked, wherein: The wiring layers adjacent to each other in the stacking direction with the insulating layer interposed therebetween are electrically connected via conductors in through holes provided in the insulating layer. The multi-layer wiring is formed by the following steps: The step of providing the insulating layer having a metal protective film on the surface and containing an inorganic filler material having an average maximum particle length B of 1 μm to 100 μm on the substrate; forming a through hole in the insulating layer; and A step of performing a dry deslagging process on the insulating layer having the through hole formed therein.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The dry deslagging treatment is performed until the average height C of the convex portion of the through-hole side surface from which the inorganic filler material originates and the average maximum particle length B of the inorganic filler material satisfy the following relationship (I): B>2C(I).

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: When the average diameter of the through-holes is set to A, the following relational formula (II) is satisfied: A>3B(II).

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The through hole is formed by at least one selected from laser processing and photolithography.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The through hole is formed as follows: The photolithography method is used to remove a region of the metal protection film corresponding to a position where the through hole is to be provided, and then the laser processing is performed on the position where the metal protection film is removed.

6. The method for manufacturing a semiconductor device according to claim 4, wherein: The through hole is formed by performing the laser processing in a state where the metal protection film is present on the surface of the insulating layer.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein: The insulating layer having the metal protective film on the surface is disposed on the substrate through the following steps: The step of providing the insulating layer on the substrate; A step of roughening the surface of the insulating layer; and The step of disposing the metal protection film on the roughened surface of the insulating layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The surface of the insulating layer is roughened by at least one selected from grinding, chemical reagent treatment and plasma etching treatment.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein: The metal protective film is formed by at least one selected from metal vapor deposition, electroless plating, and electrolytic plating.

10. The method for manufacturing a semiconductor device according to any one of claims 7 to 9, wherein: The roughened insulating layer has a surface roughness Ra of 0.1 μm to 2.0 μm.

11. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein: The insulating layer is a cured product of an epoxy resin composition.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein: The insulating layer having the metal protective film on the surface is provided on the substrate by bringing the epoxy resin composition layer in an adhesive film with metal foil having an epoxy resin composition layer and metal foil in sequence into contact with the substrate and then curing the epoxy resin composition layer. 13 . The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of forming a wiring layer on the insulating layer subjected to the dry descum treatment.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The wiring layer is formed after removing the metal protection film from the surface of the insulating layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: The wiring layer is formed on the metal protection film.

16. The method for manufacturing a semiconductor device according to any one of claims 1 to 15, wherein: Before the dry descum treatment, at least one of a wet descum treatment and a plasma ashing treatment is further performed.

17. A semiconductor device comprising: Semiconductor components; and A multilayer wiring formed by alternately stacking wiring layers and insulating layers electrically connected to the semiconductor element; in, The wiring layers adjacent to each other in the stacking direction with the insulating layer interposed therebetween are electrically connected via conductors in through holes provided in the insulating layer. The insulating layer contains an inorganic filler material having an average maximum particle length B of 1 μm to 100 μm, When the average height of the convex portions of the through-holes from which the inorganic filler material originates is C and the average diameter of the through-holes is A, the following relations (I) and (II) are satisfied: B>2C(I) A>3B(II).

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