Control circuit, chip and electronic equipment
By using reference modules and comparison modules in the control circuit, the target resistance value to be measured of the electric fuse is determined, and the error result problem caused by the failure of the electric programmable fuse to be completely fused during the fuse process is solved, and the accuracy of the circuit parameters is achieved Reservation of corrections and error ranges.
Patent Information
- Application Number
- CN202411297504.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-24
AI Technical Summary
Due to fluctuations in manufacturing process and unstable fuse energy, the electrically programmable fuse may not be completely fused during the fuse process, resulting in erroneous results during the resistance comparison, affecting the accuracy of the chip design.
A control circuit is designed, including a reference module and a comparison module. Through a resistor unit and a variable resistor unit connected in series and parallel, a voltage drop is generated using the reference current to determine the target resistance value to be measured for the electric fuse, ensuring that it is in user mode. The fuse status of the electric fuse is accurately determined and the error range is reserved.
It effectively improves the accuracy of the fuse state of the electric fuse, ensures that the circuit parameters are corrected by fuse, and reduces the impact of errors caused by circuit offset voltage.
Smart Images
Figure CN119179034A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic circuits, and in particular to a control circuit, a chip and an electronic device. Background Art
[0002] An electrically programmable fuse (eFuse) is usually a one-time programmable memory used in integrated circuits. The resistance of an electrically programmable fuse (hereinafter referred to as eFuse) is small when it is in an unprogrammed state (unblown state), while the resistance of the eFuse is large when it is in a programmed state (blown state). Therefore, the identification, function, and electrical characteristics of the integrated circuit can be modified by blowing the eFuse. For example, the low resistance state of the unblown eFuse is used as the logic state "0", and the high resistance state of the blown eFuse is used as the logic state "1". Based on the logic states before and after the blowing of the eFuse, the parameters that deviate from the chip specification range can be corrected.
[0003] At present, the blown state of the electric fuse is usually determined by comparing the resistance of the electric fuse with that of a reference resistor. For example, when the resistance of the electric fuse is greater than the resistance of the reference resistor, it can be determined that the electric fuse is in a blown state; on the contrary, if the resistance of the electric fuse is less than the resistance of the reference resistor, it can be determined that the electric fuse is in an unblown state.
[0004] However, due to fluctuations in the manufacturing process or instability in the blowing energy, the electric fuse may not be completely blown during the blowing process, resulting in erroneous results when comparing the resistance of the electric fuse with that of a reference resistor, which is not conducive to chip design. Summary of the invention
[0005] Embodiments of the present application provide a control circuit, a chip, and an electronic device.
[0006] In a first aspect, the present application provides a control circuit, comprising: a reference module and a comparison module, wherein the reference module comprises a first resistance unit and a second resistance unit connected in series, and the comparison module comprises a variable resistance unit connected in parallel with the first resistance unit and the second resistance unit; the comparison module is used to generate a first voltage drop based on a reference current flowing through the variable resistance unit when the resistance value of the variable resistance unit changes to a target resistance value to be measured, and to generate a second voltage drop based on a reference current flowing through the first resistance unit and the second resistance unit, and output a first output result based on the magnitude relationship between the first voltage drop and the second voltage drop; the comparison module is used to generate a first voltage drop based on a reference current flowing through the variable resistance unit when the first output result indicates that the first voltage drop is greater than the second voltage drop, and to generate a third voltage drop based on the reference current flowing through the first resistance unit, and output a second output result based on the magnitude relationship between the first voltage drop and the third voltage drop, wherein the second output result indicates that the first voltage drop is greater than the third voltage drop.
[0007] In the embodiment of the present application, the target resistance value to be measured of the above-mentioned variable resistance unit can be the resistance value after the electric fuse is completely blown (blown state), or it can be the resistance value after it is not completely blown (not completely blown state). Before comparing the resistance values of the electric fuse Rfuse (variable resistance unit) and the reference resistor R01 (first resistance unit), that is, when in the test mode, first determine that the target resistance value to be measured of the electric fuse Rfuse is greater than the sum of the resistance values of the reference resistor R01 and the reference resistor R02 (second resistance unit), so that the control circuit determines that the electric fuse is a completely blown electric fuse (the first output result indicates that the first voltage drop is greater than the second voltage drop). Subsequently, in the user mode, only the resistance value of the electric fuse Rfuse is compared with the reference resistor R01 to ensure that the target resistance value to be measured of the electric fuse Rfuse is greater than the resistance value of the reference resistor R01. That is to say, the control circuit can ensure that the electric fuse after being screened in the test mode is accurately determined as a completely blown electric fuse in the user mode (the second output result indicates that the first voltage drop is greater than the third voltage drop), thereby ensuring that the circuit parameters are corrected by blowing the electric fuse.
[0008] In a possible implementation of the first aspect above, a resistance value of the first resistance unit is greater than or equal to a resistance value of the second resistance unit.
[0009] In the embodiment of the present application, since the target resistance to be measured of the electric fuse Rfuse is greater than the sum of the resistance values of the reference resistors R01 and R02, and the resistance value of the reference resistor R02 is equal to or greater than the resistance value of the reference resistor R01; that is, the target resistance to be measured of the electric fuse Rfuse is not only greater than the resistance value of the reference resistor R01, but also differs from the reference resistor R0 by at least the resistance value of the reference resistor R02, thereby effectively reserving an error range caused by the circuit offset voltage.
[0010] In a possible implementation of the first aspect, the variable resistance unit includes an electric fuse, and the target resistance value to be measured is a resistance value after the electric fuse is blown.
[0011] In a possible implementation of the first aspect above, it also includes: a control module, the control module includes a first switch unit connected in parallel with the second resistance unit; the control module is used to drive the first switch unit to be in an off state when the resistance value of the variable resistance unit changes to the target resistance value to be measured, so that the reference current can flow through the first resistance unit and the second resistance unit; and the control module is used to drive the first switch unit to be in an on state when the first output result indicates that the first voltage drop is greater than the second voltage drop, so that the reference current only flows through the first resistance unit.
[0012] In a possible implementation of the first aspect above, it also includes: a bias module, the bias module includes a first mirror unit and a reference current source connected in series with the first mirror unit, and the current of the reference current source is a reference current, the reference module also includes a second mirror unit, and the comparison module also includes a third mirror unit, wherein the first mirror unit and the second mirror unit form a first current mirror branch, and the bias module provides a reference current to the reference module based on the first current mirror branch; the first mirror unit and the third mirror unit form a second current mirror branch, and the bias module provides a reference current to the comparison module based on the second current mirror branch.
[0013] In a possible implementation of the first aspect above, the second mirror unit is connected in series with the first resistor unit and the second resistor unit, and the third mirror unit is connected in series with the variable resistor unit; a first voltage drop is generated by the reference current flowing through the variable resistor unit so that the current flowing through the third mirror unit is the first current, and the first current is used as the pull-up current of the target node in the comparison module; a second voltage drop is generated by the reference current flowing through the first resistor unit and the second resistor unit so that the current flowing through the second mirror unit is the second current, and the second current is used as the pull-down current of the target node; or, a third voltage drop is generated by the reference current flowing through the first resistor unit so that the current flowing through the second mirror unit is the third current, and the third current is used as the pull-down current of the target node; the comparison module outputs the first output result or the second output result based on the magnitude relationship between the pull-up current and the pull-down current of the target node.
[0014] In a possible implementation of the first aspect above, the comparison module determines the first output result or the second output result based on the following method: when the target resistance to be measured is greater than the sum of the resistance values of the first resistance unit and the second resistance unit, the first voltage drop is greater than the second voltage drop, and the pull-up current is less than the pull-down current, and the first output result is a low-level signal; or, when the target resistance to be measured is greater than the resistance value of the first resistance unit, the first voltage drop is greater than the third voltage drop, and the pull-up current is less than the pull-down current, and the second output result is a low-level signal.
[0015] In a possible implementation of the first aspect, the first mirror unit includes a first MOS tube, the second mirror unit includes a second MOS tube, the third mirror unit includes a third MOS tube, the bias module includes a third resistor unit and a fourth resistor unit, the third resistor unit has a resistance value equal to that of the first resistor unit, and the fourth resistor unit has a resistance value equal to that of the second resistor unit, the control module includes a second switch unit, the second switch unit is connected in parallel with the fourth resistor unit, and the second switch unit is in the same open or closed state as the first switch unit; one end of the third resistor unit is connected to the output end of the power supply voltage, the other end of the second resistor unit is connected to one end of the fourth resistor unit, the other end of the fourth resistor unit is connected to the source of the first MOS tube, and one end of the first resistor unit is connected to The output end of the power supply voltage is connected, the other end of the first resistance unit is connected to one end of the second resistance unit, the other end of the second resistance unit is connected to the source of the second MOS tube, one end of the variable resistance unit is connected to the output end of the power supply voltage, the other end of the variable resistance unit is connected to the source of the third MOS tube, and the source of the first MOS tube is connected to the gate terminal of the first MOS tube, and the gate of the first MOS tube is respectively connected to the gate of the second MOS tube and the gate of the third MOS tube, so that the first MOS tube and the second MOS tube form a first current mirror branch and provide a reference current to the bias module through the first current mirror branch, and the first MOS tube and the third MOS tube form a second current mirror branch and provide a reference current to the comparison module through the second current mirror branch.
[0016] In a possible implementation of the first aspect, the reference module includes a fourth MOS tube and a fifth MOS tube, and the comparison module includes a sixth MOS tube and a seventh MOS tube; the drain of the fourth MOS tube is connected to the drain of the second MOS tube, the source of the fourth MOS tube is connected to the drain of the fifth MOS tube, the source of the fifth MOS tube is connected to the ground terminal, the drain of the sixth MOS tube is connected to the drain of the third MOS tube, the source of the sixth MOS tube is connected to the drain of the seventh MOS tube, the source of the seventh MOS tube is connected to the ground terminal, and the gate of the fourth MOS tube is connected to the gate of the sixth MOS tube, and the gate of the fourth MOS tube and the gate of the sixth MOS tube are provided with a second driving voltage, the gate of the fifth MOS tube is connected to the gate of the seventh MOS tube, and the gate of the fifth MOS tube and the gate of the seventh MOS tube are both connected to the drain of the fourth MOS tube, so that the fourth MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube form a third current mirror branch, and the reference module provides the second current or the third current to the comparison module through the third current mirror branch, so that the second current or the third current is used as the pull-down current of the target node.
[0017] In a possible implementation of the first aspect, the first MOS transistor, the second MOS transistor and the third MOS transistor are PMOS transistors, and the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are NMOS transistors.
[0018] In a second aspect, a chip is provided, in which a circuit as described in any one of the first aspects is formed.
[0019] According to a third aspect, an electronic device is provided. The electronic device includes a chip, in which a circuit as described in any one of the first aspects is formed. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 According to some embodiments of the present application, a module diagram of a control circuit 10 is shown;
[0021] Figure 2 According to some embodiments of the present application, a circuit diagram of a control circuit 10 is shown;
[0022] Figure 3 According to some embodiments of the present application, an example schematic diagram of an electronic device 100 is shown. DETAILED DESCRIPTION
[0023] The illustrative embodiments of the present application include, but are not limited to, a control circuit, a chip, and an electronic device.
[0024] The following is combined with Figures 1 to 3 The technical solution of this application is introduced.
[0025] As mentioned above, when the electric fuse is in an unblown state, the resistance of the electric fuse is less than the resistance of the reference resistor, and the logic state of the circuit in which the electric fuse is deployed is "0" at this time; when the logic state of the circuit needs to be corrected from "0" to "1", the electric fuse can be blown to put the electric fuse in a blown state, thereby making the resistance of the electric fuse greater than the resistance of the reference resistor, so as to realize the correction of the logic state of the circuit in which the electric fuse is deployed to "1".
[0026] However, due to fluctuations in the manufacturing process or instability in the melting energy, the electric fuse may be in an incompletely melted state during the melting process, resulting in an erroneous result when comparing the resistance of the electric fuse with that of the reference resistor. For example, the electric fuse is in an incompletely melted state due to the instability of the melting energy during the melting process, resulting in the resistance of the electric fuse after melting may still be smaller than the resistance of the reference resistor, that is, it is impossible to correct the logic state of the circuit in which the electric fuse is deployed from "0" to "1" by melting the electric fuse. Or for example, the resistance of the reference resistor is 100 ohms, and the electric fuse is in an incompletely melted state due to the instability of the melting energy during the melting process, resulting in the resistance of the electric fuse after melting changing to 101 ohms. Since the circuit itself may have an offset voltage, it is difficult to compare the reference resistor with a smaller resistance difference with the electric fuse, and thus it is impossible to accurately correct the circuit parameters by melting the electric fuse.
[0027] To this end, the present application proposes a control circuit, such as Figure 1 As shown, the control circuit 10 includes a reference module 11 and a comparison module 12. The reference module 11 includes a first resistance unit and a second resistance unit connected in series; the comparison module 12 includes a variable resistance unit (electric fuse) connected in parallel with the first resistance unit and the second resistance unit. The comparison module 12 is used to generate a first voltage drop based on the reference current flowing through the variable resistance unit when the resistance value of the variable resistance unit changes to the target resistance value to be measured (the resistance value after the electric fuse is blown), and to generate a second voltage drop based on the reference current flowing through the first resistance unit and the second resistance unit, and to output a first output result based on the magnitude relationship between the first voltage drop and the second voltage drop; and the comparison module 12 is used to generate a first voltage drop based on the reference current flowing through the variable resistance unit when the first output result indicates that the first voltage drop is greater than the second voltage drop, and to generate a third voltage drop based on the reference current flowing through the first resistance unit, and to output a second output result based on the magnitude relationship between the first voltage drop and the third voltage drop, wherein the second output result indicates that the first voltage drop is greater than the third voltage drop.
[0028] It can be understood that the target resistance value to be measured of the above-mentioned variable resistance unit is used to represent the resistance value after the electric fuse is blown, that is, the target resistance value to be measured can be the resistance value after the electric fuse is completely blown (blown state), or it can be the resistance value after it is not completely blown (not completely blown state). Moreover, according to the modified formula of Ohm's law U=IR, it can be known that when the first voltage drop generated by the same current flowing through the variable resistance unit is greater than the second voltage drop generated by the same current flowing through the first resistance unit and the second resistance unit, the target resistance value to be measured of the variable resistance unit is greater than the sum of the resistance values of the first resistance unit and the second resistance unit. In other words, when the resistance value after the electric fuse is blown is greater than the sum of the resistance values of the first resistance unit and the second resistance unit, the comparison module outputs a first output result indicating that the first voltage drop is greater than the second voltage drop, and the control circuit can determine that the electric fuse is a completely blown electric fuse based on the first output result. In this way, by improving the judgment standard of the electric fuse being blown, the control circuit 10 that meets the judgment standard only compares the resistance value after the electric fuse is blown with the resistance value of the first resistance unit in actual application, ensuring that the resistance value after the electric fuse is blown is greater than the resistance value of the first resistance unit, so as to judge that the electric fuse is a completely blown electric fuse.
[0029] In some embodiments, the resistance of the first resistor unit is greater than or equal to the resistance of the second resistor unit. It can be understood that since the target resistance to be measured of the variable resistor unit is greater than the sum of the resistances of the first resistor unit and the second resistor unit, and the resistance of the first resistor unit is greater than or equal to the resistance of the second resistor unit, that is, when only the resistance after the electric fuse is blown is compared with the resistance of the first resistor unit, the resistance after the electric fuse is blown must be greater than the resistance of the first resistor unit, and the difference is approximately the resistance of the second resistor unit, so that the blown state of the electric fuse can be more accurately identified. In other words, since the resistance after the electric fuse is blown must be greater than the first resistor unit, that is, the first voltage drop generated by the same current flowing through the variable resistor unit must be greater than the third voltage drop generated by flowing through the first resistor unit, in this way, the comparison module outputs a second output result indicating that the first voltage drop is greater than the third voltage drop, and the control circuit can determine that the electric fuse is a completely blown electric fuse with the second output result. In this way, it is ensured that in actual application, the above-mentioned correction of circuit parameters can be achieved by blowing the electric fuse through the control circuit 10; and the resistance value after the electric fuse is blown is at least different from the resistance value of the first resistance unit by the resistance value of the above-mentioned second resistance unit, which effectively reserves the error range caused by the circuit offset voltage, ensuring that the circuit parameters can be corrected by blowing the electric fuse.
[0030] In some embodiments, Figure 2 FIG. 1 shows a circuit diagram of a control circuit 10. Figure 2 As shown, the control circuit 10 includes a reference module 11, a comparison module 12, a control module 13 and a bias module 14; and each module is connected to the same power supply voltage VDD and the same ground terminal AGND.
[0031] In some embodiments, the bias module 14 includes a reference resistor R03 (an example of a third resistor unit), a reference resistor R04 (an example of a third resistor unit), a PMOS transistor MP1 (an example of a first mirror unit / a first MOS transistor), and a reference current source Iref. One end of the reference resistor R03 is connected to the output end of the power supply voltage VDD, the other end of the reference resistor R03 is connected to one end of the reference resistor R04, the other end of the reference resistor R04 is connected to the source of the PMOS transistor MP1, the drain of the PMOS transistor MP1 is connected to one end of the reference current source Iref, the other end of the reference current source Iref is connected to the input end of the ground terminal AGND, and the source of the PMOS transistor MP1 is short-circuited with the gate of the PMOS transistor MP1.
[0032] In some embodiments, the reference module 11 includes a reference resistor R01 (an example of a first resistor unit), a reference resistor R02 (an example of a second resistor unit), a PMOS transistor MP2 (an example of a second mirror unit / a second MOS transistor), an NMOS transistor MN4 (an example of a fourth MOS transistor), and an NMOS transistor MN5 (an example of a fifth MOS transistor). One end of the reference resistor R01 is connected to the output end of the power supply voltage VDD, the other end of the reference resistor R01 is connected to one end of the reference resistor R02, the other end of the reference resistor R02 is connected to the source of the PMOS transistor MP2, the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN4, the source of the NMOS transistor MN4 is connected to the drain of the NMOS transistor MN5, the source of the NMOS transistor MN5 is connected to the input end of the ground terminal AGND, and the drain of the NMOS transistor MN4 is short-circuited with the gate of the NMOS transistor MN5. The resistance of the reference resistor R01 is greater than or equal to the resistance of the reference resistor R02 , and the reference resistor R01 is equal to the reference resistor R03 , and the reference resistor R02 is equal to the reference resistor R04 .
[0033] In some embodiments, the comparison module 12 includes an electric fuse Rfuse (an example of a variable resistance unit), a PMOS tube MP3 (an example of a third mirror unit / a third MOS tube), an NMOS tube MN6 (an example of a sixth MOS tube), an NMOS tube MN7 (an example of a seventh MOS tube), and a comparator buffer. Among them, one end of the electric fuse Rfuse is connected to the output end of the power supply voltage VDD, the other end of the electric fuse Rfuse is connected to the source of the PMOS tube MP3, the drain of the PMOS tube MP3 is connected to the drain of the NMOS tube MN6, the source of the NMOS tube MN6 is connected to the drain of the NMOS tube MN7, the source of the NMOS tube MN7 is connected to the input end of the ground terminal AGND, and the drain of the PMOS tube MP3 is connected to the input end of the comparator buffer, and the output end of the comparator buffer is used to output the result OUT.
[0034] In some embodiments, the control module 13 includes a control terminal TEST_CTRL, a switch S1 (an example of a first switch unit), and a switch S2 (an example of a second switch unit). The output end of the control terminal TEST_CTRL is connected to the driving ends of the switch S1 and the switch S2, respectively, and the switch S1 is connected in parallel to the branch of the reference resistor R04, and the switch S2 is connected in parallel to the branch of the reference resistor R02.
[0035] In some embodiments, the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP2, and the sources of the PMOS tubes MP1 and MP2 are connected to the output end of the power supply voltage VDD through corresponding resistors, that is, the PMOS tubes MP1 and MP2 form a current mirror structure, and a first current mirror branch is formed between the PMOS tubes MP1 and MP2. The bias module can copy the current of the reference current source Iref to the reference module through the first current mirror branch, and the current copy ratio is determined based on the ratio of the channel width-to-length ratios of the PMOS tubes MP1 and MP2. Similarly, the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP3, and the sources of the PMOS tubes MP1 and MP3 are connected to the output end of the power supply voltage VDD through corresponding resistors, that is, the PMOS tubes MP1 and MP3 form a current mirror structure, and a second current mirror branch is formed between the PMOS tubes MP1 and MP3. The bias module can copy the current of the reference current source Iref to the comparison module through the second current mirror branch, and the current copy ratio is determined based on the ratio of the channel width-to-length ratios of the PMOS tubes MP1 and MP3.
[0036] In some embodiments, since the drain of NMOS tube MN4 is short-circuited with the gate of NMOS tube MN5, and the gate of NMOS tube MN5 is connected to the gate of NMOS tube MN7, the sources of NMOS tubes MN5 and MN7 are both connected to the ground terminal, that is, the drain potential of NMOS tubes MN5 and MN7 is the same, and the gate drive voltage of NMOS tubes MN5 and MN7 is the drain voltage of NMOS tube MN4. Further, since the drain potential of NMOS tubes MN5 and MN7 is the same, and the gate of NMOS tube MN4 is connected to the gate of NMOS tube MN6, that is, the drain potential of NMOS tubes MN4 and MN6 is the same, and the gate voltage of NMOS tubes MN4 and MN6 is Vbn. It can be seen that NMOS tubes MN5 and MN7 form a cascode power mirror, and NMOS tubes MN5 and MN7 form a cascode power mirror.
[0037] It can be understood that, since the third current mirror branch is formed between the NMOS tubes MN4 and MN5 and the NMOS tubes MN6 and MN7, that is, the NMOS tube MN4 can copy the current flowing through the NMOS tube MN4 to the NMOS tube MN6 through the third current mirror branch, and the NMOS tube MN5 can copy the current flowing through the NMOS tube MN7 to the NMOS tube MN6 through the third current mirror branch, and the current copy ratio is determined based on the ratio of the channel width-to-length ratios of the NMOS tubes MN4 and MN6 and the NMOS tubes MN5 and MN7. In addition, since the NMOS tubes MN4 and MN5 are connected in series with the PMOS tube MP2, that is, the currents of the NMOS tubes MN4 and MN5 are the same as those of the PMOS tube MP2, that is, the currents copied by the NMOS tubes MN4 and MN5 to the corresponding NMOS tubes MN6 and MN7 are equivalent to the current flowing through the PMOS tube MP2 being copied by the PMOS tube MP2 to the MOS tubes MN6 and MN7.
[0038] In some embodiments, the ratio of the channel width to length ratio of the PMOS transistor MP1, the PMOS transistor MP2 and the PMOS transistor MP3 is 1:1:1; the ratio of the channel width to length ratio of the NMOS transistor MN4 and the NMOS transistor MN6 is 1:1; the ratio of the channel width to length ratio of the NMOS transistor MN5 and the NMOS transistor MN7 is 1:1. It can be understood that the current flowing through the reference module 11, the comparison module 12 and the bias module 14 is the reference current Iref.
[0039] In some embodiments, Figure 2 The pull-up current at point c (an instance of the target node) is the current flowing through the PMOS tube MP3 (an instance of the first current), and the pull-down current at point c is the current flowing through the NMOS tube MN6. Since the current flowing through the NMOS tube MN6 is a copied current from the PMOS tube MP2, the pull-down current at point c is the current flowing through the PMOS tube MP2 (an instance of the second current or the third current).
[0040] In some embodiments, when it is necessary to blow the electric fuse Rfuse to correct the circuit parameters, after the electric fuse Rfuse is blown so that the resistance of the electric fuse Rfuse increases to the target resistance to be measured (corresponding to the resistance of the blown electric fuse Rfuse in a completely blown state or an incompletely blown state), the switch S1 and the switch S2 are first controlled to be disconnected through the control terminal TEST_CTRL, so that the control circuit 10 is in the test mode (normal temperature, fixed standard power supply voltage conditions). At this time, the voltage at point b (the source end of the PMOS tube MP3) is VDD-Iref*Rfuse (the value of Iref*Rfuse is an example of the first voltage drop), and the voltage at point a (the source end of the PMOS tube MP2) is VDD-Iref*(R01+R02) (the value of Iref*(R01+R02) is an example of the second voltage drop). When the target resistance to be measured of the electric fuse Rfuse is greater than the sum of the resistances of the reference resistors R01 and R02, the first voltage drop is greater than the second voltage drop, and the voltage at point b is less than the voltage at point a. Since the gate voltages of the PMOS tubes MP2 and MP3 are the same, that is, the effective threshold voltages of the PMOS tubes MP2 and MP3 are the same, then according to the MOS tube saturation region current formula (1):
[0041] I M =1 / 2*μ n* C ox *(W / L)*(Vgs-Vth) 2 (1)
[0042] In formula (1), I M is the current flowing through the corresponding MOS tube, μ n is the surface mobility of the corresponding MOS tube, C ox is the gate oxide capacitance per unit area of the corresponding MOS tube, W is the width of the channel of the corresponding MOS tube, L is the length of the channel of the corresponding MOS tube, Vgs is the gate-source voltage of the corresponding MOS tube, and Vth is the effective threshold voltage of the corresponding MOS tube.
[0043] It can be seen that, when the source terminal voltage of the PMOS tube MP3 is less than the source terminal voltage of the PMOS tube MP2, the current (IMp3) flowing through the PMOS tube MP3 is less than the current flowing through the PMOS tube MP2 (IMp2), that is, the current value of the pull-up current at point c is less than the current value of the pull-down current, and the potential at point c is a low potential. Then, the output result of the detection circuit is a low-level signal (corresponding to the example of the first output result). According to the low-level signal, it can be determined that the target resistance to be measured of the electric fuse Rfuse is greater than the sum of the resistance values of the reference resistor R01 and the reference resistor R02.
[0044] Further, when it is determined that the target resistance to be measured of the electric fuse Rfuse is greater than the sum of the resistances of the reference resistor R01 and the reference resistor R02, the switch S1 and the switch S2 are turned on through the control terminal TEST_CTRL, at which time the reference resistor R04 and the reference resistor R02 are in a short-circuit state, and the control circuit 10 is in user mode (high and low temperature, high or low power supply voltage conditions). Accordingly, at this time, the voltage at point a is VDD-Iref*R01 (the value of Iref*R01 is an example of the third voltage drop). Since the resistance of the reference resistor R01 is greater than or equal to the resistance of the reference resistor R02, the target resistance to be measured of the electric fuse Rfuse must be greater than the resistance of the reference resistor R01. Thus, according to the above formula (1), the current value of the pull-up current at point c is smaller than the current value of the pull-down current, and the potential at point c is a low potential. Then, the output result of the detection circuit is a low-level signal (corresponding to the second output result instance). According to the low-level signal, it can be determined that the target resistance of the electric fuse Rfuse is greater than the resistance of the reference resistor R01.
[0045] In this way, the control circuit 10 can ensure that the circuit parameters can be corrected by blowing the electrical fuse Rfuse, regardless of whether the electrical fuse Rfuse is completely blown.
[0046] Furthermore, since the resistance of the reference resistor R02 is equal to or greater than the resistance of the reference resistor R01, that is, the target resistance to be measured of the electric fuse Rfuse differs from the resistance of the reference resistor R01 by at least the resistance of the reference resistor R02, an error range caused by the circuit offset voltage is effectively reserved, ensuring that the circuit parameters can be corrected by blowing the electric fuse.
[0047] For example, when the target resistance to be measured of the electric fuse Rfuse is greater than the resistance of the reference resistor R01, but the difference between the target resistance to be measured of the electric fuse Rfuse and the resistance of the reference resistor R01 is small, the error of the effective threshold voltage caused by the manufacturing process of the PMOS tubes MP2 and MP3 may cause an error in the current flowing through the PMOS tubes MP2 and MP3, and it is difficult to accurately determine the potential of the point c based on the current flowing through the PMOS tubes MP2 and MP3. For example, in combination with the description of the above formula (1), when the target resistance to be measured of the electric fuse Rfuse is 101 ohms and the resistance of the reference resistor R01 is 100 ohms, the gate voltages of the PMOS tubes MP2 and MP3 are the same, that is, the effective threshold voltages of the PMOS tubes MP2 and MP3 should be the same, and the current flowing through the PMOS tube MP3 should be less than the current flowing through the PMOS tube MP2. However, due to the error in the effective threshold voltage caused by the manufacturing process of the PMOS tubes MP2 and MP3, the effective threshold voltage of the PMOS tube MP3 may be smaller than the effective threshold voltage of the PMOS tube MP2, that is, when the source terminal voltage of the PMOS tube MP3 is smaller than the source terminal voltage of the PMOS tube MP2, the current flowing through the PMOS tube MP3 may be equal to or greater than the current flowing through the PMOS tube MP2, resulting in current comparison error.
[0048] In this way, before comparing the resistance of the electric fuse Rfuse with the reference resistor R01, that is, when in the test mode, the control switches S1 and S2 are disconnected, and the circuit whose target resistance to be measured of the electric fuse Rfuse is greater than the sum of the resistances of the reference resistor R01 and the reference resistor R02 is screened out, so that the control circuit determines that the electric fuse is a completely blown electric fuse. Subsequently, in the user mode, the control switches S1 and S2 are turned on, and only the resistance of the electric fuse Rfuse is compared with the reference resistor R01. Since the target resistance to be measured of the electric fuse Rfuse is greater than the sum of the resistances of the reference resistor R01 and the reference resistor R02, and the resistance of the reference resistor R02 is equal to or greater than the resistance of the reference resistor R01; that is, the target resistance to be measured of the electric fuse Rfuse is not only greater than the resistance of the reference resistor R01, but also differs from the reference resistor R0 by at least the resistance of the reference resistor R02, effectively reserving the error range caused by the circuit offset voltage. That is to say, the control circuit 10 can ensure that the electric fuse after being screened in the test mode is accurately determined as a completely blown electric fuse in the user mode, thereby ensuring that the circuit parameters are corrected by blowing the electric fuse.
[0049] Figure 3 According to some embodiments of the present application, a schematic diagram of the structure of an electronic device 100 is shown. Figure 3As shown, the electronic device 100 includes: a processor 101, a communication interface 103 and a memory 102. Among them, the processor 101, the communication interface 103 and the memory 102 can be connected to each other through an internal bus 104, and can also communicate through other means such as wireless transmission. In the embodiment of the present application, the connection through the bus 104 is taken as an example. The bus 104 can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 104 can be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 104 can also include a power bus, a control bus, and a status signal bus. For the sake of clarity, various buses are marked as bus 104 in the figure.
[0050] The processor 101 may be composed of at least one general-purpose processor, such as a central processing unit (CPU), or a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 101 executes various types of digital storage instructions, such as software or firmware programs stored in the memory 102, which enables the electronic device 100 to provide a variety of services.
[0051] It should be noted that this embodiment can be implemented by a general physical server, for example, an ARM server or an X86 server, or it can be implemented by a virtual machine based on a general physical server combined with NFV technology. A virtual machine refers to a complete computer system with complete hardware system functions simulated by software and running in a completely isolated environment. This application does not make any specific limitations.
[0052] The memory 102 may include a volatile memory, such as a random access memory (RAM); the memory 102 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); the memory 102 may also include a combination of the above types.
[0053] The communication interface 103 can be a wired interface (such as an Ethernet interface), an internal interface (such as a PCIe bus interface), a wired interface (such as an Ethernet interface) or a wireless interface (such as a cellular network interface or a wireless LAN interface) for communicating with other devices or modules.
[0054] Need to explain, Figure 3 This is only one possible implementation of the embodiment of the present application. In actual applications, the electronic device 100 may also include more or fewer components, which will not be elaborated here.
[0055] The present application also provides a chip, which can be deployed in the electronic device 100, and the chip forms a circuit as described in any of the above embodiments. The chip can be an analog-to-digital conversion chip, an interface chip, or a power management chip.
[0056] In the accompanying drawings, some structures or features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of a structure or feature in a particular figure does not imply that such a feature is required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.
[0057] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.
[0058] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of further restrictions, the elements defined by the statement "including one" do not exclude the existence of other identical elements in the process, article or device including the elements.
[0059] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.
Claims
1. A control circuit, characterized in that: include: A reference module and a comparison module, wherein, The reference module includes a first resistance unit and a second resistance unit connected in series, and the comparison module includes a variable resistance unit connected in parallel with the first resistance unit and the second resistance unit; The comparison module is used for generating a first voltage drop based on a reference current flowing through the variable resistance unit when the resistance value of the variable resistance unit changes to a target resistance value to be measured, and generating a second voltage drop based on the reference current flowing through the first resistance unit and the second resistance unit, and outputting a first output result based on a magnitude relationship between the first voltage drop and the second voltage drop; The comparison module is used to generate the first voltage drop based on the reference current flowing through the variable resistance unit, and generate a third voltage drop based on the reference current flowing through the first resistance unit when the first output result indicates that the first voltage drop is greater than the second voltage drop, and output a second output result based on the magnitude relationship between the first voltage drop and the third voltage drop, wherein the second output result indicates that the first voltage drop is greater than the third voltage drop.
2. The circuit according to claim 1, characterized in that The resistance value of the first resistance unit is greater than or equal to the resistance value of the second resistance unit.
3. The circuit according to claim 1, characterized in that The variable resistance unit includes an electric fuse, and the target resistance to be measured is the resistance value after the electric fuse is blown.
4. The circuit according to any one of claims 1 to 3, characterized in that: Also includes: A control module, the control module comprising a first switch unit connected in parallel with the second resistance unit; The control module is used for driving the first switch unit to be in an off state when the resistance value of the variable resistance unit changes to a target resistance value to be measured, so that the reference current can flow through the first resistance unit and the second resistance unit; and The control module is used for driving the first switch unit to be in an on state when the first output result indicates that the first voltage drop is greater than the second voltage drop, so that the reference current flows only through the first resistance unit.
5. The circuit according to claim 4, characterized in that Also includes: A bias module, wherein the bias module includes a first mirror unit and a reference current source connected in series with the first mirror unit, and the current of the reference current source is the reference current, the reference module also includes a second mirror unit, and the comparison module also includes a third mirror unit, wherein: The first mirror unit and the second mirror unit form a first current mirror branch, and the bias module provides the reference current to the reference module based on the first current mirror branch; The first mirror unit and the third mirror unit form a second current mirror branch, and the bias module provides the reference current to the comparison module based on the second current mirror branch.
6. The circuit according to claim 5, characterized in that The second mirror unit is connected in series with the first resistance unit and the second resistance unit, and the third mirror unit is connected in series with the variable resistance unit; The reference current flows through the variable resistance unit to generate the first voltage drop so that the current flowing through the third mirror unit is the first current, and the first current is used as the pull-up current of the target node in the comparison module; The reference current flows through the first resistance unit and the second resistance unit to generate the second voltage drop so that the current flowing through the second mirror unit is the second current, and the second current serves as the pull-down current of the target node; or, The reference current flows through the first resistance unit to generate a third voltage drop so that the current flowing through the second mirror unit is a third current, and the third current serves as a pull-down current of the target node; The comparison module outputs the first output result or the second output result based on the magnitude relationship between the pull-up current and the pull-down current of the target node.
7. The circuit according to claim 6, characterized in that The comparison module determines the first output result or the second output result based on the following method: When the target resistance to be measured is greater than the sum of the resistances of the first resistance unit and the second resistance unit, the first voltage drop is greater than the second voltage drop, and the pull-up current is less than the pull-down current, the first output result is a low level signal; or, When the target resistance to be measured is greater than the resistance of the first resistance unit, the first voltage drop is greater than the third voltage drop, and the pull-up current is less than the pull-down current, the second output result is a low level signal.
8. The circuit according to claim 7, characterized in that The first mirror unit includes a first MOS tube, the second mirror unit includes a second MOS tube, the third mirror unit includes a third MOS tube, the bias module includes a third resistor unit and a fourth resistor unit, the third resistor unit has a resistance equal to that of the first resistor unit, the fourth resistor unit has a resistance equal to that of the second resistor unit, the control module includes a second switch unit, the second switch unit is connected in parallel with the fourth resistor unit, and the second switch unit is in the same open or closed state as the first switch unit; One end of the third resistor unit is connected to the output end of the power supply voltage, the other end of the second resistor unit is connected to one end of the fourth resistor unit, the other end of the fourth resistor unit is connected to the source of the first MOS tube, one end of the first resistor unit is connected to the output end of the power supply voltage, the other end of the first resistor unit is connected to one end of the second resistor unit, the other end of the second resistor unit is connected to the source of the second MOS tube, one end of the variable resistor unit is connected to the output end of the power supply voltage, the other end of the variable resistor unit is connected to the source of the third MOS tube, and The source of the first MOS tube is terminated with the gate of the first MOS tube, and the gate of the first MOS tube is respectively connected with the gate of the second MOS tube and the gate of the third MOS tube, so that the first MOS tube and the second MOS tube form a first current mirror branch and provide the reference current to the bias module through the first current mirror branch, and the first MOS tube and the third MOS tube form a second current mirror branch and provide the reference current to the comparison module through the second current mirror branch.
9. The circuit according to claim 8, characterized in that The reference module includes a fourth MOS tube and a fifth MOS tube, and the comparison module includes a sixth MOS tube and a seventh MOS tube; The drain of the fourth MOS tube is connected to the drain of the second MOS tube, the source of the fourth MOS tube is connected to the drain of the fifth MOS tube, the source of the fifth MOS tube is connected to the ground terminal, the drain of the sixth MOS tube is connected to the drain of the third MOS tube, the source of the sixth MOS tube is connected to the drain of the seventh MOS tube, the source of the seventh MOS tube is connected to the ground terminal, and The gate of the fourth MOS tube is connected to the gate of the sixth MOS tube, and the gate of the fourth MOS tube and the gate of the sixth MOS tube are provided with a second driving voltage, the gate of the fifth MOS tube is connected to the gate of the seventh MOS tube, and the gate of the fifth MOS tube and the gate of the seventh MOS tube are both connected to the drain of the fourth MOS tube, so that the fourth MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube form a third current mirror branch, and the reference module provides the second current or the third current to the comparison module through the third current mirror branch, so that the second current or the third current is used as the pull-down current of the target node.
10. The circuit according to claim 9, characterized in that The first MOS tube, the second MOS tube and the third MOS tube are PMOS tubes, and the fourth MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are NMOS tubes.
11. A chip, characterized in that: The chip has the circuit according to any one of claims 1 to 10 formed therein.
12. An electronic device, characterized in that: The electronic device comprises a chip, in which the circuit according to any one of claims 1 to 10 is formed.