P2L mapping table management method during transparent compression of solid state disk and SSD

Abstract

The invention provides a solid state disk, which comprises a front-end module, a compression module, a storage module, a storage module and a storage module, wherein the front-end module is used for receiving a read command, a write command and data from a host, sending the received data to the compression module, reading data according to the read command and replying the data to the host; the compression module is used for judging whether the received data can be compressed or not, compressing the data which can be compressed, and decompressing the read compressed data; the flash memory is used for storing the data and the META corresponding to the data; the flash memory controller communicates with the NAND and reads the P2L mapping table to the static random access memory; and the hardware acceleration module is used for comparing the L2P mapping table with the P2L mapping table, finding effective data and carrying out garbage collection on the PBA corresponding to the effective data. According to the invention, a compression mechanism is introduced, and the erasing of the Nand is reduced through a data compression mode, so that the writing efficiency is improved and the service life of the Nand is prolonged under the condition that the normal functions of the system are not influenced.

Description

Technical Field

[0001] The present invention relates to the field of solid state drives, and more specifically to a solid state drive and a P2L mapping table management method during SSD transparent compression. Background Art

[0002] With the rapid development of information technology, the amount of data of enterprises and individuals is growing, and the demand for large-capacity storage is becoming more and more urgent. Nowadays, SSDs generally use P2L mapping tables to record the relationship between nand physical address PBA and host LBA. During the host write process, P2L will be written to nand synchronously, and then compared with L2P table during garbage collection to confirm the location of garbage collection. L2P records the location of host LBA and nand physical address PBA. If the information in L2P does not match the information in P2L during the comparison, it means that the data at this location is written to other PBAs after that, and the data at this location does not need to be garbage collected. Generally, LBA and PBA are 1:1, but after using the compression function, the ratio of LBA and PBA will change. There may be multiple LBAs written to the same PBA, and the above process will have problems.

[0003] When transparent compression is added, the method of using the general P2L mapping table and L2P table to confirm the location that needs garbage collection will have problems, because one NAND physical address PBA will correspond to several host LBAs. The previous method can only find the location relationship of one host LBA data, so garbage collection will have problems. Summary of the invention

[0004] The object of the present invention is to provide a P2L mapping table management method during SSD transparent compression, which improves writing efficiency and prolongs the service life of Nand.

[0005] According to one aspect of the present invention, there is provided a solid state hard disk, comprising:

[0006] Front-end module: receives read commands, write commands and data from the host, sends the received data to the compression module, and reads the data according to the read command and replies to the host;

[0007] Compression module: determines whether the received data can be compressed, compresses the compressible data, and decompresses the compressed data;

[0008] Flash memory: used to store data and metadata corresponding to the data;

[0009] Flash memory controller: communicates with the flash memory and reads the P2L mapping table into the static random access memory;

[0010] Hardware acceleration module: compares the L2P mapping table with the P2L mapping table, finds valid data, and performs garbage collection on the PBA corresponding to the valid data.

[0011] In some implementations, a buffer management module is further included, and the buffer management module is used to manage the buffer storing data and metadata.

[0012] According to another aspect of the present invention, there is provided a P2L mapping table management method for transparent compression of a solid-state drive according to claim 1, wherein when a host continuously sends a write command: LBA information of compressed data is recorded at a PBA position corresponding to the P2L mapping table, and the compressed data and LBA information are written into a memory;

[0013] During garbage collection: the memory controller reads the P2L mapping table into the buffer of the static random access memory, and the hardware acceleration module compares the L2P mapping table and the P2L mapping table. If valid data exists, the corresponding PBA performs garbage collection.

[0014] In some implementations, the compressed data is stored in the buffer management module, and the flash memory controller obtains the compressed data and LBA information in the metadata from the buffer management module and writes them into the memory.

[0015] In some implementations, the compression module determines whether the received data can be compressed, and if it can be compressed, records the LBA information at a corresponding position in the P2L mapping table.

[0016] In some implementations, each PBA in the P2L mapping table records 1-4 LBAs.

[0017] In some implementations, the data unit sent by the host is 4KB.

[0018] In some implementations, the compression module compresses data in units of 4 KB, and the sum of the sizes of the compressed data is no greater than 4 KB.

[0019] In some implementations, the compression module may compress 2 or 3 or 4 4KB data into 1 data no larger than 4KB.

[0020] The beneficial effects are as follows: the present invention introduces a compression mechanism, which reduces the erasing and writing of NAND by compressing data, thereby improving the writing efficiency and extending the service life of NAND without affecting the normal function of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A schematic diagram of a system framework of a solid state drive according to an embodiment of the present invention;

[0022] Figure 2 It is a schematic diagram of a P2L mapping table management method for SSD transparent compression when the compression function is started according to one embodiment of the present invention;

[0023] Figure 3 It is a schematic diagram of a P2L mapping table management method for SSD transparent compression when compression is turned on for garbage collection according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention will be further described below in conjunction with the accompanying drawings.

[0025] like Figure 1 As shown in the figure, the solid state drive SSD includes a front-end module (NWME), a compression module, a buffer management module (BMU), a hardware acceleration module HW ACC, a flash memory controller NCTL, a CPU, and a memory NAND. The front-end module is responsible for receiving commands and data from the host, and then sending the data to the compression module. The compression module is responsible for compressing or decompressing the received data. The buffer management module is responsible for managing the buffer for storing data and META. The flash memory controller NCTL is responsible for communicating with the flash memory NAND. The hardware acceleration module HW ACC is responsible for some hardware acceleration functions.

[0026] The flash memory particles in the flash memory NAND have a characteristic that they cannot be overwritten. To rewrite, they must be erased first. Erasing is done in units of blocks, and writing is done in units of pages. There are thousands of pages in a block, so before erasing the block, you must first determine which pages have valid data. The valid data must be moved to a new location. The entire process is called garbage collection. When it is necessary to overwrite, that is, write to the same logical address, the algorithm is to find a new physical location, that is, the physical location corresponding to the logical address has changed, which is the corresponding relationship recorded in the L2P table. When garbage collection is performed, if it is found that the records of the P2L mapping table are inconsistent with the L2P mapping table, it means that the data at the corresponding location in the current P2L mapping table record has been overwritten and is in another physical location. Then the data at the current physical location is invalid and does not need garbage collection. If they are consistent, it means that the corresponding data is still at the current physical location and garbage collection is required.

[0027] In the absence of compression, when the host IO (host io) is in progress, the current LBA is written to the PBA position and recorded in the L2P mapping table. The LBA and corresponding PBA information are synchronously recorded in the P2L mapping table (16K cache is available in the dynamic random access memory DRAM), and then a P2L page is written after 1024 pages are written. The P2L page records the relationship between the PBA and LBA of the previous 4096 pages when the host IO is in progress (4-byte LBA corresponds to 4K PBA position). When garbage collection GC is in progress, the CPU will first read out the P2L mapping table in the nand flash (there will be a P2L page every 1024 pages, and the P2L page position is fixed). The hardware acceleration module HW ACC compares the content of the P2L mapping table in the flash memory NAND with the L2P table in the current dynamic random access memory DRAM: if the two are different, it means that after the P2L mapping table was written, a host IO wrote the same LBA position in the P2L mapping table, and the PBA recorded in the P2L mapping table is no longer the latest position and has become invalid data, so garbage collection is not required; the PBA position recorded in the part where the content of the P2L mapping table is the same as that of the L2P table in the current dynamic random access memory DRAM requires garbage collection.

[0028] like Figure 2 As shown, when the compression function is started, the relationship between LBA and PBA will not be determined, because multiple host LBA data will be compressed into one and written to the same PBA. The present invention can compress two 4KB data into one 4KB data, or compress three 4KB data into one 4KB data, and support compression of up to 4 4KB data into one 4KB data. A nand PBA position will correspond to multiple LBAs, because at most 4 4K are compressed into 1 4K, so each PBA needs to record at most 4 LBAs, and the P2L mapping table that needs to be recorded is 4 times that when compression is not enabled. When compression is not enabled, a P2L page is written after 1024 pages, and after compression is enabled, a P2L mapping table page is written every 256 pages.

[0029] When doing host io, the process is as follows:

[0030] When the host continuously sends write commands with a data unit of 4KB, the front-end module NVME receives the data and commands and sends the received data and commands to the compression module;

[0031] The compression module determines whether these 4KB data can be compressed and compresses them in units of 4KB. The sum of the compressed data size cannot be greater than 4KB. Two or three, or at most four, 4KB data can be compressed into one data not greater than 4KB.

[0032] The compression module provides a flag to let the software know whether the data can be compressed. When a 4KB data can be compressed, the flag of the 4KB data is set to 0. When the software recognizes that the flag of the 4KB data is set to 0, it records the LBA information in the corresponding position of the P2L mapping table. When the flag is 1, it means that the corresponding data can no longer be compressed. This data is the compressed data that needs to be written to the NAND. Take 3 4KB data compressed into 1 4KB as an example. The LBA data distribution of the 3 4KB data is LBA0, LBA1, LBA2. When the LBA0, LBA1, LBA2 host io commands (cmd) are issued, the software will record the LBA0, LBA1 and LBA2 information in sequence at the 16-byte position of the PBA corresponding to the P2L mapping table. The last 4 bytes are all F, indicating an invalid address, indicating that this PBA data corresponds to the LBA0, LBA1 and LBA2 information in sequence after decompression. At the same time, the SSD CPU will write these 16 bytes of information to the metadata META.

[0033] The compressed 4KB data is stored in the buffer management module BMU. The software sends a command to the flash controller NCTL. The flash controller NCTL obtains the compressed 4KB data and LBA information in the metadata META from the buffer management module BMU and writes it to the flash NAND. After writing 256 data pages, the 16KB P2L mapping table cache in the dynamic random access memory DRAM will be full. At this time, the content in the P2L mapping table cache needs to be written to the next page. When writing to the end of a block, the software will force the current content in the P2L mapping table cache to be written to the last page.

[0034] like Figure 3 As shown, the process of the present invention when compression is turned on for garbage collection is as follows:

[0035] The CPU of the SSD sends a command to the flash memory controller NCTL, and the flash memory controller NCTL reads the previously written P2L mapping table from a fixed position into the buffer of the static random access memory SRAM.

[0036] Start the hardware acceleration module HW ACC to compare the contents of the L2P mapping table with the read P2L mapping table in units of 16 bytes (recording 4 LBAs). If there is valid data in these 4 LBAs after comparison with the L2P mapping table, the corresponding PBA needs to be garbage collected.

[0037] The above are only some embodiments of the present invention, which are only used to illustrate the technical method of the present invention, but not to limit it. For ordinary technicians in this field, without departing from the creative concept of the present invention, modifying the technical method recorded in the above embodiments, or equivalently replacing some or all of the technical features therein, all belong to the protection scope of the present invention.

Claims

1. A solid state hard disk, characterized in that: include: Front-end module: receives read commands, write commands and data from the host, sends the received data to the compression module, and reads the data according to the read command and replies to the host; Compression module: determines whether the received data can be compressed, compresses the compressible data, and decompresses the compressed data; Flash memory: used to store data and metadata corresponding to the data; Flash memory controller: communicates with the flash memory and reads the P2L mapping table into the static random access memory; Hardware acceleration module: compares the L2P mapping table with the P2L mapping table, finds valid data, and performs garbage collection on the PBA corresponding to the valid data.

2. The solid state drive according to claim 1, wherein: It also includes a buffer management module, which is used to manage the buffer storing data and metadata.

3. A P2L mapping table management method for SSD transparent compression based on the solid state drive of claim 1, characterized in that: When the host sends write commands continuously: the LBA information of the compressed data is recorded at the PBA position corresponding to the P2L mapping table, and the compressed data and LBA information are written into the memory; During garbage collection: the memory controller reads the P2L mapping table into the buffer of the static random access memory, and the hardware acceleration module compares the L2P mapping table and the P2L mapping table. If valid data exists, the corresponding PBA performs garbage collection.

4. The method for managing a P2L mapping table during SSD transparent compression according to claim 3, characterized in that: The compressed data is stored in the buffer management module, and the flash memory controller obtains the compressed data and LBA information in the metadata from the buffer management module and writes them into the memory.

5. The method for managing a P2L mapping table during SSD transparent compression according to claim 3, characterized in that: The compression module determines whether the received data can be compressed, and if it can be compressed, records the LBA information at the corresponding position of the P2L mapping table.

6. The method for managing a P2L mapping table during SSD transparent compression according to claim 5, characterized in that: Each PBA in the P2L mapping table records 1-4 LBAs.

7. The method for managing a P2L mapping table during SSD transparent compression according to claim 3, characterized in that: The data unit sent by the host is 4KB.

8. The method for managing a P2L mapping table during SSD transparent compression according to claim 7, characterized in that: The compression module compresses data in units of 4KB, and the sum of the sizes of the compressed data is no greater than 4KB.

9. The method for managing a P2L mapping table during SSD transparent compression according to claim 8, characterized in that: The compression module can compress 2, 3 or 4 4KB data into 1 data no larger than 4KB.

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